1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Xilinx Zynq GPIO device driver
4 *
5 * Copyright (C) 2009 - 2014 Xilinx, Inc.
6 */
7
8 #include <linux/bitops.h>
9 #include <linux/clk.h>
10 #include <linux/gpio/driver.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/spinlock.h>
14 #include <linux/io.h>
15 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/of.h>
19
20 #define DRIVER_NAME "zynq-gpio"
21
22 /* Maximum banks */
23 #define ZYNQ_GPIO_MAX_BANK 4
24 #define ZYNQMP_GPIO_MAX_BANK 6
25 #define VERSAL_GPIO_MAX_BANK 4
26 #define PMC_GPIO_MAX_BANK 5
27 #define VERSAL_UNUSED_BANKS 2
28 #define EIO_GPIO_MAX_BANK 2
29
30 #define ZYNQ_GPIO_BANK0_NGPIO 32
31 #define ZYNQ_GPIO_BANK1_NGPIO 22
32 #define ZYNQ_GPIO_BANK2_NGPIO 32
33 #define ZYNQ_GPIO_BANK3_NGPIO 32
34
35 #define ZYNQMP_GPIO_BANK0_NGPIO 26
36 #define ZYNQMP_GPIO_BANK1_NGPIO 26
37 #define ZYNQMP_GPIO_BANK2_NGPIO 26
38 #define ZYNQMP_GPIO_BANK3_NGPIO 32
39 #define ZYNQMP_GPIO_BANK4_NGPIO 32
40 #define ZYNQMP_GPIO_BANK5_NGPIO 32
41
42 #define ZYNQ_GPIO_NR_GPIOS 118
43 #define ZYNQMP_GPIO_NR_GPIOS 174
44
45 #define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0
46 #define ZYNQ_GPIO_BANK0_PIN_MAX(str) (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \
47 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
48 #define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1)
49 #define ZYNQ_GPIO_BANK1_PIN_MAX(str) (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \
50 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
51 #define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1)
52 #define ZYNQ_GPIO_BANK2_PIN_MAX(str) (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \
53 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
54 #define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1)
55 #define ZYNQ_GPIO_BANK3_PIN_MAX(str) (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \
56 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
57 #define ZYNQ_GPIO_BANK4_PIN_MIN(str) (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1)
58 #define ZYNQ_GPIO_BANK4_PIN_MAX(str) (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \
59 ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
60 #define ZYNQ_GPIO_BANK5_PIN_MIN(str) (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1)
61 #define ZYNQ_GPIO_BANK5_PIN_MAX(str) (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \
62 ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
63
64 /* Register offsets for the GPIO device */
65 /* LSW Mask & Data -WO */
66 #define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
67 /* MSW Mask & Data -WO */
68 #define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
69 /* Data Register-RW */
70 #define ZYNQ_GPIO_DATA_OFFSET(BANK) (0x040 + (4 * BANK))
71 #define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK))
72 /* Direction mode reg-RW */
73 #define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK))
74 /* Output enable reg-RW */
75 #define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK))
76 /* Interrupt mask reg-RO */
77 #define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK))
78 /* Interrupt enable reg-WO */
79 #define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK))
80 /* Interrupt disable reg-WO */
81 #define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK))
82 /* Interrupt status reg-RO */
83 #define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK))
84 /* Interrupt type reg-RW */
85 #define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK))
86 /* Interrupt polarity reg-RW */
87 #define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK))
88 /* Interrupt on any, reg-RW */
89 #define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK))
90
91 /* Disable all interrupts mask */
92 #define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF
93
94 /* Mid pin number of a bank */
95 #define ZYNQ_GPIO_MID_PIN_NUM 16
96
97 /* GPIO upper 16 bit mask */
98 #define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
99
100 /* set to differentiate zynq from zynqmp, 0=zynqmp, 1=zynq */
101 #define ZYNQ_GPIO_QUIRK_IS_ZYNQ BIT(0)
102 #define GPIO_QUIRK_DATA_RO_BUG BIT(1)
103 #define GPIO_QUIRK_VERSAL BIT(2)
104
105 struct gpio_regs {
106 u32 datamsw[ZYNQMP_GPIO_MAX_BANK];
107 u32 datalsw[ZYNQMP_GPIO_MAX_BANK];
108 u32 dirm[ZYNQMP_GPIO_MAX_BANK];
109 u32 outen[ZYNQMP_GPIO_MAX_BANK];
110 u32 int_en[ZYNQMP_GPIO_MAX_BANK];
111 u32 int_dis[ZYNQMP_GPIO_MAX_BANK];
112 u32 int_type[ZYNQMP_GPIO_MAX_BANK];
113 u32 int_polarity[ZYNQMP_GPIO_MAX_BANK];
114 u32 int_any[ZYNQMP_GPIO_MAX_BANK];
115 };
116
117 /**
118 * struct zynq_gpio - gpio device private data structure
119 * @chip: instance of the gpio_chip
120 * @base_addr: base address of the GPIO device
121 * @clk: clock resource for this controller
122 * @irq: interrupt for the GPIO device
123 * @p_data: pointer to platform data
124 * @context: context registers
125 * @dirlock: lock used for direction in/out synchronization
126 */
127 struct zynq_gpio {
128 struct gpio_chip chip;
129 void __iomem *base_addr;
130 struct clk *clk;
131 int irq;
132 const struct zynq_platform_data *p_data;
133 struct gpio_regs context;
134 spinlock_t dirlock; /* lock */
135 };
136
137 /**
138 * struct zynq_platform_data - zynq gpio platform data structure
139 * @label: string to store in gpio->label
140 * @quirks: Flags is used to identify the platform
141 * @ngpio: max number of gpio pins
142 * @max_bank: maximum number of gpio banks
143 * @bank_min: this array represents bank's min pin
144 * @bank_max: this array represents bank's max pin
145 */
146 struct zynq_platform_data {
147 const char *label;
148 u32 quirks;
149 u16 ngpio;
150 int max_bank;
151 int bank_min[ZYNQMP_GPIO_MAX_BANK];
152 int bank_max[ZYNQMP_GPIO_MAX_BANK];
153 };
154
155 static const struct irq_chip zynq_gpio_level_irqchip;
156 static const struct irq_chip zynq_gpio_edge_irqchip;
157
158 /**
159 * zynq_gpio_is_zynq - test if HW is zynq or zynqmp
160 * @gpio: Pointer to driver data struct
161 *
162 * Return: 0 if zynqmp, 1 if zynq.
163 */
zynq_gpio_is_zynq(struct zynq_gpio * gpio)164 static int zynq_gpio_is_zynq(struct zynq_gpio *gpio)
165 {
166 return !!(gpio->p_data->quirks & ZYNQ_GPIO_QUIRK_IS_ZYNQ);
167 }
168
169 /**
170 * gpio_data_ro_bug - test if HW bug exists or not
171 * @gpio: Pointer to driver data struct
172 *
173 * Return: 0 if bug doesnot exist, 1 if bug exists.
174 */
gpio_data_ro_bug(struct zynq_gpio * gpio)175 static int gpio_data_ro_bug(struct zynq_gpio *gpio)
176 {
177 return !!(gpio->p_data->quirks & GPIO_QUIRK_DATA_RO_BUG);
178 }
179
180 /**
181 * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
182 * for a given pin in the GPIO device
183 * @pin_num: gpio pin number within the device
184 * @bank_num: an output parameter used to return the bank number of the gpio
185 * pin
186 * @bank_pin_num: an output parameter used to return pin number within a bank
187 * for the given gpio pin
188 * @gpio: gpio device data structure
189 *
190 * Returns the bank number and pin offset within the bank.
191 */
zynq_gpio_get_bank_pin(unsigned int pin_num,unsigned int * bank_num,unsigned int * bank_pin_num,struct zynq_gpio * gpio)192 static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
193 unsigned int *bank_num,
194 unsigned int *bank_pin_num,
195 struct zynq_gpio *gpio)
196 {
197 int bank;
198
199 for (bank = 0; bank < gpio->p_data->max_bank; bank++) {
200 if ((pin_num >= gpio->p_data->bank_min[bank]) &&
201 (pin_num <= gpio->p_data->bank_max[bank])) {
202 *bank_num = bank;
203 *bank_pin_num = pin_num -
204 gpio->p_data->bank_min[bank];
205 return;
206 }
207 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
208 bank = bank + VERSAL_UNUSED_BANKS;
209 }
210
211 /* default */
212 WARN(true, "invalid GPIO pin number: %u", pin_num);
213 *bank_num = 0;
214 *bank_pin_num = 0;
215 }
216
217 /**
218 * zynq_gpio_get_value - Get the state of the specified pin of GPIO device
219 * @chip: gpio_chip instance to be worked on
220 * @pin: gpio pin number within the device
221 *
222 * This function reads the state of the specified pin of the GPIO device.
223 *
224 * Return: 0 if the pin is low, 1 if pin is high.
225 */
zynq_gpio_get_value(struct gpio_chip * chip,unsigned int pin)226 static int zynq_gpio_get_value(struct gpio_chip *chip, unsigned int pin)
227 {
228 u32 data;
229 unsigned int bank_num, bank_pin_num;
230 struct zynq_gpio *gpio = gpiochip_get_data(chip);
231
232 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
233
234 if (gpio_data_ro_bug(gpio)) {
235 if (zynq_gpio_is_zynq(gpio)) {
236 if (bank_num <= 1) {
237 data = readl_relaxed(gpio->base_addr +
238 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
239 } else {
240 data = readl_relaxed(gpio->base_addr +
241 ZYNQ_GPIO_DATA_OFFSET(bank_num));
242 }
243 } else {
244 if (bank_num <= 2) {
245 data = readl_relaxed(gpio->base_addr +
246 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
247 } else {
248 data = readl_relaxed(gpio->base_addr +
249 ZYNQ_GPIO_DATA_OFFSET(bank_num));
250 }
251 }
252 } else {
253 data = readl_relaxed(gpio->base_addr +
254 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
255 }
256 return (data >> bank_pin_num) & 1;
257 }
258
259 /**
260 * zynq_gpio_set_value - Modify the state of the pin with specified value
261 * @chip: gpio_chip instance to be worked on
262 * @pin: gpio pin number within the device
263 * @state: value used to modify the state of the specified pin
264 *
265 * This function calculates the register offset (i.e to lower 16 bits or
266 * upper 16 bits) based on the given pin number and sets the state of a
267 * gpio pin to the specified value. The state is either 0 or non-zero.
268 */
zynq_gpio_set_value(struct gpio_chip * chip,unsigned int pin,int state)269 static int zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin,
270 int state)
271 {
272 unsigned int reg_offset, bank_num, bank_pin_num;
273 struct zynq_gpio *gpio = gpiochip_get_data(chip);
274
275 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
276
277 if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
278 /* only 16 data bits in bit maskable reg */
279 bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
280 reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
281 } else {
282 reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
283 }
284
285 /*
286 * get the 32 bit value to be written to the mask/data register where
287 * the upper 16 bits is the mask and lower 16 bits is the data
288 */
289 state = !!state;
290 state = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
291 ((state << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
292
293 writel_relaxed(state, gpio->base_addr + reg_offset);
294
295 return 0;
296 }
297
298 /**
299 * zynq_gpio_dir_in - Set the direction of the specified GPIO pin as input
300 * @chip: gpio_chip instance to be worked on
301 * @pin: gpio pin number within the device
302 *
303 * This function uses the read-modify-write sequence to set the direction of
304 * the gpio pin as input.
305 *
306 * Return: 0 always
307 */
zynq_gpio_dir_in(struct gpio_chip * chip,unsigned int pin)308 static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
309 {
310 u32 reg;
311 unsigned int bank_num, bank_pin_num;
312 unsigned long flags;
313 struct zynq_gpio *gpio = gpiochip_get_data(chip);
314
315 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
316
317 /*
318 * On zynq bank 0 pins 7 and 8 are special and cannot be used
319 * as inputs.
320 */
321 if (zynq_gpio_is_zynq(gpio) && bank_num == 0 &&
322 (bank_pin_num == 7 || bank_pin_num == 8))
323 return -EINVAL;
324
325 /* clear the bit in direction mode reg to set the pin as input */
326 spin_lock_irqsave(&gpio->dirlock, flags);
327 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
328 reg &= ~BIT(bank_pin_num);
329 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
330 spin_unlock_irqrestore(&gpio->dirlock, flags);
331
332 return 0;
333 }
334
335 /**
336 * zynq_gpio_dir_out - Set the direction of the specified GPIO pin as output
337 * @chip: gpio_chip instance to be worked on
338 * @pin: gpio pin number within the device
339 * @state: value to be written to specified pin
340 *
341 * This function sets the direction of specified GPIO pin as output, configures
342 * the Output Enable register for the pin and uses zynq_gpio_set to set
343 * the state of the pin to the value specified.
344 *
345 * Return: 0 always
346 */
zynq_gpio_dir_out(struct gpio_chip * chip,unsigned int pin,int state)347 static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin,
348 int state)
349 {
350 u32 reg;
351 unsigned int bank_num, bank_pin_num;
352 unsigned long flags;
353 struct zynq_gpio *gpio = gpiochip_get_data(chip);
354
355 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
356
357 /* set the GPIO pin as output */
358 spin_lock_irqsave(&gpio->dirlock, flags);
359 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
360 reg |= BIT(bank_pin_num);
361 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
362
363 /* configure the output enable reg for the pin */
364 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
365 reg |= BIT(bank_pin_num);
366 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
367 spin_unlock_irqrestore(&gpio->dirlock, flags);
368
369 /* set the state of the pin */
370 zynq_gpio_set_value(chip, pin, state);
371 return 0;
372 }
373
374 /**
375 * zynq_gpio_get_direction - Read the direction of the specified GPIO pin
376 * @chip: gpio_chip instance to be worked on
377 * @pin: gpio pin number within the device
378 *
379 * This function returns the direction of the specified GPIO.
380 *
381 * Return: GPIO_LINE_DIRECTION_OUT or GPIO_LINE_DIRECTION_IN
382 */
zynq_gpio_get_direction(struct gpio_chip * chip,unsigned int pin)383 static int zynq_gpio_get_direction(struct gpio_chip *chip, unsigned int pin)
384 {
385 u32 reg;
386 unsigned int bank_num, bank_pin_num;
387 struct zynq_gpio *gpio = gpiochip_get_data(chip);
388
389 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
390
391 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
392
393 if (reg & BIT(bank_pin_num))
394 return GPIO_LINE_DIRECTION_OUT;
395
396 return GPIO_LINE_DIRECTION_IN;
397 }
398
399 /**
400 * zynq_gpio_irq_mask - Disable the interrupts for a gpio pin
401 * @irq_data: per irq and chip data passed down to chip functions
402 *
403 * This function calculates gpio pin number from irq number and sets the
404 * bit in the Interrupt Disable register of the corresponding bank to disable
405 * interrupts for that pin.
406 */
zynq_gpio_irq_mask(struct irq_data * irq_data)407 static void zynq_gpio_irq_mask(struct irq_data *irq_data)
408 {
409 unsigned int device_pin_num, bank_num, bank_pin_num;
410 const unsigned long offset = irqd_to_hwirq(irq_data);
411 struct gpio_chip *chip = irq_data_get_irq_chip_data(irq_data);
412 struct zynq_gpio *gpio =
413 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
414
415 gpiochip_disable_irq(chip, offset);
416 device_pin_num = irq_data->hwirq;
417 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
418 writel_relaxed(BIT(bank_pin_num),
419 gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
420 }
421
422 /**
423 * zynq_gpio_irq_unmask - Enable the interrupts for a gpio pin
424 * @irq_data: irq data containing irq number of gpio pin for the interrupt
425 * to enable
426 *
427 * This function calculates the gpio pin number from irq number and sets the
428 * bit in the Interrupt Enable register of the corresponding bank to enable
429 * interrupts for that pin.
430 */
zynq_gpio_irq_unmask(struct irq_data * irq_data)431 static void zynq_gpio_irq_unmask(struct irq_data *irq_data)
432 {
433 unsigned int device_pin_num, bank_num, bank_pin_num;
434 const unsigned long offset = irqd_to_hwirq(irq_data);
435 struct gpio_chip *chip = irq_data_get_irq_chip_data(irq_data);
436 struct zynq_gpio *gpio =
437 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
438
439 gpiochip_enable_irq(chip, offset);
440 device_pin_num = irq_data->hwirq;
441 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
442 writel_relaxed(BIT(bank_pin_num),
443 gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num));
444 }
445
446 /**
447 * zynq_gpio_irq_ack - Acknowledge the interrupt of a gpio pin
448 * @irq_data: irq data containing irq number of gpio pin for the interrupt
449 * to ack
450 *
451 * This function calculates gpio pin number from irq number and sets the bit
452 * in the Interrupt Status Register of the corresponding bank, to ACK the irq.
453 */
zynq_gpio_irq_ack(struct irq_data * irq_data)454 static void zynq_gpio_irq_ack(struct irq_data *irq_data)
455 {
456 unsigned int device_pin_num, bank_num, bank_pin_num;
457 struct zynq_gpio *gpio =
458 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
459
460 device_pin_num = irq_data->hwirq;
461 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
462 writel_relaxed(BIT(bank_pin_num),
463 gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
464 }
465
466 /**
467 * zynq_gpio_irq_enable - Enable the interrupts for a gpio pin
468 * @irq_data: irq data containing irq number of gpio pin for the interrupt
469 * to enable
470 *
471 * Clears the INTSTS bit and unmasks the given interrupt.
472 */
zynq_gpio_irq_enable(struct irq_data * irq_data)473 static void zynq_gpio_irq_enable(struct irq_data *irq_data)
474 {
475 /*
476 * The Zynq GPIO controller does not disable interrupt detection when
477 * the interrupt is masked and only disables the propagation of the
478 * interrupt. This means when the controller detects an interrupt
479 * condition while the interrupt is logically disabled it will propagate
480 * that interrupt event once the interrupt is enabled. This will cause
481 * the interrupt consumer to see spurious interrupts to prevent this
482 * first make sure that the interrupt is not asserted and then enable
483 * it.
484 */
485 zynq_gpio_irq_ack(irq_data);
486 zynq_gpio_irq_unmask(irq_data);
487 }
488
489 /**
490 * zynq_gpio_set_irq_type - Set the irq type for a gpio pin
491 * @irq_data: irq data containing irq number of gpio pin
492 * @type: interrupt type that is to be set for the gpio pin
493 *
494 * This function gets the gpio pin number and its bank from the gpio pin number
495 * and configures the INT_TYPE, INT_POLARITY and INT_ANY registers.
496 *
497 * Return: 0, negative error otherwise.
498 * TYPE-EDGE_RISING, INT_TYPE - 1, INT_POLARITY - 1, INT_ANY - 0;
499 * TYPE-EDGE_FALLING, INT_TYPE - 1, INT_POLARITY - 0, INT_ANY - 0;
500 * TYPE-EDGE_BOTH, INT_TYPE - 1, INT_POLARITY - NA, INT_ANY - 1;
501 * TYPE-LEVEL_HIGH, INT_TYPE - 0, INT_POLARITY - 1, INT_ANY - NA;
502 * TYPE-LEVEL_LOW, INT_TYPE - 0, INT_POLARITY - 0, INT_ANY - NA
503 */
zynq_gpio_set_irq_type(struct irq_data * irq_data,unsigned int type)504 static int zynq_gpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
505 {
506 u32 int_type, int_pol, int_any;
507 unsigned int device_pin_num, bank_num, bank_pin_num;
508 struct zynq_gpio *gpio =
509 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
510
511 device_pin_num = irq_data->hwirq;
512 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
513
514 int_type = readl_relaxed(gpio->base_addr +
515 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
516 int_pol = readl_relaxed(gpio->base_addr +
517 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
518 int_any = readl_relaxed(gpio->base_addr +
519 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
520
521 /*
522 * based on the type requested, configure the INT_TYPE, INT_POLARITY
523 * and INT_ANY registers
524 */
525 switch (type) {
526 case IRQ_TYPE_EDGE_RISING:
527 int_type |= BIT(bank_pin_num);
528 int_pol |= BIT(bank_pin_num);
529 int_any &= ~BIT(bank_pin_num);
530 break;
531 case IRQ_TYPE_EDGE_FALLING:
532 int_type |= BIT(bank_pin_num);
533 int_pol &= ~BIT(bank_pin_num);
534 int_any &= ~BIT(bank_pin_num);
535 break;
536 case IRQ_TYPE_EDGE_BOTH:
537 int_type |= BIT(bank_pin_num);
538 int_any |= BIT(bank_pin_num);
539 break;
540 case IRQ_TYPE_LEVEL_HIGH:
541 int_type &= ~BIT(bank_pin_num);
542 int_pol |= BIT(bank_pin_num);
543 break;
544 case IRQ_TYPE_LEVEL_LOW:
545 int_type &= ~BIT(bank_pin_num);
546 int_pol &= ~BIT(bank_pin_num);
547 break;
548 default:
549 return -EINVAL;
550 }
551
552 writel_relaxed(int_type,
553 gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
554 writel_relaxed(int_pol,
555 gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
556 writel_relaxed(int_any,
557 gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num));
558
559 if (type & IRQ_TYPE_LEVEL_MASK)
560 irq_set_chip_handler_name_locked(irq_data,
561 &zynq_gpio_level_irqchip,
562 handle_fasteoi_irq, NULL);
563 else
564 irq_set_chip_handler_name_locked(irq_data,
565 &zynq_gpio_edge_irqchip,
566 handle_level_irq, NULL);
567
568 return 0;
569 }
570
zynq_gpio_set_wake(struct irq_data * data,unsigned int on)571 static int zynq_gpio_set_wake(struct irq_data *data, unsigned int on)
572 {
573 struct zynq_gpio *gpio =
574 gpiochip_get_data(irq_data_get_irq_chip_data(data));
575
576 irq_set_irq_wake(gpio->irq, on);
577
578 return 0;
579 }
580
zynq_gpio_irq_reqres(struct irq_data * d)581 static int zynq_gpio_irq_reqres(struct irq_data *d)
582 {
583 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
584 int ret;
585
586 ret = pm_runtime_resume_and_get(chip->parent);
587 if (ret < 0)
588 return ret;
589
590 return gpiochip_reqres_irq(chip, d->hwirq);
591 }
592
zynq_gpio_irq_relres(struct irq_data * d)593 static void zynq_gpio_irq_relres(struct irq_data *d)
594 {
595 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
596
597 gpiochip_relres_irq(chip, d->hwirq);
598 pm_runtime_put(chip->parent);
599 }
600
601 /* irq chip descriptor */
602 static const struct irq_chip zynq_gpio_level_irqchip = {
603 .name = DRIVER_NAME,
604 .irq_enable = zynq_gpio_irq_enable,
605 .irq_eoi = zynq_gpio_irq_ack,
606 .irq_mask = zynq_gpio_irq_mask,
607 .irq_unmask = zynq_gpio_irq_unmask,
608 .irq_set_type = zynq_gpio_set_irq_type,
609 .irq_set_wake = zynq_gpio_set_wake,
610 .irq_request_resources = zynq_gpio_irq_reqres,
611 .irq_release_resources = zynq_gpio_irq_relres,
612 .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED |
613 IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,
614 };
615
616 static const struct irq_chip zynq_gpio_edge_irqchip = {
617 .name = DRIVER_NAME,
618 .irq_enable = zynq_gpio_irq_enable,
619 .irq_ack = zynq_gpio_irq_ack,
620 .irq_mask = zynq_gpio_irq_mask,
621 .irq_unmask = zynq_gpio_irq_unmask,
622 .irq_set_type = zynq_gpio_set_irq_type,
623 .irq_set_wake = zynq_gpio_set_wake,
624 .irq_request_resources = zynq_gpio_irq_reqres,
625 .irq_release_resources = zynq_gpio_irq_relres,
626 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,
627 };
628
zynq_gpio_handle_bank_irq(struct zynq_gpio * gpio,unsigned int bank_num,unsigned long pending)629 static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio,
630 unsigned int bank_num,
631 unsigned long pending)
632 {
633 unsigned int bank_offset = gpio->p_data->bank_min[bank_num];
634 struct irq_domain *irqdomain = gpio->chip.irq.domain;
635 int offset;
636
637 if (!pending)
638 return;
639
640 for_each_set_bit(offset, &pending, 32)
641 generic_handle_domain_irq(irqdomain, offset + bank_offset);
642 }
643
644 /**
645 * zynq_gpio_irqhandler - IRQ handler for the gpio banks of a gpio device
646 * @desc: irq descriptor instance of the 'irq'
647 *
648 * This function reads the Interrupt Status Register of each bank to get the
649 * gpio pin number which has triggered an interrupt. It then acks the triggered
650 * interrupt and calls the pin specific handler set by the higher layer
651 * application for that pin.
652 * Note: A bug is reported if no handler is set for the gpio pin.
653 */
zynq_gpio_irqhandler(struct irq_desc * desc)654 static void zynq_gpio_irqhandler(struct irq_desc *desc)
655 {
656 u32 int_sts, int_enb;
657 unsigned int bank_num;
658 struct zynq_gpio *gpio =
659 gpiochip_get_data(irq_desc_get_handler_data(desc));
660 struct irq_chip *irqchip = irq_desc_get_chip(desc);
661
662 chained_irq_enter(irqchip, desc);
663
664 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
665 int_sts = readl_relaxed(gpio->base_addr +
666 ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
667 int_enb = readl_relaxed(gpio->base_addr +
668 ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
669 zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb);
670 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
671 bank_num = bank_num + VERSAL_UNUSED_BANKS;
672 }
673
674 chained_irq_exit(irqchip, desc);
675 }
676
zynq_gpio_save_context(struct zynq_gpio * gpio)677 static void zynq_gpio_save_context(struct zynq_gpio *gpio)
678 {
679 unsigned int bank_num;
680
681 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
682 gpio->context.datalsw[bank_num] =
683 readl_relaxed(gpio->base_addr +
684 ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num));
685 gpio->context.datamsw[bank_num] =
686 readl_relaxed(gpio->base_addr +
687 ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num));
688 gpio->context.dirm[bank_num] = readl_relaxed(gpio->base_addr +
689 ZYNQ_GPIO_DIRM_OFFSET(bank_num));
690 gpio->context.int_en[bank_num] = readl_relaxed(gpio->base_addr +
691 ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
692 gpio->context.int_type[bank_num] =
693 readl_relaxed(gpio->base_addr +
694 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
695 gpio->context.int_polarity[bank_num] =
696 readl_relaxed(gpio->base_addr +
697 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
698 gpio->context.int_any[bank_num] =
699 readl_relaxed(gpio->base_addr +
700 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
701 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
702 bank_num = bank_num + VERSAL_UNUSED_BANKS;
703 }
704 }
705
zynq_gpio_restore_context(struct zynq_gpio * gpio)706 static void zynq_gpio_restore_context(struct zynq_gpio *gpio)
707 {
708 unsigned int bank_num;
709
710 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
711 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
712 ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
713 writel_relaxed(gpio->context.datalsw[bank_num],
714 gpio->base_addr +
715 ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num));
716 writel_relaxed(gpio->context.datamsw[bank_num],
717 gpio->base_addr +
718 ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num));
719 writel_relaxed(gpio->context.dirm[bank_num],
720 gpio->base_addr +
721 ZYNQ_GPIO_DIRM_OFFSET(bank_num));
722 writel_relaxed(gpio->context.int_type[bank_num],
723 gpio->base_addr +
724 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
725 writel_relaxed(gpio->context.int_polarity[bank_num],
726 gpio->base_addr +
727 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
728 writel_relaxed(gpio->context.int_any[bank_num],
729 gpio->base_addr +
730 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
731 writel_relaxed(~(gpio->context.int_en[bank_num]),
732 gpio->base_addr +
733 ZYNQ_GPIO_INTEN_OFFSET(bank_num));
734 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
735 bank_num = bank_num + VERSAL_UNUSED_BANKS;
736 }
737 }
738
zynq_gpio_suspend(struct device * dev)739 static int zynq_gpio_suspend(struct device *dev)
740 {
741 struct zynq_gpio *gpio = dev_get_drvdata(dev);
742 struct irq_data *data = irq_get_irq_data(gpio->irq);
743
744 if (!data) {
745 dev_err(dev, "irq_get_irq_data() failed\n");
746 return -EINVAL;
747 }
748
749 if (!device_may_wakeup(dev))
750 disable_irq(gpio->irq);
751
752 if (!irqd_is_wakeup_set(data)) {
753 zynq_gpio_save_context(gpio);
754 return pm_runtime_force_suspend(dev);
755 }
756
757 return 0;
758 }
759
zynq_gpio_resume(struct device * dev)760 static int zynq_gpio_resume(struct device *dev)
761 {
762 struct zynq_gpio *gpio = dev_get_drvdata(dev);
763 struct irq_data *data = irq_get_irq_data(gpio->irq);
764 int ret;
765
766 if (!data) {
767 dev_err(dev, "irq_get_irq_data() failed\n");
768 return -EINVAL;
769 }
770
771 if (!device_may_wakeup(dev))
772 enable_irq(gpio->irq);
773
774 if (!irqd_is_wakeup_set(data)) {
775 ret = pm_runtime_force_resume(dev);
776 zynq_gpio_restore_context(gpio);
777 return ret;
778 }
779
780 return 0;
781 }
782
zynq_gpio_runtime_suspend(struct device * dev)783 static int zynq_gpio_runtime_suspend(struct device *dev)
784 {
785 struct zynq_gpio *gpio = dev_get_drvdata(dev);
786
787 clk_disable_unprepare(gpio->clk);
788
789 return 0;
790 }
791
zynq_gpio_runtime_resume(struct device * dev)792 static int zynq_gpio_runtime_resume(struct device *dev)
793 {
794 struct zynq_gpio *gpio = dev_get_drvdata(dev);
795
796 return clk_prepare_enable(gpio->clk);
797 }
798
zynq_gpio_request(struct gpio_chip * chip,unsigned int offset)799 static int zynq_gpio_request(struct gpio_chip *chip, unsigned int offset)
800 {
801 return pm_runtime_resume_and_get(chip->parent);
802 }
803
zynq_gpio_free(struct gpio_chip * chip,unsigned int offset)804 static void zynq_gpio_free(struct gpio_chip *chip, unsigned int offset)
805 {
806 pm_runtime_put(chip->parent);
807 }
808
809 static const struct dev_pm_ops zynq_gpio_dev_pm_ops = {
810 SYSTEM_SLEEP_PM_OPS(zynq_gpio_suspend, zynq_gpio_resume)
811 RUNTIME_PM_OPS(zynq_gpio_runtime_suspend, zynq_gpio_runtime_resume, NULL)
812 };
813
814 static const struct zynq_platform_data eio_gpio_def = {
815 .label = "eio_gpio",
816 .ngpio = 52,
817 .max_bank = EIO_GPIO_MAX_BANK,
818 .bank_min[0] = 0,
819 .bank_max[0] = 25, /* 0 to 25 are connected to MIOs (26 pins) */
820 .bank_min[1] = 26,
821 .bank_max[1] = 51, /* Bank 1 are connected to MIOs (26 pins) */
822 };
823
824 static const struct zynq_platform_data versal_gpio_def = {
825 .label = "versal_gpio",
826 .quirks = GPIO_QUIRK_VERSAL,
827 .ngpio = 58,
828 .max_bank = VERSAL_GPIO_MAX_BANK,
829 .bank_min[0] = 0,
830 .bank_max[0] = 25, /* 0 to 25 are connected to MIOs (26 pins) */
831 .bank_min[3] = 26,
832 .bank_max[3] = 57, /* Bank 3 is connected to FMIOs (32 pins) */
833 };
834
835 static const struct zynq_platform_data pmc_gpio_def = {
836 .label = "pmc_gpio",
837 .ngpio = 116,
838 .max_bank = PMC_GPIO_MAX_BANK,
839 .bank_min[0] = 0,
840 .bank_max[0] = 25, /* 0 to 25 are connected to MIOs (26 pins) */
841 .bank_min[1] = 26,
842 .bank_max[1] = 51, /* Bank 1 are connected to MIOs (26 pins) */
843 .bank_min[3] = 52,
844 .bank_max[3] = 83, /* Bank 3 is connected to EMIOs (32 pins) */
845 .bank_min[4] = 84,
846 .bank_max[4] = 115, /* Bank 4 is connected to EMIOs (32 pins) */
847 };
848
849 static const struct zynq_platform_data zynqmp_gpio_def = {
850 .label = "zynqmp_gpio",
851 .quirks = GPIO_QUIRK_DATA_RO_BUG,
852 .ngpio = ZYNQMP_GPIO_NR_GPIOS,
853 .max_bank = ZYNQMP_GPIO_MAX_BANK,
854 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP),
855 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP),
856 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP),
857 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP),
858 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP),
859 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP),
860 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP),
861 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP),
862 .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP),
863 .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP),
864 .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP),
865 .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP),
866 };
867
868 static const struct zynq_platform_data zynq_gpio_def = {
869 .label = "zynq_gpio",
870 .quirks = ZYNQ_GPIO_QUIRK_IS_ZYNQ | GPIO_QUIRK_DATA_RO_BUG,
871 .ngpio = ZYNQ_GPIO_NR_GPIOS,
872 .max_bank = ZYNQ_GPIO_MAX_BANK,
873 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(),
874 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(),
875 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(),
876 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(),
877 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(),
878 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(),
879 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(),
880 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(),
881 };
882
883 static const struct of_device_id zynq_gpio_of_match[] = {
884 { .compatible = "xlnx,zynq-gpio-1.0", .data = &zynq_gpio_def },
885 { .compatible = "xlnx,zynqmp-gpio-1.0", .data = &zynqmp_gpio_def },
886 { .compatible = "xlnx,versal-gpio-1.0", .data = &versal_gpio_def },
887 { .compatible = "xlnx,pmc-gpio-1.0", .data = &pmc_gpio_def },
888 { .compatible = "xlnx,eio-gpio-1.0", .data = &eio_gpio_def },
889 { /* end of table */ }
890 };
891 MODULE_DEVICE_TABLE(of, zynq_gpio_of_match);
892
893 /**
894 * zynq_gpio_probe - Initialization method for a zynq_gpio device
895 * @pdev: platform device instance
896 *
897 * This function allocates memory resources for the gpio device and registers
898 * all the banks of the device. It will also set up interrupts for the gpio
899 * pins.
900 * Note: Interrupts are disabled for all the banks during initialization.
901 *
902 * Return: 0 on success, negative error otherwise.
903 */
zynq_gpio_probe(struct platform_device * pdev)904 static int zynq_gpio_probe(struct platform_device *pdev)
905 {
906 int ret, bank_num;
907 struct zynq_gpio *gpio;
908 struct gpio_chip *chip;
909 struct gpio_irq_chip *girq;
910
911 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
912 if (!gpio)
913 return -ENOMEM;
914
915 gpio->p_data = device_get_match_data(&pdev->dev);
916 if (!gpio->p_data)
917 return dev_err_probe(&pdev->dev, -EINVAL,
918 "device_get_match_data() failed\n");
919
920 platform_set_drvdata(pdev, gpio);
921
922 gpio->base_addr = devm_platform_ioremap_resource(pdev, 0);
923 if (IS_ERR(gpio->base_addr))
924 return PTR_ERR(gpio->base_addr);
925
926 gpio->irq = platform_get_irq(pdev, 0);
927 if (gpio->irq < 0)
928 return gpio->irq;
929
930 /* configure the gpio chip */
931 chip = &gpio->chip;
932 chip->label = gpio->p_data->label;
933 chip->owner = THIS_MODULE;
934 chip->parent = &pdev->dev;
935 chip->get = zynq_gpio_get_value;
936 chip->set = zynq_gpio_set_value;
937 chip->request = zynq_gpio_request;
938 chip->free = zynq_gpio_free;
939 chip->direction_input = zynq_gpio_dir_in;
940 chip->direction_output = zynq_gpio_dir_out;
941 chip->get_direction = zynq_gpio_get_direction;
942 chip->base = of_alias_get_id(pdev->dev.of_node, "gpio");
943 chip->ngpio = gpio->p_data->ngpio;
944
945 /* Retrieve GPIO clock */
946 gpio->clk = devm_clk_get_enabled(&pdev->dev, NULL);
947 if (IS_ERR(gpio->clk))
948 return dev_err_probe(&pdev->dev, PTR_ERR(gpio->clk), "input clock not found.\n");
949
950 spin_lock_init(&gpio->dirlock);
951
952 pm_runtime_set_active(&pdev->dev);
953 pm_runtime_enable(&pdev->dev);
954 ret = pm_runtime_resume_and_get(&pdev->dev);
955 if (ret < 0)
956 goto err_pm_dis;
957
958 /* disable interrupts for all banks */
959 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
960 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
961 ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
962 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
963 bank_num = bank_num + VERSAL_UNUSED_BANKS;
964 }
965
966 /* Set up the GPIO irqchip */
967 girq = &chip->irq;
968 gpio_irq_chip_set_chip(girq, &zynq_gpio_edge_irqchip);
969 girq->parent_handler = zynq_gpio_irqhandler;
970 girq->num_parents = 1;
971 girq->parents = devm_kcalloc(&pdev->dev, 1,
972 sizeof(*girq->parents),
973 GFP_KERNEL);
974 if (!girq->parents) {
975 ret = -ENOMEM;
976 goto err_pm_put;
977 }
978 girq->parents[0] = gpio->irq;
979 girq->default_type = IRQ_TYPE_NONE;
980 girq->handler = handle_level_irq;
981
982 /* report a bug if gpio chip registration fails */
983 ret = gpiochip_add_data(chip, gpio);
984 if (ret) {
985 dev_err(&pdev->dev, "Failed to add gpio chip\n");
986 goto err_pm_put;
987 }
988
989 irq_set_status_flags(gpio->irq, IRQ_DISABLE_UNLAZY);
990 device_init_wakeup(&pdev->dev, 1);
991 pm_runtime_put(&pdev->dev);
992
993 return 0;
994
995 err_pm_put:
996 pm_runtime_put(&pdev->dev);
997 err_pm_dis:
998 pm_runtime_disable(&pdev->dev);
999
1000 return ret;
1001 }
1002
1003 /**
1004 * zynq_gpio_remove - Driver removal function
1005 * @pdev: platform device instance
1006 *
1007 * Return: 0 always
1008 */
zynq_gpio_remove(struct platform_device * pdev)1009 static void zynq_gpio_remove(struct platform_device *pdev)
1010 {
1011 struct zynq_gpio *gpio = platform_get_drvdata(pdev);
1012 int ret;
1013
1014 ret = pm_runtime_get_sync(&pdev->dev);
1015 if (ret < 0)
1016 dev_warn(&pdev->dev, "pm_runtime_get_sync() Failed\n");
1017 device_init_wakeup(&pdev->dev, 0);
1018 gpiochip_remove(&gpio->chip);
1019 device_set_wakeup_capable(&pdev->dev, 0);
1020 pm_runtime_disable(&pdev->dev);
1021 pm_runtime_put_noidle(&pdev->dev);
1022 }
1023
1024 static struct platform_driver zynq_gpio_driver = {
1025 .driver = {
1026 .name = DRIVER_NAME,
1027 .pm = pm_ptr(&zynq_gpio_dev_pm_ops),
1028 .of_match_table = zynq_gpio_of_match,
1029 },
1030 .probe = zynq_gpio_probe,
1031 .remove = zynq_gpio_remove,
1032 };
1033
1034 module_platform_driver(zynq_gpio_driver);
1035
1036 MODULE_AUTHOR("Xilinx Inc.");
1037 MODULE_DESCRIPTION("Zynq GPIO driver");
1038 MODULE_LICENSE("GPL");
1039