1 // SPDX-License-Identifier: MIT
2 //
3 // Copyright 2024 Advanced Micro Devices, Inc.
4
5 #include "dm_services.h"
6 #include "dc.h"
7
8 #include "dcn32/dcn32_init.h"
9 #include "dcn401/dcn401_init.h"
10
11 #include "resource.h"
12 #include "include/irq_service_interface.h"
13 #include "dcn401_resource.h"
14
15 #include "dcn20/dcn20_resource.h"
16 #include "dcn30/dcn30_resource.h"
17 #include "dcn32/dcn32_resource.h"
18 #include "dcn321/dcn321_resource.h"
19
20 #include "dcn10/dcn10_ipp.h"
21 #include "dcn401/dcn401_hubbub.h"
22 #include "dcn401/dcn401_mpc.h"
23 #include "dcn401/dcn401_hubp.h"
24 #include "dio/dcn10/dcn10_dio.h"
25 #include "irq/dcn401/irq_service_dcn401.h"
26 #include "dcn401/dcn401_dpp.h"
27 #include "dcn401/dcn401_optc.h"
28 #include "dcn20/dcn20_hwseq.h"
29 #include "dcn30/dcn30_hwseq.h"
30 #include "dce110/dce110_hwseq.h"
31 #include "dcn20/dcn20_opp.h"
32 #include "dcn401/dcn401_dsc.h"
33 #include "dcn30/dcn30_vpg.h"
34 #include "dcn31/dcn31_vpg.h"
35 #include "dcn30/dcn30_afmt.h"
36 #include "dcn30/dcn30_dio_stream_encoder.h"
37 #include "dcn401/dcn401_dio_stream_encoder.h"
38 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
39 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
40 #include "dcn32/dcn32_hpo_dp_link_encoder.h"
41 #include "dcn31/dcn31_apg.h"
42 #include "dcn31/dcn31_dio_link_encoder.h"
43 #include "dcn401/dcn401_dio_link_encoder.h"
44 #include "dcn10/dcn10_link_encoder.h"
45 #include "dcn321/dcn321_dio_link_encoder.h"
46 #include "dce/dce_clock_source.h"
47 #include "dce/dce_audio.h"
48 #include "dce/dce_hwseq.h"
49 #include "clk_mgr.h"
50 #include "dio/virtual/virtual_stream_encoder.h"
51 #include "dml/display_mode_vba.h"
52 #include "dcn401/dcn401_dccg.h"
53 #include "dcn10/dcn10_resource.h"
54 #include "link_service.h"
55 #include "link_enc_cfg.h"
56 #include "dcn31/dcn31_panel_cntl.h"
57
58 #include "dcn30/dcn30_dwb.h"
59 #include "dcn32/dcn32_mmhubbub.h"
60
61 #include "dcn/dcn_4_1_0_offset.h"
62 #include "dcn/dcn_4_1_0_sh_mask.h"
63 #include "nbif/nbif_6_3_1_offset.h"
64
65 #include "reg_helper.h"
66 #include "dce/dmub_abm.h"
67 #include "dce/dmub_psr.h"
68 #include "dce/dce_aux.h"
69 #include "dce/dce_i2c.h"
70
71 #include "dml/dcn30/display_mode_vba_30.h"
72 #include "vm_helper.h"
73 #include "dcn20/dcn20_vmid.h"
74
75 #include "dc_state_priv.h"
76
77 #include "dml2_0/dml2_wrapper.h"
78
79 #define DC_LOGGER_INIT(logger)
80
81 enum dcn401_clk_src_array_id {
82 DCN401_CLK_SRC_PLL0,
83 DCN401_CLK_SRC_PLL1,
84 DCN401_CLK_SRC_PLL2,
85 DCN401_CLK_SRC_PLL3,
86 //DCN401_CLK_SRC_PLL4,
87 DCN401_CLK_SRC_TOTAL
88 };
89
90 /* begin *********************
91 * macros to expend register list macro defined in HW object header file
92 */
93
94 /* DCN */
95 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
96
97 #define BASE(seg) BASE_INNER(seg)
98
99 #define SR(reg_name)\
100 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
101 reg ## reg_name
102 #define SR_ARR(reg_name, id)\
103 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
104 reg ## reg_name
105 #define SR_ARR_INIT(reg_name, id, value)\
106 REG_STRUCT[id].reg_name = value
107
108 #define SRI(reg_name, block, id)\
109 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
110 reg ## block ## id ## _ ## reg_name
111
112 #define SRI_ARR(reg_name, block, id)\
113 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
114 reg ## block ## id ## _ ## reg_name
115
116 /*
117 * Used when a reg_name would otherwise begin with an integer
118 */
119 #define SRI_ARR_US(reg_name, block, id)\
120 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## reg_name ## _BASE_IDX) + \
121 reg ## block ## id ## reg_name
122 #define SR_ARR_I2C(reg_name, id) \
123 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
124
125 #define SRI_ARR_I2C(reg_name, block, id)\
126 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
127 reg ## block ## id ## _ ## reg_name
128
129 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\
130 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
131 reg ## block ## id ## _ ## reg_name
132
133 #define SRI2(reg_name, block, id)\
134 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
135 reg ## reg_name
136 #define SRI2_ARR(reg_name, block, id)\
137 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
138 reg ## reg_name
139
140 #define SRIR(var_name, reg_name, block, id)\
141 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
142 reg ## block ## id ## _ ## reg_name
143
144 #define SRII(reg_name, block, id)\
145 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
146 reg ## block ## id ## _ ## reg_name
147
148 #define SRII_ARR_2(reg_name, block, id, inst)\
149 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
150 reg ## block ## id ## _ ## reg_name
151
152 #define SRII_MPC_RMU(reg_name, block, id)\
153 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
154 reg ## block ## id ## _ ## reg_name
155
156 #define SRII_DWB(reg_name, temp_name, block, id)\
157 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
158 reg ## block ## id ## _ ## temp_name
159
160 #define DCCG_SRII(reg_name, block, id)\
161 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
162 reg ## block ## id ## _ ## reg_name
163
164 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
165 .field_name = reg_name ## __ ## field_name ## post_fix
166
167 #define VUPDATE_SRII(reg_name, block, id)\
168 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
169 reg ## reg_name ## _ ## block ## id
170
171 /* NBIO */
172 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
173
174 #define NBIO_BASE(seg) \
175 NBIO_BASE_INNER(seg)
176
177 #define NBIO_SR(reg_name)\
178 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
179 regBIF_BX0_ ## reg_name
180 #define NBIO_SR_ARR(reg_name, id)\
181 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
182 regBIF_BX0_ ## reg_name
183
184 #define CTX ctx
185 #define REG(reg_name) \
186 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
187
188 static struct bios_registers bios_regs;
189
190 #define bios_regs_init() \
191 NBIO_SR(BIOS_SCRATCH_3),\
192 NBIO_SR(BIOS_SCRATCH_6)
193
194 #define clk_src_regs_init(index, pllid)\
195 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid)
196
197 static struct dce110_clk_src_regs clk_src_regs[5];
198
199 static const struct dce110_clk_src_shift cs_shift = {
200 CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
201 };
202
203 static const struct dce110_clk_src_mask cs_mask = {
204 CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
205 };
206
207 #define abm_regs_init(id)\
208 ABM_DCN401_REG_LIST_RI(id)
209
210 static struct dce_abm_registers abm_regs[4];
211
212 static const struct dce_abm_shift abm_shift = {
213 ABM_MASK_SH_LIST_DCN401(__SHIFT)
214 };
215
216 static const struct dce_abm_mask abm_mask = {
217 ABM_MASK_SH_LIST_DCN401(_MASK)
218 };
219
220 #define audio_regs_init(id)\
221 AUD_COMMON_REG_LIST_RI(id)
222
223 static struct dce_audio_registers audio_regs[5];
224
225 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
226 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
227 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
228 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
229
230 static const struct dce_audio_shift audio_shift = {
231 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
232 };
233
234 static const struct dce_audio_mask audio_mask = {
235 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
236 };
237
238 #define vpg_regs_init(id)\
239 VPG_DCN401_REG_LIST_RI(id)
240
241 static struct dcn31_vpg_registers vpg_regs[9];
242
243 static const struct dcn31_vpg_shift vpg_shift = {
244 DCN31_VPG_MASK_SH_LIST(__SHIFT)
245 };
246
247 static const struct dcn31_vpg_mask vpg_mask = {
248 DCN31_VPG_MASK_SH_LIST(_MASK)
249 };
250
251 #define afmt_regs_init(id)\
252 AFMT_DCN3_REG_LIST_RI(id)
253
254 static struct dcn30_afmt_registers afmt_regs[5];
255
256 static const struct dcn30_afmt_shift afmt_shift = {
257 DCN3_AFMT_MASK_SH_LIST(__SHIFT)
258 };
259
260 static const struct dcn30_afmt_mask afmt_mask = {
261 DCN3_AFMT_MASK_SH_LIST(_MASK)
262 };
263
264 #define apg_regs_init(id)\
265 APG_DCN31_REG_LIST_RI(id)
266
267 static struct dcn31_apg_registers apg_regs[4];
268
269 static const struct dcn31_apg_shift apg_shift = {
270 DCN31_APG_MASK_SH_LIST(__SHIFT)
271 };
272
273 static const struct dcn31_apg_mask apg_mask = {
274 DCN31_APG_MASK_SH_LIST(_MASK)
275 };
276
277 #define stream_enc_regs_init(id)\
278 SE_DCN4_01_REG_LIST_RI(id)
279
280 static struct dcn10_stream_enc_registers stream_enc_regs[4];
281
282 static const struct dcn10_stream_encoder_shift se_shift = {
283 SE_COMMON_MASK_SH_LIST_DCN401(__SHIFT)
284 };
285
286 static const struct dcn10_stream_encoder_mask se_mask = {
287 SE_COMMON_MASK_SH_LIST_DCN401(_MASK)
288 };
289
290 #define aux_regs_init(id)\
291 DCN2_AUX_REG_LIST_RI(id)
292
293 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5];
294
295 #define hpd_regs_init(id)\
296 HPD_REG_LIST_RI(id)
297
298 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5];
299
300 #define link_regs_init(id, phyid)\
301 LE_DCN401_REG_LIST_RI(id)
302
303 static struct dcn10_link_enc_registers link_enc_regs[4];
304
305
306 static const struct dcn10_link_enc_shift le_shift = {
307 LINK_ENCODER_MASK_SH_LIST_DCN401(__SHIFT)
308 };
309
310
311 static const struct dcn10_link_enc_mask le_mask = {
312 LINK_ENCODER_MASK_SH_LIST_DCN401(_MASK)
313 };
314
315
316 #define hpo_dp_stream_encoder_reg_init(id)\
317 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
318
319 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4];
320
321 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
322 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
323 };
324
325 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
326 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
327 };
328
329
330 #define hpo_dp_link_encoder_reg_init(id)\
331 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id)
332 /*DCN3_1_RDPCSTX_REG_LIST(0),*/
333 /*DCN3_1_RDPCSTX_REG_LIST(1),*/
334 /*DCN3_1_RDPCSTX_REG_LIST(2),*/
335 /*DCN3_1_RDPCSTX_REG_LIST(3),*/
336
337 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[4];
338
339 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
340 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
341 };
342
343 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
344 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
345 };
346
347 #define dpp_regs_init(id)\
348 DPP_REG_LIST_DCN401_COMMON_RI(id)
349
350 static struct dcn401_dpp_registers dpp_regs[4];
351
352 static const struct dcn401_dpp_shift tf_shift = {
353 DPP_REG_LIST_SH_MASK_DCN401_COMMON(__SHIFT)
354 };
355
356 static const struct dcn401_dpp_mask tf_mask = {
357 DPP_REG_LIST_SH_MASK_DCN401_COMMON(_MASK)
358 };
359
360 #define opp_regs_init(id)\
361 OPP_REG_LIST_DCN401_RI(id)
362
363 static struct dcn20_opp_registers opp_regs[4];
364
365 static const struct dcn20_opp_shift opp_shift = {
366 OPP_MASK_SH_LIST_DCN20(__SHIFT)
367 };
368
369 static const struct dcn20_opp_mask opp_mask = {
370 OPP_MASK_SH_LIST_DCN20(_MASK)
371 };
372
373 #define aux_engine_regs_init(id) \
374 AUX_COMMON_REG_LIST0_RI(id), SR_ARR_INIT(AUXN_IMPCAL, id, 0), \
375 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \
376 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \
377 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)
378
379 static struct dce110_aux_registers aux_engine_regs[5];
380
381 static const struct dce110_aux_registers_shift aux_shift = {
382 DCN_AUX_MASK_SH_LIST(__SHIFT)
383 };
384
385 static const struct dce110_aux_registers_mask aux_mask = {
386 DCN_AUX_MASK_SH_LIST(_MASK)
387 };
388
389 #define dwbc_regs_dcn401_init(id)\
390 DWBC_COMMON_REG_LIST_DCN30_RI(id)
391
392 static struct dcn30_dwbc_registers dwbc401_regs[1];
393
394 static const struct dcn30_dwbc_shift dwbc401_shift = {
395 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
396 };
397
398 static const struct dcn30_dwbc_mask dwbc401_mask = {
399 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
400 };
401
402
403 #define mcif_wb_regs_dcn3_init(id)\
404 MCIF_WB_COMMON_REG_LIST_DCN32_RI(id)
405
406 static struct dcn30_mmhubbub_registers mcif_wb30_regs[1];
407
408 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
409 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
410 };
411
412 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
413 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK)
414 };
415
416 #define dsc_regs_init(id)\
417 DSC_REG_LIST_DCN401_RI(id)
418
419 static struct dcn401_dsc_registers dsc_regs[4];
420
421 static const struct dcn401_dsc_shift dsc_shift = {
422 DSC_REG_LIST_SH_MASK_DCN401(__SHIFT)
423 };
424
425 static const struct dcn401_dsc_mask dsc_mask = {
426 DSC_REG_LIST_SH_MASK_DCN401(_MASK)
427 };
428
429 static struct dcn401_mpc_registers mpc_regs;
430
431 #define dcn_mpc_regs_init()\
432 MPC_REG_LIST_DCN4_01_RI(0),\
433 MPC_REG_LIST_DCN4_01_RI(1),\
434 MPC_REG_LIST_DCN4_01_RI(2),\
435 MPC_REG_LIST_DCN4_01_RI(3),\
436 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\
437 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\
438 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\
439 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\
440 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0)
441
442 static const struct dcn401_mpc_shift mpc_shift = {
443 MPC_COMMON_MASK_SH_LIST_DCN4_01(__SHIFT)
444 };
445
446 static const struct dcn401_mpc_mask mpc_mask = {
447 MPC_COMMON_MASK_SH_LIST_DCN4_01(_MASK)
448 };
449
450 #define optc_regs_init(id)\
451 OPTC_COMMON_REG_LIST_DCN401_RI(id)
452
453 static struct dcn_optc_registers optc_regs[4];
454
455 static const struct dcn_optc_shift optc_shift = {
456 OPTC_COMMON_MASK_SH_LIST_DCN401(__SHIFT)
457 };
458
459 static const struct dcn_optc_mask optc_mask = {
460 OPTC_COMMON_MASK_SH_LIST_DCN401(_MASK)
461 };
462
463 #define hubp_regs_init(id)\
464 HUBP_REG_LIST_DCN401_RI(id)
465
466 static struct dcn_hubp2_registers hubp_regs[4];
467
468 static const struct dcn_hubp2_shift hubp_shift = {
469 HUBP_MASK_SH_LIST_DCN401(__SHIFT)
470 };
471
472 static const struct dcn_hubp2_mask hubp_mask = {
473 HUBP_MASK_SH_LIST_DCN401(_MASK)
474 };
475
476 static struct dcn_hubbub_registers hubbub_reg;
477 #define hubbub_reg_init()\
478 HUBBUB_REG_LIST_DCN4_01_RI(0)
479
480 static const struct dcn_hubbub_shift hubbub_shift = {
481 HUBBUB_MASK_SH_LIST_DCN4_01(__SHIFT)
482 };
483
484 static const struct dcn_hubbub_mask hubbub_mask = {
485 HUBBUB_MASK_SH_LIST_DCN4_01(_MASK)
486 };
487
488 static struct dccg_registers dccg_regs;
489
490 #define dccg_regs_init()\
491 DCCG_REG_LIST_DCN401_RI()
492
493 static const struct dccg_shift dccg_shift = {
494 DCCG_MASK_SH_LIST_DCN401(__SHIFT)
495 };
496
497 static const struct dccg_mask dccg_mask = {
498 DCCG_MASK_SH_LIST_DCN401(_MASK)
499 };
500
501 #define SRII2(reg_name_pre, reg_name_post, id)\
502 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
503 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
504 reg ## reg_name_pre ## id ## _ ## reg_name_post
505
506
507 #define HWSEQ_DCN401_REG_LIST()\
508 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
509 SR(DIO_MEM_PWR_CTRL), \
510 SR(ODM_MEM_PWR_CTRL3), \
511 SR(MMHUBBUB_MEM_PWR_CNTL), \
512 SR(DCCG_GATE_DISABLE_CNTL), \
513 SR(DCCG_GATE_DISABLE_CNTL2), \
514 SR(DCFCLK_CNTL),\
515 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
516 SRII(PIXEL_RATE_CNTL, OTG, 0), \
517 SRII(PIXEL_RATE_CNTL, OTG, 1),\
518 SRII(PIXEL_RATE_CNTL, OTG, 2),\
519 SRII(PIXEL_RATE_CNTL, OTG, 3),\
520 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
521 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
522 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
523 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
524 SR(MICROSECOND_TIME_BASE_DIV), \
525 SR(MILLISECOND_TIME_BASE_DIV), \
526 SR(DISPCLK_FREQ_CHANGE_CNTL), \
527 SR(RBBMIF_TIMEOUT_DIS), \
528 SR(RBBMIF_TIMEOUT_DIS_2), \
529 SR(DCHUBBUB_CRC_CTRL), \
530 SR(DPP_TOP0_DPP_CRC_CTRL), \
531 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
532 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
533 SR(MPC_CRC_CTRL), \
534 SR(MPC_CRC_RESULT_GB), \
535 SR(MPC_CRC_RESULT_C), \
536 SR(MPC_CRC_RESULT_AR), \
537 SR(DOMAIN0_PG_CONFIG), \
538 SR(DOMAIN1_PG_CONFIG), \
539 SR(DOMAIN2_PG_CONFIG), \
540 SR(DOMAIN3_PG_CONFIG), \
541 SR(DOMAIN16_PG_CONFIG), \
542 SR(DOMAIN17_PG_CONFIG), \
543 SR(DOMAIN18_PG_CONFIG), \
544 SR(DOMAIN19_PG_CONFIG), \
545 SR(DOMAIN22_PG_CONFIG), \
546 SR(DOMAIN23_PG_CONFIG), \
547 SR(DOMAIN24_PG_CONFIG), \
548 SR(DOMAIN25_PG_CONFIG), \
549 SR(DOMAIN0_PG_STATUS), \
550 SR(DOMAIN1_PG_STATUS), \
551 SR(DOMAIN2_PG_STATUS), \
552 SR(DOMAIN3_PG_STATUS), \
553 SR(DOMAIN16_PG_STATUS), \
554 SR(DOMAIN17_PG_STATUS), \
555 SR(DOMAIN18_PG_STATUS), \
556 SR(DOMAIN19_PG_STATUS), \
557 SR(DOMAIN22_PG_STATUS), \
558 SR(DOMAIN23_PG_STATUS), \
559 SR(DOMAIN24_PG_STATUS), \
560 SR(DOMAIN25_PG_STATUS), \
561 SR(DC_IP_REQUEST_CNTL), \
562 SR(AZALIA_AUDIO_DTO), \
563 SR(HPO_TOP_HW_CONTROL),\
564 SR(AZALIA_CONTROLLER_CLOCK_GATING)
565
566 static struct dce_hwseq_registers hwseq_reg;
567
568 #define hwseq_reg_init()\
569 HWSEQ_DCN401_REG_LIST()
570
571 #define HWSEQ_DCN401_MASK_SH_LIST(mask_sh)\
572 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
573 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
574 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
575 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
576 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
577 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
578 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
579 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
580 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
581 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
582 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
583 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
584 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
585 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
586 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
587 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
588 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
589 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
590 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
591 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
592 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
593 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
594 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
595 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
596 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
597 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
598 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
599 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
600 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
601 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
602 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
603 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
604 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
605 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
606 HWS_SF(, DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
607 HWS_SF(, DOMAIN23_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
608 HWS_SF(, DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
609 HWS_SF(, DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
610 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
611 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
612 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
613 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh), \
614 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
615 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh)
616
617 static const struct dce_hwseq_shift hwseq_shift = {
618 HWSEQ_DCN401_MASK_SH_LIST(__SHIFT)
619 };
620
621 static const struct dce_hwseq_mask hwseq_mask = {
622 HWSEQ_DCN401_MASK_SH_LIST(_MASK)
623 };
624
625 #define vmid_regs_init(id)\
626 DCN20_VMID_REG_LIST_RI(id)
627
628 static struct dcn_vmid_registers vmid_regs[16];
629
630 static const struct dcn20_vmid_shift vmid_shifts = {
631 DCN20_VMID_MASK_SH_LIST(__SHIFT)
632 };
633
634 static const struct dcn20_vmid_mask vmid_masks = {
635 DCN20_VMID_MASK_SH_LIST(_MASK)
636 };
637
638 #define dio_regs_init() \
639 DIO_REG_LIST_DCN10()
640
641 static struct dcn_dio_registers dio_regs;
642
643 #define DIO_MASK_SH_LIST_DCN401(mask_sh)\
644 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh)
645
646 static const struct dcn_dio_shift dio_shift = {
647 DIO_MASK_SH_LIST_DCN401(__SHIFT)
648 };
649
650 static const struct dcn_dio_mask dio_mask = {
651 DIO_MASK_SH_LIST_DCN401(_MASK)
652 };
653
654 static const struct resource_caps res_cap_dcn4_01 = {
655 .num_timing_generator = 4,
656 .num_opp = 4,
657 .num_video_plane = 4,
658 .num_audio = 4,
659 .num_stream_encoder = 4,
660 .num_hpo_dp_stream_encoder = 4,
661 .num_hpo_dp_link_encoder = 4,
662 .num_pll = 4,
663 .num_dwb = 1,
664 .num_ddc = 4,
665 .num_vmid = 16,
666 .num_mpc_3dlut = 4,
667 .num_dsc = 4,
668 };
669
670 static const struct dc_plane_cap plane_cap = {
671 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
672 .per_pixel_alpha = true,
673
674 .pixel_format_support = {
675 .argb8888 = true,
676 .nv12 = true,
677 .fp16 = true,
678 .p010 = true,
679 .ayuv = false,
680 },
681
682 .max_upscale_factor = {
683 .argb8888 = 16000,
684 .nv12 = 16000,
685 .fp16 = 16000
686 },
687
688 // 6:1 downscaling ratio: 1000/6 = 166.666
689 .max_downscale_factor = {
690 .argb8888 = 167,
691 .nv12 = 167,
692 .fp16 = 167
693 },
694 64,
695 64
696 };
697
698 static const struct dc_debug_options debug_defaults_drv = {
699 .disable_dmcu = true,
700 .force_abm_enable = false,
701 .clock_trace = true,
702 .disable_pplib_clock_request = false,
703 .pipe_split_policy = MPC_SPLIT_AVOID,
704 .force_single_disp_pipe_split = false,
705 .disable_dcc = DCC_ENABLE,
706 .vsr_support = true,
707 .performance_trace = false,
708 .max_downscale_src_width = 7680,/*upto 8K*/
709 .disable_pplib_wm_range = false,
710 .scl_reset_length10 = true,
711 .sanity_checks = false,
712 .underflow_assert_delay_us = 0xFFFFFFFF,
713 .dwb_fi_phase = -1, // -1 = disable,
714 .dmub_command_table = true,
715 .enable_mem_low_power = {
716 .bits = {
717 .vga = false,
718 .i2c = false,
719 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
720 .dscl = false,
721 .cm = false,
722 .mpc = false,
723 .optc = true,
724 }
725 },
726 .use_max_lb = true,
727 .force_disable_subvp = false,
728 .disable_force_pstate_allow_on_hw_release = false,
729 .exit_idle_opt_for_cursor_updates = true,
730 .using_dml2 = true,
731 .using_dml21 = true,
732 .enable_single_display_2to1_odm_policy = true,
733
734 //must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions
735 .enable_double_buffered_dsc_pg_support = true,
736 .enable_dp_dig_pixel_rate_div_policy = 1,
737 .allow_sw_cursor_fallback = false,
738 .alloc_extra_way_for_cursor = true,
739 .min_prefetch_in_strobe_ns = 60000, // 60us
740 .disable_unbounded_requesting = false,
741 .dcc_meta_propagation_delay_us = 10,
742 .fams_version = {
743 .minor = 1,
744 .major = 2,
745 }, //v2.1
746 .fams2_config = {
747 .bits = {
748 .enable = true,
749 .enable_offload_flip = true,
750 .enable_stall_recovery = true,
751 }
752 },
753 .force_cositing = CHROMA_COSITING_NONE + 1,
754 };
755
756 static const struct dc_check_config config_defaults = {
757 .enable_legacy_fast_update = false,
758 };
759
dcn401_aux_engine_create(struct dc_context * ctx,uint32_t inst)760 static struct dce_aux *dcn401_aux_engine_create(
761 struct dc_context *ctx,
762 uint32_t inst)
763 {
764 struct aux_engine_dce110 *aux_engine =
765 kzalloc_obj(struct aux_engine_dce110);
766
767 if (!aux_engine)
768 return NULL;
769
770 #undef REG_STRUCT
771 #define REG_STRUCT aux_engine_regs
772 aux_engine_regs_init(0),
773 aux_engine_regs_init(1),
774 aux_engine_regs_init(2),
775 aux_engine_regs_init(3);
776
777 dce110_aux_engine_construct(aux_engine, ctx, inst,
778 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
779 &aux_engine_regs[inst],
780 &aux_mask,
781 &aux_shift,
782 ctx->dc->caps.extended_aux_timeout_support);
783
784 return &aux_engine->base;
785 }
786 #define i2c_inst_regs_init(id)\
787 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)
788
789 static struct dce_i2c_registers i2c_hw_regs[5];
790
791 static const struct dce_i2c_shift i2c_shifts = {
792 I2C_COMMON_MASK_SH_LIST_DCN401(__SHIFT)
793 };
794
795 static const struct dce_i2c_mask i2c_masks = {
796 I2C_COMMON_MASK_SH_LIST_DCN401(_MASK)
797 };
798
dcn401_i2c_hw_create(struct dc_context * ctx,uint32_t inst)799 static struct dce_i2c_hw *dcn401_i2c_hw_create(
800 struct dc_context *ctx,
801 uint32_t inst)
802 {
803 struct dce_i2c_hw *dce_i2c_hw =
804 kzalloc_obj(struct dce_i2c_hw);
805
806 if (!dce_i2c_hw)
807 return NULL;
808
809 #undef REG_STRUCT
810 #define REG_STRUCT i2c_hw_regs
811 i2c_inst_regs_init(1),
812 i2c_inst_regs_init(2),
813 i2c_inst_regs_init(3),
814 i2c_inst_regs_init(4);
815
816 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
817 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
818
819 return dce_i2c_hw;
820 }
821
dcn401_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)822 static struct clock_source *dcn401_clock_source_create(
823 struct dc_context *ctx,
824 struct dc_bios *bios,
825 enum clock_source_id id,
826 const struct dce110_clk_src_regs *regs,
827 bool dp_clk_src)
828 {
829 struct dce110_clk_src *clk_src =
830 kzalloc_obj(struct dce110_clk_src);
831
832 if (!clk_src)
833 return NULL;
834
835 if (dcn401_clk_src_construct(clk_src, ctx, bios, id,
836 regs, &cs_shift, &cs_mask)) {
837 clk_src->base.dp_clk_src = dp_clk_src;
838 return &clk_src->base;
839 }
840
841 kfree(clk_src);
842 BREAK_TO_DEBUGGER();
843 return NULL;
844 }
845
dcn401_hubbub_create(struct dc_context * ctx)846 static struct hubbub *dcn401_hubbub_create(struct dc_context *ctx)
847 {
848 int i;
849
850 struct dcn20_hubbub *hubbub2 = kzalloc_obj(struct dcn20_hubbub);
851
852 if (!hubbub2)
853 return NULL;
854
855
856 #undef REG_STRUCT
857 #define REG_STRUCT hubbub_reg
858 hubbub_reg_init();
859
860 #undef REG_STRUCT
861 #define REG_STRUCT vmid_regs
862 vmid_regs_init(0),
863 vmid_regs_init(1),
864 vmid_regs_init(2),
865 vmid_regs_init(3),
866 vmid_regs_init(4),
867 vmid_regs_init(5),
868 vmid_regs_init(6),
869 vmid_regs_init(7),
870 vmid_regs_init(8),
871 vmid_regs_init(9),
872 vmid_regs_init(10),
873 vmid_regs_init(11),
874 vmid_regs_init(12),
875 vmid_regs_init(13),
876 vmid_regs_init(14),
877 vmid_regs_init(15);
878
879 hubbub401_construct(hubbub2, ctx,
880 &hubbub_reg,
881 &hubbub_shift,
882 &hubbub_mask,
883 DCN4_01_DEFAULT_DET_SIZE, //nominal (default) detile buffer size in kbytes,
884 8, //dml2 ip_params_st.pixel_chunk_size_kbytes
885 DCN4_01_CRB_SIZE_KB); //dml2 ip_params_st.config_return_buffer_size_in_kbytes
886
887 for (i = 0; i < res_cap_dcn4_01.num_vmid; i++) {
888 struct dcn20_vmid *vmid = &hubbub2->vmid[i];
889
890 vmid->ctx = ctx;
891
892 vmid->regs = &vmid_regs[i];
893 vmid->shifts = &vmid_shifts;
894 vmid->masks = &vmid_masks;
895 }
896
897 return &hubbub2->base;
898 }
899
dcn401_dio_create(struct dc_context * ctx)900 static struct dio *dcn401_dio_create(struct dc_context *ctx)
901 {
902 struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio);
903
904 if (!dio10)
905 return NULL;
906
907 #undef REG_STRUCT
908 #define REG_STRUCT dio_regs
909 dio_regs_init();
910
911 dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask);
912
913 return &dio10->base;
914 }
915
dcn401_hubp_create(struct dc_context * ctx,uint32_t inst)916 static struct hubp *dcn401_hubp_create(
917 struct dc_context *ctx,
918 uint32_t inst)
919 {
920 struct dcn20_hubp *hubp2 =
921 kzalloc_obj(struct dcn20_hubp);
922
923 if (!hubp2)
924 return NULL;
925
926 #undef REG_STRUCT
927 #define REG_STRUCT hubp_regs
928 hubp_regs_init(0),
929 hubp_regs_init(1),
930 hubp_regs_init(2),
931 hubp_regs_init(3);
932
933 if (hubp401_construct(hubp2, ctx, inst,
934 &hubp_regs[inst], &hubp_shift, &hubp_mask))
935 return &hubp2->base;
936
937 BREAK_TO_DEBUGGER();
938 kfree(hubp2);
939 return NULL;
940 }
941
dcn401_dpp_destroy(struct dpp ** dpp)942 static void dcn401_dpp_destroy(struct dpp **dpp)
943 {
944 kfree(TO_DCN401_DPP(*dpp));
945 *dpp = NULL;
946 }
947
dcn401_dpp_create(struct dc_context * ctx,uint32_t inst)948 static struct dpp *dcn401_dpp_create(
949 struct dc_context *ctx,
950 uint32_t inst)
951 {
952 struct dcn401_dpp *dpp401 =
953 kzalloc_obj(struct dcn401_dpp);
954
955 if (!dpp401)
956 return NULL;
957
958 #undef REG_STRUCT
959 #define REG_STRUCT dpp_regs
960 dpp_regs_init(0),
961 dpp_regs_init(1),
962 dpp_regs_init(2),
963 dpp_regs_init(3);
964
965 if (dpp401_construct(dpp401, ctx, inst,
966 &dpp_regs[inst], &tf_shift, &tf_mask))
967 return &dpp401->base;
968
969 BREAK_TO_DEBUGGER();
970 kfree(dpp401);
971 return NULL;
972 }
973
dcn401_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)974 static struct mpc *dcn401_mpc_create(
975 struct dc_context *ctx,
976 int num_mpcc,
977 int num_rmu)
978 {
979 struct dcn401_mpc *mpc401 = kzalloc_obj(struct dcn401_mpc);
980
981 if (!mpc401)
982 return NULL;
983
984 #undef REG_STRUCT
985 #define REG_STRUCT mpc_regs
986 dcn_mpc_regs_init();
987
988 dcn401_mpc_construct(mpc401, ctx,
989 &mpc_regs,
990 &mpc_shift,
991 &mpc_mask,
992 num_mpcc,
993 num_rmu);
994
995 return &mpc401->base;
996 }
997
dcn401_opp_create(struct dc_context * ctx,uint32_t inst)998 static struct output_pixel_processor *dcn401_opp_create(
999 struct dc_context *ctx, uint32_t inst)
1000 {
1001 struct dcn20_opp *opp4 =
1002 kzalloc_obj(struct dcn20_opp);
1003
1004 if (!opp4) {
1005 BREAK_TO_DEBUGGER();
1006 return NULL;
1007 }
1008
1009 #undef REG_STRUCT
1010 #define REG_STRUCT opp_regs
1011 opp_regs_init(0),
1012 opp_regs_init(1),
1013 opp_regs_init(2),
1014 opp_regs_init(3);
1015
1016 dcn20_opp_construct(opp4, ctx, inst,
1017 &opp_regs[inst], &opp_shift, &opp_mask);
1018 return &opp4->base;
1019 }
1020
1021
dcn401_timing_generator_create(struct dc_context * ctx,uint32_t instance)1022 static struct timing_generator *dcn401_timing_generator_create(
1023 struct dc_context *ctx,
1024 uint32_t instance)
1025 {
1026 struct optc *tgn10 =
1027 kzalloc_obj(struct optc);
1028
1029 if (!tgn10)
1030 return NULL;
1031 #undef REG_STRUCT
1032 #define REG_STRUCT optc_regs
1033 optc_regs_init(0),
1034 optc_regs_init(1),
1035 optc_regs_init(2),
1036 optc_regs_init(3);
1037
1038 tgn10->base.inst = instance;
1039 tgn10->base.ctx = ctx;
1040
1041 tgn10->tg_regs = &optc_regs[instance];
1042 tgn10->tg_shift = &optc_shift;
1043 tgn10->tg_mask = &optc_mask;
1044
1045 dcn401_timing_generator_init(tgn10);
1046
1047 return &tgn10->base;
1048 }
1049
1050 static const struct encoder_feature_support link_enc_feature = {
1051 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1052 .max_hdmi_pixel_clock = 600000,
1053 .hdmi_ycbcr420_supported = true,
1054 .dp_ycbcr420_supported = true,
1055 .fec_supported = true,
1056 .flags.bits.IS_HBR2_CAPABLE = true,
1057 .flags.bits.IS_HBR3_CAPABLE = true,
1058 .flags.bits.IS_TPS3_CAPABLE = true,
1059 .flags.bits.IS_TPS4_CAPABLE = true
1060 };
1061
dcn401_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)1062 static struct link_encoder *dcn401_link_encoder_create(
1063 struct dc_context *ctx,
1064 const struct encoder_init_data *enc_init_data)
1065 {
1066 struct dcn20_link_encoder *enc20 =
1067 kzalloc_obj(struct dcn20_link_encoder);
1068
1069 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
1070 return NULL;
1071
1072 #undef REG_STRUCT
1073 #define REG_STRUCT link_enc_aux_regs
1074 aux_regs_init(0),
1075 aux_regs_init(1),
1076 aux_regs_init(2),
1077 aux_regs_init(3);
1078
1079 #undef REG_STRUCT
1080 #define REG_STRUCT link_enc_hpd_regs
1081 hpd_regs_init(0),
1082 hpd_regs_init(1),
1083 hpd_regs_init(2),
1084 hpd_regs_init(3);
1085 #undef REG_STRUCT
1086 #define REG_STRUCT link_enc_regs
1087 link_regs_init(0, A),
1088 link_regs_init(1, B),
1089 link_regs_init(2, C),
1090 link_regs_init(3, D);
1091
1092 dcn401_link_encoder_construct(enc20,
1093 enc_init_data,
1094 &link_enc_feature,
1095 &link_enc_regs[enc_init_data->transmitter],
1096 &link_enc_aux_regs[enc_init_data->channel - 1],
1097 &link_enc_hpd_regs[enc_init_data->hpd_source],
1098 &le_shift,
1099 &le_mask);
1100 return &enc20->enc10.base;
1101 }
1102
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1103 static void read_dce_straps(
1104 struct dc_context *ctx,
1105 struct resource_straps *straps)
1106 {
1107 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS,
1108 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1109
1110 }
1111
dcn401_create_audio(struct dc_context * ctx,unsigned int inst)1112 static struct audio *dcn401_create_audio(
1113 struct dc_context *ctx, unsigned int inst)
1114 {
1115
1116 #undef REG_STRUCT
1117 #define REG_STRUCT audio_regs
1118 audio_regs_init(0),
1119 audio_regs_init(1),
1120 audio_regs_init(2),
1121 audio_regs_init(3),
1122 audio_regs_init(4);
1123
1124 return dce_audio_create(ctx, inst,
1125 &audio_regs[inst], &audio_shift, &audio_mask);
1126 }
1127
dcn401_vpg_create(struct dc_context * ctx,uint32_t inst)1128 static struct vpg *dcn401_vpg_create(
1129 struct dc_context *ctx,
1130 uint32_t inst)
1131 {
1132 struct dcn31_vpg *vpg4 = kzalloc_obj(struct dcn31_vpg);
1133
1134 if (!vpg4)
1135 return NULL;
1136
1137
1138 #undef REG_STRUCT
1139 #define REG_STRUCT vpg_regs
1140 vpg_regs_init(0),
1141 vpg_regs_init(1),
1142 vpg_regs_init(2),
1143 vpg_regs_init(3),
1144 vpg_regs_init(4),
1145 vpg_regs_init(5),
1146 vpg_regs_init(6),
1147 vpg_regs_init(7),
1148 vpg_regs_init(8);
1149
1150 vpg31_construct(vpg4, ctx, inst,
1151 &vpg_regs[inst],
1152 &vpg_shift,
1153 &vpg_mask);
1154
1155 return &vpg4->base;
1156 }
1157
dcn401_afmt_create(struct dc_context * ctx,uint32_t inst)1158 static struct afmt *dcn401_afmt_create(
1159 struct dc_context *ctx,
1160 uint32_t inst)
1161 {
1162 struct dcn30_afmt *afmt401 = kzalloc_obj(struct dcn30_afmt);
1163
1164 if (!afmt401)
1165 return NULL;
1166
1167 #undef REG_STRUCT
1168 #define REG_STRUCT afmt_regs
1169 afmt_regs_init(0),
1170 afmt_regs_init(1),
1171 afmt_regs_init(2),
1172 afmt_regs_init(3),
1173 afmt_regs_init(4);
1174
1175 afmt3_construct(afmt401, ctx, inst,
1176 &afmt_regs[inst],
1177 &afmt_shift,
1178 &afmt_mask);
1179
1180 return &afmt401->base;
1181 }
1182
dcn401_apg_create(struct dc_context * ctx,uint32_t inst)1183 static struct apg *dcn401_apg_create(
1184 struct dc_context *ctx,
1185 uint32_t inst)
1186 {
1187 struct dcn31_apg *apg31 = kzalloc_obj(struct dcn31_apg);
1188
1189 if (!apg31)
1190 return NULL;
1191
1192 #undef REG_STRUCT
1193 #define REG_STRUCT apg_regs
1194 apg_regs_init(0),
1195 apg_regs_init(1),
1196 apg_regs_init(2),
1197 apg_regs_init(3);
1198
1199 apg31_construct(apg31, ctx, inst,
1200 &apg_regs[inst],
1201 &apg_shift,
1202 &apg_mask);
1203
1204 return &apg31->base;
1205 }
1206
dcn401_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1207 static struct stream_encoder *dcn401_stream_encoder_create(
1208 enum engine_id eng_id,
1209 struct dc_context *ctx)
1210 {
1211 struct dcn10_stream_encoder *enc1;
1212 struct vpg *vpg;
1213 struct afmt *afmt;
1214 int vpg_inst;
1215 int afmt_inst;
1216
1217 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1218 if (eng_id <= ENGINE_ID_DIGF) {
1219 vpg_inst = eng_id;
1220 afmt_inst = eng_id;
1221 } else
1222 return NULL;
1223
1224 enc1 = kzalloc_obj(struct dcn10_stream_encoder);
1225 vpg = dcn401_vpg_create(ctx, vpg_inst);
1226 afmt = dcn401_afmt_create(ctx, afmt_inst);
1227
1228 if (!enc1 || !vpg || !afmt || eng_id >= ARRAY_SIZE(stream_enc_regs)) {
1229 kfree(enc1);
1230 kfree(vpg);
1231 kfree(afmt);
1232 return NULL;
1233 }
1234 #undef REG_STRUCT
1235 #define REG_STRUCT stream_enc_regs
1236 stream_enc_regs_init(0),
1237 stream_enc_regs_init(1),
1238 stream_enc_regs_init(2),
1239 stream_enc_regs_init(3);
1240 //stream_enc_regs_init(4);
1241
1242 dcn401_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1243 eng_id, vpg, afmt,
1244 &stream_enc_regs[eng_id],
1245 &se_shift, &se_mask);
1246 return &enc1->base;
1247 }
1248
dcn401_hpo_dp_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1249 static struct hpo_dp_stream_encoder *dcn401_hpo_dp_stream_encoder_create(
1250 enum engine_id eng_id,
1251 struct dc_context *ctx)
1252 {
1253 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1254 struct vpg *vpg;
1255 struct apg *apg;
1256 uint32_t hpo_dp_inst;
1257 uint32_t vpg_inst;
1258 uint32_t apg_inst;
1259
1260 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1261 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1262
1263 /* Mapping of VPG register blocks to HPO DP block instance:
1264 * VPG[6] -> HPO_DP[0]
1265 * VPG[7] -> HPO_DP[1]
1266 * VPG[8] -> HPO_DP[2]
1267 * VPG[9] -> HPO_DP[3]
1268 */
1269 vpg_inst = hpo_dp_inst + 5;
1270
1271 /* Mapping of APG register blocks to HPO DP block instance:
1272 * APG[0] -> HPO_DP[0]
1273 * APG[1] -> HPO_DP[1]
1274 * APG[2] -> HPO_DP[2]
1275 * APG[3] -> HPO_DP[3]
1276 */
1277 apg_inst = hpo_dp_inst;
1278
1279 /* allocate HPO stream encoder and create VPG sub-block */
1280 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_stream_encoder);
1281 vpg = dcn401_vpg_create(ctx, vpg_inst);
1282 apg = dcn401_apg_create(ctx, apg_inst);
1283
1284 if (!hpo_dp_enc31 || !vpg || !apg) {
1285 kfree(hpo_dp_enc31);
1286 kfree(vpg);
1287 kfree(apg);
1288 return NULL;
1289 }
1290
1291 #undef REG_STRUCT
1292 #define REG_STRUCT hpo_dp_stream_enc_regs
1293 hpo_dp_stream_encoder_reg_init(0),
1294 hpo_dp_stream_encoder_reg_init(1),
1295 hpo_dp_stream_encoder_reg_init(2),
1296 hpo_dp_stream_encoder_reg_init(3);
1297
1298 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1299 hpo_dp_inst, eng_id, vpg, apg,
1300 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1301 &hpo_dp_se_shift, &hpo_dp_se_mask);
1302
1303 return &hpo_dp_enc31->base;
1304 }
1305
dcn401_hpo_dp_link_encoder_create(uint8_t inst,struct dc_context * ctx)1306 static struct hpo_dp_link_encoder *dcn401_hpo_dp_link_encoder_create(
1307 uint8_t inst,
1308 struct dc_context *ctx)
1309 {
1310 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1311
1312 /* allocate HPO link encoder */
1313 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_link_encoder);
1314 if (!hpo_dp_enc31)
1315 return NULL; /* out of memory */
1316
1317 #undef REG_STRUCT
1318 #define REG_STRUCT hpo_dp_link_enc_regs
1319 hpo_dp_link_encoder_reg_init(0),
1320 hpo_dp_link_encoder_reg_init(1),
1321 hpo_dp_link_encoder_reg_init(2),
1322 hpo_dp_link_encoder_reg_init(3);
1323
1324 hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst,
1325 &hpo_dp_link_enc_regs[inst],
1326 &hpo_dp_le_shift, &hpo_dp_le_mask);
1327
1328 return &hpo_dp_enc31->base;
1329 }
1330
dcn401_calc_num_avail_chans_for_mall(struct dc * dc,unsigned int num_chans)1331 static unsigned int dcn401_calc_num_avail_chans_for_mall(struct dc *dc, unsigned int num_chans)
1332 {
1333 unsigned int num_available_chans = 1;
1334
1335 /* channels for MALL must be a power of 2 */
1336 while (num_chans > 1) {
1337 num_available_chans = (num_available_chans << 1);
1338 num_chans = (num_chans >> 1);
1339 }
1340
1341 /* cannot be odd */
1342 num_available_chans &= ~1;
1343
1344 /* clamp to max available channels for MALL per ASIC */
1345 if (ASICREV_IS_GC_12_0_0_A0(dc->ctx->asic_id.hw_internal_rev)) {
1346 num_available_chans = num_available_chans > 16 ? 16 : num_available_chans;
1347 } else if (ASICREV_IS_GC_12_0_1_A0(dc->ctx->asic_id.hw_internal_rev)) {
1348 num_available_chans = num_available_chans > 8 ? 8 : num_available_chans;
1349 }
1350
1351 return num_available_chans;
1352 }
1353
dcn401_hwseq_create(struct dc_context * ctx)1354 static struct dce_hwseq *dcn401_hwseq_create(
1355 struct dc_context *ctx)
1356 {
1357 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);
1358
1359 #undef REG_STRUCT
1360 #define REG_STRUCT hwseq_reg
1361 hwseq_reg_init();
1362
1363 if (hws) {
1364 hws->ctx = ctx;
1365 hws->regs = &hwseq_reg;
1366 hws->shifts = &hwseq_shift;
1367 hws->masks = &hwseq_mask;
1368 }
1369
1370 return hws;
1371 }
1372 static const struct resource_create_funcs res_create_funcs = {
1373 .read_dce_straps = read_dce_straps,
1374 .create_audio = dcn401_create_audio,
1375 .create_stream_encoder = dcn401_stream_encoder_create,
1376 .create_hpo_dp_stream_encoder = dcn401_hpo_dp_stream_encoder_create,
1377 .create_hpo_dp_link_encoder = dcn401_hpo_dp_link_encoder_create,
1378 .create_hwseq = dcn401_hwseq_create,
1379 };
1380
dcn401_dsc_destroy(struct display_stream_compressor ** dsc)1381 static void dcn401_dsc_destroy(struct display_stream_compressor **dsc)
1382 {
1383 kfree(container_of(*dsc, struct dcn401_dsc, base));
1384 *dsc = NULL;
1385 }
1386
dcn401_resource_destruct(struct dcn401_resource_pool * pool)1387 static void dcn401_resource_destruct(struct dcn401_resource_pool *pool)
1388 {
1389 unsigned int i;
1390
1391 for (i = 0; i < pool->base.stream_enc_count; i++) {
1392 if (pool->base.stream_enc[i] != NULL) {
1393 if (pool->base.stream_enc[i]->vpg != NULL) {
1394 kfree(DCN31_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1395 pool->base.stream_enc[i]->vpg = NULL;
1396 }
1397 if (pool->base.stream_enc[i]->afmt != NULL) {
1398 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1399 pool->base.stream_enc[i]->afmt = NULL;
1400 }
1401 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1402 pool->base.stream_enc[i] = NULL;
1403 }
1404 }
1405
1406 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1407 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1408 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1409 kfree(DCN31_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1410 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1411 }
1412 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1413 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1414 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1415 }
1416 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1417 pool->base.hpo_dp_stream_enc[i] = NULL;
1418 }
1419 }
1420
1421 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1422 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1423 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1424 pool->base.hpo_dp_link_enc[i] = NULL;
1425 }
1426 }
1427
1428 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1429 if (pool->base.dscs[i] != NULL)
1430 dcn401_dsc_destroy(&pool->base.dscs[i]);
1431 }
1432
1433 if (pool->base.mpc != NULL) {
1434 kfree(TO_DCN20_MPC(pool->base.mpc));
1435 pool->base.mpc = NULL;
1436 }
1437 if (pool->base.hubbub != NULL) {
1438 kfree(TO_DCN20_HUBBUB(pool->base.hubbub));
1439 pool->base.hubbub = NULL;
1440 }
1441 for (i = 0; i < pool->base.pipe_count; i++) {
1442 if (pool->base.dpps[i] != NULL)
1443 dcn401_dpp_destroy(&pool->base.dpps[i]);
1444
1445 if (pool->base.ipps[i] != NULL)
1446 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1447
1448 if (pool->base.hubps[i] != NULL) {
1449 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1450 pool->base.hubps[i] = NULL;
1451 }
1452
1453 if (pool->base.irqs != NULL) {
1454 dal_irq_service_destroy(&pool->base.irqs);
1455 }
1456 }
1457
1458 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1459 if (pool->base.engines[i] != NULL)
1460 dce110_engine_destroy(&pool->base.engines[i]);
1461 if (pool->base.hw_i2cs[i] != NULL) {
1462 kfree(pool->base.hw_i2cs[i]);
1463 pool->base.hw_i2cs[i] = NULL;
1464 }
1465 if (pool->base.sw_i2cs[i] != NULL) {
1466 kfree(pool->base.sw_i2cs[i]);
1467 pool->base.sw_i2cs[i] = NULL;
1468 }
1469 }
1470
1471 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1472 if (pool->base.opps[i] != NULL)
1473 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1474 }
1475
1476 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1477 if (pool->base.timing_generators[i] != NULL) {
1478 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1479 pool->base.timing_generators[i] = NULL;
1480 }
1481 }
1482
1483 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1484 if (pool->base.dwbc[i] != NULL) {
1485 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1486 pool->base.dwbc[i] = NULL;
1487 }
1488 if (pool->base.mcif_wb[i] != NULL) {
1489 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1490 pool->base.mcif_wb[i] = NULL;
1491 }
1492 }
1493
1494 for (i = 0; i < pool->base.audio_count; i++) {
1495 if (pool->base.audios[i])
1496 dce_aud_destroy(&pool->base.audios[i]);
1497 }
1498
1499 for (i = 0; i < pool->base.clk_src_count; i++) {
1500 if (pool->base.clock_sources[i] != NULL) {
1501 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1502 pool->base.clock_sources[i] = NULL;
1503 }
1504 }
1505
1506 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1507 if (pool->base.mpc_lut[i] != NULL) {
1508 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1509 pool->base.mpc_lut[i] = NULL;
1510 }
1511 if (pool->base.mpc_shaper[i] != NULL) {
1512 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1513 pool->base.mpc_shaper[i] = NULL;
1514 }
1515 }
1516
1517 if (pool->base.dp_clock_source != NULL) {
1518 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1519 pool->base.dp_clock_source = NULL;
1520 }
1521
1522 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1523 if (pool->base.multiple_abms[i] != NULL)
1524 dce_abm_destroy(&pool->base.multiple_abms[i]);
1525 }
1526
1527 if (pool->base.psr != NULL)
1528 dmub_psr_destroy(&pool->base.psr);
1529
1530 if (pool->base.dccg != NULL)
1531 dcn_dccg_destroy(&pool->base.dccg);
1532
1533 if (pool->base.dio != NULL) {
1534 kfree(TO_DCN10_DIO(pool->base.dio));
1535 pool->base.dio = NULL;
1536 }
1537
1538 if (pool->base.oem_device != NULL) {
1539 struct dc *dc = pool->base.oem_device->ctx->dc;
1540
1541 dc->link_srv->destroy_ddc_service(&pool->base.oem_device);
1542 }
1543 }
1544
1545
dcn401_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)1546 static bool dcn401_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1547 {
1548 int i;
1549 uint32_t dwb_count = pool->res_cap->num_dwb;
1550
1551 for (i = 0; i < dwb_count; i++) {
1552 struct dcn30_dwbc *dwbc401 = kzalloc_obj(struct dcn30_dwbc);
1553
1554 if (!dwbc401) {
1555 dm_error("DC: failed to create dwbc401!\n");
1556 return false;
1557 }
1558
1559
1560 #undef REG_STRUCT
1561 #define REG_STRUCT dwbc401_regs
1562 dwbc_regs_dcn401_init(0);
1563
1564 dcn30_dwbc_construct(dwbc401, ctx,
1565 &dwbc401_regs[i],
1566 &dwbc401_shift,
1567 &dwbc401_mask,
1568 i);
1569
1570 pool->dwbc[i] = &dwbc401->base;
1571
1572 }
1573 return true;
1574 }
1575
dcn401_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)1576 static bool dcn401_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1577 {
1578 int i;
1579 uint32_t dwb_count = pool->res_cap->num_dwb;
1580
1581 for (i = 0; i < dwb_count; i++) {
1582 struct dcn30_mmhubbub *mcif_wb30 = kzalloc_obj(struct dcn30_mmhubbub);
1583
1584 if (!mcif_wb30) {
1585 dm_error("DC: failed to create mcif_wb30!\n");
1586 return false;
1587 }
1588
1589 #undef REG_STRUCT
1590 #define REG_STRUCT mcif_wb30_regs
1591 mcif_wb_regs_dcn3_init(0);
1592
1593 dcn32_mmhubbub_construct(mcif_wb30, ctx,
1594 &mcif_wb30_regs[i],
1595 &mcif_wb30_shift,
1596 &mcif_wb30_mask,
1597 i);
1598
1599 pool->mcif_wb[i] = &mcif_wb30->base;
1600 }
1601 return true;
1602 }
1603
dcn401_dsc_create(struct dc_context * ctx,uint32_t inst)1604 static struct display_stream_compressor *dcn401_dsc_create(
1605 struct dc_context *ctx, uint32_t inst)
1606 {
1607 struct dcn401_dsc *dsc =
1608 kzalloc_obj(struct dcn401_dsc);
1609
1610 if (!dsc) {
1611 BREAK_TO_DEBUGGER();
1612 return NULL;
1613 }
1614
1615 #undef REG_STRUCT
1616 #define REG_STRUCT dsc_regs
1617 dsc_regs_init(0),
1618 dsc_regs_init(1),
1619 dsc_regs_init(2),
1620 dsc_regs_init(3);
1621
1622 dsc401_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1623 dsc401_set_fgcg(dsc,
1624 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);
1625
1626 //dsc->max_image_width = 6016;
1627 dsc->max_image_width = 5760;
1628
1629 return &dsc->base;
1630 }
1631
dcn401_destroy_resource_pool(struct resource_pool ** pool)1632 static void dcn401_destroy_resource_pool(struct resource_pool **pool)
1633 {
1634 struct dcn401_resource_pool *dcn401_pool = TO_DCN401_RES_POOL(*pool);
1635
1636 dcn401_resource_destruct(dcn401_pool);
1637 kfree(dcn401_pool);
1638 *pool = NULL;
1639 }
1640
1641 static struct dc_cap_funcs cap_funcs = {
1642 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap,
1643 .get_subvp_en = dcn32_subvp_in_use,
1644 };
1645
dcn401_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)1646 static void dcn401_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1647 {
1648 /* re-calculate the available MALL size if required */
1649 if (bw_params->num_channels > 0) {
1650 dc->caps.max_cab_allocation_bytes = dcn401_calc_num_avail_chans_for_mall(
1651 dc, bw_params->num_channels) *
1652 dc->caps.mall_size_per_mem_channel * 1024 * 1024;
1653 dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes;
1654 }
1655
1656 DC_FP_START();
1657
1658 if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2)
1659 dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2);
1660
1661 if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2_dc_power_source)
1662 dml2_reinit(dc, &dc->dml2_dc_power_options, &dc->current_state->bw_ctx.dml2_dc_power_source);
1663
1664 DC_FP_END();
1665 }
1666
dcn401_patch_unknown_plane_state(struct dc_plane_state * plane_state)1667 enum dc_status dcn401_patch_unknown_plane_state(struct dc_plane_state *plane_state)
1668 {
1669 plane_state->tiling_info.gfxversion = DcGfxAddr3;
1670 plane_state->tiling_info.gfx_addr3.swizzle = DC_ADDR3_SW_64KB_2D;
1671 return DC_OK;
1672 }
1673
dcn401_validate_bandwidth(struct dc * dc,struct dc_state * context,enum dc_validate_mode validate_mode)1674 enum dc_status dcn401_validate_bandwidth(struct dc *dc,
1675 struct dc_state *context,
1676 enum dc_validate_mode validate_mode)
1677 {
1678 unsigned int i;
1679 enum dc_status status = DC_OK;
1680 const struct dc_stream_state *stream;
1681
1682 /* reset cursor limitations on subvp */
1683 for (i = 0; i < context->stream_count; i++) {
1684 stream = context->streams[i];
1685
1686 if (dc_state_can_clear_stream_cursor_subvp_limit(stream, context)) {
1687 dc_state_set_stream_cursor_subvp_limit(stream, context, false);
1688 }
1689 }
1690
1691 if (dc->debug.using_dml2)
1692 status = dml2_validate(dc, context,
1693 context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,
1694 validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1695
1696 if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING && status == DC_OK && dc_state_is_subvp_in_use(context)) {
1697 /* check new stream configuration still supports cursor if subvp used */
1698 for (i = 0; i < context->stream_count; i++) {
1699 stream = context->streams[i];
1700
1701 if (dc_state_get_stream_subvp_type(context, stream) != SUBVP_PHANTOM &&
1702 stream->cursor_position.enable &&
1703 !dc_stream_check_cursor_attributes(stream, context, &stream->cursor_attributes)) {
1704 /* hw cursor cannot be supported with subvp active, so disable subvp for now */
1705 dc_state_set_stream_cursor_subvp_limit(stream, context, true);
1706 status = DC_FAIL_HW_CURSOR_SUPPORT;
1707 }
1708 }
1709 }
1710
1711 if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING && status == DC_FAIL_HW_CURSOR_SUPPORT) {
1712 /* attempt to validate again with subvp disabled due to cursor */
1713 if (dc->debug.using_dml2)
1714 status = dml2_validate(dc, context,
1715 context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,
1716 validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1717 }
1718
1719 return status;
1720 }
1721
dcn401_prepare_mcache_programming(struct dc * dc,struct dc_state * context)1722 void dcn401_prepare_mcache_programming(struct dc *dc,
1723 struct dc_state *context)
1724 {
1725 if (dc->debug.using_dml21)
1726 dml2_prepare_mcache_programming(dc, context,
1727 context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2);
1728 }
1729
dcn401_build_pipe_pix_clk_params(struct pipe_ctx * pipe_ctx)1730 static void dcn401_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx)
1731 {
1732 const struct dc_stream_state *stream = pipe_ctx->stream;
1733 struct dc_link *link = stream->link;
1734 struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;
1735 struct pixel_clk_params *pixel_clk_params = &pipe_ctx->stream_res.pix_clk_params;
1736
1737 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
1738
1739 if (pipe_ctx->dsc_padding_params.dsc_hactive_padding != 0)
1740 pixel_clk_params->requested_pix_clk_100hz = pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz;
1741
1742 if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment)
1743 link_enc = link_enc_cfg_get_link_enc(link);
1744 if (link_enc)
1745 pixel_clk_params->encoder_object_id = link_enc->id;
1746
1747 pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1748 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1749 /* TODO: un-hardcode*/
1750
1751 /* TODO - DP2.0 HW: calculate requested_sym_clk for UHBR rates */
1752
1753 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
1754 LINK_RATE_REF_FREQ_IN_KHZ;
1755 pixel_clk_params->flags.ENABLE_SS = 0;
1756 pixel_clk_params->color_depth =
1757 stream->timing.display_color_depth;
1758 pixel_clk_params->flags.DISPLAY_BLANKED = 1;
1759 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
1760
1761 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1762 pixel_clk_params->color_depth = COLOR_DEPTH_888;
1763
1764 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1765 pixel_clk_params->requested_pix_clk_100hz *= 2;
1766 if (dc_is_tmds_signal(stream->signal) &&
1767 stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1768 pixel_clk_params->requested_pix_clk_100hz /= 2;
1769
1770 pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1771 pipe_ctx->clock_source,
1772 &pipe_ctx->stream_res.pix_clk_params,
1773 &pipe_ctx->pll_settings);
1774
1775 pixel_clk_params->dio_se_pix_per_cycle = 1;
1776 if (dc_is_tmds_signal(stream->signal) &&
1777 stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
1778 pixel_clk_params->dio_se_pix_per_cycle = 2;
1779 } else if (dc_is_dp_signal(stream->signal)) {
1780 /* round up to nearest power of 2, or max at 8 pixels per cycle */
1781 if (pixel_clk_params->requested_pix_clk_100hz > 4 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) {
1782 pixel_clk_params->dio_se_pix_per_cycle = 8;
1783 } else if (pixel_clk_params->requested_pix_clk_100hz > 2 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) {
1784 pixel_clk_params->dio_se_pix_per_cycle = 4;
1785 } else if (pixel_clk_params->requested_pix_clk_100hz > stream->ctx->dc->clk_mgr->dprefclk_khz * 10) {
1786 pixel_clk_params->dio_se_pix_per_cycle = 2;
1787 } else {
1788 pixel_clk_params->dio_se_pix_per_cycle = 1;
1789 }
1790 }
1791 }
1792
dcn401_get_power_profile(const struct dc_state * context)1793 static int dcn401_get_power_profile(const struct dc_state *context)
1794 {
1795 int uclk_mhz = context->bw_ctx.bw.dcn.clk.dramclk_khz / 1000;
1796 int dpm_level = 0;
1797
1798 for (int i = 0; i < context->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; i++) {
1799 if (context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz == 0 ||
1800 uclk_mhz < context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz)
1801 break;
1802 if (uclk_mhz > context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz)
1803 dpm_level++;
1804 }
1805
1806 return dpm_level;
1807 }
1808
dcn401_get_vstartup_for_pipe(struct pipe_ctx * pipe_ctx)1809 unsigned int dcn401_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx)
1810 {
1811 return pipe_ctx->global_sync.dcn4x.vstartup_lines;
1812 }
1813
1814 static struct resource_funcs dcn401_res_pool_funcs = {
1815 .destroy = dcn401_destroy_resource_pool,
1816 .link_enc_create = dcn401_link_encoder_create,
1817 .link_enc_create_minimal = NULL,
1818 .panel_cntl_create = dcn32_panel_cntl_create,
1819 .validate_bandwidth = dcn401_validate_bandwidth,
1820 .calculate_wm_and_dlg = NULL,
1821 .populate_dml_pipes = NULL,
1822 .acquire_free_pipe_as_secondary_dpp_pipe = dcn32_acquire_free_pipe_as_secondary_dpp_pipe,
1823 .acquire_free_pipe_as_secondary_opp_head = dcn32_acquire_free_pipe_as_secondary_opp_head,
1824 .release_pipe = dcn20_release_pipe,
1825 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1826 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1827 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1828 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1829 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1830 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1831 .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut,
1832 .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut,
1833 .update_bw_bounding_box = dcn401_update_bw_bounding_box,
1834 .patch_unknown_plane_state = dcn401_patch_unknown_plane_state,
1835 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
1836 .add_phantom_pipes = dcn32_add_phantom_pipes,
1837 .prepare_mcache_programming = dcn401_prepare_mcache_programming,
1838 .build_pipe_pix_clk_params = dcn401_build_pipe_pix_clk_params,
1839 .calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes,
1840 .get_power_profile = dcn401_get_power_profile,
1841 .get_vstartup_for_pipe = dcn401_get_vstartup_for_pipe,
1842 .get_max_hw_cursor_size = dcn32_get_max_hw_cursor_size
1843 };
1844
read_pipe_fuses(struct dc_context * ctx)1845 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1846 {
1847 uint32_t value = REG_READ(CC_DC_PIPE_DIS);
1848 /* DCN401 support max 4 pipes */
1849 value = value & 0xf;
1850 return value;
1851 }
1852
1853
dcn401_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn401_resource_pool * pool)1854 static bool dcn401_resource_construct(
1855 uint8_t num_virtual_links,
1856 struct dc *dc,
1857 struct dcn401_resource_pool *pool)
1858 {
1859 int i, j;
1860 struct dc_context *ctx = dc->ctx;
1861 struct irq_service_init_data init_data;
1862 struct ddc_service_init_data ddc_init_data = {0};
1863 uint32_t pipe_fuses = 0;
1864 uint32_t num_pipes = 4;
1865
1866 #undef REG_STRUCT
1867 #define REG_STRUCT bios_regs
1868 bios_regs_init();
1869
1870 #undef REG_STRUCT
1871 #define REG_STRUCT clk_src_regs
1872 clk_src_regs_init(0, A),
1873 clk_src_regs_init(1, B),
1874 clk_src_regs_init(2, C),
1875 clk_src_regs_init(3, D);
1876
1877 #undef REG_STRUCT
1878 #define REG_STRUCT abm_regs
1879 abm_regs_init(0),
1880 abm_regs_init(1),
1881 abm_regs_init(2),
1882 abm_regs_init(3);
1883
1884 #undef REG_STRUCT
1885 #define REG_STRUCT dccg_regs
1886 dccg_regs_init();
1887
1888 ctx->dc_bios->regs = &bios_regs;
1889
1890 pool->base.res_cap = &res_cap_dcn4_01;
1891
1892 /* max number of pipes for ASIC before checking for pipe fuses */
1893 num_pipes = pool->base.res_cap->num_timing_generator;
1894 pipe_fuses = read_pipe_fuses(ctx);
1895
1896 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++)
1897 if (pipe_fuses & 1 << i)
1898 num_pipes--;
1899
1900 if (pipe_fuses & 1)
1901 ASSERT(0); //Unexpected - Pipe 0 should always be fully functional!
1902
1903 if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK)
1904 ASSERT(0); //Entire DCN is harvested!
1905
1906 pool->base.funcs = &dcn401_res_pool_funcs;
1907
1908 /*************************************************
1909 * Resource + asic cap harcoding *
1910 *************************************************/
1911 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1912 pool->base.timing_generator_count = num_pipes;
1913 pool->base.pipe_count = num_pipes;
1914 pool->base.mpcc_count = num_pipes;
1915 dc->caps.max_downscale_ratio = 600;
1916 dc->caps.i2c_speed_in_khz = 95;
1917 dc->caps.i2c_speed_in_khz_hdcp = 95; /*1.4 w/a applied by default*/
1918 /* used to set cursor pitch, so must be aligned to power of 2 (HW actually supported 78x78) */
1919 dc->caps.max_cursor_size = 64;
1920 dc->caps.max_buffered_cursor_size = 64;
1921 dc->caps.cursor_not_scaled = true;
1922 dc->caps.min_horizontal_blanking_period = 80;
1923 dc->caps.dmdata_alloc_size = 2048;
1924 dc->caps.mall_size_per_mem_channel = 4;
1925 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
1926 dc->caps.cache_line_size = 64;
1927 dc->caps.cache_num_ways = 16;
1928
1929 /* Calculate the available MALL space */
1930 dc->caps.max_cab_allocation_bytes = dcn401_calc_num_avail_chans_for_mall(
1931 dc, dc->ctx->dc_bios->vram_info.num_chans) *
1932 dc->caps.mall_size_per_mem_channel * 1024 * 1024;
1933 dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes;
1934
1935 dc->caps.subvp_fw_processing_delay_us = 15;
1936 dc->caps.subvp_drr_max_vblank_margin_us = 40;
1937 dc->caps.subvp_prefetch_end_to_mall_start_us = 15;
1938 dc->caps.subvp_swath_height_margin_lines = 16;
1939 dc->caps.subvp_pstate_allow_width_us = 20;
1940 dc->caps.subvp_vertical_int_margin_us = 30;
1941 dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin
1942
1943 dc->caps.max_slave_planes = 3;
1944 dc->caps.max_slave_yuv_planes = 3;
1945 dc->caps.max_slave_rgb_planes = 3;
1946 dc->caps.post_blend_color_processing = true;
1947 dc->caps.force_dp_tps4_for_cp2520 = true;
1948 dc->caps.dp_hpo = true;
1949 dc->caps.dp_hdmi21_pcon_support = true;
1950 dc->caps.edp_dsc_support = true;
1951 dc->caps.extended_aux_timeout_support = true;
1952 dc->caps.dmcub_support = true;
1953 dc->caps.max_v_total = (1 << 15) - 1;
1954 dc->caps.vtotal_limited_by_fp2 = true;
1955
1956 if (ASICREV_IS_GC_12_0_1_A0(dc->ctx->asic_id.hw_internal_rev))
1957 dc->caps.dcc_plane_width_limit = 7680;
1958
1959 /* Color pipeline capabilities */
1960 dc->caps.color.dpp.dcn_arch = 1;
1961 dc->caps.color.dpp.input_lut_shared = 0;
1962 dc->caps.color.dpp.icsc = 1;
1963 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1964 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1965 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1966 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1967 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1968 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1969 dc->caps.color.dpp.post_csc = 1;
1970 dc->caps.color.dpp.gamma_corr = 1;
1971 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1972
1973 dc->caps.color.dpp.hw_3d_lut = 0;
1974 dc->caps.color.dpp.ogam_ram = 0;
1975 // no OGAM ROM on DCN2 and later ASICs
1976 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1977 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1978 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1979 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1980 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1981 dc->caps.color.dpp.ocsc = 0;
1982
1983 dc->caps.color.mpc.gamut_remap = 1;
1984 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC
1985 dc->caps.color.mpc.ogam_ram = 1;
1986 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1987 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1988 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1989 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1990 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1991 dc->caps.color.mpc.ocsc = 1;
1992 dc->caps.color.mpc.preblend = true;
1993 dc->config.use_spl = true;
1994 dc->config.prefer_easf = true;
1995
1996 dc->config.dcn_sharpness_range.sdr_rgb_min = 0;
1997 dc->config.dcn_sharpness_range.sdr_rgb_max = 1750;
1998 dc->config.dcn_sharpness_range.sdr_rgb_mid = 750;
1999 dc->config.dcn_sharpness_range.sdr_yuv_min = 0;
2000 dc->config.dcn_sharpness_range.sdr_yuv_max = 3500;
2001 dc->config.dcn_sharpness_range.sdr_yuv_mid = 1500;
2002 dc->config.dcn_sharpness_range.hdr_rgb_min = 0;
2003 dc->config.dcn_sharpness_range.hdr_rgb_max = 2750;
2004 dc->config.dcn_sharpness_range.hdr_rgb_mid = 1500;
2005
2006 dc->config.dcn_override_sharpness_range.sdr_rgb_min = 0;
2007 dc->config.dcn_override_sharpness_range.sdr_rgb_max = 3250;
2008 dc->config.dcn_override_sharpness_range.sdr_rgb_mid = 1250;
2009 dc->config.dcn_override_sharpness_range.sdr_yuv_min = 0;
2010 dc->config.dcn_override_sharpness_range.sdr_yuv_max = 3500;
2011 dc->config.dcn_override_sharpness_range.sdr_yuv_mid = 1500;
2012 dc->config.dcn_override_sharpness_range.hdr_rgb_min = 0;
2013 dc->config.dcn_override_sharpness_range.hdr_rgb_max = 2750;
2014 dc->config.dcn_override_sharpness_range.hdr_rgb_mid = 1500;
2015
2016 dc->config.dc_mode_clk_limit_support = true;
2017 dc->config.enable_windowed_mpo_odm = true;
2018 dc->config.set_pipe_unlock_order = true; /* Need to ensure DET gets freed before allocating */
2019
2020 /* read VBIOS LTTPR caps */
2021 {
2022 if (ctx->dc_bios->funcs->get_lttpr_caps) {
2023 enum bp_result bp_query_result;
2024 uint8_t is_vbios_lttpr_enable = 0;
2025
2026 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
2027 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
2028 }
2029
2030 /* interop bit is implicit */
2031 {
2032 dc->caps.vbios_lttpr_aware = true;
2033 }
2034 }
2035 dc->check_config = config_defaults;
2036
2037 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2038 dc->debug = debug_defaults_drv;
2039
2040 // Init the vm_helper
2041 if (dc->vm_helper)
2042 vm_helper_init(dc->vm_helper, 16);
2043
2044 /*************************************************
2045 * Create resources *
2046 *************************************************/
2047
2048 /* Clock Sources for Pixel Clock*/
2049 pool->base.clock_sources[DCN401_CLK_SRC_PLL0] =
2050 dcn401_clock_source_create(ctx, ctx->dc_bios,
2051 CLOCK_SOURCE_COMBO_PHY_PLL0,
2052 &clk_src_regs[0], false);
2053 pool->base.clock_sources[DCN401_CLK_SRC_PLL1] =
2054 dcn401_clock_source_create(ctx, ctx->dc_bios,
2055 CLOCK_SOURCE_COMBO_PHY_PLL1,
2056 &clk_src_regs[1], false);
2057 pool->base.clock_sources[DCN401_CLK_SRC_PLL2] =
2058 dcn401_clock_source_create(ctx, ctx->dc_bios,
2059 CLOCK_SOURCE_COMBO_PHY_PLL2,
2060 &clk_src_regs[2], false);
2061 pool->base.clock_sources[DCN401_CLK_SRC_PLL3] =
2062 dcn401_clock_source_create(ctx, ctx->dc_bios,
2063 CLOCK_SOURCE_COMBO_PHY_PLL3,
2064 &clk_src_regs[3], false);
2065 // pool->base.clock_sources[DCN401_CLK_SRC_PLL4] =
2066 // dcn401_clock_source_create(ctx, ctx->dc_bios,
2067 // CLOCK_SOURCE_COMBO_PHY_PLL4,
2068 // &clk_src_regs[4], false);
2069
2070 pool->base.clk_src_count = DCN401_CLK_SRC_TOTAL;
2071
2072 /* todo: not reuse phy_pll registers */
2073 pool->base.dp_clock_source =
2074 dcn401_clock_source_create(ctx, ctx->dc_bios,
2075 CLOCK_SOURCE_ID_DP_DTO,
2076 &clk_src_regs[0], true);
2077
2078 for (i = 0; i < pool->base.clk_src_count; i++) {
2079 if (pool->base.clock_sources[i] == NULL) {
2080 dm_error("DC: failed to create clock sources!\n");
2081 BREAK_TO_DEBUGGER();
2082 goto create_fail;
2083 }
2084 }
2085
2086 /* DCCG */
2087 pool->base.dccg = dccg401_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2088 if (pool->base.dccg == NULL) {
2089 dm_error("DC: failed to create dccg!\n");
2090 BREAK_TO_DEBUGGER();
2091 goto create_fail;
2092 }
2093
2094 /* IRQ Service */
2095 init_data.ctx = dc->ctx;
2096 pool->base.irqs = dal_irq_service_dcn401_create(&init_data);
2097 if (!pool->base.irqs)
2098 goto create_fail;
2099
2100 /* HUBBUB */
2101 pool->base.hubbub = dcn401_hubbub_create(ctx);
2102 if (pool->base.hubbub == NULL) {
2103 BREAK_TO_DEBUGGER();
2104 dm_error("DC: failed to create hubbub!\n");
2105 goto create_fail;
2106 }
2107
2108 /* DIO */
2109 pool->base.dio = dcn401_dio_create(ctx);
2110 if (pool->base.dio == NULL) {
2111 BREAK_TO_DEBUGGER();
2112 dm_error("DC: failed to create dio!\n");
2113 goto create_fail;
2114 }
2115
2116 /* HUBPs, DPPs, OPPs, TGs, ABMs */
2117 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2118
2119 /* if pipe is disabled, skip instance of HW pipe,
2120 * i.e, skip ASIC register instance
2121 */
2122 if (pipe_fuses & 1 << i)
2123 continue;
2124
2125 pool->base.hubps[j] = dcn401_hubp_create(ctx, i);
2126 if (pool->base.hubps[j] == NULL) {
2127 BREAK_TO_DEBUGGER();
2128 dm_error(
2129 "DC: failed to create hubps!\n");
2130 goto create_fail;
2131 }
2132
2133 pool->base.dpps[j] = dcn401_dpp_create(ctx, i);
2134 if (pool->base.dpps[j] == NULL) {
2135 BREAK_TO_DEBUGGER();
2136 dm_error(
2137 "DC: failed to create dpps!\n");
2138 goto create_fail;
2139 }
2140
2141 pool->base.opps[j] = dcn401_opp_create(ctx, i);
2142 if (pool->base.opps[j] == NULL) {
2143 BREAK_TO_DEBUGGER();
2144 dm_error(
2145 "DC: failed to create output pixel processor!\n");
2146 goto create_fail;
2147 }
2148
2149 pool->base.timing_generators[j] = dcn401_timing_generator_create(
2150 ctx, i);
2151 if (pool->base.timing_generators[j] == NULL) {
2152 BREAK_TO_DEBUGGER();
2153 dm_error("DC: failed to create tg!\n");
2154 goto create_fail;
2155 }
2156
2157 pool->base.multiple_abms[j] = dmub_abm_create(ctx,
2158 &abm_regs[i],
2159 &abm_shift,
2160 &abm_mask);
2161 if (pool->base.multiple_abms[j] == NULL) {
2162 dm_error("DC: failed to create abm for pipe %d!\n", i);
2163 BREAK_TO_DEBUGGER();
2164 goto create_fail;
2165 }
2166
2167 /* index for resource pool arrays for next valid pipe */
2168 j++;
2169 }
2170
2171 /* PSR */
2172 pool->base.psr = dmub_psr_create(ctx);
2173 if (pool->base.psr == NULL) {
2174 dm_error("DC: failed to create psr obj!\n");
2175 BREAK_TO_DEBUGGER();
2176 goto create_fail;
2177 }
2178
2179 /* MPCCs */
2180 pool->base.mpc = dcn401_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut);
2181 if (pool->base.mpc == NULL) {
2182 BREAK_TO_DEBUGGER();
2183 dm_error("DC: failed to create mpc!\n");
2184 goto create_fail;
2185 }
2186
2187 /* DSCs */
2188 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2189 pool->base.dscs[i] = dcn401_dsc_create(ctx, i);
2190 if (pool->base.dscs[i] == NULL) {
2191 BREAK_TO_DEBUGGER();
2192 dm_error("DC: failed to create display stream compressor %d!\n", i);
2193 goto create_fail;
2194 }
2195 }
2196
2197 /* DWB */
2198 if (!dcn401_dwbc_create(ctx, &pool->base)) {
2199 BREAK_TO_DEBUGGER();
2200 dm_error("DC: failed to create dwbc!\n");
2201 goto create_fail;
2202 }
2203
2204 /* MMHUBBUB */
2205 if (!dcn401_mmhubbub_create(ctx, &pool->base)) {
2206 BREAK_TO_DEBUGGER();
2207 dm_error("DC: failed to create mcif_wb!\n");
2208 goto create_fail;
2209 }
2210
2211 /* AUX and I2C */
2212 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2213 pool->base.engines[i] = dcn401_aux_engine_create(ctx, i);
2214 if (pool->base.engines[i] == NULL) {
2215 BREAK_TO_DEBUGGER();
2216 dm_error(
2217 "DC:failed to create aux engine!!\n");
2218 goto create_fail;
2219 }
2220 pool->base.hw_i2cs[i] = dcn401_i2c_hw_create(ctx, i);
2221 if (pool->base.hw_i2cs[i] == NULL) {
2222 BREAK_TO_DEBUGGER();
2223 dm_error(
2224 "DC:failed to create hw i2c!!\n");
2225 goto create_fail;
2226 }
2227 pool->base.sw_i2cs[i] = NULL;
2228 }
2229
2230 /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2231 if (!resource_construct(num_virtual_links, dc, &pool->base,
2232 &res_create_funcs))
2233 goto create_fail;
2234
2235 /* HW Sequencer init functions and Plane caps */
2236 dcn401_hw_sequencer_init_functions(dc);
2237
2238 dc->caps.max_planes = pool->base.pipe_count;
2239
2240 for (i = 0; i < dc->caps.max_planes; ++i)
2241 dc->caps.planes[i] = plane_cap;
2242
2243 dc->caps.max_odm_combine_factor = 4;
2244
2245 dc->cap_funcs = cap_funcs;
2246
2247 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
2248 ddc_init_data.ctx = dc->ctx;
2249 ddc_init_data.link = NULL;
2250 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
2251 ddc_init_data.id.enum_id = 0;
2252 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
2253 pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);
2254 } else {
2255 pool->base.oem_device = NULL;
2256 }
2257
2258 //For now enable SDPIF_REQUEST_RATE_LIMIT on DCN4_01 when vram_info.num_chans provided
2259 if (dc->config.sdpif_request_limit_words_per_umc == 0)
2260 dc->config.sdpif_request_limit_words_per_umc = 16;
2261
2262 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;
2263 dc->dml2_options.use_native_soc_bb_construction = true;
2264 dc->dml2_options.minimize_dispclk_using_odm = true;
2265 dc->dml2_options.map_dc_pipes_with_callbacks = true;
2266 dc->dml2_options.force_tdlut_enable = true;
2267
2268 resource_init_common_dml2_callbacks(dc, &dc->dml2_options);
2269 dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;
2270 dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc;
2271 dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = pool->base.funcs->calculate_mall_ways_from_bytes;
2272
2273 dc->dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc->caps.subvp_fw_processing_delay_us;
2274 dc->dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc->caps.subvp_prefetch_end_to_mall_start_us;
2275 dc->dml2_options.svp_pstate.subvp_pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us;
2276 dc->dml2_options.svp_pstate.subvp_swath_height_margin_lines = dc->caps.subvp_swath_height_margin_lines;
2277
2278 dc->dml2_options.svp_pstate.force_disable_subvp = dc->debug.force_disable_subvp;
2279 dc->dml2_options.svp_pstate.force_enable_subvp = dc->debug.force_subvp_mclk_switch;
2280
2281 dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size;
2282 dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways;
2283 dc->dml2_options.mall_cfg.max_cab_allocation_bytes = dc->caps.max_cab_allocation_bytes;
2284 dc->dml2_options.mall_cfg.mblk_height_4bpe_pixels = DCN3_2_MBLK_HEIGHT_4BPE;
2285 dc->dml2_options.mall_cfg.mblk_height_8bpe_pixels = DCN3_2_MBLK_HEIGHT_8BPE;
2286 dc->dml2_options.mall_cfg.mblk_size_bytes = DCN3_2_MALL_MBLK_SIZE_BYTES;
2287 dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH;
2288
2289 dc->dml2_options.max_segments_per_hubp = 20;
2290 dc->dml2_options.det_segment_size = DCN4_01_CRB_SEGMENT_SIZE_KB;
2291
2292 /* SPL */
2293 dc->caps.scl_caps.sharpener_support = true;
2294
2295 /* init DC limited DML2 options */
2296 memcpy(&dc->dml2_dc_power_options, &dc->dml2_options, sizeof(struct dml2_configuration_options));
2297 dc->dml2_dc_power_options.use_clock_dc_limits = true;
2298
2299 return true;
2300
2301 create_fail:
2302
2303 dcn401_resource_destruct(pool);
2304
2305 return false;
2306 }
2307
dcn401_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2308 struct resource_pool *dcn401_create_resource_pool(
2309 const struct dc_init_data *init_data,
2310 struct dc *dc)
2311 {
2312 struct dcn401_resource_pool *pool =
2313 kzalloc_obj(struct dcn401_resource_pool);
2314
2315 if (!pool)
2316 return NULL;
2317
2318 if (dcn401_resource_construct(init_data->num_virtual_links, dc, pool))
2319 return &pool->base;
2320
2321 BREAK_TO_DEBUGGER();
2322 kfree(pool);
2323 return NULL;
2324 }
2325