1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * dim2.c - MediaLB DIM2 Hardware Dependent Module
4 *
5 * Copyright (C) 2015-2016, Microchip Technology Germany II GmbH & Co. KG
6 */
7
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10 #include <linux/module.h>
11 #include <linux/printk.h>
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/platform_device.h>
15 #include <linux/interrupt.h>
16 #include <linux/slab.h>
17 #include <linux/io.h>
18 #include <linux/clk.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/sched.h>
21 #include <linux/kthread.h>
22 #include <linux/most.h>
23 #include <linux/of.h>
24 #include "hal.h"
25 #include "errors.h"
26 #include "sysfs.h"
27
28 #define DMA_CHANNELS (32 - 1) /* channel 0 is a system channel */
29
30 #define MAX_BUFFERS_PACKET 32
31 #define MAX_BUFFERS_STREAMING 32
32 #define MAX_BUF_SIZE_PACKET 2048
33 #define MAX_BUF_SIZE_STREAMING (8 * 1024)
34
35 /*
36 * The parameter representing the number of frames per sub-buffer for
37 * synchronous channels. Valid values: [0 .. 6].
38 *
39 * The values 0, 1, 2, 3, 4, 5, 6 represent corresponding number of frames per
40 * sub-buffer 1, 2, 4, 8, 16, 32, 64.
41 */
42 static u8 fcnt = 4; /* (1 << fcnt) frames per subbuffer */
43 module_param(fcnt, byte, 0000);
44 MODULE_PARM_DESC(fcnt, "Num of frames per sub-buffer for sync channels as a power of 2");
45
46 static DEFINE_SPINLOCK(dim_lock);
47
48 /**
49 * struct hdm_channel - private structure to keep channel specific data
50 * @name: channel name
51 * @is_initialized: identifier to know whether the channel is initialized
52 * @ch: HAL specific channel data
53 * @reset_dbr_size: reset DBR data buffer size
54 * @pending_list: list to keep MBO's before starting transfer
55 * @started_list: list to keep MBO's after starting transfer
56 * @direction: channel direction (TX or RX)
57 * @data_type: channel data type
58 */
59 struct hdm_channel {
60 char name[sizeof "caNNN"];
61 bool is_initialized;
62 struct dim_channel ch;
63 u16 *reset_dbr_size;
64 struct list_head pending_list; /* before dim_enqueue_buffer() */
65 struct list_head started_list; /* after dim_enqueue_buffer() */
66 enum most_channel_direction direction;
67 enum most_channel_data_type data_type;
68 };
69
70 /*
71 * struct dim2_hdm - private structure to keep interface specific data
72 * @hch: an array of channel specific data
73 * @most_iface: most interface structure
74 * @capabilities: an array of channel capability data
75 * @io_base: I/O register base address
76 * @netinfo_task: thread to deliver network status
77 * @netinfo_waitq: waitq for the thread to sleep
78 * @deliver_netinfo: to identify whether network status received
79 * @mac_addrs: INIC mac address
80 * @link_state: network link state
81 * @atx_idx: index of async tx channel
82 */
83 struct dim2_hdm {
84 struct device dev;
85 struct hdm_channel hch[DMA_CHANNELS];
86 struct most_channel_capability capabilities[DMA_CHANNELS];
87 struct most_interface most_iface;
88 char name[16 + sizeof "dim2-"];
89 void __iomem *io_base;
90 u8 clk_speed;
91 struct clk *clk;
92 struct clk *clk_pll;
93 struct task_struct *netinfo_task;
94 wait_queue_head_t netinfo_waitq;
95 int deliver_netinfo;
96 unsigned char mac_addrs[6];
97 unsigned char link_state;
98 int atx_idx;
99 struct medialb_bus bus;
100 void (*on_netinfo)(struct most_interface *most_iface,
101 unsigned char link_state, unsigned char *addrs);
102 void (*disable_platform)(struct platform_device *pdev);
103 };
104
105 struct dim2_platform_data {
106 int (*enable)(struct platform_device *pdev);
107 void (*disable)(struct platform_device *pdev);
108 u8 fcnt;
109 };
110
iface_to_hdm(struct most_interface * iface)111 static inline struct dim2_hdm *iface_to_hdm(struct most_interface *iface)
112 {
113 return container_of(iface, struct dim2_hdm, most_iface);
114 }
115
116 /* Identify a network status message */
packet_is_net_info(const u8 * p)117 static bool packet_is_net_info(const u8 *p)
118 {
119 return p[1] == 0x18 && p[2] == 0x05 && p[3] == 0x0C &&
120 p[13] == 0x3C && p[14] == 0x00 && p[15] == 0x0A;
121 }
122
state_show(struct device * dev,struct device_attribute * attr,char * buf)123 static ssize_t state_show(struct device *dev, struct device_attribute *attr,
124 char *buf)
125 {
126 bool state;
127 unsigned long flags;
128
129 spin_lock_irqsave(&dim_lock, flags);
130 state = dim_get_lock_state();
131 spin_unlock_irqrestore(&dim_lock, flags);
132
133 return sysfs_emit(buf, "%s\n", state ? "locked" : "");
134 }
135
136 static DEVICE_ATTR_RO(state);
137
138 static struct attribute *dim2_attrs[] = {
139 &dev_attr_state.attr,
140 NULL,
141 };
142
143 ATTRIBUTE_GROUPS(dim2);
144
145 /**
146 * dimcb_on_error - callback from HAL to report miscommunication between
147 * HDM and HAL
148 * @error_id: Error ID
149 * @error_message: Error message. Some text in a free format
150 */
dimcb_on_error(u8 error_id,const char * error_message)151 void dimcb_on_error(u8 error_id, const char *error_message)
152 {
153 pr_err("%s: error_id - %d, error_message - %s\n", __func__, error_id,
154 error_message);
155 }
156
157 /**
158 * try_start_dim_transfer - try to transfer a buffer on a channel
159 * @hdm_ch: channel specific data
160 *
161 * Transfer a buffer from pending_list if the channel is ready
162 */
try_start_dim_transfer(struct hdm_channel * hdm_ch)163 static int try_start_dim_transfer(struct hdm_channel *hdm_ch)
164 {
165 u16 buf_size;
166 struct list_head *head = &hdm_ch->pending_list;
167 struct mbo *mbo;
168 unsigned long flags;
169 struct dim_ch_state st;
170
171 BUG_ON(!hdm_ch);
172 BUG_ON(!hdm_ch->is_initialized);
173
174 spin_lock_irqsave(&dim_lock, flags);
175 if (list_empty(head)) {
176 spin_unlock_irqrestore(&dim_lock, flags);
177 return -EAGAIN;
178 }
179
180 if (!dim_get_channel_state(&hdm_ch->ch, &st)->ready) {
181 spin_unlock_irqrestore(&dim_lock, flags);
182 return -EAGAIN;
183 }
184
185 mbo = list_first_entry(head, struct mbo, list);
186 buf_size = mbo->buffer_length;
187
188 if (dim_dbr_space(&hdm_ch->ch) < buf_size) {
189 spin_unlock_irqrestore(&dim_lock, flags);
190 return -EAGAIN;
191 }
192
193 BUG_ON(mbo->bus_address == 0);
194 if (!dim_enqueue_buffer(&hdm_ch->ch, mbo->bus_address, buf_size)) {
195 list_del(head->next);
196 spin_unlock_irqrestore(&dim_lock, flags);
197 mbo->processed_length = 0;
198 mbo->status = MBO_E_INVAL;
199 mbo->complete(mbo);
200 return -EFAULT;
201 }
202
203 list_move_tail(head->next, &hdm_ch->started_list);
204 spin_unlock_irqrestore(&dim_lock, flags);
205
206 return 0;
207 }
208
209 /**
210 * deliver_netinfo_thread - thread to deliver network status to mostcore
211 * @data: private data
212 *
213 * Wait for network status and deliver it to mostcore once it is received
214 */
deliver_netinfo_thread(void * data)215 static int deliver_netinfo_thread(void *data)
216 {
217 struct dim2_hdm *dev = data;
218
219 while (!kthread_should_stop()) {
220 wait_event_interruptible(dev->netinfo_waitq,
221 dev->deliver_netinfo ||
222 kthread_should_stop());
223
224 if (dev->deliver_netinfo) {
225 dev->deliver_netinfo--;
226 if (dev->on_netinfo) {
227 dev->on_netinfo(&dev->most_iface,
228 dev->link_state,
229 dev->mac_addrs);
230 }
231 }
232 }
233
234 return 0;
235 }
236
237 /**
238 * retrieve_netinfo - retrieve network status from received buffer
239 * @dev: private data
240 * @mbo: received MBO
241 *
242 * Parse the message in buffer and get node address, link state, MAC address.
243 * Wake up a thread to deliver this status to mostcore
244 */
retrieve_netinfo(struct dim2_hdm * dev,struct mbo * mbo)245 static void retrieve_netinfo(struct dim2_hdm *dev, struct mbo *mbo)
246 {
247 u8 *data = mbo->virt_address;
248
249 pr_info("Node Address: 0x%03x\n", (u16)data[16] << 8 | data[17]);
250 dev->link_state = data[18];
251 pr_info("NIState: %d\n", dev->link_state);
252 memcpy(dev->mac_addrs, data + 19, 6);
253 dev->deliver_netinfo++;
254 wake_up_interruptible(&dev->netinfo_waitq);
255 }
256
257 /**
258 * service_done_flag - handle completed buffers
259 * @dev: private data
260 * @ch_idx: channel index
261 *
262 * Return back the completed buffers to mostcore, using completion callback
263 */
service_done_flag(struct dim2_hdm * dev,int ch_idx)264 static void service_done_flag(struct dim2_hdm *dev, int ch_idx)
265 {
266 struct hdm_channel *hdm_ch = dev->hch + ch_idx;
267 struct dim_ch_state st;
268 struct list_head *head;
269 struct mbo *mbo;
270 int done_buffers;
271 unsigned long flags;
272 u8 *data;
273
274 BUG_ON(!hdm_ch);
275 BUG_ON(!hdm_ch->is_initialized);
276
277 spin_lock_irqsave(&dim_lock, flags);
278
279 done_buffers = dim_get_channel_state(&hdm_ch->ch, &st)->done_buffers;
280 if (!done_buffers) {
281 spin_unlock_irqrestore(&dim_lock, flags);
282 return;
283 }
284
285 if (!dim_detach_buffers(&hdm_ch->ch, done_buffers)) {
286 spin_unlock_irqrestore(&dim_lock, flags);
287 return;
288 }
289 spin_unlock_irqrestore(&dim_lock, flags);
290
291 head = &hdm_ch->started_list;
292
293 while (done_buffers) {
294 spin_lock_irqsave(&dim_lock, flags);
295 if (list_empty(head)) {
296 spin_unlock_irqrestore(&dim_lock, flags);
297 pr_crit("hard error: started_mbo list is empty whereas DIM2 has sent buffers\n");
298 break;
299 }
300
301 mbo = list_first_entry(head, struct mbo, list);
302 list_del(head->next);
303 spin_unlock_irqrestore(&dim_lock, flags);
304
305 data = mbo->virt_address;
306
307 if (hdm_ch->data_type == MOST_CH_ASYNC &&
308 hdm_ch->direction == MOST_CH_RX &&
309 packet_is_net_info(data)) {
310 retrieve_netinfo(dev, mbo);
311
312 spin_lock_irqsave(&dim_lock, flags);
313 list_add_tail(&mbo->list, &hdm_ch->pending_list);
314 spin_unlock_irqrestore(&dim_lock, flags);
315 } else {
316 if (hdm_ch->data_type == MOST_CH_CONTROL ||
317 hdm_ch->data_type == MOST_CH_ASYNC) {
318 u32 const data_size =
319 (u32)data[0] * 256 + data[1] + 2;
320
321 mbo->processed_length =
322 min_t(u32, data_size,
323 mbo->buffer_length);
324 } else {
325 mbo->processed_length = mbo->buffer_length;
326 }
327 mbo->status = MBO_SUCCESS;
328 mbo->complete(mbo);
329 }
330
331 done_buffers--;
332 }
333 }
334
get_active_channels(struct dim2_hdm * dev,struct dim_channel ** buffer)335 static struct dim_channel **get_active_channels(struct dim2_hdm *dev,
336 struct dim_channel **buffer)
337 {
338 int idx = 0;
339 int ch_idx;
340
341 for (ch_idx = 0; ch_idx < DMA_CHANNELS; ch_idx++) {
342 if (dev->hch[ch_idx].is_initialized)
343 buffer[idx++] = &dev->hch[ch_idx].ch;
344 }
345 buffer[idx++] = NULL;
346
347 return buffer;
348 }
349
dim2_mlb_isr(int irq,void * _dev)350 static irqreturn_t dim2_mlb_isr(int irq, void *_dev)
351 {
352 struct dim2_hdm *dev = _dev;
353 unsigned long flags;
354
355 spin_lock_irqsave(&dim_lock, flags);
356 dim_service_mlb_int_irq();
357 spin_unlock_irqrestore(&dim_lock, flags);
358
359 if (dev->atx_idx >= 0 && dev->hch[dev->atx_idx].is_initialized)
360 while (!try_start_dim_transfer(dev->hch + dev->atx_idx))
361 continue;
362
363 return IRQ_HANDLED;
364 }
365
dim2_task_irq(int irq,void * _dev)366 static irqreturn_t dim2_task_irq(int irq, void *_dev)
367 {
368 struct dim2_hdm *dev = _dev;
369 unsigned long flags;
370 int ch_idx;
371
372 for (ch_idx = 0; ch_idx < DMA_CHANNELS; ch_idx++) {
373 if (!dev->hch[ch_idx].is_initialized)
374 continue;
375
376 spin_lock_irqsave(&dim_lock, flags);
377 dim_service_channel(&dev->hch[ch_idx].ch);
378 spin_unlock_irqrestore(&dim_lock, flags);
379
380 service_done_flag(dev, ch_idx);
381 while (!try_start_dim_transfer(dev->hch + ch_idx))
382 continue;
383 }
384
385 return IRQ_HANDLED;
386 }
387
388 /**
389 * dim2_ahb_isr - interrupt service routine
390 * @irq: irq number
391 * @_dev: private data
392 *
393 * Acknowledge the interrupt and service each initialized channel,
394 * if needed, in task context.
395 */
dim2_ahb_isr(int irq,void * _dev)396 static irqreturn_t dim2_ahb_isr(int irq, void *_dev)
397 {
398 struct dim2_hdm *dev = _dev;
399 struct dim_channel *buffer[DMA_CHANNELS + 1];
400 unsigned long flags;
401
402 spin_lock_irqsave(&dim_lock, flags);
403 dim_service_ahb_int_irq(get_active_channels(dev, buffer));
404 spin_unlock_irqrestore(&dim_lock, flags);
405
406 return IRQ_WAKE_THREAD;
407 }
408
409 /**
410 * complete_all_mbos - complete MBO's in a list
411 * @head: list head
412 *
413 * Delete all the entries in list and return back MBO's to mostcore using
414 * completion call back.
415 */
complete_all_mbos(struct list_head * head)416 static void complete_all_mbos(struct list_head *head)
417 {
418 unsigned long flags;
419 struct mbo *mbo;
420
421 for (;;) {
422 spin_lock_irqsave(&dim_lock, flags);
423 if (list_empty(head)) {
424 spin_unlock_irqrestore(&dim_lock, flags);
425 break;
426 }
427
428 mbo = list_first_entry(head, struct mbo, list);
429 list_del(head->next);
430 spin_unlock_irqrestore(&dim_lock, flags);
431
432 mbo->processed_length = 0;
433 mbo->status = MBO_E_CLOSE;
434 mbo->complete(mbo);
435 }
436 }
437
438 /**
439 * configure_channel - initialize a channel
440 * @most_iface: interface the channel belongs to
441 * @ch_idx: channel index to be configured
442 * @ccfg: structure that holds the configuration information
443 *
444 * Receives configuration information from mostcore and initialize
445 * the corresponding channel. Return 0 on success, negative on failure.
446 */
configure_channel(struct most_interface * most_iface,int ch_idx,struct most_channel_config * ccfg)447 static int configure_channel(struct most_interface *most_iface, int ch_idx,
448 struct most_channel_config *ccfg)
449 {
450 struct dim2_hdm *dev = iface_to_hdm(most_iface);
451 bool const is_tx = ccfg->direction == MOST_CH_TX;
452 u16 const sub_size = ccfg->subbuffer_size;
453 u16 const buf_size = ccfg->buffer_size;
454 u16 new_size;
455 unsigned long flags;
456 u8 hal_ret;
457 int const ch_addr = ch_idx * 2 + 2;
458 struct hdm_channel *const hdm_ch = dev->hch + ch_idx;
459
460 BUG_ON(ch_idx < 0 || ch_idx >= DMA_CHANNELS);
461
462 if (hdm_ch->is_initialized)
463 return -EPERM;
464
465 /* do not reset if the property was set by user, see poison_channel */
466 hdm_ch->reset_dbr_size = ccfg->dbr_size ? NULL : &ccfg->dbr_size;
467
468 /* zero value is default dbr_size, see dim2 hal */
469 hdm_ch->ch.dbr_size = ccfg->dbr_size;
470
471 switch (ccfg->data_type) {
472 case MOST_CH_CONTROL:
473 new_size = dim_norm_ctrl_async_buffer_size(buf_size);
474 if (new_size == 0) {
475 pr_err("%s: too small buffer size\n", hdm_ch->name);
476 return -EINVAL;
477 }
478 ccfg->buffer_size = new_size;
479 if (new_size != buf_size)
480 pr_warn("%s: fixed buffer size (%d -> %d)\n",
481 hdm_ch->name, buf_size, new_size);
482 spin_lock_irqsave(&dim_lock, flags);
483 hal_ret = dim_init_control(&hdm_ch->ch, is_tx, ch_addr,
484 is_tx ? new_size * 2 : new_size);
485 break;
486 case MOST_CH_ASYNC:
487 new_size = dim_norm_ctrl_async_buffer_size(buf_size);
488 if (new_size == 0) {
489 pr_err("%s: too small buffer size\n", hdm_ch->name);
490 return -EINVAL;
491 }
492 ccfg->buffer_size = new_size;
493 if (new_size != buf_size)
494 pr_warn("%s: fixed buffer size (%d -> %d)\n",
495 hdm_ch->name, buf_size, new_size);
496 spin_lock_irqsave(&dim_lock, flags);
497 hal_ret = dim_init_async(&hdm_ch->ch, is_tx, ch_addr,
498 is_tx ? new_size * 2 : new_size);
499 break;
500 case MOST_CH_ISOC:
501 new_size = dim_norm_isoc_buffer_size(buf_size, sub_size);
502 if (new_size == 0) {
503 pr_err("%s: invalid sub-buffer size or too small buffer size\n",
504 hdm_ch->name);
505 return -EINVAL;
506 }
507 ccfg->buffer_size = new_size;
508 if (new_size != buf_size)
509 pr_warn("%s: fixed buffer size (%d -> %d)\n",
510 hdm_ch->name, buf_size, new_size);
511 spin_lock_irqsave(&dim_lock, flags);
512 hal_ret = dim_init_isoc(&hdm_ch->ch, is_tx, ch_addr, sub_size);
513 break;
514 case MOST_CH_SYNC:
515 new_size = dim_norm_sync_buffer_size(buf_size, sub_size);
516 if (new_size == 0) {
517 pr_err("%s: invalid sub-buffer size or too small buffer size\n",
518 hdm_ch->name);
519 return -EINVAL;
520 }
521 ccfg->buffer_size = new_size;
522 if (new_size != buf_size)
523 pr_warn("%s: fixed buffer size (%d -> %d)\n",
524 hdm_ch->name, buf_size, new_size);
525 spin_lock_irqsave(&dim_lock, flags);
526 hal_ret = dim_init_sync(&hdm_ch->ch, is_tx, ch_addr, sub_size);
527 break;
528 default:
529 pr_err("%s: configure failed, bad channel type: %d\n",
530 hdm_ch->name, ccfg->data_type);
531 return -EINVAL;
532 }
533
534 if (hal_ret != DIM_NO_ERROR) {
535 spin_unlock_irqrestore(&dim_lock, flags);
536 pr_err("%s: configure failed (%d), type: %d, is_tx: %d\n",
537 hdm_ch->name, hal_ret, ccfg->data_type, (int)is_tx);
538 return -ENODEV;
539 }
540
541 hdm_ch->data_type = ccfg->data_type;
542 hdm_ch->direction = ccfg->direction;
543 hdm_ch->is_initialized = true;
544
545 if (hdm_ch->data_type == MOST_CH_ASYNC &&
546 hdm_ch->direction == MOST_CH_TX &&
547 dev->atx_idx < 0)
548 dev->atx_idx = ch_idx;
549
550 spin_unlock_irqrestore(&dim_lock, flags);
551 ccfg->dbr_size = hdm_ch->ch.dbr_size;
552
553 return 0;
554 }
555
556 /**
557 * enqueue - enqueue a buffer for data transfer
558 * @most_iface: intended interface
559 * @ch_idx: ID of the channel the buffer is intended for
560 * @mbo: pointer to the buffer object
561 *
562 * Push the buffer into pending_list and try to transfer one buffer from
563 * pending_list. Return 0 on success, negative on failure.
564 */
enqueue(struct most_interface * most_iface,int ch_idx,struct mbo * mbo)565 static int enqueue(struct most_interface *most_iface, int ch_idx,
566 struct mbo *mbo)
567 {
568 struct dim2_hdm *dev = iface_to_hdm(most_iface);
569 struct hdm_channel *hdm_ch = dev->hch + ch_idx;
570 unsigned long flags;
571
572 BUG_ON(ch_idx < 0 || ch_idx >= DMA_CHANNELS);
573
574 if (!hdm_ch->is_initialized)
575 return -EPERM;
576
577 if (mbo->bus_address == 0)
578 return -EFAULT;
579
580 spin_lock_irqsave(&dim_lock, flags);
581 list_add_tail(&mbo->list, &hdm_ch->pending_list);
582 spin_unlock_irqrestore(&dim_lock, flags);
583
584 (void)try_start_dim_transfer(hdm_ch);
585
586 return 0;
587 }
588
589 /**
590 * request_netinfo - triggers retrieving of network info
591 * @most_iface: pointer to the interface
592 * @ch_idx: corresponding channel ID
593 * @on_netinfo: call-back used to deliver network status to mostcore
594 *
595 * Send a command to INIC which triggers retrieving of network info by means of
596 * "Message exchange over MDP/MEP". Return 0 on success, negative on failure.
597 */
request_netinfo(struct most_interface * most_iface,int ch_idx,void (* on_netinfo)(struct most_interface *,unsigned char,unsigned char *))598 static void request_netinfo(struct most_interface *most_iface, int ch_idx,
599 void (*on_netinfo)(struct most_interface *,
600 unsigned char, unsigned char *))
601 {
602 struct dim2_hdm *dev = iface_to_hdm(most_iface);
603 struct mbo *mbo;
604 u8 *data;
605
606 dev->on_netinfo = on_netinfo;
607 if (!on_netinfo)
608 return;
609
610 if (dev->atx_idx < 0) {
611 pr_err("Async Tx Not initialized\n");
612 return;
613 }
614
615 mbo = most_get_mbo(&dev->most_iface, dev->atx_idx, NULL);
616 if (!mbo)
617 return;
618
619 mbo->buffer_length = 5;
620
621 data = mbo->virt_address;
622
623 data[0] = 0x00; /* PML High byte */
624 data[1] = 0x03; /* PML Low byte */
625 data[2] = 0x02; /* PMHL */
626 data[3] = 0x08; /* FPH */
627 data[4] = 0x40; /* FMF (FIFO cmd msg - Triggers NAOverMDP) */
628
629 most_submit_mbo(mbo);
630 }
631
632 /**
633 * poison_channel - poison buffers of a channel
634 * @most_iface: pointer to the interface the channel to be poisoned belongs to
635 * @ch_idx: corresponding channel ID
636 *
637 * Destroy a channel and complete all the buffers in both started_list &
638 * pending_list. Return 0 on success, negative on failure.
639 */
poison_channel(struct most_interface * most_iface,int ch_idx)640 static int poison_channel(struct most_interface *most_iface, int ch_idx)
641 {
642 struct dim2_hdm *dev = iface_to_hdm(most_iface);
643 struct hdm_channel *hdm_ch = dev->hch + ch_idx;
644 unsigned long flags;
645 u8 hal_ret;
646 int ret = 0;
647
648 BUG_ON(ch_idx < 0 || ch_idx >= DMA_CHANNELS);
649
650 if (!hdm_ch->is_initialized)
651 return -EPERM;
652
653 spin_lock_irqsave(&dim_lock, flags);
654 hal_ret = dim_destroy_channel(&hdm_ch->ch);
655 hdm_ch->is_initialized = false;
656 if (ch_idx == dev->atx_idx)
657 dev->atx_idx = -1;
658 spin_unlock_irqrestore(&dim_lock, flags);
659 if (hal_ret != DIM_NO_ERROR) {
660 pr_err("HAL Failed to close channel %s\n", hdm_ch->name);
661 ret = -EFAULT;
662 }
663
664 complete_all_mbos(&hdm_ch->started_list);
665 complete_all_mbos(&hdm_ch->pending_list);
666 if (hdm_ch->reset_dbr_size)
667 *hdm_ch->reset_dbr_size = 0;
668
669 return ret;
670 }
671
dma_alloc(struct mbo * mbo,u32 size)672 static void *dma_alloc(struct mbo *mbo, u32 size)
673 {
674 struct device *dev = mbo->ifp->driver_dev;
675
676 return dma_alloc_coherent(dev, size, &mbo->bus_address, GFP_KERNEL);
677 }
678
dma_free(struct mbo * mbo,u32 size)679 static void dma_free(struct mbo *mbo, u32 size)
680 {
681 struct device *dev = mbo->ifp->driver_dev;
682
683 dma_free_coherent(dev, size, mbo->virt_address, mbo->bus_address);
684 }
685
686 static const struct of_device_id dim2_of_match[];
687
688 static struct {
689 const char *clock_speed;
690 u8 clk_speed;
691 } clk_mt[] = {
692 { "256fs", CLK_256FS },
693 { "512fs", CLK_512FS },
694 { "1024fs", CLK_1024FS },
695 { "2048fs", CLK_2048FS },
696 { "3072fs", CLK_3072FS },
697 { "4096fs", CLK_4096FS },
698 { "6144fs", CLK_6144FS },
699 { "8192fs", CLK_8192FS },
700 };
701
702 /**
703 * get_dim2_clk_speed - converts string to DIM2 clock speed value
704 *
705 * @clock_speed: string in the format "{NUMBER}fs"
706 * @val: pointer to get one of the CLK_{NUMBER}FS values
707 *
708 * By success stores one of the CLK_{NUMBER}FS in the *val and returns 0,
709 * otherwise returns -EINVAL.
710 */
get_dim2_clk_speed(const char * clock_speed,u8 * val)711 static int get_dim2_clk_speed(const char *clock_speed, u8 *val)
712 {
713 int i;
714
715 for (i = 0; i < ARRAY_SIZE(clk_mt); i++) {
716 if (!strcmp(clock_speed, clk_mt[i].clock_speed)) {
717 *val = clk_mt[i].clk_speed;
718 return 0;
719 }
720 }
721 return -EINVAL;
722 }
723
dim2_release(struct device * d)724 static void dim2_release(struct device *d)
725 {
726 struct dim2_hdm *dev = container_of(d, struct dim2_hdm, dev);
727 unsigned long flags;
728
729 kthread_stop(dev->netinfo_task);
730
731 spin_lock_irqsave(&dim_lock, flags);
732 dim_shutdown();
733 spin_unlock_irqrestore(&dim_lock, flags);
734
735 if (dev->disable_platform)
736 dev->disable_platform(to_platform_device(d->parent));
737
738 kfree(dev);
739 }
740
741 /*
742 * dim2_probe - dim2 probe handler
743 * @pdev: platform device structure
744 *
745 * Register the dim2 interface with mostcore and initialize it.
746 * Return 0 on success, negative on failure.
747 */
dim2_probe(struct platform_device * pdev)748 static int dim2_probe(struct platform_device *pdev)
749 {
750 const struct dim2_platform_data *pdata;
751 const struct of_device_id *of_id;
752 const char *clock_speed;
753 struct dim2_hdm *dev;
754 struct resource *res;
755 int ret, i;
756 u8 hal_ret;
757 u8 dev_fcnt = fcnt;
758 int irq;
759
760 enum { MLB_INT_IDX, AHB0_INT_IDX };
761
762 dev = kzalloc_obj(*dev);
763 if (!dev)
764 return -ENOMEM;
765
766 dev->atx_idx = -1;
767
768 platform_set_drvdata(pdev, dev);
769
770 ret = of_property_read_string(pdev->dev.of_node,
771 "microchip,clock-speed", &clock_speed);
772 if (ret) {
773 dev_err(&pdev->dev, "missing dt property clock-speed\n");
774 goto err_free_dev;
775 }
776
777 ret = get_dim2_clk_speed(clock_speed, &dev->clk_speed);
778 if (ret) {
779 dev_err(&pdev->dev, "bad dt property clock-speed\n");
780 goto err_free_dev;
781 }
782
783 dev->io_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
784 if (IS_ERR(dev->io_base)) {
785 ret = PTR_ERR(dev->io_base);
786 goto err_free_dev;
787 }
788
789 of_id = of_match_node(dim2_of_match, pdev->dev.of_node);
790 pdata = of_id->data;
791 if (pdata) {
792 if (pdata->enable) {
793 ret = pdata->enable(pdev);
794 if (ret)
795 goto err_free_dev;
796 }
797 dev->disable_platform = pdata->disable;
798 if (pdata->fcnt)
799 dev_fcnt = pdata->fcnt;
800 }
801
802 dev_info(&pdev->dev, "sync: num of frames per sub-buffer: %u\n",
803 dev_fcnt);
804 hal_ret = dim_startup(dev->io_base, dev->clk_speed, dev_fcnt);
805 if (hal_ret != DIM_NO_ERROR) {
806 dev_err(&pdev->dev, "dim_startup failed: %d\n", hal_ret);
807 ret = -ENODEV;
808 goto err_disable_platform;
809 }
810
811 irq = platform_get_irq(pdev, AHB0_INT_IDX);
812 if (irq < 0) {
813 ret = irq;
814 goto err_shutdown_dim;
815 }
816
817 ret = devm_request_threaded_irq(&pdev->dev, irq, dim2_ahb_isr,
818 dim2_task_irq, 0, "dim2_ahb0_int", dev);
819 if (ret) {
820 dev_err(&pdev->dev, "failed to request ahb0_int irq %d\n", irq);
821 goto err_shutdown_dim;
822 }
823
824 irq = platform_get_irq(pdev, MLB_INT_IDX);
825 if (irq < 0) {
826 ret = irq;
827 goto err_shutdown_dim;
828 }
829
830 ret = devm_request_irq(&pdev->dev, irq, dim2_mlb_isr, 0,
831 "dim2_mlb_int", dev);
832 if (ret) {
833 dev_err(&pdev->dev, "failed to request mlb_int irq %d\n", irq);
834 goto err_shutdown_dim;
835 }
836
837 init_waitqueue_head(&dev->netinfo_waitq);
838 dev->deliver_netinfo = 0;
839 dev->netinfo_task = kthread_run(&deliver_netinfo_thread, dev,
840 "dim2_netinfo");
841 if (IS_ERR(dev->netinfo_task)) {
842 ret = PTR_ERR(dev->netinfo_task);
843 goto err_shutdown_dim;
844 }
845
846 for (i = 0; i < DMA_CHANNELS; i++) {
847 struct most_channel_capability *cap = dev->capabilities + i;
848 struct hdm_channel *hdm_ch = dev->hch + i;
849
850 INIT_LIST_HEAD(&hdm_ch->pending_list);
851 INIT_LIST_HEAD(&hdm_ch->started_list);
852 hdm_ch->is_initialized = false;
853 snprintf(hdm_ch->name, sizeof(hdm_ch->name), "ca%d", i * 2 + 2);
854
855 cap->name_suffix = hdm_ch->name;
856 cap->direction = MOST_CH_RX | MOST_CH_TX;
857 cap->data_type = MOST_CH_CONTROL | MOST_CH_ASYNC |
858 MOST_CH_ISOC | MOST_CH_SYNC;
859 cap->num_buffers_packet = MAX_BUFFERS_PACKET;
860 cap->buffer_size_packet = MAX_BUF_SIZE_PACKET;
861 cap->num_buffers_streaming = MAX_BUFFERS_STREAMING;
862 cap->buffer_size_streaming = MAX_BUF_SIZE_STREAMING;
863 }
864
865 {
866 const char *fmt;
867
868 if (sizeof(res->start) == sizeof(long long))
869 fmt = "dim2-%016llx";
870 else if (sizeof(res->start) == sizeof(long))
871 fmt = "dim2-%016lx";
872 else
873 fmt = "dim2-%016x";
874
875 snprintf(dev->name, sizeof(dev->name), fmt, res->start);
876 }
877
878 dev->most_iface.interface = ITYPE_MEDIALB_DIM2;
879 dev->most_iface.description = dev->name;
880 dev->most_iface.num_channels = DMA_CHANNELS;
881 dev->most_iface.channel_vector = dev->capabilities;
882 dev->most_iface.configure = configure_channel;
883 dev->most_iface.enqueue = enqueue;
884 dev->most_iface.dma_alloc = dma_alloc;
885 dev->most_iface.dma_free = dma_free;
886 dev->most_iface.poison_channel = poison_channel;
887 dev->most_iface.request_netinfo = request_netinfo;
888 dev->most_iface.driver_dev = &pdev->dev;
889 dev->most_iface.dev = &dev->dev;
890 dev->dev.init_name = dev->name;
891 dev->dev.parent = &pdev->dev;
892 dev->dev.release = dim2_release;
893
894 return most_register_interface(&dev->most_iface);
895
896 err_shutdown_dim:
897 dim_shutdown();
898 err_disable_platform:
899 if (dev->disable_platform)
900 dev->disable_platform(pdev);
901 err_free_dev:
902 kfree(dev);
903
904 return ret;
905 }
906
907 /**
908 * dim2_remove - dim2 remove handler
909 * @pdev: platform device structure
910 *
911 * Unregister the interface from mostcore
912 */
dim2_remove(struct platform_device * pdev)913 static void dim2_remove(struct platform_device *pdev)
914 {
915 struct dim2_hdm *dev = platform_get_drvdata(pdev);
916
917 most_deregister_interface(&dev->most_iface);
918 }
919
920 /* platform specific functions [[ */
921
fsl_mx6_enable(struct platform_device * pdev)922 static int fsl_mx6_enable(struct platform_device *pdev)
923 {
924 struct dim2_hdm *dev = platform_get_drvdata(pdev);
925 int ret;
926
927 dev->clk = devm_clk_get(&pdev->dev, "mlb");
928 if (IS_ERR_OR_NULL(dev->clk)) {
929 dev_err(&pdev->dev, "unable to get mlb clock\n");
930 return -EFAULT;
931 }
932
933 ret = clk_prepare_enable(dev->clk);
934 if (ret) {
935 dev_err(&pdev->dev, "%s\n", "clk_prepare_enable failed");
936 return ret;
937 }
938
939 if (dev->clk_speed >= CLK_2048FS) {
940 /* enable pll */
941 dev->clk_pll = devm_clk_get(&pdev->dev, "pll8_mlb");
942 if (IS_ERR_OR_NULL(dev->clk_pll)) {
943 dev_err(&pdev->dev, "unable to get mlb pll clock\n");
944 clk_disable_unprepare(dev->clk);
945 return -EFAULT;
946 }
947
948 writel(0x888, dev->io_base + 0x38);
949 clk_prepare_enable(dev->clk_pll);
950 }
951
952 return 0;
953 }
954
fsl_mx6_disable(struct platform_device * pdev)955 static void fsl_mx6_disable(struct platform_device *pdev)
956 {
957 struct dim2_hdm *dev = platform_get_drvdata(pdev);
958
959 if (dev->clk_speed >= CLK_2048FS)
960 clk_disable_unprepare(dev->clk_pll);
961
962 clk_disable_unprepare(dev->clk);
963 }
964
rcar_gen2_enable(struct platform_device * pdev)965 static int rcar_gen2_enable(struct platform_device *pdev)
966 {
967 struct dim2_hdm *dev = platform_get_drvdata(pdev);
968 int ret;
969
970 dev->clk = devm_clk_get(&pdev->dev, NULL);
971 if (IS_ERR(dev->clk)) {
972 dev_err(&pdev->dev, "cannot get clock\n");
973 return PTR_ERR(dev->clk);
974 }
975
976 ret = clk_prepare_enable(dev->clk);
977 if (ret) {
978 dev_err(&pdev->dev, "%s\n", "clk_prepare_enable failed");
979 return ret;
980 }
981
982 if (dev->clk_speed >= CLK_2048FS) {
983 /* enable MLP pll and LVDS drivers */
984 writel(0x03, dev->io_base + 0x600);
985 /* set bias */
986 writel(0x888, dev->io_base + 0x38);
987 } else {
988 /* PLL */
989 writel(0x04, dev->io_base + 0x600);
990 }
991
992 /* BBCR = 0b11 */
993 writel(0x03, dev->io_base + 0x500);
994 writel(0x0002FF02, dev->io_base + 0x508);
995
996 return 0;
997 }
998
rcar_gen2_disable(struct platform_device * pdev)999 static void rcar_gen2_disable(struct platform_device *pdev)
1000 {
1001 struct dim2_hdm *dev = platform_get_drvdata(pdev);
1002
1003 clk_disable_unprepare(dev->clk);
1004
1005 /* disable PLLs and LVDS drivers */
1006 writel(0x0, dev->io_base + 0x600);
1007 }
1008
rcar_gen3_enable(struct platform_device * pdev)1009 static int rcar_gen3_enable(struct platform_device *pdev)
1010 {
1011 struct dim2_hdm *dev = platform_get_drvdata(pdev);
1012 u32 enable_512fs = dev->clk_speed == CLK_512FS;
1013 int ret;
1014
1015 dev->clk = devm_clk_get(&pdev->dev, NULL);
1016 if (IS_ERR(dev->clk)) {
1017 dev_err(&pdev->dev, "cannot get clock\n");
1018 return PTR_ERR(dev->clk);
1019 }
1020
1021 ret = clk_prepare_enable(dev->clk);
1022 if (ret) {
1023 dev_err(&pdev->dev, "%s\n", "clk_prepare_enable failed");
1024 return ret;
1025 }
1026
1027 /* PLL */
1028 writel(0x04, dev->io_base + 0x600);
1029
1030 writel(enable_512fs, dev->io_base + 0x604);
1031
1032 /* BBCR = 0b11 */
1033 writel(0x03, dev->io_base + 0x500);
1034 writel(0x0002FF02, dev->io_base + 0x508);
1035
1036 return 0;
1037 }
1038
rcar_gen3_disable(struct platform_device * pdev)1039 static void rcar_gen3_disable(struct platform_device *pdev)
1040 {
1041 struct dim2_hdm *dev = platform_get_drvdata(pdev);
1042
1043 clk_disable_unprepare(dev->clk);
1044
1045 /* disable PLLs and LVDS drivers */
1046 writel(0x0, dev->io_base + 0x600);
1047 }
1048
1049 /* ]] platform specific functions */
1050
1051 enum dim2_platforms { FSL_MX6, RCAR_GEN2, RCAR_GEN3 };
1052
1053 static struct dim2_platform_data plat_data[] = {
1054 [FSL_MX6] = {
1055 .enable = fsl_mx6_enable,
1056 .disable = fsl_mx6_disable,
1057 },
1058 [RCAR_GEN2] = {
1059 .enable = rcar_gen2_enable,
1060 .disable = rcar_gen2_disable,
1061 },
1062 [RCAR_GEN3] = {
1063 .enable = rcar_gen3_enable,
1064 .disable = rcar_gen3_disable,
1065 .fcnt = 3,
1066 },
1067 };
1068
1069 static const struct of_device_id dim2_of_match[] = {
1070 {
1071 .compatible = "fsl,imx6q-mlb150",
1072 .data = plat_data + FSL_MX6
1073 },
1074 {
1075 .compatible = "renesas,mlp",
1076 .data = plat_data + RCAR_GEN2
1077 },
1078 {
1079 .compatible = "renesas,rcar-gen3-mlp",
1080 .data = plat_data + RCAR_GEN3
1081 },
1082 {
1083 .compatible = "xlnx,axi4-os62420_3pin-1.00.a",
1084 },
1085 {
1086 .compatible = "xlnx,axi4-os62420_6pin-1.00.a",
1087 },
1088 {},
1089 };
1090
1091 MODULE_DEVICE_TABLE(of, dim2_of_match);
1092
1093 static struct platform_driver dim2_driver = {
1094 .probe = dim2_probe,
1095 .remove = dim2_remove,
1096 .driver = {
1097 .name = "hdm_dim2",
1098 .of_match_table = dim2_of_match,
1099 .dev_groups = dim2_groups,
1100 },
1101 };
1102
1103 module_platform_driver(dim2_driver);
1104
1105 MODULE_AUTHOR("Andrey Shvetsov <andrey.shvetsov@k2l.de>");
1106 MODULE_DESCRIPTION("MediaLB DIM2 Hardware Dependent Module");
1107 MODULE_LICENSE("GPL");
1108