1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * jc42.c - driver for Jedec JC42.4 compliant temperature sensors
4 *
5 * Copyright (c) 2010 Ericsson AB.
6 *
7 * Derived from lm77.c by Andras BALI <drewie@freemail.hu>.
8 *
9 * JC42.4 compliant temperature sensors are typically used on memory modules.
10 */
11
12 #include <linux/bitops.h>
13 #include <linux/bitfield.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/slab.h>
17 #include <linux/jiffies.h>
18 #include <linux/i2c.h>
19 #include <linux/hwmon.h>
20 #include <linux/err.h>
21 #include <linux/regmap.h>
22
23 /* Addresses to scan */
24 static const unsigned short normal_i2c[] = {
25 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, I2C_CLIENT_END };
26
27 /* JC42 registers. All registers are 16 bit. */
28 #define JC42_REG_CAP 0x00
29 #define JC42_REG_CONFIG 0x01
30 #define JC42_REG_TEMP_UPPER 0x02
31 #define JC42_REG_TEMP_LOWER 0x03
32 #define JC42_REG_TEMP_CRITICAL 0x04
33 #define JC42_REG_TEMP 0x05
34 #define JC42_REG_MANID 0x06
35 #define JC42_REG_DEVICEID 0x07
36 #define JC42_REG_SMBUS 0x22 /* NXP and Atmel, possibly others? */
37
38 /* Status bits in temperature register */
39 #define JC42_ALARM_CRIT BIT(15)
40 #define JC42_ALARM_MAX BIT(14)
41 #define JC42_ALARM_MIN BIT(13)
42
43 /* Configuration register defines */
44 #define JC42_CFG_CRIT_ONLY BIT(2)
45 #define JC42_CFG_TCRIT_LOCK BIT(6)
46 #define JC42_CFG_EVENT_LOCK BIT(7)
47 #define JC42_CFG_SHUTDOWN BIT(8)
48 #define JC42_CFG_HYST_MASK GENMASK(10, 9)
49
50 /* Capabilities */
51 #define JC42_CAP_RANGE BIT(2)
52
53 /* Manufacturer IDs */
54 #define ADT_MANID 0x11d4 /* Analog Devices */
55 #define ATMEL_MANID 0x001f /* Atmel */
56 #define ATMEL_MANID2 0x1114 /* Atmel */
57 #define MAX_MANID 0x004d /* Maxim */
58 #define IDT_MANID 0x00b3 /* IDT */
59 #define MCP_MANID 0x0054 /* Microchip */
60 #define NXP_MANID 0x1131 /* NXP Semiconductors */
61 #define ONS_MANID 0x1b09 /* ON Semiconductor */
62 #define STM_MANID 0x104a /* ST Microelectronics */
63 #define GT_MANID 0x1c68 /* Giantec */
64 #define GT_MANID2 0x132d /* Giantec, 2nd mfg ID */
65 #define SI_MANID 0x1c85 /* Seiko Instruments */
66
67 /* SMBUS register */
68 #define SMBUS_STMOUT BIT(7) /* SMBus time-out, active low */
69
70 /* Supported chips */
71
72 /* Analog Devices */
73 #define ADT7408_DEVID 0x0801
74 #define ADT7408_DEVID_MASK 0xffff
75
76 /* Atmel */
77 #define AT30TS00_DEVID 0x8201
78 #define AT30TS00_DEVID_MASK 0xffff
79
80 #define GT34TS02_DEVID 0x3300
81 #define GT34TS02_DEVID_MASK 0xff00
82
83 #define TS3000_DEVID 0x2900 /* Also matches TSE2002 */
84 #define TS3000_DEVID_MASK 0xff00
85
86 #define TS3001_DEVID 0x3000
87 #define TS3001_DEVID_MASK 0xff00
88
89 /* Maxim */
90 #define MAX6604_DEVID 0x3e00
91 #define MAX6604_DEVID_MASK 0xffff
92
93 /* Microchip */
94 #define MCP9804_DEVID 0x0200
95 #define MCP9804_DEVID_MASK 0xfffc
96
97 #define MCP9808_DEVID 0x0400
98 #define MCP9808_DEVID_MASK 0xfffc
99
100 #define MCP98242_DEVID 0x2000
101 #define MCP98242_DEVID_MASK 0xfffc
102
103 #define MCP98243_DEVID 0x2100
104 #define MCP98243_DEVID_MASK 0xfffc
105
106 #define MCP9843_DEVID 0x0000 /* Also matches mcp9805 */
107 #define MCP9843_DEVID_MASK 0xfffe
108
109 /* NXP */
110 #define SE97_DEVID 0xa200
111 #define SE97_DEVID_MASK 0xfffc
112
113 #define SE98_DEVID 0xa100
114 #define SE98_DEVID_MASK 0xfffc
115
116 /* ON Semiconductor */
117 #define CAT6095_DEVID 0x0800 /* Also matches CAT34TS02 */
118 #define CAT6095_DEVID_MASK 0xffe0
119
120 #define CAT34TS02C_DEVID 0x0a00
121 #define CAT34TS02C_DEVID_MASK 0xfff0
122
123 /* ST Microelectronics */
124 #define STTS424_DEVID 0x0101
125 #define STTS424_DEVID_MASK 0xffff
126
127 #define STTS424E_DEVID 0x0000
128 #define STTS424E_DEVID_MASK 0xfffe
129
130 #define STTS2002_DEVID 0x0300
131 #define STTS2002_DEVID_MASK 0xffff
132
133 #define STTS3000_DEVID 0x0200
134 #define STTS3000_DEVID_MASK 0xffff
135
136 /* TSE2004 compliant sensors */
137 #define TSE2004_DEVID 0x2200
138 #define TSE2004_DEVID_MASK 0xff00
139
140 static u16 jc42_hysteresis[] = { 0, 1500, 3000, 6000 };
141
142 struct jc42_chips {
143 u16 manid;
144 u16 devid;
145 u16 devid_mask;
146 };
147
148 static struct jc42_chips jc42_chips[] = {
149 { ADT_MANID, ADT7408_DEVID, ADT7408_DEVID_MASK },
150 { ATMEL_MANID, AT30TS00_DEVID, AT30TS00_DEVID_MASK },
151 { ATMEL_MANID2, TSE2004_DEVID, TSE2004_DEVID_MASK },
152 { GT_MANID, TSE2004_DEVID, TSE2004_DEVID_MASK },
153 { GT_MANID2, GT34TS02_DEVID, GT34TS02_DEVID_MASK },
154 { IDT_MANID, TSE2004_DEVID, TSE2004_DEVID_MASK },
155 { IDT_MANID, TS3000_DEVID, TS3000_DEVID_MASK },
156 { IDT_MANID, TS3001_DEVID, TS3001_DEVID_MASK },
157 { MAX_MANID, MAX6604_DEVID, MAX6604_DEVID_MASK },
158 { MCP_MANID, MCP9804_DEVID, MCP9804_DEVID_MASK },
159 { MCP_MANID, MCP9808_DEVID, MCP9808_DEVID_MASK },
160 { MCP_MANID, MCP98242_DEVID, MCP98242_DEVID_MASK },
161 { MCP_MANID, MCP98243_DEVID, MCP98243_DEVID_MASK },
162 { MCP_MANID, TSE2004_DEVID, TSE2004_DEVID_MASK },
163 { MCP_MANID, MCP9843_DEVID, MCP9843_DEVID_MASK },
164 { NXP_MANID, SE97_DEVID, SE97_DEVID_MASK },
165 { ONS_MANID, CAT6095_DEVID, CAT6095_DEVID_MASK },
166 { ONS_MANID, CAT34TS02C_DEVID, CAT34TS02C_DEVID_MASK },
167 { ONS_MANID, TSE2004_DEVID, TSE2004_DEVID_MASK },
168 { ONS_MANID, TSE2004_DEVID, TSE2004_DEVID_MASK },
169 { NXP_MANID, SE98_DEVID, SE98_DEVID_MASK },
170 { SI_MANID, TSE2004_DEVID, TSE2004_DEVID_MASK },
171 { STM_MANID, STTS424_DEVID, STTS424_DEVID_MASK },
172 { STM_MANID, STTS424E_DEVID, STTS424E_DEVID_MASK },
173 { STM_MANID, STTS2002_DEVID, STTS2002_DEVID_MASK },
174 { STM_MANID, TSE2004_DEVID, TSE2004_DEVID_MASK },
175 { STM_MANID, STTS3000_DEVID, STTS3000_DEVID_MASK },
176 };
177
178 /* Each client has this additional data */
179 struct jc42_data {
180 struct regmap *regmap;
181 bool extended; /* true if extended range supported */
182 bool valid;
183 u16 orig_config; /* original configuration */
184 u16 config; /* current configuration */
185 };
186
187 #define JC42_TEMP_MIN_EXTENDED (-40000)
188 #define JC42_TEMP_MIN 0
189 #define JC42_TEMP_MAX 125000
190
jc42_temp_to_reg(long temp,bool extended)191 static u16 jc42_temp_to_reg(long temp, bool extended)
192 {
193 int ntemp = clamp_val(temp,
194 extended ? JC42_TEMP_MIN_EXTENDED :
195 JC42_TEMP_MIN, JC42_TEMP_MAX);
196
197 /* convert from 0.001 to 0.0625 resolution */
198 return (ntemp * 2 / 125) & 0x1fff;
199 }
200
jc42_temp_from_reg(s16 reg)201 static int jc42_temp_from_reg(s16 reg)
202 {
203 reg = sign_extend32(reg, 12);
204
205 /* convert from 0.0625 to 0.001 resolution */
206 return reg * 125 / 2;
207 }
208
jc42_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * val)209 static int jc42_read(struct device *dev, enum hwmon_sensor_types type,
210 u32 attr, int channel, long *val)
211 {
212 struct jc42_data *data = dev_get_drvdata(dev);
213 unsigned int regval;
214 int ret, temp, hyst;
215
216 switch (attr) {
217 case hwmon_temp_input:
218 ret = regmap_read(data->regmap, JC42_REG_TEMP, ®val);
219 if (ret)
220 break;
221
222 *val = jc42_temp_from_reg(regval);
223 break;
224 case hwmon_temp_min:
225 ret = regmap_read(data->regmap, JC42_REG_TEMP_LOWER, ®val);
226 if (ret)
227 break;
228
229 *val = jc42_temp_from_reg(regval);
230 break;
231 case hwmon_temp_max:
232 ret = regmap_read(data->regmap, JC42_REG_TEMP_UPPER, ®val);
233 if (ret)
234 break;
235
236 *val = jc42_temp_from_reg(regval);
237 break;
238 case hwmon_temp_crit:
239 ret = regmap_read(data->regmap, JC42_REG_TEMP_CRITICAL,
240 ®val);
241 if (ret)
242 break;
243
244 *val = jc42_temp_from_reg(regval);
245 break;
246 case hwmon_temp_max_hyst:
247 ret = regmap_read(data->regmap, JC42_REG_TEMP_UPPER, ®val);
248 if (ret)
249 break;
250
251 temp = jc42_temp_from_reg(regval);
252 hyst = jc42_hysteresis[FIELD_GET(JC42_CFG_HYST_MASK,
253 data->config)];
254 *val = temp - hyst;
255 break;
256 case hwmon_temp_crit_hyst:
257 ret = regmap_read(data->regmap, JC42_REG_TEMP_CRITICAL,
258 ®val);
259 if (ret)
260 break;
261
262 temp = jc42_temp_from_reg(regval);
263 hyst = jc42_hysteresis[FIELD_GET(JC42_CFG_HYST_MASK,
264 data->config)];
265 *val = temp - hyst;
266 break;
267 case hwmon_temp_min_alarm:
268 ret = regmap_read(data->regmap, JC42_REG_TEMP, ®val);
269 if (ret)
270 break;
271
272 *val = FIELD_GET(JC42_ALARM_MIN, regval);
273 break;
274 case hwmon_temp_max_alarm:
275 ret = regmap_read(data->regmap, JC42_REG_TEMP, ®val);
276 if (ret)
277 break;
278
279 *val = FIELD_GET(JC42_ALARM_MAX, regval);
280 break;
281 case hwmon_temp_crit_alarm:
282 ret = regmap_read(data->regmap, JC42_REG_TEMP, ®val);
283 if (ret)
284 break;
285
286 *val = FIELD_GET(JC42_ALARM_CRIT, regval);
287 break;
288 default:
289 ret = -EOPNOTSUPP;
290 break;
291 }
292
293 return ret;
294 }
295
jc42_write(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long val)296 static int jc42_write(struct device *dev, enum hwmon_sensor_types type,
297 u32 attr, int channel, long val)
298 {
299 struct jc42_data *data = dev_get_drvdata(dev);
300 unsigned int regval;
301 int diff, hyst;
302 int ret;
303
304 switch (attr) {
305 case hwmon_temp_min:
306 ret = regmap_write(data->regmap, JC42_REG_TEMP_LOWER,
307 jc42_temp_to_reg(val, data->extended));
308 break;
309 case hwmon_temp_max:
310 ret = regmap_write(data->regmap, JC42_REG_TEMP_UPPER,
311 jc42_temp_to_reg(val, data->extended));
312 break;
313 case hwmon_temp_crit:
314 ret = regmap_write(data->regmap, JC42_REG_TEMP_CRITICAL,
315 jc42_temp_to_reg(val, data->extended));
316 break;
317 case hwmon_temp_crit_hyst:
318 ret = regmap_read(data->regmap, JC42_REG_TEMP_CRITICAL,
319 ®val);
320 if (ret)
321 break;
322
323 /*
324 * JC42.4 compliant chips only support four hysteresis values.
325 * Pick best choice and go from there.
326 */
327 val = clamp_val(val, (data->extended ? JC42_TEMP_MIN_EXTENDED
328 : JC42_TEMP_MIN) - 6000,
329 JC42_TEMP_MAX);
330 diff = jc42_temp_from_reg(regval) - val;
331 hyst = 0;
332 if (diff > 0) {
333 if (diff < 2250)
334 hyst = 1; /* 1.5 degrees C */
335 else if (diff < 4500)
336 hyst = 2; /* 3.0 degrees C */
337 else
338 hyst = 3; /* 6.0 degrees C */
339 }
340 data->config = (data->config & ~JC42_CFG_HYST_MASK) |
341 FIELD_PREP(JC42_CFG_HYST_MASK, hyst);
342 ret = regmap_write(data->regmap, JC42_REG_CONFIG,
343 data->config);
344 break;
345 default:
346 ret = -EOPNOTSUPP;
347 break;
348 }
349
350 return ret;
351 }
352
jc42_is_visible(const void * _data,enum hwmon_sensor_types type,u32 attr,int channel)353 static umode_t jc42_is_visible(const void *_data, enum hwmon_sensor_types type,
354 u32 attr, int channel)
355 {
356 const struct jc42_data *data = _data;
357 unsigned int config = data->config;
358 umode_t mode = 0444;
359
360 switch (attr) {
361 case hwmon_temp_min:
362 case hwmon_temp_max:
363 if (!(config & JC42_CFG_EVENT_LOCK))
364 mode |= 0200;
365 break;
366 case hwmon_temp_crit:
367 if (!(config & JC42_CFG_TCRIT_LOCK))
368 mode |= 0200;
369 break;
370 case hwmon_temp_crit_hyst:
371 if (!(config & (JC42_CFG_EVENT_LOCK | JC42_CFG_TCRIT_LOCK)))
372 mode |= 0200;
373 break;
374 case hwmon_temp_input:
375 case hwmon_temp_max_hyst:
376 case hwmon_temp_min_alarm:
377 case hwmon_temp_max_alarm:
378 case hwmon_temp_crit_alarm:
379 break;
380 default:
381 mode = 0;
382 break;
383 }
384 return mode;
385 }
386
387 /* Return 0 if detection is successful, -ENODEV otherwise */
jc42_detect(struct i2c_client * client,struct i2c_board_info * info)388 static int jc42_detect(struct i2c_client *client, struct i2c_board_info *info)
389 {
390 struct i2c_adapter *adapter = client->adapter;
391 int i, config, cap, manid, devid;
392
393 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA |
394 I2C_FUNC_SMBUS_WORD_DATA))
395 return -ENODEV;
396
397 cap = i2c_smbus_read_word_swapped(client, JC42_REG_CAP);
398 config = i2c_smbus_read_word_swapped(client, JC42_REG_CONFIG);
399 manid = i2c_smbus_read_word_swapped(client, JC42_REG_MANID);
400 devid = i2c_smbus_read_word_swapped(client, JC42_REG_DEVICEID);
401
402 if (cap < 0 || config < 0 || manid < 0 || devid < 0)
403 return -ENODEV;
404
405 if ((cap & 0xff00) || (config & 0xf820))
406 return -ENODEV;
407
408 if ((devid & TSE2004_DEVID_MASK) == TSE2004_DEVID &&
409 (cap & 0x0062) != 0x0062)
410 return -ENODEV;
411
412 for (i = 0; i < ARRAY_SIZE(jc42_chips); i++) {
413 struct jc42_chips *chip = &jc42_chips[i];
414 if (manid == chip->manid &&
415 (devid & chip->devid_mask) == chip->devid) {
416 strscpy(info->type, "jc42", I2C_NAME_SIZE);
417 return 0;
418 }
419 }
420 return -ENODEV;
421 }
422
423 static const struct hwmon_channel_info * const jc42_info[] = {
424 HWMON_CHANNEL_INFO(chip,
425 HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL),
426 HWMON_CHANNEL_INFO(temp,
427 HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX |
428 HWMON_T_CRIT | HWMON_T_MAX_HYST |
429 HWMON_T_CRIT_HYST | HWMON_T_MIN_ALARM |
430 HWMON_T_MAX_ALARM | HWMON_T_CRIT_ALARM),
431 NULL
432 };
433
434 static const struct hwmon_ops jc42_hwmon_ops = {
435 .is_visible = jc42_is_visible,
436 .read = jc42_read,
437 .write = jc42_write,
438 };
439
440 static const struct hwmon_chip_info jc42_chip_info = {
441 .ops = &jc42_hwmon_ops,
442 .info = jc42_info,
443 };
444
jc42_readable_reg(struct device * dev,unsigned int reg)445 static bool jc42_readable_reg(struct device *dev, unsigned int reg)
446 {
447 return (reg >= JC42_REG_CAP && reg <= JC42_REG_DEVICEID) ||
448 reg == JC42_REG_SMBUS;
449 }
450
jc42_writable_reg(struct device * dev,unsigned int reg)451 static bool jc42_writable_reg(struct device *dev, unsigned int reg)
452 {
453 return (reg >= JC42_REG_CONFIG && reg <= JC42_REG_TEMP_CRITICAL) ||
454 reg == JC42_REG_SMBUS;
455 }
456
jc42_volatile_reg(struct device * dev,unsigned int reg)457 static bool jc42_volatile_reg(struct device *dev, unsigned int reg)
458 {
459 return reg == JC42_REG_CONFIG || reg == JC42_REG_TEMP;
460 }
461
462 static const struct regmap_config jc42_regmap_config = {
463 .reg_bits = 8,
464 .val_bits = 16,
465 .val_format_endian = REGMAP_ENDIAN_BIG,
466 .max_register = JC42_REG_SMBUS,
467 .writeable_reg = jc42_writable_reg,
468 .readable_reg = jc42_readable_reg,
469 .volatile_reg = jc42_volatile_reg,
470 .cache_type = REGCACHE_MAPLE,
471 };
472
jc42_probe(struct i2c_client * client)473 static int jc42_probe(struct i2c_client *client)
474 {
475 struct device *dev = &client->dev;
476 struct device *hwmon_dev;
477 unsigned int config, cap;
478 struct jc42_data *data;
479 int ret;
480
481 data = devm_kzalloc(dev, sizeof(struct jc42_data), GFP_KERNEL);
482 if (!data)
483 return -ENOMEM;
484
485 data->regmap = devm_regmap_init_i2c(client, &jc42_regmap_config);
486 if (IS_ERR(data->regmap))
487 return PTR_ERR(data->regmap);
488
489 i2c_set_clientdata(client, data);
490
491 ret = regmap_read(data->regmap, JC42_REG_CAP, &cap);
492 if (ret)
493 return ret;
494
495 data->extended = !!(cap & JC42_CAP_RANGE);
496
497 if (device_property_read_bool(dev, "smbus-timeout-disable")) {
498 /*
499 * Not all chips support this register, but from a
500 * quick read of various datasheets no chip appears
501 * incompatible with the below attempt to disable
502 * the timeout. And the whole thing is opt-in...
503 */
504 ret = regmap_set_bits(data->regmap, JC42_REG_SMBUS,
505 SMBUS_STMOUT);
506 if (ret)
507 return ret;
508 }
509
510 ret = regmap_read(data->regmap, JC42_REG_CONFIG, &config);
511 if (ret)
512 return ret;
513
514 data->orig_config = config;
515 if (config & JC42_CFG_SHUTDOWN) {
516 config &= ~JC42_CFG_SHUTDOWN;
517 regmap_write(data->regmap, JC42_REG_CONFIG, config);
518 }
519 data->config = config;
520
521 hwmon_dev = devm_hwmon_device_register_with_info(dev, "jc42",
522 data, &jc42_chip_info,
523 NULL);
524 return PTR_ERR_OR_ZERO(hwmon_dev);
525 }
526
jc42_remove(struct i2c_client * client)527 static void jc42_remove(struct i2c_client *client)
528 {
529 struct jc42_data *data = i2c_get_clientdata(client);
530
531 /* Restore original configuration except hysteresis */
532 if ((data->config & ~JC42_CFG_HYST_MASK) !=
533 (data->orig_config & ~JC42_CFG_HYST_MASK)) {
534 int config;
535
536 config = (data->orig_config & ~JC42_CFG_HYST_MASK)
537 | (data->config & JC42_CFG_HYST_MASK);
538 regmap_write(data->regmap, JC42_REG_CONFIG, config);
539 }
540 }
541
542 #ifdef CONFIG_PM
543
jc42_suspend(struct device * dev)544 static int jc42_suspend(struct device *dev)
545 {
546 struct jc42_data *data = dev_get_drvdata(dev);
547
548 data->config |= JC42_CFG_SHUTDOWN;
549 regmap_write(data->regmap, JC42_REG_CONFIG, data->config);
550
551 regcache_cache_only(data->regmap, true);
552 regcache_mark_dirty(data->regmap);
553
554 return 0;
555 }
556
jc42_resume(struct device * dev)557 static int jc42_resume(struct device *dev)
558 {
559 struct jc42_data *data = dev_get_drvdata(dev);
560
561 regcache_cache_only(data->regmap, false);
562
563 data->config &= ~JC42_CFG_SHUTDOWN;
564 regmap_write(data->regmap, JC42_REG_CONFIG, data->config);
565
566 /* Restore cached register values to hardware */
567 return regcache_sync(data->regmap);
568 }
569
570 static const struct dev_pm_ops jc42_dev_pm_ops = {
571 .suspend = jc42_suspend,
572 .resume = jc42_resume,
573 };
574
575 #define JC42_DEV_PM_OPS (&jc42_dev_pm_ops)
576 #else
577 #define JC42_DEV_PM_OPS NULL
578 #endif /* CONFIG_PM */
579
580 static const struct i2c_device_id jc42_id[] = {
581 { .name = "jc42" },
582 { }
583 };
584 MODULE_DEVICE_TABLE(i2c, jc42_id);
585
586 static const struct of_device_id jc42_of_ids[] = {
587 { .compatible = "jedec,jc-42.4-temp", },
588 { }
589 };
590 MODULE_DEVICE_TABLE(of, jc42_of_ids);
591
592 static struct i2c_driver jc42_driver = {
593 .class = I2C_CLASS_HWMON,
594 .driver = {
595 .name = "jc42",
596 .pm = JC42_DEV_PM_OPS,
597 .of_match_table = jc42_of_ids,
598 },
599 .probe = jc42_probe,
600 .remove = jc42_remove,
601 .id_table = jc42_id,
602 .detect = jc42_detect,
603 .address_list = normal_i2c,
604 };
605
606 module_i2c_driver(jc42_driver);
607
608 MODULE_AUTHOR("Guenter Roeck <linux@roeck-us.net>");
609 MODULE_DESCRIPTION("JC42 driver");
610 MODULE_LICENSE("GPL");
611