1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * cs42l42.c -- CS42L42 ALSA SoC audio driver 4 * 5 * Copyright 2016 Cirrus Logic, Inc. 6 * 7 * Author: James Schulman <james.schulman@cirrus.com> 8 * Author: Brian Austin <brian.austin@cirrus.com> 9 * Author: Michael White <michael.white@cirrus.com> 10 */ 11 12 #include <linux/cleanup.h> 13 #include <linux/module.h> 14 #include <linux/moduleparam.h> 15 #include <linux/types.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/regmap.h> 19 #include <linux/slab.h> 20 #include <linux/acpi.h> 21 #include <linux/platform_device.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/property.h> 24 #include <linux/regulator/consumer.h> 25 #include <linux/gpio/consumer.h> 26 #include <sound/core.h> 27 #include <sound/pcm.h> 28 #include <sound/pcm_params.h> 29 #include <sound/soc.h> 30 #include <sound/soc-dapm.h> 31 #include <sound/initval.h> 32 #include <sound/tlv.h> 33 #include <dt-bindings/sound/cs42l42.h> 34 35 #include "cs42l42.h" 36 #include "cirrus_legacy.h" 37 38 static const char * const cs42l42_supply_names[] = { 39 "VA", 40 "VP", 41 "VCP", 42 "VD_FILT", 43 "VL", 44 }; 45 46 static const struct reg_default cs42l42_reg_defaults[] = { 47 { CS42L42_FRZ_CTL, 0x00 }, 48 { CS42L42_SRC_CTL, 0x10 }, 49 { CS42L42_MCLK_CTL, 0x02 }, 50 { CS42L42_SFTRAMP_RATE, 0xA4 }, 51 { CS42L42_SLOW_START_ENABLE, 0x70 }, 52 { CS42L42_I2C_DEBOUNCE, 0x88 }, 53 { CS42L42_I2C_STRETCH, 0x03 }, 54 { CS42L42_I2C_TIMEOUT, 0xB7 }, 55 { CS42L42_PWR_CTL1, 0xFF }, 56 { CS42L42_PWR_CTL2, 0x84 }, 57 { CS42L42_PWR_CTL3, 0x20 }, 58 { CS42L42_RSENSE_CTL1, 0x40 }, 59 { CS42L42_RSENSE_CTL2, 0x00 }, 60 { CS42L42_OSC_SWITCH, 0x00 }, 61 { CS42L42_RSENSE_CTL3, 0x1B }, 62 { CS42L42_TSENSE_CTL, 0x1B }, 63 { CS42L42_TSRS_INT_DISABLE, 0x00 }, 64 { CS42L42_HSDET_CTL1, 0x77 }, 65 { CS42L42_HSDET_CTL2, 0x00 }, 66 { CS42L42_HS_SWITCH_CTL, 0xF3 }, 67 { CS42L42_HS_CLAMP_DISABLE, 0x00 }, 68 { CS42L42_MCLK_SRC_SEL, 0x00 }, 69 { CS42L42_SPDIF_CLK_CFG, 0x00 }, 70 { CS42L42_FSYNC_PW_LOWER, 0x00 }, 71 { CS42L42_FSYNC_PW_UPPER, 0x00 }, 72 { CS42L42_FSYNC_P_LOWER, 0xF9 }, 73 { CS42L42_FSYNC_P_UPPER, 0x00 }, 74 { CS42L42_ASP_CLK_CFG, 0x00 }, 75 { CS42L42_ASP_FRM_CFG, 0x10 }, 76 { CS42L42_FS_RATE_EN, 0x00 }, 77 { CS42L42_IN_ASRC_CLK, 0x00 }, 78 { CS42L42_OUT_ASRC_CLK, 0x00 }, 79 { CS42L42_PLL_DIV_CFG1, 0x00 }, 80 { CS42L42_ADC_OVFL_INT_MASK, 0x01 }, 81 { CS42L42_MIXER_INT_MASK, 0x0F }, 82 { CS42L42_SRC_INT_MASK, 0x0F }, 83 { CS42L42_ASP_RX_INT_MASK, 0x1F }, 84 { CS42L42_ASP_TX_INT_MASK, 0x0F }, 85 { CS42L42_CODEC_INT_MASK, 0x03 }, 86 { CS42L42_SRCPL_INT_MASK, 0x7F }, 87 { CS42L42_VPMON_INT_MASK, 0x01 }, 88 { CS42L42_PLL_LOCK_INT_MASK, 0x01 }, 89 { CS42L42_TSRS_PLUG_INT_MASK, 0x0F }, 90 { CS42L42_PLL_CTL1, 0x00 }, 91 { CS42L42_PLL_DIV_FRAC0, 0x00 }, 92 { CS42L42_PLL_DIV_FRAC1, 0x00 }, 93 { CS42L42_PLL_DIV_FRAC2, 0x00 }, 94 { CS42L42_PLL_DIV_INT, 0x40 }, 95 { CS42L42_PLL_CTL3, 0x10 }, 96 { CS42L42_PLL_CAL_RATIO, 0x80 }, 97 { CS42L42_PLL_CTL4, 0x03 }, 98 { CS42L42_LOAD_DET_EN, 0x00 }, 99 { CS42L42_HSBIAS_SC_AUTOCTL, 0x03 }, 100 { CS42L42_WAKE_CTL, 0xC0 }, 101 { CS42L42_ADC_DISABLE_MUTE, 0x00 }, 102 { CS42L42_TIPSENSE_CTL, 0x02 }, 103 { CS42L42_MISC_DET_CTL, 0x03 }, 104 { CS42L42_MIC_DET_CTL1, 0x1F }, 105 { CS42L42_MIC_DET_CTL2, 0x2F }, 106 { CS42L42_DET_INT1_MASK, 0xE0 }, 107 { CS42L42_DET_INT2_MASK, 0xFF }, 108 { CS42L42_HS_BIAS_CTL, 0xC2 }, 109 { CS42L42_ADC_CTL, 0x00 }, 110 { CS42L42_ADC_VOLUME, 0x00 }, 111 { CS42L42_ADC_WNF_HPF_CTL, 0x71 }, 112 { CS42L42_DAC_CTL1, 0x00 }, 113 { CS42L42_DAC_CTL2, 0x02 }, 114 { CS42L42_HP_CTL, 0x0D }, 115 { CS42L42_CLASSH_CTL, 0x07 }, 116 { CS42L42_MIXER_CHA_VOL, 0x3F }, 117 { CS42L42_MIXER_ADC_VOL, 0x3F }, 118 { CS42L42_MIXER_CHB_VOL, 0x3F }, 119 { CS42L42_EQ_COEF_IN0, 0x00 }, 120 { CS42L42_EQ_COEF_IN1, 0x00 }, 121 { CS42L42_EQ_COEF_IN2, 0x00 }, 122 { CS42L42_EQ_COEF_IN3, 0x00 }, 123 { CS42L42_EQ_COEF_RW, 0x00 }, 124 { CS42L42_EQ_COEF_OUT0, 0x00 }, 125 { CS42L42_EQ_COEF_OUT1, 0x00 }, 126 { CS42L42_EQ_COEF_OUT2, 0x00 }, 127 { CS42L42_EQ_COEF_OUT3, 0x00 }, 128 { CS42L42_EQ_INIT_STAT, 0x00 }, 129 { CS42L42_EQ_START_FILT, 0x00 }, 130 { CS42L42_EQ_MUTE_CTL, 0x00 }, 131 { CS42L42_SP_RX_CH_SEL, 0x04 }, 132 { CS42L42_SP_RX_ISOC_CTL, 0x04 }, 133 { CS42L42_SP_RX_FS, 0x8C }, 134 { CS42l42_SPDIF_CH_SEL, 0x0E }, 135 { CS42L42_SP_TX_ISOC_CTL, 0x04 }, 136 { CS42L42_SP_TX_FS, 0xCC }, 137 { CS42L42_SPDIF_SW_CTL1, 0x3F }, 138 { CS42L42_SRC_SDIN_FS, 0x40 }, 139 { CS42L42_SRC_SDOUT_FS, 0x40 }, 140 { CS42L42_SPDIF_CTL1, 0x01 }, 141 { CS42L42_SPDIF_CTL2, 0x00 }, 142 { CS42L42_SPDIF_CTL3, 0x00 }, 143 { CS42L42_SPDIF_CTL4, 0x42 }, 144 { CS42L42_ASP_TX_SZ_EN, 0x00 }, 145 { CS42L42_ASP_TX_CH_EN, 0x00 }, 146 { CS42L42_ASP_TX_CH_AP_RES, 0x0F }, 147 { CS42L42_ASP_TX_CH1_BIT_MSB, 0x00 }, 148 { CS42L42_ASP_TX_CH1_BIT_LSB, 0x00 }, 149 { CS42L42_ASP_TX_HIZ_DLY_CFG, 0x00 }, 150 { CS42L42_ASP_TX_CH2_BIT_MSB, 0x00 }, 151 { CS42L42_ASP_TX_CH2_BIT_LSB, 0x00 }, 152 { CS42L42_ASP_RX_DAI0_EN, 0x00 }, 153 { CS42L42_ASP_RX_DAI0_CH1_AP_RES, 0x03 }, 154 { CS42L42_ASP_RX_DAI0_CH1_BIT_MSB, 0x00 }, 155 { CS42L42_ASP_RX_DAI0_CH1_BIT_LSB, 0x00 }, 156 { CS42L42_ASP_RX_DAI0_CH2_AP_RES, 0x03 }, 157 { CS42L42_ASP_RX_DAI0_CH2_BIT_MSB, 0x00 }, 158 { CS42L42_ASP_RX_DAI0_CH2_BIT_LSB, 0x00 }, 159 { CS42L42_ASP_RX_DAI0_CH3_AP_RES, 0x03 }, 160 { CS42L42_ASP_RX_DAI0_CH3_BIT_MSB, 0x00 }, 161 { CS42L42_ASP_RX_DAI0_CH3_BIT_LSB, 0x00 }, 162 { CS42L42_ASP_RX_DAI0_CH4_AP_RES, 0x03 }, 163 { CS42L42_ASP_RX_DAI0_CH4_BIT_MSB, 0x00 }, 164 { CS42L42_ASP_RX_DAI0_CH4_BIT_LSB, 0x00 }, 165 { CS42L42_ASP_RX_DAI1_CH1_AP_RES, 0x03 }, 166 { CS42L42_ASP_RX_DAI1_CH1_BIT_MSB, 0x00 }, 167 { CS42L42_ASP_RX_DAI1_CH1_BIT_LSB, 0x00 }, 168 { CS42L42_ASP_RX_DAI1_CH2_AP_RES, 0x03 }, 169 { CS42L42_ASP_RX_DAI1_CH2_BIT_MSB, 0x00 }, 170 { CS42L42_ASP_RX_DAI1_CH2_BIT_LSB, 0x00 }, 171 }; 172 173 bool cs42l42_readable_register(struct device *dev, unsigned int reg) 174 { 175 switch (reg) { 176 case CS42L42_PAGE_REGISTER: 177 case CS42L42_DEVID_AB: 178 case CS42L42_DEVID_CD: 179 case CS42L42_DEVID_E: 180 case CS42L42_FABID: 181 case CS42L42_REVID: 182 case CS42L42_FRZ_CTL: 183 case CS42L42_SRC_CTL: 184 case CS42L42_MCLK_STATUS: 185 case CS42L42_MCLK_CTL: 186 case CS42L42_SFTRAMP_RATE: 187 case CS42L42_SLOW_START_ENABLE: 188 case CS42L42_I2C_DEBOUNCE: 189 case CS42L42_I2C_STRETCH: 190 case CS42L42_I2C_TIMEOUT: 191 case CS42L42_PWR_CTL1: 192 case CS42L42_PWR_CTL2: 193 case CS42L42_PWR_CTL3: 194 case CS42L42_RSENSE_CTL1: 195 case CS42L42_RSENSE_CTL2: 196 case CS42L42_OSC_SWITCH: 197 case CS42L42_OSC_SWITCH_STATUS: 198 case CS42L42_RSENSE_CTL3: 199 case CS42L42_TSENSE_CTL: 200 case CS42L42_TSRS_INT_DISABLE: 201 case CS42L42_TRSENSE_STATUS: 202 case CS42L42_HSDET_CTL1: 203 case CS42L42_HSDET_CTL2: 204 case CS42L42_HS_SWITCH_CTL: 205 case CS42L42_HS_DET_STATUS: 206 case CS42L42_HS_CLAMP_DISABLE: 207 case CS42L42_MCLK_SRC_SEL: 208 case CS42L42_SPDIF_CLK_CFG: 209 case CS42L42_FSYNC_PW_LOWER: 210 case CS42L42_FSYNC_PW_UPPER: 211 case CS42L42_FSYNC_P_LOWER: 212 case CS42L42_FSYNC_P_UPPER: 213 case CS42L42_ASP_CLK_CFG: 214 case CS42L42_ASP_FRM_CFG: 215 case CS42L42_FS_RATE_EN: 216 case CS42L42_IN_ASRC_CLK: 217 case CS42L42_OUT_ASRC_CLK: 218 case CS42L42_PLL_DIV_CFG1: 219 case CS42L42_ADC_OVFL_STATUS: 220 case CS42L42_MIXER_STATUS: 221 case CS42L42_SRC_STATUS: 222 case CS42L42_ASP_RX_STATUS: 223 case CS42L42_ASP_TX_STATUS: 224 case CS42L42_CODEC_STATUS: 225 case CS42L42_DET_INT_STATUS1: 226 case CS42L42_DET_INT_STATUS2: 227 case CS42L42_SRCPL_INT_STATUS: 228 case CS42L42_VPMON_STATUS: 229 case CS42L42_PLL_LOCK_STATUS: 230 case CS42L42_TSRS_PLUG_STATUS: 231 case CS42L42_ADC_OVFL_INT_MASK: 232 case CS42L42_MIXER_INT_MASK: 233 case CS42L42_SRC_INT_MASK: 234 case CS42L42_ASP_RX_INT_MASK: 235 case CS42L42_ASP_TX_INT_MASK: 236 case CS42L42_CODEC_INT_MASK: 237 case CS42L42_SRCPL_INT_MASK: 238 case CS42L42_VPMON_INT_MASK: 239 case CS42L42_PLL_LOCK_INT_MASK: 240 case CS42L42_TSRS_PLUG_INT_MASK: 241 case CS42L42_PLL_CTL1: 242 case CS42L42_PLL_DIV_FRAC0: 243 case CS42L42_PLL_DIV_FRAC1: 244 case CS42L42_PLL_DIV_FRAC2: 245 case CS42L42_PLL_DIV_INT: 246 case CS42L42_PLL_CTL3: 247 case CS42L42_PLL_CAL_RATIO: 248 case CS42L42_PLL_CTL4: 249 case CS42L42_LOAD_DET_RCSTAT: 250 case CS42L42_LOAD_DET_DONE: 251 case CS42L42_LOAD_DET_EN: 252 case CS42L42_HSBIAS_SC_AUTOCTL: 253 case CS42L42_WAKE_CTL: 254 case CS42L42_ADC_DISABLE_MUTE: 255 case CS42L42_TIPSENSE_CTL: 256 case CS42L42_MISC_DET_CTL: 257 case CS42L42_MIC_DET_CTL1: 258 case CS42L42_MIC_DET_CTL2: 259 case CS42L42_DET_STATUS1: 260 case CS42L42_DET_STATUS2: 261 case CS42L42_DET_INT1_MASK: 262 case CS42L42_DET_INT2_MASK: 263 case CS42L42_HS_BIAS_CTL: 264 case CS42L42_ADC_CTL: 265 case CS42L42_ADC_VOLUME: 266 case CS42L42_ADC_WNF_HPF_CTL: 267 case CS42L42_DAC_CTL1: 268 case CS42L42_DAC_CTL2: 269 case CS42L42_HP_CTL: 270 case CS42L42_CLASSH_CTL: 271 case CS42L42_MIXER_CHA_VOL: 272 case CS42L42_MIXER_ADC_VOL: 273 case CS42L42_MIXER_CHB_VOL: 274 case CS42L42_EQ_COEF_IN0: 275 case CS42L42_EQ_COEF_IN1: 276 case CS42L42_EQ_COEF_IN2: 277 case CS42L42_EQ_COEF_IN3: 278 case CS42L42_EQ_COEF_RW: 279 case CS42L42_EQ_COEF_OUT0: 280 case CS42L42_EQ_COEF_OUT1: 281 case CS42L42_EQ_COEF_OUT2: 282 case CS42L42_EQ_COEF_OUT3: 283 case CS42L42_EQ_INIT_STAT: 284 case CS42L42_EQ_START_FILT: 285 case CS42L42_EQ_MUTE_CTL: 286 case CS42L42_SP_RX_CH_SEL: 287 case CS42L42_SP_RX_ISOC_CTL: 288 case CS42L42_SP_RX_FS: 289 case CS42l42_SPDIF_CH_SEL: 290 case CS42L42_SP_TX_ISOC_CTL: 291 case CS42L42_SP_TX_FS: 292 case CS42L42_SPDIF_SW_CTL1: 293 case CS42L42_SRC_SDIN_FS: 294 case CS42L42_SRC_SDOUT_FS: 295 case CS42L42_SOFT_RESET_REBOOT: 296 case CS42L42_SPDIF_CTL1: 297 case CS42L42_SPDIF_CTL2: 298 case CS42L42_SPDIF_CTL3: 299 case CS42L42_SPDIF_CTL4: 300 case CS42L42_ASP_TX_SZ_EN: 301 case CS42L42_ASP_TX_CH_EN: 302 case CS42L42_ASP_TX_CH_AP_RES: 303 case CS42L42_ASP_TX_CH1_BIT_MSB: 304 case CS42L42_ASP_TX_CH1_BIT_LSB: 305 case CS42L42_ASP_TX_HIZ_DLY_CFG: 306 case CS42L42_ASP_TX_CH2_BIT_MSB: 307 case CS42L42_ASP_TX_CH2_BIT_LSB: 308 case CS42L42_ASP_RX_DAI0_EN: 309 case CS42L42_ASP_RX_DAI0_CH1_AP_RES: 310 case CS42L42_ASP_RX_DAI0_CH1_BIT_MSB: 311 case CS42L42_ASP_RX_DAI0_CH1_BIT_LSB: 312 case CS42L42_ASP_RX_DAI0_CH2_AP_RES: 313 case CS42L42_ASP_RX_DAI0_CH2_BIT_MSB: 314 case CS42L42_ASP_RX_DAI0_CH2_BIT_LSB: 315 case CS42L42_ASP_RX_DAI0_CH3_AP_RES: 316 case CS42L42_ASP_RX_DAI0_CH3_BIT_MSB: 317 case CS42L42_ASP_RX_DAI0_CH3_BIT_LSB: 318 case CS42L42_ASP_RX_DAI0_CH4_AP_RES: 319 case CS42L42_ASP_RX_DAI0_CH4_BIT_MSB: 320 case CS42L42_ASP_RX_DAI0_CH4_BIT_LSB: 321 case CS42L42_ASP_RX_DAI1_CH1_AP_RES: 322 case CS42L42_ASP_RX_DAI1_CH1_BIT_MSB: 323 case CS42L42_ASP_RX_DAI1_CH1_BIT_LSB: 324 case CS42L42_ASP_RX_DAI1_CH2_AP_RES: 325 case CS42L42_ASP_RX_DAI1_CH2_BIT_MSB: 326 case CS42L42_ASP_RX_DAI1_CH2_BIT_LSB: 327 case CS42L42_SUB_REVID: 328 return true; 329 default: 330 return false; 331 } 332 } 333 EXPORT_SYMBOL_NS_GPL(cs42l42_readable_register, "SND_SOC_CS42L42_CORE"); 334 335 bool cs42l42_volatile_register(struct device *dev, unsigned int reg) 336 { 337 switch (reg) { 338 case CS42L42_DEVID_AB: 339 case CS42L42_DEVID_CD: 340 case CS42L42_DEVID_E: 341 case CS42L42_MCLK_STATUS: 342 case CS42L42_OSC_SWITCH_STATUS: 343 case CS42L42_TRSENSE_STATUS: 344 case CS42L42_HS_DET_STATUS: 345 case CS42L42_ADC_OVFL_STATUS: 346 case CS42L42_MIXER_STATUS: 347 case CS42L42_SRC_STATUS: 348 case CS42L42_ASP_RX_STATUS: 349 case CS42L42_ASP_TX_STATUS: 350 case CS42L42_CODEC_STATUS: 351 case CS42L42_DET_INT_STATUS1: 352 case CS42L42_DET_INT_STATUS2: 353 case CS42L42_SRCPL_INT_STATUS: 354 case CS42L42_VPMON_STATUS: 355 case CS42L42_PLL_LOCK_STATUS: 356 case CS42L42_TSRS_PLUG_STATUS: 357 case CS42L42_LOAD_DET_RCSTAT: 358 case CS42L42_LOAD_DET_DONE: 359 case CS42L42_DET_STATUS1: 360 case CS42L42_DET_STATUS2: 361 case CS42L42_SOFT_RESET_REBOOT: 362 return true; 363 default: 364 return false; 365 } 366 } 367 EXPORT_SYMBOL_NS_GPL(cs42l42_volatile_register, "SND_SOC_CS42L42_CORE"); 368 369 const struct regmap_range_cfg cs42l42_page_range = { 370 .name = "Pages", 371 .range_min = 0, 372 .range_max = CS42L42_MAX_REGISTER, 373 .selector_reg = CS42L42_PAGE_REGISTER, 374 .selector_mask = 0xff, 375 .selector_shift = 0, 376 .window_start = 0, 377 .window_len = 256, 378 }; 379 EXPORT_SYMBOL_NS_GPL(cs42l42_page_range, "SND_SOC_CS42L42_CORE"); 380 381 const struct regmap_config cs42l42_regmap = { 382 .reg_bits = 8, 383 .val_bits = 8, 384 385 .readable_reg = cs42l42_readable_register, 386 .volatile_reg = cs42l42_volatile_register, 387 388 .ranges = &cs42l42_page_range, 389 .num_ranges = 1, 390 391 .max_register = CS42L42_MAX_REGISTER, 392 .reg_defaults = cs42l42_reg_defaults, 393 .num_reg_defaults = ARRAY_SIZE(cs42l42_reg_defaults), 394 .cache_type = REGCACHE_MAPLE, 395 396 .use_single_read = true, 397 .use_single_write = true, 398 }; 399 EXPORT_SYMBOL_NS_GPL(cs42l42_regmap, "SND_SOC_CS42L42_CORE"); 400 401 static DECLARE_TLV_DB_SCALE(adc_tlv, -9700, 100, true); 402 static DECLARE_TLV_DB_SCALE(mixer_tlv, -6300, 100, true); 403 404 static int cs42l42_slow_start_put(struct snd_kcontrol *kcontrol, 405 struct snd_ctl_elem_value *ucontrol) 406 { 407 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 408 u8 val; 409 410 /* all bits of SLOW_START_EN must change together */ 411 switch (ucontrol->value.integer.value[0]) { 412 case 0: 413 val = 0; 414 break; 415 case 1: 416 val = CS42L42_SLOW_START_EN_MASK; 417 break; 418 default: 419 return -EINVAL; 420 } 421 422 return snd_soc_component_update_bits(component, CS42L42_SLOW_START_ENABLE, 423 CS42L42_SLOW_START_EN_MASK, val); 424 } 425 426 static const char * const cs42l42_hpf_freq_text[] = { 427 "1.86Hz", "120Hz", "235Hz", "466Hz" 428 }; 429 430 static SOC_ENUM_SINGLE_DECL(cs42l42_hpf_freq_enum, CS42L42_ADC_WNF_HPF_CTL, 431 CS42L42_ADC_HPF_CF_SHIFT, 432 cs42l42_hpf_freq_text); 433 434 static const char * const cs42l42_wnf3_freq_text[] = { 435 "160Hz", "180Hz", "200Hz", "220Hz", 436 "240Hz", "260Hz", "280Hz", "300Hz" 437 }; 438 439 static SOC_ENUM_SINGLE_DECL(cs42l42_wnf3_freq_enum, CS42L42_ADC_WNF_HPF_CTL, 440 CS42L42_ADC_WNF_CF_SHIFT, 441 cs42l42_wnf3_freq_text); 442 443 static const struct snd_kcontrol_new cs42l42_snd_controls[] = { 444 /* ADC Volume and Filter Controls */ 445 SOC_SINGLE("ADC Notch Switch", CS42L42_ADC_CTL, 446 CS42L42_ADC_NOTCH_DIS_SHIFT, true, true), 447 SOC_SINGLE("ADC Weak Force Switch", CS42L42_ADC_CTL, 448 CS42L42_ADC_FORCE_WEAK_VCM_SHIFT, true, false), 449 SOC_SINGLE("ADC Invert Switch", CS42L42_ADC_CTL, 450 CS42L42_ADC_INV_SHIFT, true, false), 451 SOC_SINGLE("ADC Boost Switch", CS42L42_ADC_CTL, 452 CS42L42_ADC_DIG_BOOST_SHIFT, true, false), 453 SOC_SINGLE_S8_TLV("ADC Volume", CS42L42_ADC_VOLUME, -97, 12, adc_tlv), 454 SOC_SINGLE("ADC WNF Switch", CS42L42_ADC_WNF_HPF_CTL, 455 CS42L42_ADC_WNF_EN_SHIFT, true, false), 456 SOC_SINGLE("ADC HPF Switch", CS42L42_ADC_WNF_HPF_CTL, 457 CS42L42_ADC_HPF_EN_SHIFT, true, false), 458 SOC_ENUM("HPF Corner Freq", cs42l42_hpf_freq_enum), 459 SOC_ENUM("WNF 3dB Freq", cs42l42_wnf3_freq_enum), 460 461 /* DAC Volume and Filter Controls */ 462 SOC_SINGLE("DACA Invert Switch", CS42L42_DAC_CTL1, 463 CS42L42_DACA_INV_SHIFT, true, false), 464 SOC_SINGLE("DACB Invert Switch", CS42L42_DAC_CTL1, 465 CS42L42_DACB_INV_SHIFT, true, false), 466 SOC_SINGLE("DAC HPF Switch", CS42L42_DAC_CTL2, 467 CS42L42_DAC_HPF_EN_SHIFT, true, false), 468 SOC_DOUBLE_R_TLV("Mixer Volume", CS42L42_MIXER_CHA_VOL, 469 CS42L42_MIXER_CHB_VOL, CS42L42_MIXER_CH_VOL_SHIFT, 470 0x3f, 1, mixer_tlv), 471 472 SOC_SINGLE_EXT("Slow Start Switch", CS42L42_SLOW_START_ENABLE, 473 CS42L42_SLOW_START_EN_SHIFT, true, false, 474 snd_soc_get_volsw, cs42l42_slow_start_put), 475 }; 476 477 static int cs42l42_hp_adc_ev(struct snd_soc_dapm_widget *w, 478 struct snd_kcontrol *kcontrol, int event) 479 { 480 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 481 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 482 483 switch (event) { 484 case SND_SOC_DAPM_PRE_PMU: 485 cs42l42->hp_adc_up_pending = true; 486 break; 487 case SND_SOC_DAPM_POST_PMU: 488 /* Only need one delay if HP and ADC are both powering-up */ 489 if (cs42l42->hp_adc_up_pending) { 490 usleep_range(CS42L42_HP_ADC_EN_TIME_US, 491 CS42L42_HP_ADC_EN_TIME_US + 1000); 492 cs42l42->hp_adc_up_pending = false; 493 } 494 break; 495 default: 496 break; 497 } 498 499 return 0; 500 } 501 502 static const struct snd_soc_dapm_widget cs42l42_dapm_widgets[] = { 503 /* Playback Path */ 504 SND_SOC_DAPM_OUTPUT("HP"), 505 SND_SOC_DAPM_DAC_E("DAC", NULL, CS42L42_PWR_CTL1, CS42L42_HP_PDN_SHIFT, 1, 506 cs42l42_hp_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 507 SND_SOC_DAPM_MIXER("MIXER", CS42L42_PWR_CTL1, CS42L42_MIXER_PDN_SHIFT, 1, NULL, 0), 508 SND_SOC_DAPM_AIF_IN("SDIN1", NULL, 0, SND_SOC_NOPM, 0, 0), 509 SND_SOC_DAPM_AIF_IN("SDIN2", NULL, 1, SND_SOC_NOPM, 0, 0), 510 511 /* Playback Requirements */ 512 SND_SOC_DAPM_SUPPLY("ASP DAI0", CS42L42_PWR_CTL1, CS42L42_ASP_DAI_PDN_SHIFT, 1, NULL, 0), 513 514 /* Capture Path */ 515 SND_SOC_DAPM_INPUT("HS"), 516 SND_SOC_DAPM_ADC_E("ADC", NULL, CS42L42_PWR_CTL1, CS42L42_ADC_PDN_SHIFT, 1, 517 cs42l42_hp_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 518 SND_SOC_DAPM_AIF_OUT("SDOUT1", NULL, 0, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH1_SHIFT, 0), 519 SND_SOC_DAPM_AIF_OUT("SDOUT2", NULL, 1, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH2_SHIFT, 0), 520 521 /* Capture Requirements */ 522 SND_SOC_DAPM_SUPPLY("ASP DAO0", CS42L42_PWR_CTL1, CS42L42_ASP_DAO_PDN_SHIFT, 1, NULL, 0), 523 SND_SOC_DAPM_SUPPLY("ASP TX EN", CS42L42_ASP_TX_SZ_EN, CS42L42_ASP_TX_EN_SHIFT, 0, NULL, 0), 524 525 /* Playback/Capture Requirements */ 526 SND_SOC_DAPM_SUPPLY("SCLK", CS42L42_ASP_CLK_CFG, CS42L42_ASP_SCLK_EN_SHIFT, 0, NULL, 0), 527 528 /* Soundwire SRC power control */ 529 SND_SOC_DAPM_PGA("DACSRC", CS42L42_PWR_CTL2, CS42L42_DAC_SRC_PDNB_SHIFT, 0, NULL, 0), 530 SND_SOC_DAPM_PGA("ADCSRC", CS42L42_PWR_CTL2, CS42L42_ADC_SRC_PDNB_SHIFT, 0, NULL, 0), 531 }; 532 533 static const struct snd_soc_dapm_route cs42l42_audio_map[] = { 534 /* Playback Path */ 535 {"HP", NULL, "DAC"}, 536 {"DAC", NULL, "MIXER"}, 537 {"MIXER", NULL, "SDIN1"}, 538 {"MIXER", NULL, "SDIN2"}, 539 {"SDIN1", NULL, "Playback"}, 540 {"SDIN2", NULL, "Playback"}, 541 542 /* Playback Requirements */ 543 {"SDIN1", NULL, "ASP DAI0"}, 544 {"SDIN2", NULL, "ASP DAI0"}, 545 {"SDIN1", NULL, "SCLK"}, 546 {"SDIN2", NULL, "SCLK"}, 547 548 /* Capture Path */ 549 {"ADC", NULL, "HS"}, 550 { "SDOUT1", NULL, "ADC" }, 551 { "SDOUT2", NULL, "ADC" }, 552 { "Capture", NULL, "SDOUT1" }, 553 { "Capture", NULL, "SDOUT2" }, 554 555 /* Capture Requirements */ 556 { "SDOUT1", NULL, "ASP DAO0" }, 557 { "SDOUT2", NULL, "ASP DAO0" }, 558 { "SDOUT1", NULL, "SCLK" }, 559 { "SDOUT2", NULL, "SCLK" }, 560 { "SDOUT1", NULL, "ASP TX EN" }, 561 { "SDOUT2", NULL, "ASP TX EN" }, 562 }; 563 564 static int cs42l42_set_jack(struct snd_soc_component *component, struct snd_soc_jack *jk, void *d) 565 { 566 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 567 568 /* Prevent race with interrupt handler */ 569 guard(mutex)(&cs42l42->irq_lock); 570 cs42l42->jack = jk; 571 572 if (jk) { 573 switch (cs42l42->hs_type) { 574 case CS42L42_PLUG_CTIA: 575 case CS42L42_PLUG_OMTP: 576 snd_soc_jack_report(jk, SND_JACK_HEADSET, SND_JACK_HEADSET); 577 break; 578 case CS42L42_PLUG_HEADPHONE: 579 snd_soc_jack_report(jk, SND_JACK_HEADPHONE, SND_JACK_HEADPHONE); 580 break; 581 default: 582 break; 583 } 584 } 585 586 return 0; 587 } 588 589 const struct snd_soc_component_driver cs42l42_soc_component = { 590 .set_jack = cs42l42_set_jack, 591 .dapm_widgets = cs42l42_dapm_widgets, 592 .num_dapm_widgets = ARRAY_SIZE(cs42l42_dapm_widgets), 593 .dapm_routes = cs42l42_audio_map, 594 .num_dapm_routes = ARRAY_SIZE(cs42l42_audio_map), 595 .controls = cs42l42_snd_controls, 596 .num_controls = ARRAY_SIZE(cs42l42_snd_controls), 597 .endianness = 1, 598 }; 599 EXPORT_SYMBOL_NS_GPL(cs42l42_soc_component, "SND_SOC_CS42L42_CORE"); 600 601 /* Switch to SCLK. Atomic delay after the write to allow the switch to complete. */ 602 static const struct reg_sequence cs42l42_to_sclk_seq[] = { 603 { 604 .reg = CS42L42_OSC_SWITCH, 605 .def = CS42L42_SCLK_PRESENT_MASK, 606 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US, 607 }, 608 }; 609 610 /* Switch to OSC. Atomic delay after the write to allow the switch to complete. */ 611 static const struct reg_sequence cs42l42_to_osc_seq[] = { 612 { 613 .reg = CS42L42_OSC_SWITCH, 614 .def = 0, 615 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US, 616 }, 617 }; 618 619 struct cs42l42_pll_params { 620 u32 sclk; 621 u8 mclk_src_sel; 622 u8 sclk_prediv; 623 u8 pll_div_int; 624 u32 pll_div_frac; 625 u8 pll_mode; 626 u8 pll_divout; 627 u32 mclk_int; 628 u8 pll_cal_ratio; 629 u8 n; 630 }; 631 632 /* 633 * Common PLL Settings for given SCLK 634 * Table 4-5 from the Datasheet 635 */ 636 static const struct cs42l42_pll_params pll_ratio_table[] = { 637 { 1411200, 1, 0x00, 0x80, 0x000000, 0x03, 0x10, 11289600, 128, 2}, 638 { 1536000, 1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125, 2}, 639 { 2304000, 1, 0x00, 0x55, 0xC00000, 0x02, 0x10, 12288000, 85, 2}, 640 { 2400000, 1, 0x00, 0x50, 0x000000, 0x03, 0x10, 12000000, 80, 2}, 641 { 2822400, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1}, 642 { 3000000, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1}, 643 { 3072000, 1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1}, 644 { 4000000, 1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000, 96, 1}, 645 { 4096000, 1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000, 94, 1}, 646 { 4800000, 1, 0x01, 0x50, 0x000000, 0x03, 0x10, 12000000, 80, 2}, 647 { 4800000, 1, 0x01, 0x50, 0x000000, 0x01, 0x10, 12288000, 82, 2}, 648 { 5644800, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1}, 649 { 6000000, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1}, 650 { 6144000, 1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1}, 651 { 6144000, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12288000, 128, 1}, 652 { 9600000, 1, 0x02, 0x50, 0x000000, 0x03, 0x10, 12000000, 80, 2}, 653 { 9600000, 1, 0x02, 0x50, 0x000000, 0x01, 0x10, 12288000, 82, 2}, 654 { 11289600, 0, 0, 0, 0, 0, 0, 11289600, 0, 1}, 655 { 12000000, 0, 0, 0, 0, 0, 0, 12000000, 0, 1}, 656 { 12288000, 0, 0, 0, 0, 0, 0, 12288000, 0, 1}, 657 { 19200000, 1, 0x03, 0x50, 0x000000, 0x03, 0x10, 12000000, 80, 2}, 658 { 19200000, 1, 0x03, 0x50, 0x000000, 0x01, 0x10, 12288000, 82, 2}, 659 { 22579200, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1}, 660 { 24000000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1}, 661 { 24576000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12288000, 128, 1} 662 }; 663 664 int cs42l42_pll_config(struct snd_soc_component *component, unsigned int clk, 665 unsigned int sample_rate) 666 { 667 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 668 int i; 669 670 /* Don't reconfigure if there is an audio stream running */ 671 if (cs42l42->stream_use) { 672 if (pll_ratio_table[cs42l42->pll_config].sclk == clk) 673 return 0; 674 else 675 return -EBUSY; 676 } 677 678 for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) { 679 /* MCLKint must be a multiple of the sample rate */ 680 if (pll_ratio_table[i].mclk_int % sample_rate) 681 continue; 682 683 if (pll_ratio_table[i].sclk == clk) { 684 cs42l42->pll_config = i; 685 686 /* Configure the internal sample rate */ 687 snd_soc_component_update_bits(component, CS42L42_MCLK_CTL, 688 CS42L42_INTERNAL_FS_MASK, 689 ((pll_ratio_table[i].mclk_int != 690 12000000) && 691 (pll_ratio_table[i].mclk_int != 692 24000000)) << 693 CS42L42_INTERNAL_FS_SHIFT); 694 if (pll_ratio_table[i].mclk_src_sel == 0) { 695 /* Pass the clock straight through */ 696 snd_soc_component_update_bits(component, 697 CS42L42_PLL_CTL1, 698 CS42L42_PLL_START_MASK, 0); 699 } else { 700 /* Configure PLL per table 4-5 */ 701 snd_soc_component_update_bits(component, 702 CS42L42_PLL_DIV_CFG1, 703 CS42L42_SCLK_PREDIV_MASK, 704 pll_ratio_table[i].sclk_prediv 705 << CS42L42_SCLK_PREDIV_SHIFT); 706 snd_soc_component_update_bits(component, 707 CS42L42_PLL_DIV_INT, 708 CS42L42_PLL_DIV_INT_MASK, 709 pll_ratio_table[i].pll_div_int 710 << CS42L42_PLL_DIV_INT_SHIFT); 711 snd_soc_component_update_bits(component, 712 CS42L42_PLL_DIV_FRAC0, 713 CS42L42_PLL_DIV_FRAC_MASK, 714 CS42L42_FRAC0_VAL( 715 pll_ratio_table[i].pll_div_frac) 716 << CS42L42_PLL_DIV_FRAC_SHIFT); 717 snd_soc_component_update_bits(component, 718 CS42L42_PLL_DIV_FRAC1, 719 CS42L42_PLL_DIV_FRAC_MASK, 720 CS42L42_FRAC1_VAL( 721 pll_ratio_table[i].pll_div_frac) 722 << CS42L42_PLL_DIV_FRAC_SHIFT); 723 snd_soc_component_update_bits(component, 724 CS42L42_PLL_DIV_FRAC2, 725 CS42L42_PLL_DIV_FRAC_MASK, 726 CS42L42_FRAC2_VAL( 727 pll_ratio_table[i].pll_div_frac) 728 << CS42L42_PLL_DIV_FRAC_SHIFT); 729 snd_soc_component_update_bits(component, 730 CS42L42_PLL_CTL4, 731 CS42L42_PLL_MODE_MASK, 732 pll_ratio_table[i].pll_mode 733 << CS42L42_PLL_MODE_SHIFT); 734 snd_soc_component_update_bits(component, 735 CS42L42_PLL_CTL3, 736 CS42L42_PLL_DIVOUT_MASK, 737 (pll_ratio_table[i].pll_divout * pll_ratio_table[i].n) 738 << CS42L42_PLL_DIVOUT_SHIFT); 739 snd_soc_component_update_bits(component, 740 CS42L42_PLL_CAL_RATIO, 741 CS42L42_PLL_CAL_RATIO_MASK, 742 pll_ratio_table[i].pll_cal_ratio 743 << CS42L42_PLL_CAL_RATIO_SHIFT); 744 } 745 return 0; 746 } 747 } 748 749 return -EINVAL; 750 } 751 EXPORT_SYMBOL_NS_GPL(cs42l42_pll_config, "SND_SOC_CS42L42_CORE"); 752 753 void cs42l42_src_config(struct snd_soc_component *component, unsigned int sample_rate) 754 { 755 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 756 unsigned int fs; 757 758 /* Don't reconfigure if there is an audio stream running */ 759 if (cs42l42->stream_use) 760 return; 761 762 /* SRC MCLK must be as close as possible to 125 * sample rate */ 763 if (sample_rate <= 48000) 764 fs = CS42L42_CLK_IASRC_SEL_6; 765 else 766 fs = CS42L42_CLK_IASRC_SEL_12; 767 768 /* Set the sample rates (96k or lower) */ 769 snd_soc_component_update_bits(component, 770 CS42L42_FS_RATE_EN, 771 CS42L42_FS_EN_MASK, 772 (CS42L42_FS_EN_IASRC_96K | 773 CS42L42_FS_EN_OASRC_96K) << 774 CS42L42_FS_EN_SHIFT); 775 776 snd_soc_component_update_bits(component, 777 CS42L42_IN_ASRC_CLK, 778 CS42L42_CLK_IASRC_SEL_MASK, 779 fs << CS42L42_CLK_IASRC_SEL_SHIFT); 780 snd_soc_component_update_bits(component, 781 CS42L42_OUT_ASRC_CLK, 782 CS42L42_CLK_OASRC_SEL_MASK, 783 fs << CS42L42_CLK_OASRC_SEL_SHIFT); 784 } 785 EXPORT_SYMBOL_NS_GPL(cs42l42_src_config, "SND_SOC_CS42L42_CORE"); 786 787 static int cs42l42_asp_config(struct snd_soc_component *component, 788 unsigned int sclk, unsigned int sample_rate) 789 { 790 u32 fsync = sclk / sample_rate; 791 792 /* Set up the LRCLK */ 793 if (((fsync * sample_rate) != sclk) || ((fsync % 2) != 0)) { 794 dev_err(component->dev, 795 "Unsupported sclk %d/sample rate %d\n", 796 sclk, 797 sample_rate); 798 return -EINVAL; 799 } 800 /* Set the LRCLK period */ 801 snd_soc_component_update_bits(component, 802 CS42L42_FSYNC_P_LOWER, 803 CS42L42_FSYNC_PERIOD_MASK, 804 CS42L42_FRAC0_VAL(fsync - 1) << 805 CS42L42_FSYNC_PERIOD_SHIFT); 806 snd_soc_component_update_bits(component, 807 CS42L42_FSYNC_P_UPPER, 808 CS42L42_FSYNC_PERIOD_MASK, 809 CS42L42_FRAC1_VAL(fsync - 1) << 810 CS42L42_FSYNC_PERIOD_SHIFT); 811 /* Set the LRCLK to 50% duty cycle */ 812 fsync = fsync / 2; 813 snd_soc_component_update_bits(component, 814 CS42L42_FSYNC_PW_LOWER, 815 CS42L42_FSYNC_PULSE_WIDTH_MASK, 816 CS42L42_FRAC0_VAL(fsync - 1) << 817 CS42L42_FSYNC_PULSE_WIDTH_SHIFT); 818 snd_soc_component_update_bits(component, 819 CS42L42_FSYNC_PW_UPPER, 820 CS42L42_FSYNC_PULSE_WIDTH_MASK, 821 CS42L42_FRAC1_VAL(fsync - 1) << 822 CS42L42_FSYNC_PULSE_WIDTH_SHIFT); 823 824 return 0; 825 } 826 827 static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 828 { 829 struct snd_soc_component *component = codec_dai->component; 830 u32 asp_cfg_val = 0; 831 832 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 833 case SND_SOC_DAIFMT_CBC_CFP: 834 asp_cfg_val |= CS42L42_ASP_MASTER_MODE << 835 CS42L42_ASP_MODE_SHIFT; 836 break; 837 case SND_SOC_DAIFMT_CBC_CFC: 838 asp_cfg_val |= CS42L42_ASP_SLAVE_MODE << 839 CS42L42_ASP_MODE_SHIFT; 840 break; 841 default: 842 return -EINVAL; 843 } 844 845 /* interface format */ 846 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 847 case SND_SOC_DAIFMT_I2S: 848 /* 849 * 5050 mode, frame starts on falling edge of LRCLK, 850 * frame delayed by 1.0 SCLKs 851 */ 852 snd_soc_component_update_bits(component, 853 CS42L42_ASP_FRM_CFG, 854 CS42L42_ASP_STP_MASK | 855 CS42L42_ASP_5050_MASK | 856 CS42L42_ASP_FSD_MASK, 857 CS42L42_ASP_5050_MASK | 858 (CS42L42_ASP_FSD_1_0 << 859 CS42L42_ASP_FSD_SHIFT)); 860 break; 861 default: 862 return -EINVAL; 863 } 864 865 /* Bitclock/frame inversion */ 866 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 867 case SND_SOC_DAIFMT_NB_NF: 868 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT; 869 break; 870 case SND_SOC_DAIFMT_NB_IF: 871 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT; 872 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT; 873 break; 874 case SND_SOC_DAIFMT_IB_NF: 875 break; 876 case SND_SOC_DAIFMT_IB_IF: 877 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT; 878 break; 879 } 880 881 snd_soc_component_update_bits(component, CS42L42_ASP_CLK_CFG, CS42L42_ASP_MODE_MASK | 882 CS42L42_ASP_SCPOL_MASK | 883 CS42L42_ASP_LCPOL_MASK, 884 asp_cfg_val); 885 886 return 0; 887 } 888 889 static int cs42l42_dai_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) 890 { 891 struct snd_soc_component *component = dai->component; 892 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 893 894 /* 895 * Sample rates < 44.1 kHz would produce an out-of-range SCLK with 896 * a standard I2S frame. If the machine driver sets SCLK it must be 897 * legal. 898 */ 899 if (cs42l42->sclk) 900 return 0; 901 902 /* Machine driver has not set a SCLK, limit bottom end to 44.1 kHz */ 903 return snd_pcm_hw_constraint_minmax(substream->runtime, 904 SNDRV_PCM_HW_PARAM_RATE, 905 44100, 96000); 906 } 907 908 static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream, 909 struct snd_pcm_hw_params *params, 910 struct snd_soc_dai *dai) 911 { 912 struct snd_soc_component *component = dai->component; 913 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 914 unsigned int channels = params_channels(params); 915 unsigned int width = (params_width(params) / 8) - 1; 916 unsigned int sample_rate = params_rate(params); 917 unsigned int slot_width = 0; 918 unsigned int val = 0; 919 unsigned int bclk; 920 int ret; 921 922 if (cs42l42->bclk_ratio) { 923 /* machine driver has set the BCLK/samp-rate ratio */ 924 bclk = cs42l42->bclk_ratio * params_rate(params); 925 } else if (cs42l42->sclk) { 926 /* machine driver has set the SCLK */ 927 bclk = cs42l42->sclk; 928 } else { 929 /* 930 * Assume 24-bit samples are in 32-bit slots, to prevent SCLK being 931 * more than assumed (which would result in overclocking). 932 */ 933 if (params_width(params) == 24) 934 slot_width = 32; 935 936 /* I2S frame always has multiple of 2 channels */ 937 bclk = snd_soc_tdm_params_to_bclk(params, slot_width, 0, 2); 938 } 939 940 switch (substream->stream) { 941 case SNDRV_PCM_STREAM_CAPTURE: 942 /* channel 2 on high LRCLK */ 943 val = CS42L42_ASP_TX_CH2_AP_MASK | 944 (width << CS42L42_ASP_TX_CH2_RES_SHIFT) | 945 (width << CS42L42_ASP_TX_CH1_RES_SHIFT); 946 947 snd_soc_component_update_bits(component, CS42L42_ASP_TX_CH_AP_RES, 948 CS42L42_ASP_TX_CH1_AP_MASK | CS42L42_ASP_TX_CH2_AP_MASK | 949 CS42L42_ASP_TX_CH2_RES_MASK | CS42L42_ASP_TX_CH1_RES_MASK, val); 950 break; 951 case SNDRV_PCM_STREAM_PLAYBACK: 952 val |= width << CS42L42_ASP_RX_CH_RES_SHIFT; 953 /* channel 1 on low LRCLK */ 954 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH1_AP_RES, 955 CS42L42_ASP_RX_CH_AP_MASK | 956 CS42L42_ASP_RX_CH_RES_MASK, val); 957 /* Channel 2 on high LRCLK */ 958 val |= CS42L42_ASP_RX_CH_AP_HI << CS42L42_ASP_RX_CH_AP_SHIFT; 959 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH2_AP_RES, 960 CS42L42_ASP_RX_CH_AP_MASK | 961 CS42L42_ASP_RX_CH_RES_MASK, val); 962 963 /* Channel B comes from the last active channel */ 964 snd_soc_component_update_bits(component, CS42L42_SP_RX_CH_SEL, 965 CS42L42_SP_RX_CHB_SEL_MASK, 966 (channels - 1) << CS42L42_SP_RX_CHB_SEL_SHIFT); 967 968 /* Both LRCLK slots must be enabled */ 969 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_EN, 970 CS42L42_ASP_RX0_CH_EN_MASK, 971 BIT(CS42L42_ASP_RX0_CH1_SHIFT) | 972 BIT(CS42L42_ASP_RX0_CH2_SHIFT)); 973 break; 974 default: 975 break; 976 } 977 978 ret = cs42l42_pll_config(component, bclk, sample_rate); 979 if (ret) 980 return ret; 981 982 ret = cs42l42_asp_config(component, bclk, sample_rate); 983 if (ret) 984 return ret; 985 986 cs42l42_src_config(component, sample_rate); 987 988 return 0; 989 } 990 991 static int cs42l42_set_sysclk(struct snd_soc_dai *dai, 992 int clk_id, unsigned int freq, int dir) 993 { 994 struct snd_soc_component *component = dai->component; 995 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 996 int i; 997 998 if (freq == 0) { 999 cs42l42->sclk = 0; 1000 return 0; 1001 } 1002 1003 for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) { 1004 if (pll_ratio_table[i].sclk == freq) { 1005 cs42l42->sclk = freq; 1006 return 0; 1007 } 1008 } 1009 1010 dev_err(component->dev, "SCLK %u not supported\n", freq); 1011 1012 return -EINVAL; 1013 } 1014 1015 static int cs42l42_set_bclk_ratio(struct snd_soc_dai *dai, 1016 unsigned int bclk_ratio) 1017 { 1018 struct snd_soc_component *component = dai->component; 1019 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 1020 1021 cs42l42->bclk_ratio = bclk_ratio; 1022 1023 return 0; 1024 } 1025 1026 int cs42l42_mute_stream(struct snd_soc_dai *dai, int mute, int stream) 1027 { 1028 struct snd_soc_component *component = dai->component; 1029 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 1030 unsigned int regval; 1031 int ret; 1032 1033 if (mute) { 1034 /* Mute the headphone */ 1035 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 1036 snd_soc_component_update_bits(component, CS42L42_HP_CTL, 1037 CS42L42_HP_ANA_AMUTE_MASK | 1038 CS42L42_HP_ANA_BMUTE_MASK, 1039 CS42L42_HP_ANA_AMUTE_MASK | 1040 CS42L42_HP_ANA_BMUTE_MASK); 1041 1042 cs42l42->stream_use &= ~(1 << stream); 1043 if (!cs42l42->stream_use) { 1044 /* 1045 * Switch to the internal oscillator. 1046 * SCLK must remain running until after this clock switch. 1047 * Without a source of clock the I2C bus doesn't work. 1048 */ 1049 regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_osc_seq, 1050 ARRAY_SIZE(cs42l42_to_osc_seq)); 1051 1052 /* Must disconnect PLL before stopping it */ 1053 snd_soc_component_update_bits(component, 1054 CS42L42_MCLK_SRC_SEL, 1055 CS42L42_MCLK_SRC_SEL_MASK, 1056 0); 1057 usleep_range(100, 200); 1058 1059 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1, 1060 CS42L42_PLL_START_MASK, 0); 1061 } 1062 } else { 1063 if (!cs42l42->stream_use) { 1064 /* SCLK must be running before codec unmute. 1065 * 1066 * PLL must not be started with ADC and HP both off 1067 * otherwise the FILT+ supply will not charge properly. 1068 * DAPM widgets power-up before stream unmute so at least 1069 * one of the "DAC" or "ADC" widgets will already have 1070 * powered-up. 1071 */ 1072 if (pll_ratio_table[cs42l42->pll_config].mclk_src_sel) { 1073 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1, 1074 CS42L42_PLL_START_MASK, 1); 1075 1076 if (pll_ratio_table[cs42l42->pll_config].n > 1) { 1077 usleep_range(CS42L42_PLL_DIVOUT_TIME_US, 1078 CS42L42_PLL_DIVOUT_TIME_US * 2); 1079 regval = pll_ratio_table[cs42l42->pll_config].pll_divout; 1080 snd_soc_component_update_bits(component, CS42L42_PLL_CTL3, 1081 CS42L42_PLL_DIVOUT_MASK, 1082 regval << 1083 CS42L42_PLL_DIVOUT_SHIFT); 1084 } 1085 1086 ret = regmap_read_poll_timeout(cs42l42->regmap, 1087 CS42L42_PLL_LOCK_STATUS, 1088 regval, 1089 (regval & 1), 1090 CS42L42_PLL_LOCK_POLL_US, 1091 CS42L42_PLL_LOCK_TIMEOUT_US); 1092 if (ret < 0) 1093 dev_warn(component->dev, "PLL failed to lock: %d\n", ret); 1094 1095 /* PLL must be running to drive glitchless switch logic */ 1096 snd_soc_component_update_bits(component, 1097 CS42L42_MCLK_SRC_SEL, 1098 CS42L42_MCLK_SRC_SEL_MASK, 1099 CS42L42_MCLK_SRC_SEL_MASK); 1100 } 1101 1102 /* Mark SCLK as present, turn off internal oscillator */ 1103 regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_sclk_seq, 1104 ARRAY_SIZE(cs42l42_to_sclk_seq)); 1105 } 1106 cs42l42->stream_use |= 1 << stream; 1107 1108 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 1109 /* Un-mute the headphone */ 1110 snd_soc_component_update_bits(component, CS42L42_HP_CTL, 1111 CS42L42_HP_ANA_AMUTE_MASK | 1112 CS42L42_HP_ANA_BMUTE_MASK, 1113 0); 1114 } 1115 } 1116 1117 return 0; 1118 } 1119 EXPORT_SYMBOL_NS_GPL(cs42l42_mute_stream, "SND_SOC_CS42L42_CORE"); 1120 1121 #define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 1122 SNDRV_PCM_FMTBIT_S24_LE |\ 1123 SNDRV_PCM_FMTBIT_S32_LE) 1124 1125 static const struct snd_soc_dai_ops cs42l42_ops = { 1126 .startup = cs42l42_dai_startup, 1127 .hw_params = cs42l42_pcm_hw_params, 1128 .set_fmt = cs42l42_set_dai_fmt, 1129 .set_sysclk = cs42l42_set_sysclk, 1130 .set_bclk_ratio = cs42l42_set_bclk_ratio, 1131 .mute_stream = cs42l42_mute_stream, 1132 }; 1133 1134 struct snd_soc_dai_driver cs42l42_dai = { 1135 .name = "cs42l42", 1136 .playback = { 1137 .stream_name = "Playback", 1138 .channels_min = 1, 1139 .channels_max = 2, 1140 .rates = SNDRV_PCM_RATE_8000_96000, 1141 .formats = CS42L42_FORMATS, 1142 }, 1143 .capture = { 1144 .stream_name = "Capture", 1145 .channels_min = 1, 1146 .channels_max = 2, 1147 .rates = SNDRV_PCM_RATE_8000_96000, 1148 .formats = CS42L42_FORMATS, 1149 }, 1150 .symmetric_rate = 1, 1151 .symmetric_sample_bits = 1, 1152 .ops = &cs42l42_ops, 1153 }; 1154 EXPORT_SYMBOL_NS_GPL(cs42l42_dai, "SND_SOC_CS42L42_CORE"); 1155 1156 static void cs42l42_manual_hs_type_detect(struct cs42l42_private *cs42l42) 1157 { 1158 unsigned int hs_det_status; 1159 unsigned int hs_det_comp1; 1160 unsigned int hs_det_comp2; 1161 unsigned int hs_det_sw; 1162 1163 /* Set hs detect to manual, active mode */ 1164 regmap_update_bits(cs42l42->regmap, 1165 CS42L42_HSDET_CTL2, 1166 CS42L42_HSDET_CTRL_MASK | 1167 CS42L42_HSDET_SET_MASK | 1168 CS42L42_HSBIAS_REF_MASK | 1169 CS42L42_HSDET_AUTO_TIME_MASK, 1170 (1 << CS42L42_HSDET_CTRL_SHIFT) | 1171 (0 << CS42L42_HSDET_SET_SHIFT) | 1172 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1173 (0 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1174 1175 /* Configure HS DET comparator reference levels. */ 1176 regmap_update_bits(cs42l42->regmap, 1177 CS42L42_HSDET_CTL1, 1178 CS42L42_HSDET_COMP1_LVL_MASK | 1179 CS42L42_HSDET_COMP2_LVL_MASK, 1180 (CS42L42_HSDET_COMP1_LVL_VAL << CS42L42_HSDET_COMP1_LVL_SHIFT) | 1181 (CS42L42_HSDET_COMP2_LVL_VAL << CS42L42_HSDET_COMP2_LVL_SHIFT)); 1182 1183 /* Open the SW_HSB_HS3 switch and close SW_HSB_HS4 for a Type 1 headset. */ 1184 regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP1); 1185 1186 msleep(100); 1187 1188 regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status); 1189 1190 hs_det_comp1 = (hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >> 1191 CS42L42_HSDET_COMP1_OUT_SHIFT; 1192 hs_det_comp2 = (hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >> 1193 CS42L42_HSDET_COMP2_OUT_SHIFT; 1194 1195 /* Close the SW_HSB_HS3 switch for a Type 2 headset. */ 1196 regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP2); 1197 1198 msleep(100); 1199 1200 regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status); 1201 1202 hs_det_comp1 |= ((hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >> 1203 CS42L42_HSDET_COMP1_OUT_SHIFT) << 1; 1204 hs_det_comp2 |= ((hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >> 1205 CS42L42_HSDET_COMP2_OUT_SHIFT) << 1; 1206 1207 /* Use Comparator 1 with 1.25V Threshold. */ 1208 switch (hs_det_comp1) { 1209 case CS42L42_HSDET_COMP_TYPE1: 1210 cs42l42->hs_type = CS42L42_PLUG_CTIA; 1211 hs_det_sw = CS42L42_HSDET_SW_TYPE1; 1212 break; 1213 case CS42L42_HSDET_COMP_TYPE2: 1214 cs42l42->hs_type = CS42L42_PLUG_OMTP; 1215 hs_det_sw = CS42L42_HSDET_SW_TYPE2; 1216 break; 1217 default: 1218 /* Fallback to Comparator 2 with 1.75V Threshold. */ 1219 switch (hs_det_comp2) { 1220 case CS42L42_HSDET_COMP_TYPE1: 1221 cs42l42->hs_type = CS42L42_PLUG_CTIA; 1222 hs_det_sw = CS42L42_HSDET_SW_TYPE1; 1223 break; 1224 case CS42L42_HSDET_COMP_TYPE2: 1225 cs42l42->hs_type = CS42L42_PLUG_OMTP; 1226 hs_det_sw = CS42L42_HSDET_SW_TYPE2; 1227 break; 1228 /* Detect Type 3 and Type 4 Headsets as Headphones */ 1229 default: 1230 cs42l42->hs_type = CS42L42_PLUG_HEADPHONE; 1231 hs_det_sw = CS42L42_HSDET_SW_TYPE3; 1232 break; 1233 } 1234 } 1235 1236 /* Set Switches */ 1237 regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, hs_det_sw); 1238 1239 /* Set HSDET mode to Manual—Disabled */ 1240 regmap_update_bits(cs42l42->regmap, 1241 CS42L42_HSDET_CTL2, 1242 CS42L42_HSDET_CTRL_MASK | 1243 CS42L42_HSDET_SET_MASK | 1244 CS42L42_HSBIAS_REF_MASK | 1245 CS42L42_HSDET_AUTO_TIME_MASK, 1246 (0 << CS42L42_HSDET_CTRL_SHIFT) | 1247 (0 << CS42L42_HSDET_SET_SHIFT) | 1248 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1249 (0 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1250 1251 /* Configure HS DET comparator reference levels. */ 1252 regmap_update_bits(cs42l42->regmap, 1253 CS42L42_HSDET_CTL1, 1254 CS42L42_HSDET_COMP1_LVL_MASK | 1255 CS42L42_HSDET_COMP2_LVL_MASK, 1256 (CS42L42_HSDET_COMP1_LVL_DEFAULT << CS42L42_HSDET_COMP1_LVL_SHIFT) | 1257 (CS42L42_HSDET_COMP2_LVL_DEFAULT << CS42L42_HSDET_COMP2_LVL_SHIFT)); 1258 } 1259 1260 static void cs42l42_process_hs_type_detect(struct cs42l42_private *cs42l42) 1261 { 1262 unsigned int hs_det_status; 1263 unsigned int int_status; 1264 1265 /* Read and save the hs detection result */ 1266 regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status); 1267 1268 /* Mask the auto detect interrupt */ 1269 regmap_update_bits(cs42l42->regmap, 1270 CS42L42_CODEC_INT_MASK, 1271 CS42L42_PDN_DONE_MASK | 1272 CS42L42_HSDET_AUTO_DONE_MASK, 1273 (1 << CS42L42_PDN_DONE_SHIFT) | 1274 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 1275 1276 1277 cs42l42->hs_type = (hs_det_status & CS42L42_HSDET_TYPE_MASK) >> 1278 CS42L42_HSDET_TYPE_SHIFT; 1279 1280 /* Set hs detect to automatic, disabled mode */ 1281 regmap_update_bits(cs42l42->regmap, 1282 CS42L42_HSDET_CTL2, 1283 CS42L42_HSDET_CTRL_MASK | 1284 CS42L42_HSDET_SET_MASK | 1285 CS42L42_HSBIAS_REF_MASK | 1286 CS42L42_HSDET_AUTO_TIME_MASK, 1287 (2 << CS42L42_HSDET_CTRL_SHIFT) | 1288 (2 << CS42L42_HSDET_SET_SHIFT) | 1289 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1290 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1291 1292 /* Run Manual detection if auto detect has not found a headset. 1293 * We Re-Run with Manual Detection if the original detection was invalid or headphones, 1294 * to ensure that a headset mic is detected in all cases. 1295 */ 1296 if (cs42l42->hs_type == CS42L42_PLUG_INVALID || 1297 cs42l42->hs_type == CS42L42_PLUG_HEADPHONE) { 1298 dev_dbg(cs42l42->dev, "Running Manual Detection Fallback\n"); 1299 cs42l42_manual_hs_type_detect(cs42l42); 1300 } 1301 1302 /* Set up button detection */ 1303 if ((cs42l42->hs_type == CS42L42_PLUG_CTIA) || 1304 (cs42l42->hs_type == CS42L42_PLUG_OMTP)) { 1305 /* Set auto HS bias settings to default */ 1306 regmap_update_bits(cs42l42->regmap, 1307 CS42L42_HSBIAS_SC_AUTOCTL, 1308 CS42L42_HSBIAS_SENSE_EN_MASK | 1309 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1310 CS42L42_TIP_SENSE_EN_MASK | 1311 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1312 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1313 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1314 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1315 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1316 1317 /* Set up hs detect level sensitivity */ 1318 regmap_update_bits(cs42l42->regmap, 1319 CS42L42_MIC_DET_CTL1, 1320 CS42L42_LATCH_TO_VP_MASK | 1321 CS42L42_EVENT_STAT_SEL_MASK | 1322 CS42L42_HS_DET_LEVEL_MASK, 1323 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1324 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1325 (cs42l42->bias_thresholds[0] << 1326 CS42L42_HS_DET_LEVEL_SHIFT)); 1327 1328 /* Set auto HS bias settings to default */ 1329 regmap_update_bits(cs42l42->regmap, 1330 CS42L42_HSBIAS_SC_AUTOCTL, 1331 CS42L42_HSBIAS_SENSE_EN_MASK | 1332 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1333 CS42L42_TIP_SENSE_EN_MASK | 1334 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1335 (cs42l42->hs_bias_sense_en << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1336 (1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1337 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1338 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1339 1340 /* Turn on level detect circuitry */ 1341 regmap_update_bits(cs42l42->regmap, 1342 CS42L42_MISC_DET_CTL, 1343 CS42L42_HSBIAS_CTL_MASK | 1344 CS42L42_PDN_MIC_LVL_DET_MASK, 1345 (3 << CS42L42_HSBIAS_CTL_SHIFT) | 1346 (0 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1347 1348 msleep(cs42l42->btn_det_init_dbnce); 1349 1350 /* Clear any button interrupts before unmasking them */ 1351 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2, 1352 &int_status); 1353 1354 /* Unmask button detect interrupts */ 1355 regmap_update_bits(cs42l42->regmap, 1356 CS42L42_DET_INT2_MASK, 1357 CS42L42_M_DETECT_TF_MASK | 1358 CS42L42_M_DETECT_FT_MASK | 1359 CS42L42_M_HSBIAS_HIZ_MASK | 1360 CS42L42_M_SHORT_RLS_MASK | 1361 CS42L42_M_SHORT_DET_MASK, 1362 (0 << CS42L42_M_DETECT_TF_SHIFT) | 1363 (0 << CS42L42_M_DETECT_FT_SHIFT) | 1364 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1365 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1366 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1367 } else { 1368 /* Make sure button detect and HS bias circuits are off */ 1369 regmap_update_bits(cs42l42->regmap, 1370 CS42L42_MISC_DET_CTL, 1371 CS42L42_HSBIAS_CTL_MASK | 1372 CS42L42_PDN_MIC_LVL_DET_MASK, 1373 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1374 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1375 } 1376 1377 regmap_update_bits(cs42l42->regmap, 1378 CS42L42_DAC_CTL2, 1379 CS42L42_HPOUT_PULLDOWN_MASK | 1380 CS42L42_HPOUT_LOAD_MASK | 1381 CS42L42_HPOUT_CLAMP_MASK | 1382 CS42L42_DAC_HPF_EN_MASK | 1383 CS42L42_DAC_MON_EN_MASK, 1384 (0 << CS42L42_HPOUT_PULLDOWN_SHIFT) | 1385 (0 << CS42L42_HPOUT_LOAD_SHIFT) | 1386 (0 << CS42L42_HPOUT_CLAMP_SHIFT) | 1387 (1 << CS42L42_DAC_HPF_EN_SHIFT) | 1388 (0 << CS42L42_DAC_MON_EN_SHIFT)); 1389 1390 /* Unmask tip sense interrupts */ 1391 regmap_update_bits(cs42l42->regmap, 1392 CS42L42_TSRS_PLUG_INT_MASK, 1393 CS42L42_TS_PLUG_MASK | 1394 CS42L42_TS_UNPLUG_MASK, 1395 (0 << CS42L42_TS_PLUG_SHIFT) | 1396 (0 << CS42L42_TS_UNPLUG_SHIFT)); 1397 } 1398 1399 static void cs42l42_init_hs_type_detect(struct cs42l42_private *cs42l42) 1400 { 1401 /* Mask tip sense interrupts */ 1402 regmap_update_bits(cs42l42->regmap, 1403 CS42L42_TSRS_PLUG_INT_MASK, 1404 CS42L42_TS_PLUG_MASK | 1405 CS42L42_TS_UNPLUG_MASK, 1406 (1 << CS42L42_TS_PLUG_SHIFT) | 1407 (1 << CS42L42_TS_UNPLUG_SHIFT)); 1408 1409 /* Make sure button detect and HS bias circuits are off */ 1410 regmap_update_bits(cs42l42->regmap, 1411 CS42L42_MISC_DET_CTL, 1412 CS42L42_HSBIAS_CTL_MASK | 1413 CS42L42_PDN_MIC_LVL_DET_MASK, 1414 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1415 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1416 1417 /* Set auto HS bias settings to default */ 1418 regmap_update_bits(cs42l42->regmap, 1419 CS42L42_HSBIAS_SC_AUTOCTL, 1420 CS42L42_HSBIAS_SENSE_EN_MASK | 1421 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1422 CS42L42_TIP_SENSE_EN_MASK | 1423 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1424 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1425 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1426 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1427 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1428 1429 /* Set hs detect to manual, disabled mode */ 1430 regmap_update_bits(cs42l42->regmap, 1431 CS42L42_HSDET_CTL2, 1432 CS42L42_HSDET_CTRL_MASK | 1433 CS42L42_HSDET_SET_MASK | 1434 CS42L42_HSBIAS_REF_MASK | 1435 CS42L42_HSDET_AUTO_TIME_MASK, 1436 (0 << CS42L42_HSDET_CTRL_SHIFT) | 1437 (2 << CS42L42_HSDET_SET_SHIFT) | 1438 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1439 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1440 1441 regmap_update_bits(cs42l42->regmap, 1442 CS42L42_DAC_CTL2, 1443 CS42L42_HPOUT_PULLDOWN_MASK | 1444 CS42L42_HPOUT_LOAD_MASK | 1445 CS42L42_HPOUT_CLAMP_MASK | 1446 CS42L42_DAC_HPF_EN_MASK | 1447 CS42L42_DAC_MON_EN_MASK, 1448 (8 << CS42L42_HPOUT_PULLDOWN_SHIFT) | 1449 (0 << CS42L42_HPOUT_LOAD_SHIFT) | 1450 (1 << CS42L42_HPOUT_CLAMP_SHIFT) | 1451 (1 << CS42L42_DAC_HPF_EN_SHIFT) | 1452 (1 << CS42L42_DAC_MON_EN_SHIFT)); 1453 1454 /* Power up HS bias to 2.7V */ 1455 regmap_update_bits(cs42l42->regmap, 1456 CS42L42_MISC_DET_CTL, 1457 CS42L42_HSBIAS_CTL_MASK | 1458 CS42L42_PDN_MIC_LVL_DET_MASK, 1459 (3 << CS42L42_HSBIAS_CTL_SHIFT) | 1460 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1461 1462 /* Wait for HS bias to ramp up */ 1463 msleep(cs42l42->hs_bias_ramp_time); 1464 1465 /* Unmask auto detect interrupt */ 1466 regmap_update_bits(cs42l42->regmap, 1467 CS42L42_CODEC_INT_MASK, 1468 CS42L42_PDN_DONE_MASK | 1469 CS42L42_HSDET_AUTO_DONE_MASK, 1470 (1 << CS42L42_PDN_DONE_SHIFT) | 1471 (0 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 1472 1473 /* Set hs detect to automatic, enabled mode */ 1474 regmap_update_bits(cs42l42->regmap, 1475 CS42L42_HSDET_CTL2, 1476 CS42L42_HSDET_CTRL_MASK | 1477 CS42L42_HSDET_SET_MASK | 1478 CS42L42_HSBIAS_REF_MASK | 1479 CS42L42_HSDET_AUTO_TIME_MASK, 1480 (3 << CS42L42_HSDET_CTRL_SHIFT) | 1481 (2 << CS42L42_HSDET_SET_SHIFT) | 1482 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1483 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1484 } 1485 1486 static void cs42l42_cancel_hs_type_detect(struct cs42l42_private *cs42l42) 1487 { 1488 /* Mask button detect interrupts */ 1489 regmap_update_bits(cs42l42->regmap, 1490 CS42L42_DET_INT2_MASK, 1491 CS42L42_M_DETECT_TF_MASK | 1492 CS42L42_M_DETECT_FT_MASK | 1493 CS42L42_M_HSBIAS_HIZ_MASK | 1494 CS42L42_M_SHORT_RLS_MASK | 1495 CS42L42_M_SHORT_DET_MASK, 1496 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1497 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1498 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1499 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1500 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1501 1502 /* Ground HS bias */ 1503 regmap_update_bits(cs42l42->regmap, 1504 CS42L42_MISC_DET_CTL, 1505 CS42L42_HSBIAS_CTL_MASK | 1506 CS42L42_PDN_MIC_LVL_DET_MASK, 1507 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1508 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1509 1510 /* Set auto HS bias settings to default */ 1511 regmap_update_bits(cs42l42->regmap, 1512 CS42L42_HSBIAS_SC_AUTOCTL, 1513 CS42L42_HSBIAS_SENSE_EN_MASK | 1514 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1515 CS42L42_TIP_SENSE_EN_MASK | 1516 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1517 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1518 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1519 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1520 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1521 1522 /* Set hs detect to manual, disabled mode */ 1523 regmap_update_bits(cs42l42->regmap, 1524 CS42L42_HSDET_CTL2, 1525 CS42L42_HSDET_CTRL_MASK | 1526 CS42L42_HSDET_SET_MASK | 1527 CS42L42_HSBIAS_REF_MASK | 1528 CS42L42_HSDET_AUTO_TIME_MASK, 1529 (0 << CS42L42_HSDET_CTRL_SHIFT) | 1530 (2 << CS42L42_HSDET_SET_SHIFT) | 1531 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1532 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1533 } 1534 1535 static int cs42l42_handle_button_press(struct cs42l42_private *cs42l42) 1536 { 1537 int bias_level; 1538 unsigned int detect_status; 1539 1540 /* Mask button detect interrupts */ 1541 regmap_update_bits(cs42l42->regmap, 1542 CS42L42_DET_INT2_MASK, 1543 CS42L42_M_DETECT_TF_MASK | 1544 CS42L42_M_DETECT_FT_MASK | 1545 CS42L42_M_HSBIAS_HIZ_MASK | 1546 CS42L42_M_SHORT_RLS_MASK | 1547 CS42L42_M_SHORT_DET_MASK, 1548 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1549 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1550 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1551 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1552 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1553 1554 usleep_range(cs42l42->btn_det_event_dbnce * 1000, 1555 cs42l42->btn_det_event_dbnce * 2000); 1556 1557 /* Test all 4 level detect biases */ 1558 bias_level = 1; 1559 do { 1560 /* Adjust button detect level sensitivity */ 1561 regmap_update_bits(cs42l42->regmap, 1562 CS42L42_MIC_DET_CTL1, 1563 CS42L42_LATCH_TO_VP_MASK | 1564 CS42L42_EVENT_STAT_SEL_MASK | 1565 CS42L42_HS_DET_LEVEL_MASK, 1566 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1567 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1568 (cs42l42->bias_thresholds[bias_level] << 1569 CS42L42_HS_DET_LEVEL_SHIFT)); 1570 1571 regmap_read(cs42l42->regmap, CS42L42_DET_STATUS2, 1572 &detect_status); 1573 } while ((detect_status & CS42L42_HS_TRUE_MASK) && 1574 (++bias_level < CS42L42_NUM_BIASES)); 1575 1576 switch (bias_level) { 1577 case 1: /* Function C button press */ 1578 bias_level = SND_JACK_BTN_2; 1579 dev_dbg(cs42l42->dev, "Function C button press\n"); 1580 break; 1581 case 2: /* Function B button press */ 1582 bias_level = SND_JACK_BTN_1; 1583 dev_dbg(cs42l42->dev, "Function B button press\n"); 1584 break; 1585 case 3: /* Function D button press */ 1586 bias_level = SND_JACK_BTN_3; 1587 dev_dbg(cs42l42->dev, "Function D button press\n"); 1588 break; 1589 case 4: /* Function A button press */ 1590 bias_level = SND_JACK_BTN_0; 1591 dev_dbg(cs42l42->dev, "Function A button press\n"); 1592 break; 1593 default: 1594 bias_level = 0; 1595 break; 1596 } 1597 1598 /* Set button detect level sensitivity back to default */ 1599 regmap_update_bits(cs42l42->regmap, 1600 CS42L42_MIC_DET_CTL1, 1601 CS42L42_LATCH_TO_VP_MASK | 1602 CS42L42_EVENT_STAT_SEL_MASK | 1603 CS42L42_HS_DET_LEVEL_MASK, 1604 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1605 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1606 (cs42l42->bias_thresholds[0] << CS42L42_HS_DET_LEVEL_SHIFT)); 1607 1608 /* Clear any button interrupts before unmasking them */ 1609 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2, 1610 &detect_status); 1611 1612 /* Unmask button detect interrupts */ 1613 regmap_update_bits(cs42l42->regmap, 1614 CS42L42_DET_INT2_MASK, 1615 CS42L42_M_DETECT_TF_MASK | 1616 CS42L42_M_DETECT_FT_MASK | 1617 CS42L42_M_HSBIAS_HIZ_MASK | 1618 CS42L42_M_SHORT_RLS_MASK | 1619 CS42L42_M_SHORT_DET_MASK, 1620 (0 << CS42L42_M_DETECT_TF_SHIFT) | 1621 (0 << CS42L42_M_DETECT_FT_SHIFT) | 1622 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1623 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1624 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1625 1626 return bias_level; 1627 } 1628 1629 struct cs42l42_irq_params { 1630 u16 status_addr; 1631 u16 mask_addr; 1632 u8 mask; 1633 }; 1634 1635 static const struct cs42l42_irq_params irq_params_table[] = { 1636 {CS42L42_ADC_OVFL_STATUS, CS42L42_ADC_OVFL_INT_MASK, 1637 CS42L42_ADC_OVFL_VAL_MASK}, 1638 {CS42L42_MIXER_STATUS, CS42L42_MIXER_INT_MASK, 1639 CS42L42_MIXER_VAL_MASK}, 1640 {CS42L42_SRC_STATUS, CS42L42_SRC_INT_MASK, 1641 CS42L42_SRC_VAL_MASK}, 1642 {CS42L42_ASP_RX_STATUS, CS42L42_ASP_RX_INT_MASK, 1643 CS42L42_ASP_RX_VAL_MASK}, 1644 {CS42L42_ASP_TX_STATUS, CS42L42_ASP_TX_INT_MASK, 1645 CS42L42_ASP_TX_VAL_MASK}, 1646 {CS42L42_CODEC_STATUS, CS42L42_CODEC_INT_MASK, 1647 CS42L42_CODEC_VAL_MASK}, 1648 {CS42L42_DET_INT_STATUS1, CS42L42_DET_INT1_MASK, 1649 CS42L42_DET_INT_VAL1_MASK}, 1650 {CS42L42_DET_INT_STATUS2, CS42L42_DET_INT2_MASK, 1651 CS42L42_DET_INT_VAL2_MASK}, 1652 {CS42L42_SRCPL_INT_STATUS, CS42L42_SRCPL_INT_MASK, 1653 CS42L42_SRCPL_VAL_MASK}, 1654 {CS42L42_VPMON_STATUS, CS42L42_VPMON_INT_MASK, 1655 CS42L42_VPMON_VAL_MASK}, 1656 {CS42L42_PLL_LOCK_STATUS, CS42L42_PLL_LOCK_INT_MASK, 1657 CS42L42_PLL_LOCK_VAL_MASK}, 1658 {CS42L42_TSRS_PLUG_STATUS, CS42L42_TSRS_PLUG_INT_MASK, 1659 CS42L42_TSRS_PLUG_VAL_MASK} 1660 }; 1661 1662 irqreturn_t cs42l42_irq_thread(int irq, void *data) 1663 { 1664 struct cs42l42_private *cs42l42 = (struct cs42l42_private *)data; 1665 unsigned int stickies[12]; 1666 unsigned int masks[12]; 1667 unsigned int current_plug_status; 1668 unsigned int current_button_status; 1669 unsigned int i; 1670 1671 guard(pm_runtime_active_auto)(cs42l42->dev); 1672 guard(mutex)(&cs42l42->irq_lock); 1673 if (cs42l42->suspended || !cs42l42->init_done) 1674 return IRQ_NONE; 1675 1676 /* Read sticky registers to clear interurpt */ 1677 for (i = 0; i < ARRAY_SIZE(stickies); i++) { 1678 regmap_read(cs42l42->regmap, irq_params_table[i].status_addr, 1679 &(stickies[i])); 1680 regmap_read(cs42l42->regmap, irq_params_table[i].mask_addr, 1681 &(masks[i])); 1682 stickies[i] = stickies[i] & (~masks[i]) & 1683 irq_params_table[i].mask; 1684 } 1685 1686 /* Read tip sense status before handling type detect */ 1687 current_plug_status = (stickies[11] & 1688 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >> 1689 CS42L42_TS_PLUG_SHIFT; 1690 1691 /* Read button sense status */ 1692 current_button_status = stickies[7] & 1693 (CS42L42_M_DETECT_TF_MASK | 1694 CS42L42_M_DETECT_FT_MASK | 1695 CS42L42_M_HSBIAS_HIZ_MASK); 1696 1697 /* 1698 * Check auto-detect status. Don't assume a previous unplug event has 1699 * cleared the flags. If the jack is unplugged and plugged during 1700 * system suspend there won't have been an unplug event. 1701 */ 1702 if ((~masks[5]) & irq_params_table[5].mask) { 1703 if (stickies[5] & CS42L42_HSDET_AUTO_DONE_MASK) { 1704 cs42l42_process_hs_type_detect(cs42l42); 1705 switch (cs42l42->hs_type) { 1706 case CS42L42_PLUG_CTIA: 1707 case CS42L42_PLUG_OMTP: 1708 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADSET, 1709 SND_JACK_HEADSET | 1710 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1711 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1712 break; 1713 case CS42L42_PLUG_HEADPHONE: 1714 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADPHONE, 1715 SND_JACK_HEADSET | 1716 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1717 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1718 break; 1719 default: 1720 break; 1721 } 1722 dev_dbg(cs42l42->dev, "Auto detect done (%d)\n", cs42l42->hs_type); 1723 } 1724 } 1725 1726 /* Check tip sense status */ 1727 if ((~masks[11]) & irq_params_table[11].mask) { 1728 switch (current_plug_status) { 1729 case CS42L42_TS_PLUG: 1730 if (cs42l42->plug_state != CS42L42_TS_PLUG) { 1731 cs42l42->plug_state = CS42L42_TS_PLUG; 1732 cs42l42_init_hs_type_detect(cs42l42); 1733 } 1734 break; 1735 1736 case CS42L42_TS_UNPLUG: 1737 if (cs42l42->plug_state != CS42L42_TS_UNPLUG) { 1738 cs42l42->plug_state = CS42L42_TS_UNPLUG; 1739 cs42l42_cancel_hs_type_detect(cs42l42); 1740 1741 snd_soc_jack_report(cs42l42->jack, 0, 1742 SND_JACK_HEADSET | 1743 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1744 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1745 1746 dev_dbg(cs42l42->dev, "Unplug event\n"); 1747 } 1748 break; 1749 1750 default: 1751 cs42l42->plug_state = CS42L42_TS_TRANS; 1752 } 1753 } 1754 1755 /* Check button detect status */ 1756 if (cs42l42->plug_state == CS42L42_TS_PLUG && ((~masks[7]) & irq_params_table[7].mask)) { 1757 if (!(current_button_status & 1758 CS42L42_M_HSBIAS_HIZ_MASK)) { 1759 1760 if (current_button_status & CS42L42_M_DETECT_TF_MASK) { 1761 dev_dbg(cs42l42->dev, "Button released\n"); 1762 snd_soc_jack_report(cs42l42->jack, 0, 1763 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1764 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1765 } else if (current_button_status & CS42L42_M_DETECT_FT_MASK) { 1766 snd_soc_jack_report(cs42l42->jack, 1767 cs42l42_handle_button_press(cs42l42), 1768 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1769 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1770 } 1771 } 1772 } 1773 1774 return IRQ_HANDLED; 1775 } 1776 EXPORT_SYMBOL_NS_GPL(cs42l42_irq_thread, "SND_SOC_CS42L42_CORE"); 1777 1778 static void cs42l42_set_interrupt_masks(struct cs42l42_private *cs42l42) 1779 { 1780 regmap_update_bits(cs42l42->regmap, CS42L42_ADC_OVFL_INT_MASK, 1781 CS42L42_ADC_OVFL_MASK, 1782 (1 << CS42L42_ADC_OVFL_SHIFT)); 1783 1784 regmap_update_bits(cs42l42->regmap, CS42L42_MIXER_INT_MASK, 1785 CS42L42_MIX_CHB_OVFL_MASK | 1786 CS42L42_MIX_CHA_OVFL_MASK | 1787 CS42L42_EQ_OVFL_MASK | 1788 CS42L42_EQ_BIQUAD_OVFL_MASK, 1789 (1 << CS42L42_MIX_CHB_OVFL_SHIFT) | 1790 (1 << CS42L42_MIX_CHA_OVFL_SHIFT) | 1791 (1 << CS42L42_EQ_OVFL_SHIFT) | 1792 (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT)); 1793 1794 regmap_update_bits(cs42l42->regmap, CS42L42_SRC_INT_MASK, 1795 CS42L42_SRC_ILK_MASK | 1796 CS42L42_SRC_OLK_MASK | 1797 CS42L42_SRC_IUNLK_MASK | 1798 CS42L42_SRC_OUNLK_MASK, 1799 (1 << CS42L42_SRC_ILK_SHIFT) | 1800 (1 << CS42L42_SRC_OLK_SHIFT) | 1801 (1 << CS42L42_SRC_IUNLK_SHIFT) | 1802 (1 << CS42L42_SRC_OUNLK_SHIFT)); 1803 1804 regmap_update_bits(cs42l42->regmap, CS42L42_ASP_RX_INT_MASK, 1805 CS42L42_ASPRX_NOLRCK_MASK | 1806 CS42L42_ASPRX_EARLY_MASK | 1807 CS42L42_ASPRX_LATE_MASK | 1808 CS42L42_ASPRX_ERROR_MASK | 1809 CS42L42_ASPRX_OVLD_MASK, 1810 (1 << CS42L42_ASPRX_NOLRCK_SHIFT) | 1811 (1 << CS42L42_ASPRX_EARLY_SHIFT) | 1812 (1 << CS42L42_ASPRX_LATE_SHIFT) | 1813 (1 << CS42L42_ASPRX_ERROR_SHIFT) | 1814 (1 << CS42L42_ASPRX_OVLD_SHIFT)); 1815 1816 regmap_update_bits(cs42l42->regmap, CS42L42_ASP_TX_INT_MASK, 1817 CS42L42_ASPTX_NOLRCK_MASK | 1818 CS42L42_ASPTX_EARLY_MASK | 1819 CS42L42_ASPTX_LATE_MASK | 1820 CS42L42_ASPTX_SMERROR_MASK, 1821 (1 << CS42L42_ASPTX_NOLRCK_SHIFT) | 1822 (1 << CS42L42_ASPTX_EARLY_SHIFT) | 1823 (1 << CS42L42_ASPTX_LATE_SHIFT) | 1824 (1 << CS42L42_ASPTX_SMERROR_SHIFT)); 1825 1826 regmap_update_bits(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 1827 CS42L42_PDN_DONE_MASK | 1828 CS42L42_HSDET_AUTO_DONE_MASK, 1829 (1 << CS42L42_PDN_DONE_SHIFT) | 1830 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 1831 1832 regmap_update_bits(cs42l42->regmap, CS42L42_SRCPL_INT_MASK, 1833 CS42L42_SRCPL_ADC_LK_MASK | 1834 CS42L42_SRCPL_DAC_LK_MASK | 1835 CS42L42_SRCPL_ADC_UNLK_MASK | 1836 CS42L42_SRCPL_DAC_UNLK_MASK, 1837 (1 << CS42L42_SRCPL_ADC_LK_SHIFT) | 1838 (1 << CS42L42_SRCPL_DAC_LK_SHIFT) | 1839 (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT) | 1840 (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT)); 1841 1842 regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT1_MASK, 1843 CS42L42_TIP_SENSE_UNPLUG_MASK | 1844 CS42L42_TIP_SENSE_PLUG_MASK | 1845 CS42L42_HSBIAS_SENSE_MASK, 1846 (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT) | 1847 (1 << CS42L42_TIP_SENSE_PLUG_SHIFT) | 1848 (1 << CS42L42_HSBIAS_SENSE_SHIFT)); 1849 1850 regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT2_MASK, 1851 CS42L42_M_DETECT_TF_MASK | 1852 CS42L42_M_DETECT_FT_MASK | 1853 CS42L42_M_HSBIAS_HIZ_MASK | 1854 CS42L42_M_SHORT_RLS_MASK | 1855 CS42L42_M_SHORT_DET_MASK, 1856 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1857 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1858 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1859 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1860 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1861 1862 regmap_update_bits(cs42l42->regmap, CS42L42_VPMON_INT_MASK, 1863 CS42L42_VPMON_MASK, 1864 (1 << CS42L42_VPMON_SHIFT)); 1865 1866 regmap_update_bits(cs42l42->regmap, CS42L42_PLL_LOCK_INT_MASK, 1867 CS42L42_PLL_LOCK_MASK, 1868 (1 << CS42L42_PLL_LOCK_SHIFT)); 1869 1870 regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 1871 CS42L42_RS_PLUG_MASK | 1872 CS42L42_RS_UNPLUG_MASK | 1873 CS42L42_TS_PLUG_MASK | 1874 CS42L42_TS_UNPLUG_MASK, 1875 (1 << CS42L42_RS_PLUG_SHIFT) | 1876 (1 << CS42L42_RS_UNPLUG_SHIFT) | 1877 (0 << CS42L42_TS_PLUG_SHIFT) | 1878 (0 << CS42L42_TS_UNPLUG_SHIFT)); 1879 } 1880 1881 static void cs42l42_setup_hs_type_detect(struct cs42l42_private *cs42l42) 1882 { 1883 unsigned int reg; 1884 1885 cs42l42->hs_type = CS42L42_PLUG_INVALID; 1886 1887 /* 1888 * DETECT_MODE must always be 0 with ADC and HP both off otherwise the 1889 * FILT+ supply will not charge properly. 1890 */ 1891 regmap_update_bits(cs42l42->regmap, CS42L42_MISC_DET_CTL, 1892 CS42L42_DETECT_MODE_MASK, 0); 1893 1894 /* Latch analog controls to VP power domain */ 1895 regmap_update_bits(cs42l42->regmap, CS42L42_MIC_DET_CTL1, 1896 CS42L42_LATCH_TO_VP_MASK | 1897 CS42L42_EVENT_STAT_SEL_MASK | 1898 CS42L42_HS_DET_LEVEL_MASK, 1899 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1900 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1901 (cs42l42->bias_thresholds[0] << 1902 CS42L42_HS_DET_LEVEL_SHIFT)); 1903 1904 /* Remove ground noise-suppression clamps */ 1905 regmap_update_bits(cs42l42->regmap, 1906 CS42L42_HS_CLAMP_DISABLE, 1907 CS42L42_HS_CLAMP_DISABLE_MASK, 1908 (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT)); 1909 1910 /* Enable the tip sense circuit */ 1911 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 1912 CS42L42_TS_INV_MASK, CS42L42_TS_INV_MASK); 1913 1914 regmap_update_bits(cs42l42->regmap, CS42L42_TIPSENSE_CTL, 1915 CS42L42_TIP_SENSE_CTRL_MASK | 1916 CS42L42_TIP_SENSE_INV_MASK | 1917 CS42L42_TIP_SENSE_DEBOUNCE_MASK, 1918 (3 << CS42L42_TIP_SENSE_CTRL_SHIFT) | 1919 (!cs42l42->ts_inv << CS42L42_TIP_SENSE_INV_SHIFT) | 1920 (2 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT)); 1921 1922 /* Save the initial status of the tip sense */ 1923 regmap_read(cs42l42->regmap, 1924 CS42L42_TSRS_PLUG_STATUS, 1925 ®); 1926 cs42l42->plug_state = (((char) reg) & 1927 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >> 1928 CS42L42_TS_PLUG_SHIFT; 1929 } 1930 1931 static const unsigned int threshold_defaults[] = { 1932 CS42L42_HS_DET_LEVEL_15, 1933 CS42L42_HS_DET_LEVEL_8, 1934 CS42L42_HS_DET_LEVEL_4, 1935 CS42L42_HS_DET_LEVEL_1 1936 }; 1937 1938 static int cs42l42_handle_device_data(struct device *dev, 1939 struct cs42l42_private *cs42l42) 1940 { 1941 unsigned int val; 1942 u32 thresholds[CS42L42_NUM_BIASES]; 1943 int ret; 1944 int i; 1945 1946 ret = device_property_read_u32(dev, "cirrus,ts-inv", &val); 1947 if (!ret) { 1948 switch (val) { 1949 case CS42L42_TS_INV_EN: 1950 case CS42L42_TS_INV_DIS: 1951 cs42l42->ts_inv = val; 1952 break; 1953 default: 1954 dev_err(dev, 1955 "Wrong cirrus,ts-inv DT value %d\n", 1956 val); 1957 cs42l42->ts_inv = CS42L42_TS_INV_DIS; 1958 } 1959 } else { 1960 cs42l42->ts_inv = CS42L42_TS_INV_DIS; 1961 } 1962 1963 ret = device_property_read_u32(dev, "cirrus,ts-dbnc-rise", &val); 1964 if (!ret) { 1965 switch (val) { 1966 case CS42L42_TS_DBNCE_0: 1967 case CS42L42_TS_DBNCE_125: 1968 case CS42L42_TS_DBNCE_250: 1969 case CS42L42_TS_DBNCE_500: 1970 case CS42L42_TS_DBNCE_750: 1971 case CS42L42_TS_DBNCE_1000: 1972 case CS42L42_TS_DBNCE_1250: 1973 case CS42L42_TS_DBNCE_1500: 1974 cs42l42->ts_dbnc_rise = val; 1975 break; 1976 default: 1977 dev_err(dev, 1978 "Wrong cirrus,ts-dbnc-rise DT value %d\n", 1979 val); 1980 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000; 1981 } 1982 } else { 1983 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000; 1984 } 1985 1986 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 1987 CS42L42_TS_RISE_DBNCE_TIME_MASK, 1988 (cs42l42->ts_dbnc_rise << 1989 CS42L42_TS_RISE_DBNCE_TIME_SHIFT)); 1990 1991 ret = device_property_read_u32(dev, "cirrus,ts-dbnc-fall", &val); 1992 if (!ret) { 1993 switch (val) { 1994 case CS42L42_TS_DBNCE_0: 1995 case CS42L42_TS_DBNCE_125: 1996 case CS42L42_TS_DBNCE_250: 1997 case CS42L42_TS_DBNCE_500: 1998 case CS42L42_TS_DBNCE_750: 1999 case CS42L42_TS_DBNCE_1000: 2000 case CS42L42_TS_DBNCE_1250: 2001 case CS42L42_TS_DBNCE_1500: 2002 cs42l42->ts_dbnc_fall = val; 2003 break; 2004 default: 2005 dev_err(dev, 2006 "Wrong cirrus,ts-dbnc-fall DT value %d\n", 2007 val); 2008 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0; 2009 } 2010 } else { 2011 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0; 2012 } 2013 2014 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 2015 CS42L42_TS_FALL_DBNCE_TIME_MASK, 2016 (cs42l42->ts_dbnc_fall << 2017 CS42L42_TS_FALL_DBNCE_TIME_SHIFT)); 2018 2019 ret = device_property_read_u32(dev, "cirrus,btn-det-init-dbnce", &val); 2020 if (!ret) { 2021 if (val <= CS42L42_BTN_DET_INIT_DBNCE_MAX) 2022 cs42l42->btn_det_init_dbnce = val; 2023 else { 2024 dev_err(dev, 2025 "Wrong cirrus,btn-det-init-dbnce DT value %d\n", 2026 val); 2027 cs42l42->btn_det_init_dbnce = 2028 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT; 2029 } 2030 } else { 2031 cs42l42->btn_det_init_dbnce = 2032 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT; 2033 } 2034 2035 ret = device_property_read_u32(dev, "cirrus,btn-det-event-dbnce", &val); 2036 if (!ret) { 2037 if (val <= CS42L42_BTN_DET_EVENT_DBNCE_MAX) 2038 cs42l42->btn_det_event_dbnce = val; 2039 else { 2040 dev_err(dev, 2041 "Wrong cirrus,btn-det-event-dbnce DT value %d\n", val); 2042 cs42l42->btn_det_event_dbnce = 2043 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT; 2044 } 2045 } else { 2046 cs42l42->btn_det_event_dbnce = 2047 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT; 2048 } 2049 2050 ret = device_property_read_u32_array(dev, "cirrus,bias-lvls", 2051 thresholds, ARRAY_SIZE(thresholds)); 2052 if (!ret) { 2053 for (i = 0; i < CS42L42_NUM_BIASES; i++) { 2054 if (thresholds[i] <= CS42L42_HS_DET_LEVEL_MAX) 2055 cs42l42->bias_thresholds[i] = thresholds[i]; 2056 else { 2057 dev_err(dev, 2058 "Wrong cirrus,bias-lvls[%d] DT value %d\n", i, 2059 thresholds[i]); 2060 cs42l42->bias_thresholds[i] = threshold_defaults[i]; 2061 } 2062 } 2063 } else { 2064 for (i = 0; i < CS42L42_NUM_BIASES; i++) 2065 cs42l42->bias_thresholds[i] = threshold_defaults[i]; 2066 } 2067 2068 ret = device_property_read_u32(dev, "cirrus,hs-bias-ramp-rate", &val); 2069 if (!ret) { 2070 switch (val) { 2071 case CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL: 2072 cs42l42->hs_bias_ramp_rate = val; 2073 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME0; 2074 break; 2075 case CS42L42_HSBIAS_RAMP_FAST: 2076 cs42l42->hs_bias_ramp_rate = val; 2077 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME1; 2078 break; 2079 case CS42L42_HSBIAS_RAMP_SLOW: 2080 cs42l42->hs_bias_ramp_rate = val; 2081 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 2082 break; 2083 case CS42L42_HSBIAS_RAMP_SLOWEST: 2084 cs42l42->hs_bias_ramp_rate = val; 2085 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME3; 2086 break; 2087 default: 2088 dev_err(dev, 2089 "Wrong cirrus,hs-bias-ramp-rate DT value %d\n", 2090 val); 2091 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW; 2092 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 2093 } 2094 } else { 2095 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW; 2096 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 2097 } 2098 2099 regmap_update_bits(cs42l42->regmap, CS42L42_HS_BIAS_CTL, 2100 CS42L42_HSBIAS_RAMP_MASK, 2101 (cs42l42->hs_bias_ramp_rate << 2102 CS42L42_HSBIAS_RAMP_SHIFT)); 2103 2104 if (device_property_read_bool(dev, "cirrus,hs-bias-sense-disable")) 2105 cs42l42->hs_bias_sense_en = 0; 2106 else 2107 cs42l42->hs_bias_sense_en = 1; 2108 2109 return 0; 2110 } 2111 2112 /* Datasheet suspend sequence */ 2113 static const struct reg_sequence __maybe_unused cs42l42_shutdown_seq[] = { 2114 REG_SEQ0(CS42L42_MIC_DET_CTL1, 0x9F), 2115 REG_SEQ0(CS42L42_ADC_OVFL_INT_MASK, 0x01), 2116 REG_SEQ0(CS42L42_MIXER_INT_MASK, 0x0F), 2117 REG_SEQ0(CS42L42_SRC_INT_MASK, 0x0F), 2118 REG_SEQ0(CS42L42_ASP_RX_INT_MASK, 0x1F), 2119 REG_SEQ0(CS42L42_ASP_TX_INT_MASK, 0x0F), 2120 REG_SEQ0(CS42L42_CODEC_INT_MASK, 0x03), 2121 REG_SEQ0(CS42L42_SRCPL_INT_MASK, 0x7F), 2122 REG_SEQ0(CS42L42_VPMON_INT_MASK, 0x01), 2123 REG_SEQ0(CS42L42_PLL_LOCK_INT_MASK, 0x01), 2124 REG_SEQ0(CS42L42_TSRS_PLUG_INT_MASK, 0x0F), 2125 REG_SEQ0(CS42L42_WAKE_CTL, 0xE1), 2126 REG_SEQ0(CS42L42_DET_INT1_MASK, 0xE0), 2127 REG_SEQ0(CS42L42_DET_INT2_MASK, 0xFF), 2128 REG_SEQ0(CS42L42_MIXER_CHA_VOL, 0x3F), 2129 REG_SEQ0(CS42L42_MIXER_ADC_VOL, 0x3F), 2130 REG_SEQ0(CS42L42_MIXER_CHB_VOL, 0x3F), 2131 REG_SEQ0(CS42L42_HP_CTL, 0x0F), 2132 REG_SEQ0(CS42L42_ASP_RX_DAI0_EN, 0x00), 2133 REG_SEQ0(CS42L42_ASP_CLK_CFG, 0x00), 2134 REG_SEQ0(CS42L42_HSDET_CTL2, 0x00), 2135 REG_SEQ0(CS42L42_PWR_CTL1, 0xFE), 2136 REG_SEQ0(CS42L42_PWR_CTL2, 0x8C), 2137 REG_SEQ0(CS42L42_DAC_CTL2, 0x02), 2138 REG_SEQ0(CS42L42_HS_CLAMP_DISABLE, 0x00), 2139 REG_SEQ0(CS42L42_MISC_DET_CTL, 0x03), 2140 REG_SEQ0(CS42L42_TIPSENSE_CTL, 0x02), 2141 REG_SEQ0(CS42L42_HSBIAS_SC_AUTOCTL, 0x03), 2142 REG_SEQ0(CS42L42_PWR_CTL1, 0xFF) 2143 }; 2144 2145 int cs42l42_suspend(struct device *dev) 2146 { 2147 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev); 2148 unsigned int reg; 2149 u8 save_regs[ARRAY_SIZE(cs42l42_shutdown_seq)]; 2150 int i, ret; 2151 2152 if (!cs42l42->init_done) 2153 return 0; 2154 2155 /* 2156 * Wait for threaded irq handler to be idle and stop it processing 2157 * future interrupts. This ensures a safe disable if the interrupt 2158 * is shared. 2159 */ 2160 scoped_guard(mutex, &cs42l42->irq_lock) { 2161 cs42l42->suspended = true; 2162 2163 /* Save register values that will be overwritten by shutdown sequence */ 2164 for (i = 0; i < ARRAY_SIZE(cs42l42_shutdown_seq); ++i) { 2165 regmap_read(cs42l42->regmap, cs42l42_shutdown_seq[i].reg, ®); 2166 save_regs[i] = (u8)reg; 2167 } 2168 2169 /* Shutdown codec */ 2170 regmap_multi_reg_write(cs42l42->regmap, 2171 cs42l42_shutdown_seq, 2172 ARRAY_SIZE(cs42l42_shutdown_seq)); 2173 2174 /* All interrupt sources are now disabled */ 2175 } 2176 2177 /* Wait for power-down complete */ 2178 msleep(CS42L42_PDN_DONE_TIME_MS); 2179 ret = regmap_read_poll_timeout(cs42l42->regmap, 2180 CS42L42_CODEC_STATUS, reg, 2181 (reg & CS42L42_PDN_DONE_MASK), 2182 CS42L42_PDN_DONE_POLL_US, 2183 CS42L42_PDN_DONE_TIMEOUT_US); 2184 if (ret) 2185 dev_warn(dev, "Failed to get PDN_DONE: %d\n", ret); 2186 2187 /* Discharge FILT+ */ 2188 regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL2, 2189 CS42L42_DISCHARGE_FILT_MASK, CS42L42_DISCHARGE_FILT_MASK); 2190 2191 regcache_cache_only(cs42l42->regmap, true); 2192 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0); 2193 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies); 2194 2195 /* Restore register values to the regmap cache */ 2196 for (i = 0; i < ARRAY_SIZE(cs42l42_shutdown_seq); ++i) 2197 regmap_write(cs42l42->regmap, cs42l42_shutdown_seq[i].reg, save_regs[i]); 2198 2199 /* The cached address page register value is now stale */ 2200 regcache_drop_region(cs42l42->regmap, CS42L42_PAGE_REGISTER, CS42L42_PAGE_REGISTER); 2201 2202 dev_dbg(dev, "System suspended\n"); 2203 2204 return 0; 2205 2206 } 2207 EXPORT_SYMBOL_NS_GPL(cs42l42_suspend, "SND_SOC_CS42L42_CORE"); 2208 2209 int cs42l42_resume(struct device *dev) 2210 { 2211 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev); 2212 int ret; 2213 2214 if (!cs42l42->init_done) 2215 return 0; 2216 2217 /* 2218 * If jack was unplugged and re-plugged during suspend it could 2219 * have changed type but the tip-sense state hasn't changed. 2220 * Force a plugged state to be re-evaluated. 2221 */ 2222 if (cs42l42->plug_state != CS42L42_TS_UNPLUG) 2223 cs42l42->plug_state = CS42L42_TS_TRANS; 2224 2225 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies); 2226 if (ret != 0) { 2227 dev_err(dev, "Failed to enable supplies: %d\n", ret); 2228 return ret; 2229 } 2230 2231 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1); 2232 usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2); 2233 2234 dev_dbg(dev, "System resume powered up\n"); 2235 2236 return 0; 2237 } 2238 EXPORT_SYMBOL_NS_GPL(cs42l42_resume, "SND_SOC_CS42L42_CORE"); 2239 2240 void cs42l42_resume_restore(struct device *dev) 2241 { 2242 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev); 2243 2244 regcache_cache_only(cs42l42->regmap, false); 2245 regcache_mark_dirty(cs42l42->regmap); 2246 2247 scoped_guard(mutex, &cs42l42->irq_lock) { 2248 /* Sync LATCH_TO_VP first so the VP domain registers sync correctly */ 2249 regcache_sync_region(cs42l42->regmap, CS42L42_MIC_DET_CTL1, CS42L42_MIC_DET_CTL1); 2250 regcache_sync(cs42l42->regmap); 2251 2252 cs42l42->suspended = false; 2253 } 2254 2255 dev_dbg(dev, "System resumed\n"); 2256 } 2257 EXPORT_SYMBOL_NS_GPL(cs42l42_resume_restore, "SND_SOC_CS42L42_CORE"); 2258 2259 static int __maybe_unused cs42l42_i2c_resume(struct device *dev) 2260 { 2261 int ret; 2262 2263 ret = cs42l42_resume(dev); 2264 if (ret) 2265 return ret; 2266 2267 cs42l42_resume_restore(dev); 2268 2269 return 0; 2270 } 2271 2272 int cs42l42_common_probe(struct cs42l42_private *cs42l42, 2273 const struct snd_soc_component_driver *component_drv, 2274 struct snd_soc_dai_driver *dai) 2275 { 2276 int ret, i; 2277 2278 dev_set_drvdata(cs42l42->dev, cs42l42); 2279 mutex_init(&cs42l42->irq_lock); 2280 2281 BUILD_BUG_ON(ARRAY_SIZE(cs42l42_supply_names) != ARRAY_SIZE(cs42l42->supplies)); 2282 for (i = 0; i < ARRAY_SIZE(cs42l42->supplies); i++) 2283 cs42l42->supplies[i].supply = cs42l42_supply_names[i]; 2284 2285 ret = devm_regulator_bulk_get(cs42l42->dev, 2286 ARRAY_SIZE(cs42l42->supplies), 2287 cs42l42->supplies); 2288 if (ret != 0) { 2289 dev_err(cs42l42->dev, 2290 "Failed to request supplies: %d\n", ret); 2291 return ret; 2292 } 2293 2294 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies), 2295 cs42l42->supplies); 2296 if (ret != 0) { 2297 dev_err(cs42l42->dev, 2298 "Failed to enable supplies: %d\n", ret); 2299 return ret; 2300 } 2301 2302 /* Reset the Device */ 2303 cs42l42->reset_gpio = devm_gpiod_get_optional(cs42l42->dev, 2304 "reset", GPIOD_OUT_LOW); 2305 if (IS_ERR(cs42l42->reset_gpio)) { 2306 ret = PTR_ERR(cs42l42->reset_gpio); 2307 goto err_disable_noreset; 2308 } 2309 2310 if (cs42l42->reset_gpio) { 2311 dev_dbg(cs42l42->dev, "Found reset GPIO\n"); 2312 2313 /* 2314 * ACPI can override the default GPIO state we requested 2315 * so ensure that we start with RESET low. 2316 */ 2317 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0); 2318 2319 /* Ensure minimum reset pulse width */ 2320 usleep_range(10, 500); 2321 2322 /* 2323 * On SoundWire keep the chip in reset until we get an UNATTACH 2324 * notification from the SoundWire core. This acts as a 2325 * synchronization point to reject stale ATTACH notifications 2326 * if the chip was already enumerated before we reset it. 2327 */ 2328 if (cs42l42->sdw_peripheral) 2329 cs42l42->sdw_waiting_first_unattach = true; 2330 else 2331 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1); 2332 } 2333 usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2); 2334 2335 /* Request IRQ if one was specified */ 2336 if (cs42l42->irq) { 2337 ret = request_threaded_irq(cs42l42->irq, 2338 NULL, cs42l42_irq_thread, 2339 IRQF_ONESHOT | IRQF_TRIGGER_LOW, 2340 "cs42l42", cs42l42); 2341 if (ret) { 2342 dev_err_probe(cs42l42->dev, ret, 2343 "Failed to request IRQ\n"); 2344 goto err_disable_noirq; 2345 } 2346 } 2347 2348 /* Register codec now so it can EPROBE_DEFER */ 2349 ret = devm_snd_soc_register_component(cs42l42->dev, component_drv, dai, 1); 2350 if (ret < 0) 2351 goto err; 2352 2353 return 0; 2354 2355 err: 2356 if (cs42l42->irq) 2357 free_irq(cs42l42->irq, cs42l42); 2358 2359 err_disable_noirq: 2360 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0); 2361 err_disable_noreset: 2362 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies); 2363 2364 return ret; 2365 } 2366 EXPORT_SYMBOL_NS_GPL(cs42l42_common_probe, "SND_SOC_CS42L42_CORE"); 2367 2368 int cs42l42_init(struct cs42l42_private *cs42l42) 2369 { 2370 unsigned int reg; 2371 int devid, ret; 2372 2373 /* initialize codec */ 2374 devid = cirrus_read_device_id(cs42l42->regmap, CS42L42_DEVID_AB); 2375 if (devid < 0) { 2376 ret = devid; 2377 dev_err(cs42l42->dev, "Failed to read device ID: %d\n", ret); 2378 goto err_disable; 2379 } 2380 2381 if (devid != cs42l42->devid) { 2382 ret = -ENODEV; 2383 dev_err(cs42l42->dev, 2384 "CS42L%x Device ID (%X). Expected %X\n", 2385 cs42l42->devid & 0xff, devid, cs42l42->devid); 2386 goto err_disable; 2387 } 2388 2389 ret = regmap_read(cs42l42->regmap, CS42L42_REVID, ®); 2390 if (ret < 0) { 2391 dev_err(cs42l42->dev, "Get Revision ID failed\n"); 2392 goto err_shutdown; 2393 } 2394 2395 dev_info(cs42l42->dev, 2396 "Cirrus Logic CS42L%x, Revision: %02X\n", 2397 cs42l42->devid & 0xff, reg & 0xFF); 2398 2399 /* Power up the codec */ 2400 regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL1, 2401 CS42L42_ASP_DAO_PDN_MASK | 2402 CS42L42_ASP_DAI_PDN_MASK | 2403 CS42L42_MIXER_PDN_MASK | 2404 CS42L42_EQ_PDN_MASK | 2405 CS42L42_HP_PDN_MASK | 2406 CS42L42_ADC_PDN_MASK | 2407 CS42L42_PDN_ALL_MASK, 2408 (1 << CS42L42_ASP_DAO_PDN_SHIFT) | 2409 (1 << CS42L42_ASP_DAI_PDN_SHIFT) | 2410 (1 << CS42L42_MIXER_PDN_SHIFT) | 2411 (1 << CS42L42_EQ_PDN_SHIFT) | 2412 (1 << CS42L42_HP_PDN_SHIFT) | 2413 (1 << CS42L42_ADC_PDN_SHIFT) | 2414 (0 << CS42L42_PDN_ALL_SHIFT)); 2415 2416 ret = cs42l42_handle_device_data(cs42l42->dev, cs42l42); 2417 if (ret != 0) 2418 goto err_shutdown; 2419 2420 /* 2421 * SRC power is linked to ASP power so doesn't work in Soundwire mode. 2422 * Override it and use DAPM to control SRC power for Soundwire. 2423 */ 2424 if (cs42l42->sdw_peripheral) { 2425 regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL2, 2426 CS42L42_SRC_PDN_OVERRIDE_MASK | 2427 CS42L42_DAC_SRC_PDNB_MASK | 2428 CS42L42_ADC_SRC_PDNB_MASK, 2429 CS42L42_SRC_PDN_OVERRIDE_MASK); 2430 } 2431 2432 /* Setup headset detection */ 2433 cs42l42_setup_hs_type_detect(cs42l42); 2434 2435 /* 2436 * Set init_done before unmasking interrupts so any triggered 2437 * immediately will be handled. 2438 */ 2439 cs42l42->init_done = true; 2440 2441 /* Mask/Unmask Interrupts */ 2442 cs42l42_set_interrupt_masks(cs42l42); 2443 2444 return 0; 2445 2446 err_shutdown: 2447 regmap_write(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 0xff); 2448 regmap_write(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 0xff); 2449 regmap_write(cs42l42->regmap, CS42L42_PWR_CTL1, 0xff); 2450 2451 err_disable: 2452 if (cs42l42->irq) 2453 free_irq(cs42l42->irq, cs42l42); 2454 2455 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0); 2456 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), 2457 cs42l42->supplies); 2458 return ret; 2459 } 2460 EXPORT_SYMBOL_NS_GPL(cs42l42_init, "SND_SOC_CS42L42_CORE"); 2461 2462 void cs42l42_common_remove(struct cs42l42_private *cs42l42) 2463 { 2464 if (cs42l42->irq) 2465 free_irq(cs42l42->irq, cs42l42); 2466 2467 /* 2468 * The driver might not have control of reset and power supplies, 2469 * so ensure that the chip internals are powered down. 2470 */ 2471 if (cs42l42->init_done) { 2472 regmap_write(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 0xff); 2473 regmap_write(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 0xff); 2474 regmap_write(cs42l42->regmap, CS42L42_PWR_CTL1, 0xff); 2475 } 2476 2477 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0); 2478 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies); 2479 } 2480 EXPORT_SYMBOL_NS_GPL(cs42l42_common_remove, "SND_SOC_CS42L42_CORE"); 2481 2482 MODULE_DESCRIPTION("ASoC CS42L42 driver"); 2483 MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>"); 2484 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>"); 2485 MODULE_AUTHOR("Michael White, Cirrus Logic Inc, <michael.white@cirrus.com>"); 2486 MODULE_AUTHOR("Lucas Tanure <tanureal@opensource.cirrus.com>"); 2487 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>"); 2488 MODULE_AUTHOR("Vitaly Rodionov <vitalyr@opensource.cirrus.com>"); 2489 MODULE_LICENSE("GPL"); 2490