1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // rt1320-sdw.c -- rt1320 SDCA ALSA SoC amplifier audio driver
4 //
5 // Copyright(c) 2024 Realtek Semiconductor Corp.
6 //
7 //
8 #include <linux/delay.h>
9 #include <linux/device.h>
10 #include <linux/pm_runtime.h>
11 #include <linux/module.h>
12 #include <linux/regmap.h>
13 #include <linux/dmi.h>
14 #include <linux/firmware.h>
15 #include <sound/core.h>
16 #include <sound/pcm.h>
17 #include <sound/pcm_params.h>
18 #include <sound/soc-dapm.h>
19 #include <sound/initval.h>
20 #include <sound/tlv.h>
21 #include <sound/sdw.h>
22 #include "rt1320-sdw.h"
23 #include "rt-sdw-common.h"
24
25 /*
26 * The 'blind writes' is an SDCA term to deal with platform-specific initialization.
27 * It might include vendor-specific or SDCA control registers.
28 */
29 static const struct reg_sequence rt1320_blind_write[] = {
30 { 0xc003, 0xe0 },
31 { 0xc01b, 0xfc },
32 { 0xc5c3, 0xf2 },
33 { 0xc5c2, 0x00 },
34 { 0xc5c6, 0x10 },
35 { 0xc5c4, 0x12 },
36 { 0xc5c8, 0x03 },
37 { 0xc5d8, 0x0a },
38 { 0xc5f7, 0x22 },
39 { 0xc5f6, 0x22 },
40 { 0xc5d0, 0x0f },
41 { 0xc5d1, 0x89 },
42 { 0xc057, 0x51 },
43 { 0xc054, 0x35 },
44 { 0xc053, 0x55 },
45 { 0xc052, 0x55 },
46 { 0xc051, 0x13 },
47 { 0xc050, 0x15 },
48 { 0xc060, 0x77 },
49 { 0xc061, 0x55 },
50 { 0xc063, 0x55 },
51 { 0xc065, 0xa5 },
52 { 0xc06b, 0x0a },
53 { 0xca05, 0xd6 },
54 { 0xca25, 0xd6 },
55 { 0xcd00, 0x05 },
56 { 0xc604, 0x40 },
57 { 0xc609, 0x40 },
58 { 0xc046, 0xff },
59 { 0xc045, 0xff },
60 { 0xc044, 0xff },
61 { 0xc043, 0xff },
62 { 0xc042, 0xff },
63 { 0xc041, 0xff },
64 { 0xc040, 0xff },
65 { 0xcc10, 0x01 },
66 { 0xc700, 0xf0 },
67 { 0xc701, 0x13 },
68 { 0xc901, 0x04 },
69 { 0xc900, 0x73 },
70 { 0xde03, 0x05 },
71 { 0xdd0b, 0x0d },
72 { 0xdd0a, 0xff },
73 { 0xdd09, 0x0d },
74 { 0xdd08, 0xff },
75 { 0xc570, 0x08 },
76 { 0xe803, 0xbe },
77 { 0xc003, 0xc0 },
78 { 0xc081, 0xfe },
79 { 0xce31, 0x0d },
80 { 0xce30, 0xae },
81 { 0xce37, 0x0b },
82 { 0xce36, 0xd2 },
83 { 0xce39, 0x04 },
84 { 0xce38, 0x80 },
85 { 0xce3f, 0x00 },
86 { 0xce3e, 0x00 },
87 { 0xd470, 0x8b },
88 { 0xd471, 0x18 },
89 { 0xc019, 0x10 },
90 { 0xd487, 0x3f },
91 { 0xd486, 0xc3 },
92 { 0x3fc2bfc7, 0x00 },
93 { 0x3fc2bfc6, 0x00 },
94 { 0x3fc2bfc5, 0x00 },
95 { 0x3fc2bfc4, 0x01 },
96 { 0x0000d486, 0x43 },
97 { 0x1000db00, 0x02 },
98 { 0x1000db01, 0x00 },
99 { 0x1000db02, 0x11 },
100 { 0x1000db03, 0x00 },
101 { 0x1000db04, 0x00 },
102 { 0x1000db05, 0x82 },
103 { 0x1000db06, 0x04 },
104 { 0x1000db07, 0xf1 },
105 { 0x1000db08, 0x00 },
106 { 0x1000db09, 0x00 },
107 { 0x1000db0a, 0x40 },
108 { 0x0000d540, 0x01 },
109 { 0xd172, 0x2a },
110 { 0xc5d6, 0x01 },
111 { 0xd478, 0xff },
112 };
113
114 static const struct reg_sequence rt1320_vc_blind_write[] = {
115 { 0xc003, 0xe0 },
116 { 0xe80a, 0x01 },
117 { 0xc5c3, 0xf2 },
118 { 0xc5c8, 0x03 },
119 { 0xc057, 0x51 },
120 { 0xc054, 0x35 },
121 { 0xca05, 0xd6 },
122 { 0xca07, 0x07 },
123 { 0xca25, 0xd6 },
124 { 0xca27, 0x07 },
125 { 0xc604, 0x40 },
126 { 0xc609, 0x40 },
127 { 0xc046, 0xff },
128 { 0xc045, 0xff },
129 { 0xc044, 0xff },
130 { 0xc043, 0xff },
131 { 0xc042, 0xff },
132 { 0xc041, 0x7f },
133 { 0xc040, 0xff },
134 { 0xcc10, 0x01 },
135 { 0xc700, 0xf0 },
136 { 0xc701, 0x13 },
137 { 0xc901, 0x04 },
138 { 0xc900, 0x73 },
139 { 0xde03, 0x05 },
140 { 0xdd0b, 0x0d },
141 { 0xdd0a, 0xff },
142 { 0xdd09, 0x0d },
143 { 0xdd08, 0xff },
144 { 0xc570, 0x08 },
145 { 0xc086, 0x02 },
146 { 0xc085, 0x7f },
147 { 0xc084, 0x00 },
148 { 0xc081, 0xfe },
149 { 0xf084, 0x0f },
150 { 0xf083, 0xff },
151 { 0xf082, 0xff },
152 { 0xf081, 0xff },
153 { 0xf080, 0xff },
154 { 0xe801, 0x01 },
155 { 0xe802, 0xf8 },
156 { 0xe803, 0xbe },
157 { 0xc003, 0xc0 },
158 { 0xd470, 0xec },
159 { 0xd471, 0x3a },
160 { 0xd474, 0x11 },
161 { 0xd475, 0x32 },
162 { 0xd478, 0xff },
163 { 0xd479, 0x20 },
164 { 0xd47a, 0x10 },
165 { 0xd47c, 0xff },
166 { 0xc019, 0x10 },
167 { 0xd487, 0x0b },
168 { 0xd487, 0x3b },
169 { 0xd486, 0xc3 },
170 { 0xc598, 0x04 },
171 { 0xdb03, 0xf0 },
172 { 0xdb09, 0x00 },
173 { 0xdb08, 0x7a },
174 { 0xdb19, 0x02 },
175 { 0xdb07, 0x5a },
176 { 0xdb05, 0x45 },
177 { 0xd500, 0x00 },
178 { 0xd500, 0x17 },
179 { 0xd600, 0x01 },
180 { 0xd601, 0x02 },
181 { 0xd602, 0x03 },
182 { 0xd603, 0x04 },
183 { 0xd64c, 0x03 },
184 { 0xd64d, 0x03 },
185 { 0xd64e, 0x03 },
186 { 0xd64f, 0x03 },
187 { 0xd650, 0x03 },
188 { 0xd651, 0x03 },
189 { 0xd652, 0x03 },
190 { 0xd610, 0x01 },
191 { 0xd608, 0x03 },
192 { 0xd609, 0x00 },
193 { 0x3fc2bf83, 0x00 },
194 { 0x3fc2bf82, 0x00 },
195 { 0x3fc2bf81, 0x00 },
196 { 0x3fc2bf80, 0x00 },
197 { 0x3fc2bfc7, 0x00 },
198 { 0x3fc2bfc6, 0x00 },
199 { 0x3fc2bfc5, 0x00 },
200 { 0x3fc2bfc4, 0x00 },
201 { 0x3fc2bfc3, 0x00 },
202 { 0x3fc2bfc2, 0x00 },
203 { 0x3fc2bfc1, 0x00 },
204 { 0x3fc2bfc0, 0x07 },
205 { 0x1000cc46, 0x00 },
206 { 0x0000d486, 0x43 },
207 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00 },
208 { 0x1000db00, 0x07 },
209 { 0x1000db01, 0x00 },
210 { 0x1000db02, 0x11 },
211 { 0x1000db03, 0x00 },
212 { 0x1000db04, 0x00 },
213 { 0x1000db05, 0x82 },
214 { 0x1000db06, 0x04 },
215 { 0x1000db07, 0xf1 },
216 { 0x1000db08, 0x00 },
217 { 0x1000db09, 0x00 },
218 { 0x1000db0a, 0x40 },
219 { 0x1000db0b, 0x02 },
220 { 0x1000db0c, 0xf2 },
221 { 0x1000db0d, 0x00 },
222 { 0x1000db0e, 0x00 },
223 { 0x1000db0f, 0xe0 },
224 { 0x1000db10, 0x00 },
225 { 0x1000db11, 0x10 },
226 { 0x1000db12, 0x00 },
227 { 0x1000db13, 0x00 },
228 { 0x1000db14, 0x45 },
229 { 0x1000db15, 0x0d },
230 { 0x1000db16, 0x01 },
231 { 0x1000db17, 0x00 },
232 { 0x1000db18, 0x00 },
233 { 0x1000db19, 0xbf },
234 { 0x1000db1a, 0x13 },
235 { 0x1000db1b, 0x09 },
236 { 0x1000db1c, 0x00 },
237 { 0x1000db1d, 0x00 },
238 { 0x1000db1e, 0x00 },
239 { 0x1000db1f, 0x12 },
240 { 0x1000db20, 0x09 },
241 { 0x1000db21, 0x00 },
242 { 0x1000db22, 0x00 },
243 { 0x1000db23, 0x00 },
244 { 0x0000d540, 0x21 },
245 { 0xc01b, 0xfc },
246 { 0xc5d1, 0x89 },
247 { 0xc5d8, 0x0a },
248 { 0xc5f7, 0x22 },
249 { 0xc5f6, 0x22 },
250 { 0xc065, 0xa5 },
251 { 0xc06b, 0x0a },
252 { 0xd172, 0x2a },
253 { 0xc5d6, 0x01 },
254 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
255 };
256
257 static const struct reg_sequence rt1321_blind_write[] = {
258 { 0x0000c003, 0xf0 },
259 { 0x0000c01b, 0xfc },
260 { 0x0000c5c3, 0xf2 },
261 { 0x0000c5c2, 0x00 },
262 { 0x0000c5c1, 0x10 },
263 { 0x0000c5c0, 0x04 },
264 { 0x0000c5c7, 0x03 },
265 { 0x0000c5c6, 0x10 },
266 { 0x0000c526, 0x47 },
267 { 0x0000c5c4, 0x12 },
268 { 0x0000c5c5, 0x60 },
269 { 0x0000c520, 0x10 },
270 { 0x0000c521, 0x32 },
271 { 0x0000c5c7, 0x00 },
272 { 0x0000c5c8, 0x03 },
273 { 0x0000c5d3, 0x08 },
274 { 0x0000c5d2, 0x0a },
275 { 0x0000c5d1, 0x49 },
276 { 0x0000c5d0, 0x0f },
277 { 0x0000c580, 0x10 },
278 { 0x0000c581, 0x32 },
279 { 0x0000c582, 0x01 },
280 { 0x0000cb00, 0x03 },
281 { 0x0000cb02, 0x52 },
282 { 0x0000cb04, 0x80 },
283 { 0x0000cb0b, 0x01 },
284 { 0x0000c682, 0x60 },
285 { 0x0000c019, 0x10 },
286 { 0x0000c5f0, 0x01 },
287 { 0x0000c5f7, 0x22 },
288 { 0x0000c5f6, 0x22 },
289 { 0x0000c057, 0x51 },
290 { 0x0000c054, 0x55 },
291 { 0x0000c053, 0x55 },
292 { 0x0000c052, 0x55 },
293 { 0x0000c051, 0x01 },
294 { 0x0000c050, 0x15 },
295 { 0x0000c060, 0x99 },
296 { 0x0000c030, 0x55 },
297 { 0x0000c061, 0x55 },
298 { 0x0000c063, 0x55 },
299 { 0x0000c065, 0xa5 },
300 { 0x0000c06b, 0x0a },
301 { 0x0000ca05, 0xd6 },
302 { 0x0000ca07, 0x07 },
303 { 0x0000ca25, 0xd6 },
304 { 0x0000ca27, 0x07 },
305 { 0x0000cd00, 0x05 },
306 { 0x0000c604, 0x40 },
307 { 0x0000c609, 0x40 },
308 { 0x0000c046, 0xf7 },
309 { 0x0000c045, 0xff },
310 { 0x0000c044, 0xff },
311 { 0x0000c043, 0xff },
312 { 0x0000c042, 0xff },
313 { 0x0000c041, 0xff },
314 { 0x0000c040, 0xff },
315 { 0x0000c049, 0xff },
316 { 0x0000c028, 0x3f },
317 { 0x0000c020, 0x3f },
318 { 0x0000c032, 0x13 },
319 { 0x0000c033, 0x01 },
320 { 0x0000cc10, 0x01 },
321 { 0x0000dc20, 0x03 },
322 { 0x0000de03, 0x05 },
323 { 0x0000dc00, 0x00 },
324 { 0x0000c700, 0xf0 },
325 { 0x0000c701, 0x13 },
326 { 0x0000c900, 0xc3 },
327 { 0x0000c570, 0x08 },
328 { 0x0000c086, 0x02 },
329 { 0x0000c085, 0x7f },
330 { 0x0000c084, 0x00 },
331 { 0x0000c081, 0xff },
332 { 0x0000f084, 0x0f },
333 { 0x0000f083, 0xff },
334 { 0x0000f082, 0xff },
335 { 0x0000f081, 0xff },
336 { 0x0000f080, 0xff },
337 { 0x20003003, 0x3f },
338 { 0x20005818, 0x81 },
339 { 0x20009018, 0x81 },
340 { 0x2000301c, 0x81 },
341 { 0x0000c003, 0xc0 },
342 { 0x0000c047, 0x80 },
343 { 0x0000d541, 0x80 },
344 { 0x0000d487, 0x0b },
345 { 0x0000d487, 0x3b },
346 { 0x0000d486, 0xc3 },
347 { 0x0000d470, 0x89 },
348 { 0x0000d471, 0x3a },
349 { 0x0000d472, 0x1d },
350 { 0x0000d478, 0xff },
351 { 0x0000d479, 0x20 },
352 { 0x0000d47a, 0x10 },
353 { 0x0000d73c, 0xb7 },
354 { 0x0000d73d, 0xd7 },
355 { 0x0000d73e, 0x00 },
356 { 0x0000d73f, 0x10 },
357 { 0x1000cd56, 0x00 },
358 { 0x3fc2dfc3, 0x00 },
359 { 0x3fc2dfc2, 0x00 },
360 { 0x3fc2dfc1, 0x00 },
361 { 0x3fc2dfc0, 0x07 },
362 { 0x3fc2dfc7, 0x00 },
363 { 0x3fc2dfc6, 0x00 },
364 { 0x3fc2dfc5, 0x00 },
365 { 0x3fc2dfc4, 0x01 },
366 { 0x3fc2df83, 0x00 },
367 { 0x3fc2df82, 0x00 },
368 { 0x3fc2df81, 0x00 },
369 { 0x3fc2df80, 0x00 },
370 { 0x0000d541, 0x40 },
371 { 0x0000d486, 0x43 },
372 { 0x1000db00, 0x03 },
373 { 0x1000db01, 0x00 },
374 { 0x1000db02, 0x10 },
375 { 0x1000db03, 0x00 },
376 { 0x1000db04, 0x00 },
377 { 0x1000db05, 0x45 },
378 { 0x1000db06, 0x12 },
379 { 0x1000db07, 0x09 },
380 { 0x1000db08, 0x00 },
381 { 0x1000db09, 0x00 },
382 { 0x1000db0a, 0x00 },
383 { 0x1000db0b, 0x13 },
384 { 0x1000db0c, 0x09 },
385 { 0x1000db0d, 0x00 },
386 { 0x1000db0e, 0x00 },
387 { 0x1000db0f, 0x00 },
388 { 0x0000d540, 0x21 },
389 { 0x41000189, 0x00 },
390 { 0x4100018a, 0x00 },
391 { 0x41001988, 0x00 },
392 { 0x41081400, 0x09 },
393 { 0x40801508, 0x03 },
394 { 0x40801588, 0x03 },
395 { 0x40801809, 0x00 },
396 { 0x4080180a, 0x00 },
397 { 0x4080180b, 0x00 },
398 { 0x4080180c, 0x00 },
399 { 0x40801b09, 0x00 },
400 { 0x40801b0a, 0x00 },
401 { 0x40801b0b, 0x00 },
402 { 0x40801b0c, 0x00 },
403 { 0x0000d714, 0x17 },
404 { 0x20009012, 0x00 },
405 { 0x0000dd0b, 0x0d },
406 { 0x0000dd0a, 0xff },
407 { 0x0000dd09, 0x0d },
408 { 0x0000dd08, 0xff },
409 { 0x0000d172, 0x2a },
410 { 0x41001988, 0x03 },
411 };
412
413 static const struct reg_sequence rt1321_va1_blind_write[] = {
414 { 0x0000c003, 0xf0 },
415 { 0x0000c01b, 0xfc },
416 { 0x0000c5c3, 0xf2 },
417 { 0x0000c5c2, 0x00 },
418 { 0x0000c5c1, 0x10 },
419 { 0x0000c5c0, 0x04 },
420 { 0x0000c5c7, 0x03 },
421 { 0x0000c5c6, 0x10 },
422 { 0x0000c526, 0x47 },
423 { 0x0000c5c4, 0x12 },
424 { 0x0000c5c5, 0x60 },
425 { 0x0000c520, 0x10 },
426 { 0x0000c521, 0x32 },
427 { 0x0000c5c7, 0x00 },
428 { 0x0000c5c8, 0x03 },
429 { 0x0000c5d3, 0x08 },
430 { 0x0000c5d2, 0x0a },
431 { 0x0000c5d1, 0x49 },
432 { 0x0000c5d0, 0x0f },
433 { 0x0000c580, 0x10 },
434 { 0x0000c581, 0x32 },
435 { 0x0000c582, 0x01 },
436 { 0x0000c682, 0x60 },
437 { 0x0000c019, 0x10 },
438 { 0x0000c5f0, 0x01 },
439 { 0x0000c5f7, 0x22 },
440 { 0x0000c5f6, 0x22 },
441 { 0x0000c057, 0x51 },
442 { 0x0000c054, 0x55 },
443 { 0x0000c053, 0x55 },
444 { 0x0000c052, 0x55 },
445 { 0x0000c051, 0x01 },
446 { 0x0000c050, 0x15 },
447 { 0x0000c060, 0x99 },
448 { 0x0000c030, 0x55 },
449 { 0x0000c061, 0x55 },
450 { 0x0000c063, 0x55 },
451 { 0x0000c065, 0xa5 },
452 { 0x0000c06b, 0x0a },
453 { 0x0000ca05, 0xd6 },
454 { 0x0000ca06, 0x11 },
455 { 0x0000ca07, 0x1e },
456 { 0x0000ca25, 0xd6 },
457 { 0x0000ca26, 0x11 },
458 { 0x0000ca27, 0x1e },
459 { 0x0000cd00, 0x05 },
460 { 0x0000cd81, 0x49 },
461 { 0x0000cd82, 0x49 },
462 { 0x0000c604, 0x40 },
463 { 0x0000c609, 0x40 },
464 { 0x0000c046, 0xf7 },
465 { 0x0000c045, 0xff },
466 { 0x0000c044, 0xff },
467 { 0x0000c043, 0xff },
468 { 0x0000c042, 0xff },
469 { 0x0000c041, 0xff },
470 { 0x0000c040, 0xff },
471 { 0x0000c049, 0xff },
472 { 0x0000c028, 0x3f },
473 { 0x0000c020, 0x3f },
474 { 0x0000c032, 0x13 },
475 { 0x0000c033, 0x01 },
476 { 0x0000cc10, 0x01 },
477 { 0x0000dc20, 0x03 },
478 { 0x0000de03, 0x05 },
479 { 0x0000dc00, 0x00 },
480 { 0x0000c700, 0xf0 },
481 { 0x0000c701, 0x13 },
482 { 0x0000c900, 0xc3 },
483 { 0x0000c570, 0x08 },
484 { 0x0000c086, 0x02 },
485 { 0x0000c085, 0x7f },
486 { 0x0000c084, 0x00 },
487 { 0x0000c081, 0xff },
488 { 0x0000f084, 0x0f },
489 { 0x0000f083, 0xff },
490 { 0x0000f082, 0xff },
491 { 0x0000f081, 0xff },
492 { 0x0000f080, 0xff },
493 { 0x20003003, 0x3f },
494 { 0x20005818, 0x81 },
495 { 0x20009018, 0x81 },
496 { 0x2000301c, 0x81 },
497 { 0x0000c003, 0xc0 },
498 { 0x0000c047, 0x80 },
499 { 0x0000d541, 0x80 },
500 { 0x0000d487, 0x0b },
501 { 0x0000d487, 0x3b },
502 { 0x0000d486, 0xc3 },
503 { 0x0000d470, 0x89 },
504 { 0x0000d471, 0x3a },
505 { 0x0000d472, 0x3d },
506 { 0x0000d474, 0x11 },
507 { 0x0000d475, 0x32 },
508 { 0x0000d476, 0x64 },
509 { 0x0000d477, 0x10 },
510 { 0x0000d478, 0xff },
511 { 0x0000d479, 0x20 },
512 { 0x0000d47a, 0x10 },
513 { 0x0000d73c, 0xb7 },
514 { 0x0000d73d, 0xd7 },
515 { 0x0000d73e, 0x00 },
516 { 0x0000d73f, 0x10 },
517 { 0x1000cd56, 0x00 },
518 { 0x3fc2dfc0, 0x03 },
519 { 0x3fc2dfc1, 0x00 },
520 { 0x3fc2dfc2, 0x00 },
521 { 0x3fc2dfc3, 0x00 },
522 { 0x3fc2dfc4, 0x01 },
523 { 0x3fc2dfc5, 0x00 },
524 { 0x3fc2dfc6, 0x00 },
525 { 0x3fc2dfc7, 0x00 },
526 { 0x3fc2df80, 0x00 },
527 { 0x3fc2df81, 0x00 },
528 { 0x3fc2df82, 0x00 },
529 { 0x3fc2df83, 0x00 },
530 { 0x0000d541, 0x40 },
531 { 0x0000d486, 0x43 },
532 { 0x1000db00, 0x04 },
533 { 0x1000db01, 0x00 },
534 { 0x1000db02, 0x10 },
535 { 0x1000db03, 0x00 },
536 { 0x1000db04, 0x00 },
537 { 0x1000db05, 0x45 },
538 { 0x1000db06, 0x0d },
539 { 0x1000db07, 0x01 },
540 { 0x1000db08, 0x00 },
541 { 0x1000db09, 0x00 },
542 { 0x1000db0a, 0xbf },
543 { 0x1000db0b, 0x0b },
544 { 0x1000db0c, 0x11 },
545 { 0x1000db0d, 0x00 },
546 { 0x1000db0e, 0x00 },
547 { 0x1000db0f, 0x00 },
548 { 0x1000db10, 0x2c },
549 { 0x1000db11, 0xfa },
550 { 0x1000db12, 0x00 },
551 { 0x1000db13, 0x00 },
552 { 0x1000db14, 0x09 },
553 { 0x0000d540, 0x21 },
554 { 0x0000c570, 0x08 },
555 { 0x0000d714, 0x17 },
556 { 0x0000c5c3, 0xf2 },
557 { 0x0000c5c8, 0x03 },
558 { 0x20009012, 0x00 },
559 { 0x0000dd08, 0x17 },
560 { 0x0000dd09, 0x0e },
561 { 0x0000dd0a, 0x17 },
562 { 0x0000dd0b, 0x0e },
563 { 0x0000c570, 0x08 },
564 { 0x0000d471, 0x3a },
565 { 0x0000db00, 0x00 },
566 { 0x0000db01, 0x00 },
567 { 0x0000db02, 0x73 },
568 { 0x0000db03, 0x00 },
569 { 0x0000db04, 0x00 },
570 { 0x0000db05, 0x00 },
571 { 0x0000db06, 0x00 },
572 { 0x0000db07, 0x00 },
573 { 0x0000db08, 0x7f },
574 { 0x0000db09, 0x00 },
575 { 0x0000db1a, 0x00 },
576 { 0x0000db1b, 0x00 },
577 { 0x0000db19, 0x00 },
578 };
579
580 static const struct reg_sequence rt1321_va2_blind_write[] = {
581 { 0x0000c003, 0xf0 },
582 { 0x0000c01b, 0xfc },
583 { 0x0000c5c3, 0xf2 },
584 { 0x0000c5c2, 0x00 },
585 { 0x0000c5c1, 0x10 },
586 { 0x0000c5c0, 0x04 },
587 { 0x0000c5c7, 0x03 },
588 { 0x0000c5c6, 0x10 },
589 { 0x0000c526, 0x47 },
590 { 0x0000c5c4, 0x12 },
591 { 0x0000c5c5, 0x60 },
592 { 0x0000c520, 0x10 },
593 { 0x0000c521, 0x32 },
594 { 0x0000c5c7, 0x00 },
595 { 0x0000c5c8, 0x03 },
596 { 0x0000c5d3, 0x08 },
597 { 0x0000c5d2, 0x0a },
598 { 0x0000c5d1, 0x49 },
599 { 0x0000c5d0, 0x0f },
600 { 0x0000c580, 0x10 },
601 { 0x0000c581, 0x32 },
602 { 0x0000c582, 0x01 },
603 { 0x0000c682, 0x60 },
604 { 0x0000c019, 0x10 },
605 { 0x0000c5f0, 0x01 },
606 { 0x0000c5f7, 0x22 },
607 { 0x0000c5f6, 0x22 },
608 { 0x0000c057, 0x51 },
609 { 0x0000c054, 0x55 },
610 { 0x0000c053, 0x55 },
611 { 0x0000c052, 0x55 },
612 { 0x0000c051, 0x01 },
613 { 0x0000c050, 0x15 },
614 { 0x0000c060, 0x99 },
615 { 0x0000c030, 0x55 },
616 { 0x0000c061, 0x55 },
617 { 0x0000c063, 0x55 },
618 { 0x0000c065, 0xa5 },
619 { 0x0000c06b, 0x0a },
620 { 0x0000ca05, 0xd6 },
621 { 0x0000ca06, 0x11 },
622 { 0x0000ca07, 0x1e },
623 { 0x0000ca25, 0xd6 },
624 { 0x0000ca26, 0x11 },
625 { 0x0000ca27, 0x1e },
626 { 0x0000cd00, 0x05 },
627 { 0x0000cd81, 0x49 },
628 { 0x0000cd82, 0x49 },
629 { 0x0000c604, 0x40 },
630 { 0x0000c609, 0x40 },
631 { 0x0000c046, 0xf7 },
632 { 0x0000c045, 0xff },
633 { 0x0000c044, 0xff },
634 { 0x0000c043, 0xff },
635 { 0x0000c042, 0xff },
636 { 0x0000c041, 0xff },
637 { 0x0000c040, 0xff },
638 { 0x0000c049, 0xff },
639 { 0x0000c028, 0x3f },
640 { 0x0000c020, 0x3f },
641 { 0x0000c032, 0x13 },
642 { 0x0000c033, 0x01 },
643 { 0x0000cc10, 0x01 },
644 { 0x0000dc20, 0x03 },
645 { 0x0000de03, 0x05 },
646 { 0x0000dc00, 0x00 },
647 { 0x0000c700, 0xf0 },
648 { 0x0000c701, 0x13 },
649 { 0x0000c900, 0xc3 },
650 { 0x0000c570, 0x08 },
651 { 0x0000c086, 0x02 },
652 { 0x0000c085, 0x7f },
653 { 0x0000c084, 0x00 },
654 { 0x0000c081, 0xff },
655 { 0x0000f084, 0x0f },
656 { 0x0000f083, 0xff },
657 { 0x0000f082, 0xff },
658 { 0x0000f081, 0xff },
659 { 0x0000f080, 0xff },
660 { 0x20003003, 0x3f },
661 { 0x20005818, 0x81 },
662 { 0x20009018, 0x81 },
663 { 0x2000301c, 0x81 },
664 { 0x0000c003, 0xc0 },
665 { 0x0000c047, 0x80 },
666 { 0x0000d541, 0x80 },
667 { 0x0000d487, 0x0b },
668 { 0x0000d487, 0x3b },
669 { 0x0000d486, 0xc3 },
670 { 0x0000d470, 0x89 },
671 { 0x0000d471, 0x3a },
672 { 0x0000d472, 0x3d },
673 { 0x0000d474, 0x11 },
674 { 0x0000d475, 0x32 },
675 { 0x0000d476, 0x64 },
676 { 0x0000d477, 0x10 },
677 { 0x0000d478, 0xff },
678 { 0x0000d479, 0x20 },
679 { 0x0000d47a, 0x10 },
680 { 0x10008000, 0x67 },
681 { 0x10008001, 0x80 },
682 { 0x10008002, 0x00 },
683 { 0x10008003, 0x00 },
684 { 0x1000cd56, 0x00 },
685 { 0x0000d486, 0x43 },
686 { 0x3fc2dfc3, 0x00 },
687 { 0x3fc2dfc2, 0x00 },
688 { 0x3fc2dfc1, 0x00 },
689 { 0x3fc2dfc0, 0x03 },
690 { 0x3fc2dfc7, 0x00 },
691 { 0x3fc2dfc6, 0x00 },
692 { 0x3fc2dfc5, 0x00 },
693 { 0x3fc2dfc4, 0x01 },
694 { 0x3fc2dfa3, 0x00 },
695 { 0x3fc2dfa2, 0x00 },
696 { 0x3fc2dfa1, 0x00 },
697 { 0x3fc2dfa0, 0x00 },
698 { 0x3fc2df80, 0x10 },
699 { 0x3fc2df81, 0x20 },
700 { 0x3fc2df82, 0x00 },
701 { 0x3fc2df83, 0x00 },
702 { 0x3fc2df84, 0x50 },
703 { 0x3fc2df85, 0x19 },
704 { 0x3fc2df86, 0x00 },
705 { 0x3fc2df87, 0x00 },
706 { 0x3fc2df88, 0x52 },
707 { 0x3fc2df89, 0x23 },
708 { 0x3fc2df8a, 0x00 },
709 { 0x3fc2df8b, 0x00 },
710 { 0x3fc2df8c, 0xe0 },
711 { 0x3fc2df8d, 0x2e },
712 { 0x3fc2df8e, 0x00 },
713 { 0x3fc2df8f, 0x00 },
714 { 0x3fc2df90, 0xe0 },
715 { 0x3fc2df91, 0x2e },
716 { 0x3fc2df92, 0x00 },
717 { 0x3fc2df93, 0x00 },
718 { 0x3fc2df94, 0x01 },
719 { 0x3fc2df95, 0x08 },
720 { 0x3fc2df96, 0x00 },
721 { 0x3fc2df97, 0x00 },
722 { 0x3fc2df40, 0x80 },
723 { 0x3fc2df41, 0xbb },
724 { 0x3fc2df42, 0x00 },
725 { 0x3fc2df43, 0x00 },
726 { 0x3fc2df44, 0xc0 },
727 { 0x3fc2df45, 0x99 },
728 { 0x3fc2df46, 0x01 },
729 { 0x3fc2df47, 0x00 },
730 { 0x3fc2df48, 0x00 },
731 { 0x3fc2df49, 0x00 },
732 { 0x3fc2df4a, 0x00 },
733 { 0x3fc2df4b, 0x00 },
734 { 0x3fc2df4c, 0x00 },
735 { 0x3fc2df4d, 0x00 },
736 { 0x3fc2df4e, 0x00 },
737 { 0x3fc2df4f, 0x00 },
738 { 0x3fc2df50, 0x01 },
739 { 0x3fc2df51, 0x00 },
740 { 0x3fc2df52, 0x00 },
741 { 0x3fc2df53, 0x00 },
742 { 0x3fc2df54, 0x01 },
743 { 0x3fc2df55, 0x00 },
744 { 0x3fc2df56, 0x00 },
745 { 0x3fc2df57, 0x00 },
746 { 0x3fc2df58, 0x00 },
747 { 0x3fc2df59, 0x00 },
748 { 0x3fc2df5a, 0x00 },
749 { 0x3fc2df5b, 0x00 },
750 { 0x3fc2df5c, 0x01 },
751 { 0x3fc2df5d, 0x00 },
752 { 0x3fc2df5e, 0x00 },
753 { 0x3fc2df5f, 0x00 },
754 { 0x3fc2df60, 0x00 },
755 { 0x3fc2df61, 0x00 },
756 { 0x3fc2df62, 0x00 },
757 { 0x3fc2df63, 0x00 },
758 { 0x3fc2df64, 0x00 },
759 { 0x3fc2df65, 0x00 },
760 { 0x3fc2df66, 0x00 },
761 { 0x3fc2df67, 0x10 },
762 { 0x3fc2df68, 0x01 },
763 { 0x3fc2df69, 0x00 },
764 { 0x3fc2df6a, 0x00 },
765 { 0x3fc2df6b, 0x00 },
766 { 0x3fc2df6c, 0x01 },
767 { 0x3fc2df6d, 0x00 },
768 { 0x3fc2df6e, 0x00 },
769 { 0x3fc2df6f, 0x00 },
770 { 0x3fc2df70, 0x04 },
771 { 0x3fc2df71, 0x00 },
772 { 0x3fc2df72, 0x00 },
773 { 0x3fc2df73, 0x00 },
774 { 0x3fc2df74, 0x01 },
775 { 0x3fc2df75, 0x00 },
776 { 0x3fc2df76, 0x00 },
777 { 0x3fc2df77, 0x00 },
778 { 0x1000db00, 0x04 },
779 { 0x1000db01, 0x00 },
780 { 0x1000db02, 0x10 },
781 { 0x1000db03, 0x00 },
782 { 0x1000db04, 0x00 },
783 { 0x1000db05, 0x45 },
784 { 0x1000db06, 0x0d },
785 { 0x1000db07, 0x01 },
786 { 0x1000db08, 0x00 },
787 { 0x1000db09, 0x00 },
788 { 0x1000db0a, 0xbf },
789 { 0x1000db0b, 0x0b },
790 { 0x1000db0c, 0x11 },
791 { 0x1000db0d, 0x00 },
792 { 0x1000db0e, 0x00 },
793 { 0x1000db0f, 0x00 },
794 { 0x1000db10, 0x2c },
795 { 0x1000db11, 0xfa },
796 { 0x1000db12, 0x00 },
797 { 0x1000db13, 0x00 },
798 { 0x1000db14, 0x09 },
799 { 0x0000d540, 0x21 },
800 { 0x0000d714, 0x17 },
801 { 0x0000dd0b, 0x0d },
802 { 0x0000dd0a, 0xff },
803 { 0x0000dd09, 0x0d },
804 { 0x0000dd08, 0xff },
805 { 0x0000c5fb, 0x12 },
806 { 0x0000c570, 0x08 },
807 };
808
809 static const struct reg_default rt1320_reg_defaults[] = {
810 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
811 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 },
812 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 },
813 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 },
814 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 },
815 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 },
816 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x0b },
817 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), 0x03 },
818 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 },
819 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 },
820 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE27, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
821 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
822 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0), 0x00 },
823 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 },
824 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), 0x03 },
825 };
826
827 static const struct reg_default rt1320_mbq_defaults[] = {
828 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 },
829 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 },
830 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 },
831 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 },
832 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 },
833 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 },
834 };
835
rt1320_readable_register(struct device * dev,unsigned int reg)836 static bool rt1320_readable_register(struct device *dev, unsigned int reg)
837 {
838 switch (reg) {
839 case 0x004d:
840 case 0xc000 ... 0xc086:
841 case 0xc400 ... 0xc409:
842 case 0xc480 ... 0xc48f:
843 case 0xc4c0 ... 0xc4c4:
844 case 0xc4e0 ... 0xc4e7:
845 case 0xc500:
846 case 0xc560 ... 0xc56b:
847 case 0xc570:
848 case 0xc580 ... 0xc59a:
849 case 0xc5b0 ... 0xc60f:
850 case 0xc640 ... 0xc64f:
851 case 0xc670:
852 case 0xc680 ... 0xc683:
853 case 0xc700 ... 0xc76f:
854 case 0xc800 ... 0xc801:
855 case 0xc820:
856 case 0xc900 ... 0xc901:
857 case 0xc920 ... 0xc921:
858 case 0xca00 ... 0xca07:
859 case 0xca20 ... 0xca27:
860 case 0xca40 ... 0xca4b:
861 case 0xca60 ... 0xca68:
862 case 0xca80 ... 0xca88:
863 case 0xcb00 ... 0xcb0c:
864 case 0xcc00 ... 0xcc12:
865 case 0xcc80 ... 0xcc81:
866 case 0xcd00:
867 case 0xcd80 ... 0xcd82:
868 case 0xce00 ... 0xce4d:
869 case 0xcf00 ... 0xcf25:
870 case 0xd000 ... 0xd0ff:
871 case 0xd100 ... 0xd1ff:
872 case 0xd200 ... 0xd2ff:
873 case 0xd300 ... 0xd3ff:
874 case 0xd400 ... 0xd403:
875 case 0xd410 ... 0xd417:
876 case 0xd470 ... 0xd497:
877 case 0xd4dc ... 0xd50f:
878 case 0xd520 ... 0xd543:
879 case 0xd560 ... 0xd5ef:
880 case 0xd600 ... 0xd663:
881 case 0xda00 ... 0xda6e:
882 case 0xda80 ... 0xda9e:
883 case 0xdb00 ... 0xdb7f:
884 case 0xdc00:
885 case 0xdc20 ... 0xdc21:
886 case 0xdd00 ... 0xdd17:
887 case 0xde00 ... 0xde09:
888 case 0xdf00 ... 0xdf1b:
889 case 0xe000 ... 0xe847:
890 case 0xf01e:
891 case 0xf717 ... 0xf719:
892 case 0xf720 ... 0xf723:
893 case 0x1000cd91 ... 0x1000cd96:
894 case RT1321_PATCH_MAIN_VER ... RT1321_PATCH_BETA_VER:
895 case 0x1000f008:
896 case 0x1000f021:
897 case 0x20003000 ... 0x2000300f:
898 case 0x2000301c:
899 case 0x20003040 ... 0x20003059:
900 case 0x20005800 ... 0x2000580f:
901 case 0x20005818:
902 case 0x20005840 ... 0x20005859:
903 case 0x20009000 ... 0x2000900f:
904 case 0x20009018:
905 case 0x20009040 ... 0x20009059:
906 case 0x3fc000c0 ... 0x3fc2dfc8:
907 case 0x3fe00000 ... 0x3fe36fff:
908 /* 0x40801508/0x40801809/0x4080180a/0x40801909/0x4080190a */
909 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_REQ_POWER_STATE, 0):
910 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01):
911 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_02):
912 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_01):
913 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_02):
914 /* 0x40880900/0x40880980 */
915 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0):
916 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0):
917 /* 0x40881500 */
918 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0):
919 /* 0x41000189/0x4100018a */
920 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01):
921 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02):
922 /* 0x41001388 */
923 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE27, RT1320_SDCA_CTL_REQ_POWER_STATE, 0):
924 /* 0x41001988 */
925 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0):
926 /* 0x41080000 */
927 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0):
928 /* 0x41080200 */
929 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0):
930 /* 0x41080900 */
931 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0):
932 /* 0x41080980 */
933 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0):
934 /* 0x41081080 */
935 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0):
936 /* 0x41081480/0x41081488 */
937 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_MODE, 0):
938 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS, 0):
939 /* 0x41081980 */
940 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0):
941 return true;
942 default:
943 return false;
944 }
945 }
946
rt1320_volatile_register(struct device * dev,unsigned int reg)947 static bool rt1320_volatile_register(struct device *dev, unsigned int reg)
948 {
949 switch (reg) {
950 case 0x004d:
951 case 0xc000:
952 case 0xc003:
953 case 0xc081:
954 case 0xc402 ... 0xc406:
955 case 0xc48c ... 0xc48f:
956 case 0xc560:
957 case 0xc5b5 ... 0xc5b7:
958 case 0xc5c3:
959 case 0xc5c8:
960 case 0xc5fc ... 0xc5ff:
961 case 0xc680 ... 0xc683:
962 case 0xc820:
963 case 0xc900:
964 case 0xc920:
965 case 0xca42:
966 case 0xca62:
967 case 0xca82:
968 case 0xcd00:
969 case 0xce03:
970 case 0xce10:
971 case 0xce14 ... 0xce17:
972 case 0xce44 ... 0xce49:
973 case 0xce4c ... 0xce4d:
974 case 0xcf0c:
975 case 0xcf10 ... 0xcf25:
976 case 0xd486 ... 0xd487:
977 case 0xd4e5 ... 0xd4e6:
978 case 0xd4e8 ... 0xd4ff:
979 case 0xd530:
980 case 0xd540 ... 0xd541:
981 case 0xd543:
982 case 0xdb58 ... 0xdb5f:
983 case 0xdb60 ... 0xdb63:
984 case 0xdb68 ... 0xdb69:
985 case 0xdb6d:
986 case 0xdb70 ... 0xdb71:
987 case 0xdb76:
988 case 0xdb7a:
989 case 0xdb7c ... 0xdb7f:
990 case 0xdd0c ... 0xdd13:
991 case 0xde02:
992 case 0xdf14 ... 0xdf1b:
993 case 0xe80b:
994 case 0xe83c ... 0xe847:
995 case 0xf01e:
996 case 0xf717 ... 0xf719:
997 case 0xf720 ... 0xf723:
998 case 0x10000000 ... 0x10008fff:
999 case 0x1000c000 ... 0x1000dfff:
1000 case 0x1000f008:
1001 case 0x1000f021:
1002 case 0x2000300e ... 0x2000300f:
1003 case 0x2000301c:
1004 case 0x20003040 ... 0x20003059:
1005 case 0x2000580e ... 0x2000580f:
1006 case 0x20005818:
1007 case 0x20005840 ... 0x20005859:
1008 case 0x2000900e ... 0x2000900f:
1009 case 0x20009018:
1010 case 0x20009040 ... 0x20009059:
1011 case 0x3fc2ab80 ... 0x3fc2ac4c:
1012 case 0x3fc2b780:
1013 case 0x3fc2bf80 ... 0x3fc2bf83:
1014 case 0x3fc2bfc0 ... 0x3fc2bfc8:
1015 case 0x3fc2d300 ... 0x3fc2d3cc:
1016 case 0x3fc2dfc0 ... 0x3fc2dfc8:
1017 case 0x3fe2e000 ... 0x3fe2e003:
1018 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0):
1019 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0):
1020 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_MODE, 0):
1021 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS, 0):
1022 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0):
1023 return true;
1024 default:
1025 return false;
1026 }
1027 }
1028
rt1320_mbq_readable_register(struct device * dev,unsigned int reg)1029 static bool rt1320_mbq_readable_register(struct device *dev, unsigned int reg)
1030 {
1031 switch (reg) {
1032 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01):
1033 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_02):
1034 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01):
1035 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_02):
1036 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01):
1037 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02):
1038 return true;
1039 default:
1040 return false;
1041 }
1042 }
1043
1044 static const struct regmap_config rt1320_sdw_regmap = {
1045 .reg_bits = 32,
1046 .val_bits = 8,
1047 .readable_reg = rt1320_readable_register,
1048 .volatile_reg = rt1320_volatile_register,
1049 .max_register = 0x41081980,
1050 .reg_defaults = rt1320_reg_defaults,
1051 .num_reg_defaults = ARRAY_SIZE(rt1320_reg_defaults),
1052 .cache_type = REGCACHE_MAPLE,
1053 .use_single_read = true,
1054 .use_single_write = true,
1055 };
1056
1057 static const struct regmap_config rt1320_mbq_regmap = {
1058 .name = "sdw-mbq",
1059 .reg_bits = 32,
1060 .val_bits = 16,
1061 .readable_reg = rt1320_mbq_readable_register,
1062 .max_register = 0x41000192,
1063 .reg_defaults = rt1320_mbq_defaults,
1064 .num_reg_defaults = ARRAY_SIZE(rt1320_mbq_defaults),
1065 .cache_type = REGCACHE_MAPLE,
1066 .use_single_read = true,
1067 .use_single_write = true,
1068 };
1069
rt1320_read_prop(struct sdw_slave * slave)1070 static int rt1320_read_prop(struct sdw_slave *slave)
1071 {
1072 struct sdw_slave_prop *prop = &slave->prop;
1073 int nval;
1074 int i, j;
1075 u32 bit;
1076 unsigned long addr;
1077 struct sdw_dpn_prop *dpn;
1078
1079 /*
1080 * Due to support the multi-lane, we call 'sdw_slave_read_prop' to get the lane mapping
1081 */
1082 sdw_slave_read_prop(slave);
1083
1084 prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
1085 prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
1086
1087 prop->paging_support = true;
1088 prop->lane_control_support = true;
1089
1090 /* first we need to allocate memory for set bits in port lists */
1091 prop->source_ports = BIT(4) | BIT(8) | BIT(10);
1092 prop->sink_ports = BIT(1);
1093
1094 nval = hweight32(prop->source_ports);
1095 prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
1096 sizeof(*prop->src_dpn_prop), GFP_KERNEL);
1097 if (!prop->src_dpn_prop)
1098 return -ENOMEM;
1099
1100 i = 0;
1101 dpn = prop->src_dpn_prop;
1102 addr = prop->source_ports;
1103 for_each_set_bit(bit, &addr, 32) {
1104 dpn[i].num = bit;
1105 dpn[i].type = SDW_DPN_FULL;
1106 dpn[i].simple_ch_prep_sm = true;
1107 dpn[i].ch_prep_timeout = 10;
1108 i++;
1109 }
1110
1111 /* do this again for sink now */
1112 nval = hweight32(prop->sink_ports);
1113 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
1114 sizeof(*prop->sink_dpn_prop), GFP_KERNEL);
1115 if (!prop->sink_dpn_prop)
1116 return -ENOMEM;
1117
1118 j = 0;
1119 dpn = prop->sink_dpn_prop;
1120 addr = prop->sink_ports;
1121 for_each_set_bit(bit, &addr, 32) {
1122 dpn[j].num = bit;
1123 dpn[j].type = SDW_DPN_FULL;
1124 dpn[j].simple_ch_prep_sm = true;
1125 dpn[j].ch_prep_timeout = 10;
1126 j++;
1127 }
1128
1129 prop->dp0_prop = devm_kzalloc(&slave->dev, sizeof(*prop->dp0_prop), GFP_KERNEL);
1130 if (!prop->dp0_prop)
1131 return -ENOMEM;
1132
1133 prop->dp0_prop->simple_ch_prep_sm = true;
1134 prop->dp0_prop->ch_prep_timeout = 10;
1135
1136 /* set the timeout values */
1137 prop->clk_stop_timeout = 64;
1138
1139 /* BIOS may set wake_capable. Make sure it is 0 as wake events are disabled. */
1140 prop->wake_capable = 0;
1141
1142 return 0;
1143 }
1144
rt1320_pde_transition_delay(struct rt1320_sdw_priv * rt1320,unsigned char func,unsigned char entity,unsigned char ps)1145 static int rt1320_pde_transition_delay(struct rt1320_sdw_priv *rt1320, unsigned char func,
1146 unsigned char entity, unsigned char ps)
1147 {
1148 unsigned int delay = 2000, val;
1149
1150 pm_runtime_mark_last_busy(&rt1320->sdw_slave->dev);
1151
1152 /* waiting for Actual PDE becomes to PS0/PS3 */
1153 while (delay) {
1154 regmap_read(rt1320->regmap,
1155 SDW_SDCA_CTL(func, entity, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), &val);
1156 if (val == ps)
1157 break;
1158
1159 usleep_range(1000, 1500);
1160 delay--;
1161 }
1162 if (!delay) {
1163 dev_warn(&rt1320->sdw_slave->dev, "%s PDE to %s is NOT ready", __func__, ps?"PS3":"PS0");
1164 return -ETIMEDOUT;
1165 }
1166
1167 return 0;
1168 }
1169
rt1320_data_rw(struct rt1320_sdw_priv * rt1320,unsigned int start,unsigned char * data,unsigned int size,enum rt1320_rw_type rw)1170 static void rt1320_data_rw(struct rt1320_sdw_priv *rt1320, unsigned int start,
1171 unsigned char *data, unsigned int size, enum rt1320_rw_type rw)
1172 {
1173 struct device *dev = &rt1320->sdw_slave->dev;
1174 unsigned int tmp;
1175 int ret = -1;
1176 int i, j;
1177
1178 pm_runtime_set_autosuspend_delay(dev, 20000);
1179 pm_runtime_mark_last_busy(dev);
1180
1181 switch (rw) {
1182 case RT1320_BRA_WRITE:
1183 case RT1320_BRA_READ:
1184 ret = sdw_bpt_send_sync(rt1320->sdw_slave->bus, rt1320->sdw_slave, &rt1320->bra_msg);
1185 if (ret < 0)
1186 dev_err(dev, "%s: Failed to send BRA message: %d\n", __func__, ret);
1187 fallthrough;
1188 case RT1320_PARAM_WRITE:
1189 case RT1320_PARAM_READ:
1190 if (ret < 0) {
1191 /* if BRA fails, we try to access by the control word */
1192 if (rw == RT1320_BRA_WRITE || rw == RT1320_BRA_READ) {
1193 for (i = 0; i < rt1320->bra_msg.sections; i++) {
1194 pm_runtime_mark_last_busy(dev);
1195 for (j = 0; j < rt1320->bra_msg.sec[i].len; j++) {
1196 if (rw == RT1320_BRA_WRITE) {
1197 regmap_write(rt1320->regmap,
1198 rt1320->bra_msg.sec[i].addr + j, rt1320->bra_msg.sec[i].buf[j]);
1199 } else {
1200 regmap_read(rt1320->regmap, rt1320->bra_msg.sec[i].addr + j, &tmp);
1201 rt1320->bra_msg.sec[i].buf[j] = tmp;
1202 }
1203 }
1204 }
1205 } else {
1206 for (i = 0; i < size; i++) {
1207 if (rw == RT1320_PARAM_WRITE)
1208 regmap_write(rt1320->regmap, start + i, data[i]);
1209 else {
1210 regmap_read(rt1320->regmap, start + i, &tmp);
1211 data[i] = tmp;
1212 }
1213 }
1214 }
1215 }
1216 break;
1217 }
1218
1219 pm_runtime_set_autosuspend_delay(dev, 3000);
1220 pm_runtime_mark_last_busy(dev);
1221 }
1222
rt1320_rsgain_to_rsratio(struct rt1320_sdw_priv * rt1320,unsigned int rsgain)1223 static unsigned long long rt1320_rsgain_to_rsratio(struct rt1320_sdw_priv *rt1320, unsigned int rsgain)
1224 {
1225 unsigned long long base = 1000000000U;
1226 unsigned long long step = 1960784U;
1227 unsigned long long tmp, result;
1228
1229 if (rsgain == 0 || rsgain == 0x1ff)
1230 result = 1000000000;
1231 else if (rsgain & 0x100) {
1232 tmp = 0xff - (rsgain & 0xff);
1233 tmp = tmp * step;
1234 result = base + tmp;
1235 } else {
1236 tmp = (rsgain & 0xff);
1237 tmp = tmp * step;
1238 result = base - tmp;
1239 }
1240
1241 return result;
1242 }
1243
rt1320_pr_read(struct rt1320_sdw_priv * rt1320,unsigned int reg,unsigned int * val)1244 static void rt1320_pr_read(struct rt1320_sdw_priv *rt1320, unsigned int reg, unsigned int *val)
1245 {
1246 unsigned int byte3, byte2, byte1, byte0;
1247
1248 regmap_write(rt1320->regmap, 0xc483, 0x80);
1249 regmap_write(rt1320->regmap, 0xc482, 0x40);
1250 regmap_write(rt1320->regmap, 0xc481, 0x0c);
1251 regmap_write(rt1320->regmap, 0xc480, 0x10);
1252
1253 regmap_write(rt1320->regmap, 0xc487, ((reg & 0xff000000) >> 24));
1254 regmap_write(rt1320->regmap, 0xc486, ((reg & 0x00ff0000) >> 16));
1255 regmap_write(rt1320->regmap, 0xc485, ((reg & 0x0000ff00) >> 8));
1256 regmap_write(rt1320->regmap, 0xc484, (reg & 0x000000ff));
1257
1258 regmap_write(rt1320->regmap, 0xc482, 0xc0);
1259
1260 regmap_read(rt1320->regmap, 0xc48f, &byte3);
1261 regmap_read(rt1320->regmap, 0xc48e, &byte2);
1262 regmap_read(rt1320->regmap, 0xc48d, &byte1);
1263 regmap_read(rt1320->regmap, 0xc48c, &byte0);
1264
1265 *val = (byte3 << 24) | (byte2 << 16) | (byte1 << 8) | byte0;
1266 }
1267
rt1320_check_fw_ready(struct rt1320_sdw_priv * rt1320)1268 static int rt1320_check_fw_ready(struct rt1320_sdw_priv *rt1320)
1269 {
1270 struct device *dev = &rt1320->sdw_slave->dev;
1271 unsigned int tmp, retry = 0;
1272 unsigned int cmd_addr;
1273
1274 switch (rt1320->dev_id) {
1275 case RT1320_DEV_ID:
1276 cmd_addr = RT1320_CMD_ID;
1277 break;
1278 case RT1321_DEV_ID:
1279 cmd_addr = RT1321_CMD_ID;
1280 break;
1281 default:
1282 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id);
1283 return -EINVAL;
1284 }
1285
1286 pm_runtime_mark_last_busy(dev);
1287 /* check the value of cmd_addr becomes to zero */
1288 while (retry < 500) {
1289 regmap_read(rt1320->regmap, cmd_addr, &tmp);
1290 if (tmp == 0)
1291 break;
1292 usleep_range(1000, 1100);
1293 retry++;
1294 }
1295 if (retry == 500) {
1296 dev_warn(dev, "%s FW is NOT ready!", __func__);
1297 return -ETIMEDOUT;
1298 }
1299
1300 return 0;
1301 }
1302
rt1320_dspfw_status(struct rt1320_sdw_priv * rt1320)1303 static int rt1320_dspfw_status(struct rt1320_sdw_priv *rt1320)
1304 {
1305 struct device *dev = &rt1320->sdw_slave->dev;
1306 unsigned int fw_status_addr, fw_ready;
1307 unsigned int dspfw_run;
1308
1309 switch (rt1320->dev_id) {
1310 case RT1320_DEV_ID:
1311 fw_status_addr = RT1320_DSPFW_STATUS_ADDR;
1312 break;
1313 case RT1321_DEV_ID:
1314 fw_status_addr = RT1321_DSPFW_STATUS_ADDR;
1315 break;
1316 default:
1317 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id);
1318 return -EINVAL;
1319 }
1320
1321 regmap_read(rt1320->regmap, fw_status_addr, &fw_ready);
1322 fw_ready &= 0x1;
1323
1324 if (rt1320->dev_id == RT1321_DEV_ID) {
1325 regmap_read(rt1320->regmap, 0xf01e, &dspfw_run);
1326 dspfw_run &= 0x1;
1327 fw_ready = (!dspfw_run && fw_ready);
1328 }
1329
1330 if (fw_ready) {
1331 dev_dbg(dev, "%s, DSP FW was already\n", __func__);
1332 return 1;
1333 }
1334
1335 dev_dbg(dev, "%s, DSP FW is NOT ready. Please load DSP FW first\n", __func__);
1336 return 0;
1337 }
1338
rt1320_check_power_state_ready(struct rt1320_sdw_priv * rt1320,enum rt1320_power_state ps)1339 static int rt1320_check_power_state_ready(struct rt1320_sdw_priv *rt1320, enum rt1320_power_state ps)
1340 {
1341 struct device *dev = &rt1320->sdw_slave->dev;
1342 unsigned int retry = 0, tmp;
1343
1344 pm_runtime_mark_last_busy(dev);
1345 while (retry < 200) {
1346 regmap_read(rt1320->regmap, RT1320_POWER_STATE, &tmp);
1347 dev_dbg(dev, "%s, RT1320_POWER_STATE=0x%x\n", __func__, tmp);
1348 if (tmp >= ps)
1349 break;
1350 usleep_range(1000, 1500);
1351 retry++;
1352 }
1353 if (retry == 200) {
1354 dev_warn(dev, "%s FW Power State is NOT ready!", __func__);
1355 return -ETIMEDOUT;
1356 }
1357
1358 return 0;
1359 }
1360
rt1320_process_fw_param(struct rt1320_sdw_priv * rt1320,unsigned char * buf,unsigned int buf_size)1361 static int rt1320_process_fw_param(struct rt1320_sdw_priv *rt1320, unsigned char *buf, unsigned int buf_size)
1362 {
1363 struct device *dev = &rt1320->sdw_slave->dev;
1364 struct rt1320_paramcmd *paramhr = (struct rt1320_paramcmd *)buf;
1365 unsigned char moudleid = paramhr->moudleid;
1366 unsigned char cmdtype = paramhr->commandtype;
1367 unsigned int fw_param_addr;
1368 unsigned int start_addr;
1369 int ret = 0;
1370
1371 switch (rt1320->dev_id) {
1372 case RT1320_DEV_ID:
1373 fw_param_addr = RT1320_FW_PARAM_ADDR;
1374 start_addr = RT1320_CMD_PARAM_ADDR;
1375 break;
1376 case RT1321_DEV_ID:
1377 fw_param_addr = RT1321_FW_PARAM_ADDR;
1378 start_addr = RT1321_CMD_PARAM_ADDR;
1379 break;
1380 default:
1381 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id);
1382 return -EINVAL;
1383 }
1384
1385 ret = rt1320_check_fw_ready(rt1320);
1386 if (ret < 0)
1387 goto _timeout_;
1388
1389 /* don't set offset 0x0/0x1, it will be set later*/
1390 paramhr->moudleid = 0;
1391 paramhr->commandtype = 0;
1392 rt1320_data_rw(rt1320, fw_param_addr, buf, buf_size, RT1320_PARAM_WRITE);
1393
1394 dev_dbg(dev, "%s, moudleid=%d, cmdtype=%d, paramid=%d, paramlength=%d\n", __func__,
1395 moudleid, cmdtype, paramhr->paramid, paramhr->paramlength);
1396
1397 if (cmdtype == RT1320_SET_PARAM) {
1398 regmap_write(rt1320->regmap, fw_param_addr, moudleid);
1399 regmap_write(rt1320->regmap, fw_param_addr + 1, 0x01);
1400 }
1401 if (cmdtype == RT1320_GET_PARAM) {
1402 regmap_write(rt1320->regmap, fw_param_addr, moudleid);
1403 regmap_write(rt1320->regmap, fw_param_addr + 1, 0x02);
1404 ret = rt1320_check_fw_ready(rt1320);
1405 if (ret < 0)
1406 goto _timeout_;
1407
1408 rt1320_data_rw(rt1320, start_addr, buf + 0x10, paramhr->commandlength, RT1320_PARAM_READ);
1409 }
1410 return 0;
1411
1412 _timeout_:
1413 dev_err(&rt1320->sdw_slave->dev, "%s: FW is NOT ready for SET/GET_PARAM\n", __func__);
1414 return ret;
1415 }
1416
rt1320_fw_param_protocol(struct rt1320_sdw_priv * rt1320,enum rt1320_fw_cmdid cmdid,unsigned int paramid,void * parambuf,unsigned int paramsize)1417 static int rt1320_fw_param_protocol(struct rt1320_sdw_priv *rt1320, enum rt1320_fw_cmdid cmdid,
1418 unsigned int paramid, void *parambuf, unsigned int paramsize)
1419 {
1420 struct device *dev = &rt1320->sdw_slave->dev;
1421 unsigned char *tempbuf = NULL;
1422 struct rt1320_paramcmd paramhr;
1423 int ret = 0;
1424
1425 tempbuf = kzalloc(sizeof(paramhr) + paramsize, GFP_KERNEL);
1426 if (!tempbuf)
1427 return -ENOMEM;
1428
1429 if (rt1320->dev_id == RT1321_DEV_ID && rt1320->version_id == RT1321_VA2)
1430 paramid += 0x0bff0000;
1431
1432 paramhr.moudleid = 1;
1433 paramhr.commandtype = cmdid;
1434 /* 8 is "sizeof(paramid) + sizeof(paramlength)" */
1435 paramhr.commandlength = 8 + paramsize;
1436 paramhr.paramid = paramid;
1437 paramhr.paramlength = paramsize;
1438
1439 memcpy(tempbuf, ¶mhr, sizeof(paramhr));
1440 if (cmdid == RT1320_SET_PARAM)
1441 memcpy(tempbuf + sizeof(paramhr), parambuf, paramsize);
1442
1443 ret = rt1320_process_fw_param(rt1320, tempbuf, sizeof(paramhr) + paramsize);
1444 if (ret < 0) {
1445 dev_err(dev, "%s: process_fw_param failed\n", __func__);
1446 goto _finish_;
1447 }
1448
1449 if (cmdid == RT1320_GET_PARAM)
1450 memcpy(parambuf, tempbuf + sizeof(paramhr), paramsize);
1451
1452 _finish_:
1453 kfree(tempbuf);
1454 return ret;
1455 }
1456
rt1320_set_advancemode(struct rt1320_sdw_priv * rt1320)1457 static void rt1320_set_advancemode(struct rt1320_sdw_priv *rt1320)
1458 {
1459 struct device *dev = &rt1320->sdw_slave->dev;
1460 struct rt1320_datafixpoint r0_data[2];
1461 unsigned short l_advancegain, r_advancegain;
1462 FwPara_Get_HwSwGain audDriverDataHwSwGain = {0};
1463 unsigned int HwAdvGain = 0;
1464 int ret;
1465
1466 /* Get new hardware advance gain by ID 1300 */
1467 ret = rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 1300,
1468 &audDriverDataHwSwGain, sizeof(audDriverDataHwSwGain));
1469 if (ret == 0) {
1470 HwAdvGain = audDriverDataHwSwGain.HwAdvGain;
1471 dev_dbg(dev, "%s, HwAdvGain=%d\n", __func__, HwAdvGain);
1472 dev_dbg(dev, "%s, HwBasGain=%d\n", __func__, audDriverDataHwSwGain.HwBasGain);
1473 dev_dbg(dev, "%s, SwAdvGain=%d\n", __func__, audDriverDataHwSwGain.SwAdvGain);
1474 dev_dbg(dev, "%s, SwBasGain=%d\n", __func__, audDriverDataHwSwGain.SwBasGain);
1475 } else {
1476 dev_dbg(dev, "%s: param 1300 not supported, ret=%d\n", __func__, ret);
1477 }
1478
1479 /* Get advance gain/r0 */
1480 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 6, &r0_data[0], sizeof(struct rt1320_datafixpoint));
1481 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 7, &r0_data[1], sizeof(struct rt1320_datafixpoint));
1482
1483 if (HwAdvGain != 0) {
1484 l_advancegain = HwAdvGain & 0xffff;
1485 r_advancegain = (HwAdvGain >> 16) & 0xffff;
1486 } else {
1487 l_advancegain = r0_data[0].advancegain;
1488 r_advancegain = r0_data[1].advancegain;
1489 }
1490 dev_dbg(dev, "%s, LR advanceGain=0x%x 0x%x\n", __func__, l_advancegain, r_advancegain);
1491
1492 /* set R0 and enable protection by SetParameter id 6, 7 */
1493 r0_data[0].silencedetect = 0;
1494 r0_data[0].r0 = rt1320->r0_l_reg;
1495 r0_data[1].silencedetect = 0;
1496 r0_data[1].r0 = rt1320->r0_r_reg;
1497 dev_dbg(dev, "%s, write LR r0=%d, %d\n", __func__, r0_data[0].r0, r0_data[1].r0);
1498
1499 rt1320_fw_param_protocol(rt1320, RT1320_SET_PARAM, 6, &r0_data[0], sizeof(struct rt1320_datafixpoint));
1500 rt1320_fw_param_protocol(rt1320, RT1320_SET_PARAM, 7, &r0_data[1], sizeof(struct rt1320_datafixpoint));
1501 ret = rt1320_check_fw_ready(rt1320);
1502 if (ret < 0)
1503 dev_err(dev, "%s: Failed to set FW param 6,7!\n", __func__);
1504
1505 if (l_advancegain != 0 && r_advancegain != 0) {
1506 regmap_write(rt1320->regmap, 0xdd0b, (l_advancegain & 0xff00) >> 8);
1507 regmap_write(rt1320->regmap, 0xdd0a, (l_advancegain & 0xff));
1508 regmap_write(rt1320->regmap, 0xdd09, (r_advancegain & 0xff00) >> 8);
1509 regmap_write(rt1320->regmap, 0xdd08, (r_advancegain & 0xff));
1510 dev_dbg(dev, "%s, set Advance mode gain\n", __func__);
1511 }
1512 }
1513
rt1320_invrs_load(struct rt1320_sdw_priv * rt1320)1514 static int rt1320_invrs_load(struct rt1320_sdw_priv *rt1320)
1515 {
1516 struct device *dev = &rt1320->sdw_slave->dev;
1517 unsigned long long l_rsratio, r_rsratio;
1518 unsigned int pr_1058, pr_1059, pr_105a;
1519 unsigned long long l_invrs, r_invrs;
1520 unsigned long long factor = (1 << 28);
1521 unsigned int l_rsgain, r_rsgain;
1522 struct rt1320_datafixpoint r0_data[2];
1523 int ret;
1524
1525 /* read L/Rch Rs Gain - it uses for compensating the R0 value */
1526 rt1320_pr_read(rt1320, 0x1058, &pr_1058);
1527 rt1320_pr_read(rt1320, 0x1059, &pr_1059);
1528 rt1320_pr_read(rt1320, 0x105a, &pr_105a);
1529 l_rsgain = ((pr_1059 & 0x7f) << 2) | ((pr_105a & 0xc0) >> 6);
1530 r_rsgain = ((pr_1058 & 0xff) << 1) | ((pr_1059 & 0x80) >> 7);
1531 dev_dbg(dev, "%s, LR rsgain=0x%x, 0x%x\n", __func__, l_rsgain, r_rsgain);
1532
1533 l_rsratio = rt1320_rsgain_to_rsratio(rt1320, l_rsgain);
1534 r_rsratio = rt1320_rsgain_to_rsratio(rt1320, r_rsgain);
1535 dev_dbg(dev, "%s, LR rsratio=%lld, %lld\n", __func__, l_rsratio, r_rsratio);
1536
1537 l_invrs = div_u64(l_rsratio * factor, 1000000000U);
1538 r_invrs = div_u64(r_rsratio * factor, 1000000000U);
1539
1540 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 6, &r0_data[0], sizeof(struct rt1320_datafixpoint));
1541 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 7, &r0_data[1], sizeof(struct rt1320_datafixpoint));
1542
1543 r0_data[0].invrs = l_invrs;
1544 r0_data[1].invrs = r_invrs;
1545 dev_dbg(dev, "%s, write DSP LR invrs=0x%x, 0x%x\n", __func__, r0_data[0].invrs, r0_data[1].invrs);
1546
1547 rt1320_fw_param_protocol(rt1320, RT1320_SET_PARAM, 6, &r0_data[0], sizeof(struct rt1320_datafixpoint));
1548 rt1320_fw_param_protocol(rt1320, RT1320_SET_PARAM, 7, &r0_data[1], sizeof(struct rt1320_datafixpoint));
1549 ret = rt1320_check_fw_ready(rt1320);
1550 if (ret < 0)
1551 dev_err(dev, "%s: Failed to set FW param 6,7!\n", __func__);
1552
1553 return ret;
1554 }
1555
rt1320_calc_r0(struct rt1320_sdw_priv * rt1320)1556 static void rt1320_calc_r0(struct rt1320_sdw_priv *rt1320)
1557 {
1558 struct device *dev = &rt1320->sdw_slave->dev;
1559 unsigned long long l_calir0, r_calir0, l_calir0_lo, r_calir0_lo;
1560
1561 l_calir0 = rt1320->r0_l_reg >> 27;
1562 r_calir0 = rt1320->r0_r_reg >> 27;
1563 l_calir0_lo = ((rt1320->r0_l_reg & ((1ull << 27) - 1)) * 1000) >> 27;
1564 r_calir0_lo = ((rt1320->r0_r_reg & ((1ull << 27) - 1)) * 1000) >> 27;
1565
1566 dev_dbg(dev, "%s, l_calir0=%lld.%03lld ohm, r_calir0=%lld.%03lld ohm\n", __func__,
1567 l_calir0, l_calir0_lo, r_calir0, r_calir0_lo);
1568 }
1569
rt1320_pilot_tone_output(struct rt1320_sdw_priv * rt1320)1570 static int rt1320_pilot_tone_output(struct rt1320_sdw_priv *rt1320)
1571 {
1572 struct device *dev = &rt1320->sdw_slave->dev;
1573 int l_targetpostgain, r_targetpostgain;
1574 unsigned long long factor = (1 << 12);
1575 int l_pilotgain[9], r_pilotgain[9];
1576 const int postgain_step = 234;
1577 int targetGain;
1578
1579 switch (rt1320->dev_id) {
1580 case RT1320_DEV_ID:
1581 targetGain = -320000;
1582 break;
1583 case RT1321_DEV_ID:
1584 targetGain = -420000;
1585 if (rt1320->version_id == RT1321_VA0)
1586 targetGain = -320000;
1587 break;
1588 default:
1589 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id);
1590 return -EINVAL;
1591 }
1592
1593 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 70, &l_pilotgain[0], sizeof(l_pilotgain));
1594 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 71, &r_pilotgain[0], sizeof(r_pilotgain));
1595 dev_dbg(dev, "%s, LR pilotgain %d, %d\n", __func__, l_pilotgain[2], r_pilotgain[2]);
1596
1597 /* calculate pilot tone gain */
1598 l_pilotgain[2] = (l_pilotgain[2] * 10000) / factor;
1599 r_pilotgain[2] = (r_pilotgain[2] * 10000) / factor;
1600
1601 /* calculate post gain to meet target gain */
1602 l_targetpostgain = abs(targetGain - l_pilotgain[2]) / postgain_step;
1603 r_targetpostgain = abs(targetGain - r_pilotgain[2]) / postgain_step;
1604 l_targetpostgain = 0xfff - l_targetpostgain;
1605 r_targetpostgain = 0xfff - r_targetpostgain;
1606 dev_dbg(dev, "%s, LR targetpostgain=0x%x, 0x%x\n", __func__, l_targetpostgain, r_targetpostgain);
1607
1608 regmap_write(rt1320->regmap, 0xdd0b, (l_targetpostgain & 0xf00) >> 8);
1609 regmap_write(rt1320->regmap, 0xdd0a, l_targetpostgain & 0xff);
1610 regmap_write(rt1320->regmap, 0xdd09, (r_targetpostgain & 0xf00) >> 8);
1611 regmap_write(rt1320->regmap, 0xdd08, r_targetpostgain & 0xff);
1612
1613 return 0;
1614 }
1615
rt1320_calibrate(struct rt1320_sdw_priv * rt1320)1616 static void rt1320_calibrate(struct rt1320_sdw_priv *rt1320)
1617 {
1618 struct device *dev = &rt1320->sdw_slave->dev;
1619 struct rt1320_datafixpoint audfixpoint[2];
1620 unsigned int reg_c5fb, reg_c570, reg_cd00;
1621 unsigned int vol_reg[4];
1622 unsigned long long l_meanr0, r_meanr0;
1623 int l_re[5], r_re[5];
1624 int ret, tmp;
1625 unsigned long long factor = (1 << 27);
1626 unsigned short l_advancegain, r_advancegain;
1627 unsigned int delay_s = 7; /* delay seconds for the calibration */
1628 int dspfw_status;
1629
1630 if (!rt1320->component)
1631 return;
1632
1633 regmap_read(rt1320->regmap, 0xdd0b, &vol_reg[3]);
1634 regmap_read(rt1320->regmap, 0xdd0a, &vol_reg[2]);
1635 regmap_read(rt1320->regmap, 0xdd09, &vol_reg[1]);
1636 regmap_read(rt1320->regmap, 0xdd08, &vol_reg[0]);
1637 regmap_read(rt1320->regmap, 0xc5fb, ®_c5fb);
1638 regmap_read(rt1320->regmap, 0xc570, ®_c570);
1639 regmap_read(rt1320->regmap, 0xcd00, ®_cd00);
1640
1641 regmap_write(rt1320->regmap,
1642 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00);
1643 ret = rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x00);
1644 if (ret < 0) {
1645 dev_dbg(dev, "%s, PDE=PS0 is NOT ready\n", __func__);
1646 goto _finish_;
1647 }
1648
1649 dspfw_status = rt1320_dspfw_status(rt1320);
1650 if (dspfw_status <= 0) {
1651 dev_dbg(dev, "%s, DSP FW is NOT ready. Please load DSP FW first\n", __func__);
1652 goto _finish_;
1653 }
1654
1655 ret = rt1320_check_power_state_ready(rt1320, RT1320_NORMAL_STATE);
1656 if (ret < 0) {
1657 dev_dbg(dev, "%s, DSP FW PS is NOT ready\n", __func__);
1658 goto _finish_;
1659 }
1660
1661 /* fine tune pilot tone output */
1662 ret = rt1320_pilot_tone_output(rt1320);
1663 if (ret < 0) {
1664 dev_dbg(dev, "%s, Failed to tune pilot tone output\n", __func__);
1665 goto _finish_;
1666 }
1667
1668 if (rt1320->dev_id == RT1321_DEV_ID) {
1669 regmap_update_bits(rt1320->regmap, 0xc047, 0x80, 0x00);
1670 regmap_write(rt1320->regmap, 0xc5c4, 0x12);
1671 }
1672
1673 regmap_write(rt1320->regmap, 0xc5fb, 0x00);
1674 regmap_write(rt1320->regmap, 0xc570, 0x0b);
1675 regmap_write(rt1320->regmap, 0xcd00, 0xc5);
1676
1677 /* disable silence detection */
1678 regmap_update_bits(rt1320->regmap, 0xc044, 0xe0, 0x00);
1679 dev_dbg(dev, "%s, disable silence detection\n", __func__);
1680
1681 ret = rt1320_check_power_state_ready(rt1320, RT1320_K_R0_STATE);
1682 if (ret < 0) {
1683 dev_dbg(dev, "%s, check class D status before k r0\n", __func__);
1684 goto _finish_;
1685 }
1686
1687 for (tmp = 0; tmp < delay_s; tmp++) {
1688 msleep(1000);
1689 pm_runtime_mark_last_busy(dev);
1690
1691 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 11, &l_re[0], sizeof(l_re));
1692 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 12, &r_re[0], sizeof(r_re));
1693
1694 dev_dbg(dev, "%s, LR re=0x%x, 0x%x\n", __func__, l_re[4], r_re[4]);
1695 dev_dbg(dev, "%s, waiting for calibration R0...%d seconds\n", __func__, tmp + 1);
1696 }
1697
1698 /* Get Calibration data */
1699 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 11, &l_re[0], sizeof(l_re));
1700 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 12, &r_re[0], sizeof(r_re));
1701 dev_dbg(dev, "%s, LR re=0x%x, 0x%x\n", __func__, l_re[4], r_re[4]);
1702
1703 /* Get advance gain/mean r0 */
1704 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 6, &audfixpoint[0], sizeof(struct rt1320_datafixpoint));
1705 l_meanr0 = audfixpoint[0].meanr0;
1706 l_advancegain = audfixpoint[0].advancegain;
1707 l_meanr0 = ((l_meanr0 * 1000U) / factor);
1708 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 7, &audfixpoint[1], sizeof(struct rt1320_datafixpoint));
1709 r_meanr0 = audfixpoint[1].meanr0;
1710 r_advancegain = audfixpoint[1].advancegain;
1711 r_meanr0 = ((r_meanr0 * 1000U) / factor);
1712 dev_dbg(dev, "%s, LR meanr0=%lld, %lld\n", __func__, l_meanr0, r_meanr0);
1713 dev_dbg(dev, "%s, LR advanceGain=0x%x, 0x%x\n", __func__, l_advancegain, r_advancegain);
1714 dev_dbg(dev, "%s, LR invrs=0x%x, 0x%x\n", __func__, audfixpoint[0].invrs, audfixpoint[1].invrs);
1715
1716 /* enable silence detection */
1717 regmap_update_bits(rt1320->regmap, 0xc044, 0xe0, 0xe0);
1718 dev_dbg(dev, "%s, enable silence detection\n", __func__);
1719
1720 regmap_write(rt1320->regmap, 0xc5fb, reg_c5fb);
1721 regmap_write(rt1320->regmap, 0xc570, reg_c570);
1722 regmap_write(rt1320->regmap, 0xcd00, reg_cd00);
1723
1724 rt1320->r0_l_reg = l_re[4];
1725 rt1320->r0_r_reg = r_re[4];
1726 rt1320->cali_done = true;
1727 rt1320_calc_r0(rt1320);
1728
1729 _finish_:
1730 regmap_write(rt1320->regmap,
1731 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03);
1732 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x03);
1733
1734 if (rt1320->dev_id == RT1321_DEV_ID) {
1735 regmap_update_bits(rt1320->regmap, 0xc047, 0x80, 0x80);
1736 regmap_write(rt1320->regmap, 0xc5c4, 0x10);
1737 }
1738
1739 /* advance gain will be set when R0 load, not here */
1740 regmap_write(rt1320->regmap, 0xdd0b, vol_reg[3]);
1741 regmap_write(rt1320->regmap, 0xdd0a, vol_reg[2]);
1742 regmap_write(rt1320->regmap, 0xdd09, vol_reg[1]);
1743 regmap_write(rt1320->regmap, 0xdd08, vol_reg[0]);
1744 }
1745
rt1320_r0_cali_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1746 static int rt1320_r0_cali_get(struct snd_kcontrol *kcontrol,
1747 struct snd_ctl_elem_value *ucontrol)
1748 {
1749 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1750 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
1751
1752 ucontrol->value.integer.value[0] = rt1320->cali_done;
1753 return 0;
1754 }
1755
rt1320_r0_cali_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1756 static int rt1320_r0_cali_put(struct snd_kcontrol *kcontrol,
1757 struct snd_ctl_elem_value *ucontrol)
1758 {
1759 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1760 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
1761 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(rt1320->component);
1762 int ret;
1763
1764 if (!rt1320->hw_init)
1765 return 0;
1766
1767 ret = pm_runtime_resume(component->dev);
1768 if (ret < 0 && ret != -EACCES)
1769 return ret;
1770
1771 rt1320->cali_done = false;
1772 snd_soc_dapm_mutex_lock(dapm);
1773 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF &&
1774 ucontrol->value.integer.value[0]) {
1775 rt1320_calibrate(rt1320);
1776 }
1777 snd_soc_dapm_mutex_unlock(dapm);
1778
1779 return 0;
1780 }
1781
1782 /*
1783 * The 'patch code' is written to the patch code area.
1784 * The patch code area is used for SDCA register expansion flexibility.
1785 */
rt1320_load_mcu_patch(struct rt1320_sdw_priv * rt1320)1786 static void rt1320_load_mcu_patch(struct rt1320_sdw_priv *rt1320)
1787 {
1788 struct sdw_slave *slave = rt1320->sdw_slave;
1789 const struct firmware *patch __free(firmware) = NULL;
1790 const char *filename;
1791 unsigned int addr, val, min_addr, max_addr;
1792 const unsigned char *ptr;
1793 int ret, i;
1794
1795 switch (rt1320->dev_id) {
1796 case RT1320_DEV_ID:
1797 if (rt1320->version_id <= RT1320_VB)
1798 filename = RT1320_VAB_MCU_PATCH;
1799 else
1800 filename = RT1320_VC_MCU_PATCH;
1801 min_addr = 0x10007000;
1802 max_addr = 0x10007fff;
1803 break;
1804 case RT1321_DEV_ID:
1805 if (rt1320->version_id == RT1321_VA2)
1806 return;
1807
1808 filename = RT1321_VA_MCU_PATCH;
1809 min_addr = 0x10008000;
1810 max_addr = 0x10008fff;
1811 break;
1812 default:
1813 dev_err(&slave->dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id);
1814 return;
1815 }
1816
1817 /* load the patch code here */
1818 ret = request_firmware(&patch, filename, &slave->dev);
1819 if (ret) {
1820 dev_err(&slave->dev, "%s: Failed to load %s firmware", __func__, filename);
1821 regmap_write(rt1320->regmap, 0xc598, 0x00);
1822 regmap_write(rt1320->regmap, min_addr, 0x67);
1823 regmap_write(rt1320->regmap, min_addr + 0x1, 0x80);
1824 regmap_write(rt1320->regmap, min_addr + 0x2, 0x00);
1825 regmap_write(rt1320->regmap, min_addr + 0x3, 0x00);
1826 if (rt1320->dev_id == RT1321_DEV_ID) {
1827 regmap_write(rt1320->regmap, 0xd73c, 0x67);
1828 regmap_write(rt1320->regmap, 0xd73d, 0x80);
1829 regmap_write(rt1320->regmap, 0xd73e, 0x00);
1830 regmap_write(rt1320->regmap, 0xd73f, 0x00);
1831 }
1832 } else {
1833 ptr = (const unsigned char *)patch->data;
1834 if ((patch->size % 8) == 0) {
1835 for (i = 0; i < patch->size; i += 8) {
1836 addr = (ptr[i] & 0xff) | (ptr[i + 1] & 0xff) << 8 |
1837 (ptr[i + 2] & 0xff) << 16 | (ptr[i + 3] & 0xff) << 24;
1838 val = (ptr[i + 4] & 0xff) | (ptr[i + 5] & 0xff) << 8 |
1839 (ptr[i + 6] & 0xff) << 16 | (ptr[i + 7] & 0xff) << 24;
1840
1841 if (addr > max_addr || addr < min_addr) {
1842 dev_err(&slave->dev, "%s: the address 0x%x is wrong", __func__, addr);
1843 return;
1844 }
1845 if (val > 0xff) {
1846 dev_err(&slave->dev, "%s: the value 0x%x is wrong", __func__, val);
1847 return;
1848 }
1849 regmap_write(rt1320->regmap, addr, val);
1850 }
1851 }
1852 }
1853 }
1854
rt1320_vab_preset(struct rt1320_sdw_priv * rt1320)1855 static void rt1320_vab_preset(struct rt1320_sdw_priv *rt1320)
1856 {
1857 unsigned int i, reg, val, delay;
1858
1859 for (i = 0; i < ARRAY_SIZE(rt1320_blind_write); i++) {
1860 reg = rt1320_blind_write[i].reg;
1861 val = rt1320_blind_write[i].def;
1862 delay = rt1320_blind_write[i].delay_us;
1863
1864 if (reg == 0x3fc2bfc7)
1865 rt1320_load_mcu_patch(rt1320);
1866
1867 regmap_write(rt1320->regmap, reg, val);
1868 if (delay)
1869 usleep_range(delay, delay + 1000);
1870 }
1871 }
1872
rt1320_t0_load(struct rt1320_sdw_priv * rt1320,unsigned int l_t0,unsigned int r_t0)1873 static void rt1320_t0_load(struct rt1320_sdw_priv *rt1320, unsigned int l_t0, unsigned int r_t0)
1874 {
1875 struct device *dev = &rt1320->sdw_slave->dev;
1876 unsigned int factor = (1 << 22);
1877 int l_t0_data[38], r_t0_data[38];
1878 int dspfw_status;
1879
1880 regmap_write(rt1320->regmap,
1881 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23,
1882 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00);
1883 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x00);
1884
1885 dspfw_status = rt1320_dspfw_status(rt1320);
1886 if (dspfw_status <= 0) {
1887 dev_warn(dev, "%s, DSP FW is NOT ready\n", __func__);
1888 goto _exit_;
1889 }
1890
1891 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 3, &l_t0_data[0], sizeof(l_t0_data));
1892 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 4, &r_t0_data[0], sizeof(r_t0_data));
1893
1894 l_t0_data[37] = l_t0 * factor;
1895 r_t0_data[37] = r_t0 * factor;
1896
1897 dev_dbg(dev, "%s, write LR t0=0x%x, 0x%x\n", __func__, l_t0_data[37], r_t0_data[37]);
1898
1899 rt1320_fw_param_protocol(rt1320, RT1320_SET_PARAM, 3, &l_t0_data[0], sizeof(l_t0_data));
1900 rt1320_fw_param_protocol(rt1320, RT1320_SET_PARAM, 4, &r_t0_data[0], sizeof(r_t0_data));
1901 if (rt1320_check_fw_ready(rt1320) < 0)
1902 dev_err(dev, "%s: Failed to set FW param 3,4!\n", __func__);
1903
1904 rt1320->temp_l_calib = l_t0;
1905 rt1320->temp_r_calib = r_t0;
1906
1907 memset(&l_t0_data[0], 0x00, sizeof(l_t0_data));
1908 memset(&r_t0_data[0], 0x00, sizeof(r_t0_data));
1909 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 3, &l_t0_data[0], sizeof(l_t0_data));
1910 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 4, &r_t0_data[0], sizeof(r_t0_data));
1911 dev_dbg(dev, "%s, read after writing LR t0=0x%x, 0x%x\n", __func__, l_t0_data[37], r_t0_data[37]);
1912
1913 _exit_:
1914 regmap_write(rt1320->regmap,
1915 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23,
1916 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03);
1917 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x03);
1918 }
1919
rt1320_rae_load(struct rt1320_sdw_priv * rt1320)1920 static int rt1320_rae_load(struct rt1320_sdw_priv *rt1320)
1921 {
1922 struct device *dev = &rt1320->sdw_slave->dev;
1923 static const char func_tag[] = "FUNC";
1924 static const char xu_tag[] = "XU";
1925 const struct firmware *rae_fw __free(firmware) = NULL;
1926 unsigned int fw_offset;
1927 unsigned char *fw_data;
1928 unsigned char *param_data;
1929 unsigned int addr, size;
1930 unsigned int func, value;
1931 const char *dmi_vendor, *dmi_product, *dmi_sku;
1932 int len_vendor, len_product, len_sku;
1933 char rae_filename[512];
1934 char tag[5];
1935 int ret = 0;
1936 int retry = 200;
1937
1938 dmi_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
1939 dmi_product = dmi_get_system_info(DMI_PRODUCT_NAME);
1940 dmi_sku = dmi_get_system_info(DMI_PRODUCT_SKU);
1941
1942 if (dmi_vendor && dmi_product && dmi_sku) {
1943 len_vendor = strchrnul(dmi_vendor, ' ') - dmi_vendor;
1944 len_product = strchrnul(dmi_product, ' ') - dmi_product;
1945 len_sku = strchrnul(dmi_sku, ' ') - dmi_sku;
1946
1947 snprintf(rae_filename, sizeof(rae_filename),
1948 "realtek/rt1320/rt1320_RAE_%.*s_%.*s_%.*s.dat",
1949 len_vendor, dmi_vendor, len_product, dmi_product, len_sku, dmi_sku);
1950 dev_dbg(dev, "%s: try to load RAE file %s\n", __func__, rae_filename);
1951 } else {
1952 dev_warn(dev, "%s: Can't find proper RAE file name\n", __func__);
1953 return -EINVAL;
1954 }
1955
1956 regmap_write(rt1320->regmap,
1957 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23,
1958 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00);
1959 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x00);
1960
1961 request_firmware(&rae_fw, rae_filename, dev);
1962 if (rae_fw) {
1963
1964 switch (rt1320->dev_id) {
1965 case RT1320_DEV_ID:
1966 /* RAE CRC clear */
1967 regmap_write(rt1320->regmap, 0xe80b, 0x0f);
1968 /* RAE stop & CRC disable */
1969 regmap_update_bits(rt1320->regmap, 0xe803, 0xbc, 0x00);
1970 while (--retry) {
1971 regmap_read(rt1320->regmap, 0xe83f, &value);
1972 if (value & 0x40)
1973 break;
1974 usleep_range(1000, 1100);
1975 }
1976 if (!retry && !(value & 0x40)) {
1977 dev_err(dev, "%s: RAE is not ready to load\n", __func__);
1978 return -ETIMEDOUT;
1979 }
1980 break;
1981 case RT1321_DEV_ID:
1982 /* RAE CRC clear */
1983 regmap_write(rt1320->regmap, 0x2000300e, 0xc0);
1984 regmap_write(rt1320->regmap, 0x2000300f, 0x0f);
1985 /* RAE stop & Phase sync & CRC disable */
1986 regmap_update_bits(rt1320->regmap, 0x20003003, 0xfe, 0x00);
1987 regmap_update_bits(rt1320->regmap, 0xc047, 0x80, 0x00);
1988 regmap_update_bits(rt1320->regmap, 0x2000301c, 0x01, 0x00);
1989 /* check whether write state is ready */
1990 while (--retry) {
1991 regmap_read(rt1320->regmap, 0x20003043, &value);
1992 if (value & 0x40)
1993 break;
1994 usleep_range(1000, 1100);
1995 }
1996 if (!retry && !(value & 0x40)) {
1997 dev_err(dev, "%s: RAE is not ready to load\n", __func__);
1998 return -ETIMEDOUT;
1999 }
2000 break;
2001 default:
2002 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id);
2003 return -EINVAL;
2004 }
2005
2006 dev_dbg(dev, "%s, rae_fw size=0x%zx\n", __func__, rae_fw->size);
2007 regcache_cache_bypass(rt1320->regmap, true);
2008 for (fw_offset = 0; fw_offset < rae_fw->size;) {
2009
2010 dev_dbg(dev, "%s, fw_offset=0x%x\n", __func__, fw_offset);
2011
2012 fw_data = (unsigned char *)&rae_fw->data[fw_offset];
2013
2014 memcpy(tag, fw_data, 4);
2015 tag[4] = '\0';
2016 dev_dbg(dev, "%s, tag=%s\n", __func__, tag);
2017 if (strcmp(tag, xu_tag) == 0) {
2018 dev_dbg(dev, "%s: This is a XU tag", __func__);
2019 memcpy(&addr, (fw_data + 4), 4);
2020 memcpy(&size, (fw_data + 8), 4);
2021 param_data = (unsigned char *)(fw_data + 12);
2022
2023 dev_dbg(dev, "%s: addr=0x%x, size=0x%x\n", __func__, addr, size);
2024
2025 /*
2026 * UI register ranges from 0x1000d000 to 0x1000d7ff
2027 * UI registers should be accessed by tuning tool.
2028 * So, there registers should be cached.
2029 */
2030 if (addr <= 0x1000d7ff && addr >= 0x1000d000)
2031 regcache_cache_bypass(rt1320->regmap, false);
2032
2033 rt1320_data_rw(rt1320, addr, param_data, size, RT1320_PARAM_WRITE);
2034
2035 regcache_cache_bypass(rt1320->regmap, true);
2036
2037 fw_offset += (size + 12);
2038 } else if (strcmp(tag, func_tag) == 0) {
2039 dev_err(dev, "%s: This is a FUNC tag", __func__);
2040
2041 memcpy(&func, (fw_data + 4), 4);
2042 memcpy(&value, (fw_data + 8), 4);
2043
2044 dev_dbg(dev, "%s: func=0x%x, value=0x%x\n", __func__, func, value);
2045 if (func == 1) //DelayMs
2046 msleep(value);
2047
2048 fw_offset += 12;
2049 } else {
2050 dev_err(dev, "%s: This is NOT a XU file (wrong tag)", __func__);
2051 break;
2052 }
2053 }
2054
2055 regcache_cache_bypass(rt1320->regmap, false);
2056
2057 } else {
2058 dev_err(dev, "%s: Failed to load %s firmware\n", __func__, rae_filename);
2059 ret = -EINVAL;
2060 goto _exit_;
2061 }
2062
2063 switch (rt1320->dev_id) {
2064 case RT1320_DEV_ID:
2065 /* RAE CRC enable */
2066 regmap_update_bits(rt1320->regmap, 0xe803, 0x0c, 0x0c);
2067 /* RAE update */
2068 regmap_update_bits(rt1320->regmap, 0xe80b, 0x80, 0x00);
2069 regmap_update_bits(rt1320->regmap, 0xe80b, 0x80, 0x80);
2070 /* RAE run */
2071 regmap_update_bits(rt1320->regmap, 0xe803, 0x80, 0x80);
2072 regmap_read(rt1320->regmap, 0xe80b, &value);
2073 dev_dbg(dev, "%s: CAE run => 0xe80b reg = 0x%x\n", __func__, value);
2074 break;
2075 case RT1321_DEV_ID:
2076 /* RAE CRC enable */
2077 regmap_update_bits(rt1320->regmap, 0x20003003, 0x30, 0x30);
2078 /* RAE update */
2079 regmap_update_bits(rt1320->regmap, 0x2000301c, 0x80, 0x00);
2080 regmap_update_bits(rt1320->regmap, 0x2000301c, 0x80, 0x80);
2081 regmap_update_bits(rt1320->regmap, 0x20009018, 0x80, 0x00);
2082 regmap_update_bits(rt1320->regmap, 0x20009018, 0x80, 0x80);
2083 regmap_update_bits(rt1320->regmap, 0x20005818, 0x80, 0x00);
2084 regmap_update_bits(rt1320->regmap, 0x20005818, 0x80, 0x80);
2085 /* RAE run */
2086 regmap_update_bits(rt1320->regmap, 0x2000301c, 0x01, 0x01);
2087 /* Phase sync eanble */
2088 regmap_update_bits(rt1320->regmap, 0xc047, 0x80, 0x80);
2089 break;
2090 }
2091
2092 rt1320->rae_update_done = true;
2093
2094 _exit_:
2095 regmap_write(rt1320->regmap,
2096 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23,
2097 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03);
2098 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x03);
2099
2100 return ret;
2101 }
2102
rt1320_dspfw_load_code(struct rt1320_sdw_priv * rt1320)2103 static void rt1320_dspfw_load_code(struct rt1320_sdw_priv *rt1320)
2104 {
2105 struct rt1320_imageinfo {
2106 unsigned int addr;
2107 unsigned int size;
2108 };
2109
2110 struct rt1320_dspfwheader {
2111 unsigned int sync;
2112 short num;
2113 short crc;
2114 };
2115
2116 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(rt1320->component);
2117 struct device *dev = &rt1320->sdw_slave->dev;
2118 unsigned int val, i, fw_offset;
2119 struct rt1320_dspfwheader *fwheader;
2120 struct rt1320_imageinfo *ptr_img;
2121 struct sdw_bpt_section sec[10];
2122 const struct firmware *fw __free(firmware) = NULL;
2123 unsigned char *fw_data;
2124 bool dev_fw_match = false;
2125 static const char hdr_sig[] = "AFX";
2126 unsigned int hdr_size = 0;
2127 const char *dmi_vendor, *dmi_product, *dmi_sku;
2128 int len_vendor, len_product, len_sku;
2129 unsigned char boot_mode = 0; /* 0: from RAM; 1: from ROM */
2130 unsigned char has_0x3fc00000 = 0;
2131 char filename[512];
2132
2133 dmi_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
2134 dmi_product = dmi_get_system_info(DMI_PRODUCT_NAME);
2135 dmi_sku = dmi_get_system_info(DMI_PRODUCT_SKU);
2136
2137 if (dmi_vendor && dmi_product && dmi_sku) {
2138 len_vendor = strchrnul(dmi_vendor, ' ') - dmi_vendor;
2139 len_product = strchrnul(dmi_product, ' ') - dmi_product;
2140 len_sku = strchrnul(dmi_sku, ' ') - dmi_sku;
2141
2142 snprintf(filename, sizeof(filename),
2143 "realtek/rt1320/rt1320_%.*s_%.*s_%.*s.dat",
2144 len_vendor, dmi_vendor, len_product, dmi_product, len_sku, dmi_sku);
2145
2146 dev_dbg(dev, "%s: try to load FW file %s\n", __func__, filename);
2147 } else if (rt1320->dspfw_name) {
2148 snprintf(filename, sizeof(filename), "rt1320_%s.dat",
2149 rt1320->dspfw_name);
2150 dev_dbg(dev, "%s: try to load FW file %s\n", __func__, filename);
2151 } else {
2152 dev_warn(dev, "%s: Can't find proper FW file name\n", __func__);
2153 return;
2154 }
2155
2156 snd_soc_dapm_mutex_lock(dapm);
2157 regmap_write(rt1320->regmap,
2158 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23,
2159 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00);
2160 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x00);
2161
2162 if (rt1320_dspfw_status(rt1320)) {
2163 dev_dbg(dev, "%s, DSP FW was already\n", __func__);
2164 rt1320->fw_load_done = true;
2165 goto _exit_;
2166 }
2167
2168 request_firmware(&fw, filename, dev);
2169 if (fw) {
2170 fwheader = (struct rt1320_dspfwheader *)fw->data;
2171 dev_dbg(dev, "%s, fw sync = 0x%x, num=%d, crc=0x%x\n", __func__,
2172 fwheader->sync, fwheader->num, fwheader->crc);
2173
2174 if (fwheader->sync != 0x0a1c5679) {
2175 dev_err(dev, "%s: FW sync error\n", __func__);
2176 goto _exit_;
2177 }
2178
2179 fw_offset = sizeof(struct rt1320_dspfwheader) + (sizeof(struct rt1320_imageinfo) * fwheader->num);
2180 dev_dbg(dev, "%s, fw_offset = 0x%x\n", __func__, fw_offset);
2181
2182 regcache_cache_bypass(rt1320->regmap, true);
2183
2184 for (i = 0; i < fwheader->num; i++) {
2185 ptr_img = (struct rt1320_imageinfo *)&fw->data[sizeof(struct rt1320_dspfwheader) + (sizeof(struct rt1320_imageinfo) * i)];
2186
2187 dev_dbg(dev, "%s, fw_offset=0x%x, load fw addr=0x%x, size=%d\n", __func__,
2188 fw_offset, ptr_img->addr, ptr_img->size);
2189
2190 fw_data = (unsigned char *)&fw->data[fw_offset];
2191
2192 /* The binary file has a header of 64 bytes */
2193 if (memcmp(fw_data, hdr_sig, sizeof(hdr_sig)) == 0)
2194 hdr_size = 64;
2195 else
2196 hdr_size = 0;
2197
2198 sec[i].addr = ptr_img->addr;
2199 sec[i].len = ptr_img->size - hdr_size;
2200 sec[i].buf = fw_data + hdr_size;
2201
2202 dev_dbg(dev, "%s, hdr_size=%d, sec[%d].buf[0]=0x%x\n",
2203 __func__, hdr_size, i, sec[i].buf[0]);
2204
2205 switch (rt1320->dev_id) {
2206 case RT1320_DEV_ID:
2207 if (ptr_img->addr == 0x3fc29d80)
2208 if (fw_data[9] == '0')
2209 dev_fw_match = true;
2210 break;
2211 case RT1321_DEV_ID:
2212 if (ptr_img->addr == 0x3fc00000) {
2213 if (fw_data[7] == '1')
2214 dev_fw_match = true;
2215 has_0x3fc00000 = 1;
2216 }
2217 break;
2218 default:
2219 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id);
2220 goto _exit_;
2221 }
2222
2223 fw_offset += ptr_img->size;
2224 }
2225
2226 if (rt1320->dev_id == RT1321_DEV_ID && rt1320->version_id == RT1321_VA2) {
2227 /*
2228 * For 1321 VA2, if the FW doesn't include the section for address 0x3fc00000,
2229 * it means the FW will boot from ROM and force dev_fw_match to true to download FW by BRA.
2230 */
2231 if (!has_0x3fc00000) {
2232 boot_mode = 1;
2233 dev_fw_match = true;
2234 }
2235 dev_dbg(dev, "%s: Boot from %s for VA2\n", __func__, (boot_mode ? "ROM" : "RAM"));
2236 }
2237
2238 /* change to IRAM */
2239 if (!boot_mode)
2240 regmap_update_bits(rt1320->regmap, 0xf01e, 0x80, 0x00);
2241
2242 if (dev_fw_match) {
2243 dev_dbg(dev, "%s, starting BRA downloading FW..\n", __func__);
2244 rt1320->bra_msg.dev_num = rt1320->sdw_slave->dev_num;
2245 rt1320->bra_msg.flags = SDW_MSG_FLAG_WRITE;
2246 rt1320->bra_msg.sections = fwheader->num;
2247 rt1320->bra_msg.sec = &sec[0];
2248 rt1320_data_rw(rt1320, 0, NULL, 0, RT1320_BRA_WRITE);
2249 dev_dbg(dev, "%s, BRA downloading FW done..\n", __func__);
2250 }
2251
2252 regcache_cache_bypass(rt1320->regmap, false);
2253
2254 if (!dev_fw_match) {
2255 dev_err(dev, "%s: FW file doesn't match to device\n", __func__);
2256 goto _exit_;
2257 }
2258 } else {
2259 dev_err(dev, "%s: Failed to load %s firmware\n", __func__, filename);
2260 goto _exit_;
2261 }
2262
2263 switch (rt1320->dev_id) {
2264 case RT1320_DEV_ID:
2265 /* run RAM code */
2266 regmap_read(rt1320->regmap, 0x3fc2bfc0, &val);
2267 val |= 0x8;
2268 regmap_write(rt1320->regmap, 0x3fc2bfc0, val);
2269 /* clear frame counter */
2270 regmap_write(rt1320->regmap, 0x3fc2bfcb, 0x00);
2271 regmap_write(rt1320->regmap, 0x3fc2bfca, 0x00);
2272 regmap_write(rt1320->regmap, 0x3fc2bfc9, 0x00);
2273 regmap_write(rt1320->regmap, 0x3fc2bfc8, 0x00);
2274 break;
2275 case RT1321_DEV_ID:
2276 if (!boot_mode) {
2277 /* run RAM code */
2278 regmap_read(rt1320->regmap, 0x3fc2dfc0, &val);
2279 val |= 0x8;
2280 regmap_write(rt1320->regmap, 0x3fc2dfc0, val);
2281 }
2282 /* clear frame counter */
2283 regmap_write(rt1320->regmap, 0x3fc2dfcb, 0x00);
2284 regmap_write(rt1320->regmap, 0x3fc2dfca, 0x00);
2285 regmap_write(rt1320->regmap, 0x3fc2dfc9, 0x00);
2286 regmap_write(rt1320->regmap, 0x3fc2dfc8, 0x00);
2287 /* enable handshake */
2288 regmap_write(rt1320->regmap, 0x3fc2dfc4, 0x00);
2289 regmap_write(rt1320->regmap, 0xd470, 0xad);
2290 /* minimum phase settings */
2291 regmap_write(rt1320->regmap, 0xc5c4, 0x10);
2292 regmap_write(rt1320->regmap, 0x20003003, 0x31);
2293 regmap_update_bits(rt1320->regmap, 0x20003002, 0x40, 0x00);
2294 regmap_write(rt1320->regmap, 0xc5b3, 0x01);
2295 regmap_write(rt1320->regmap, 0xc052, 0x11);
2296 break;
2297 }
2298
2299 /* enable DSP FW */
2300 regmap_write(rt1320->regmap, 0xc081, 0xfc);
2301 regmap_update_bits(rt1320->regmap, 0xf01e, 0x1, 0x0);
2302
2303 /* RsRatio should restore into DSP FW when FW was ready */
2304 rt1320_invrs_load(rt1320);
2305
2306 /* DSP clock switches to PLL */
2307 regmap_write(rt1320->regmap, 0xc081, 0xfc);
2308 /* pass DSP settings */
2309 regmap_write(rt1320->regmap, 0xc5c3, 0xf3);
2310 regmap_write(rt1320->regmap, 0xc5c8, 0x05);
2311
2312 rt1320->fw_load_done = true;
2313
2314 pm_runtime_set_autosuspend_delay(dev, 3000);
2315 pm_runtime_mark_last_busy(dev);
2316
2317 _exit_:
2318 regmap_write(rt1320->regmap,
2319 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23,
2320 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03);
2321 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x03);
2322
2323 snd_soc_dapm_mutex_unlock(dapm);
2324 }
2325
rt1320_load_dspfw_work(struct work_struct * work)2326 static void rt1320_load_dspfw_work(struct work_struct *work)
2327 {
2328 struct rt1320_sdw_priv *rt1320 =
2329 container_of(work, struct rt1320_sdw_priv, load_dspfw_work);
2330 int ret;
2331
2332 ret = pm_runtime_resume(rt1320->component->dev);
2333 if (ret < 0 && ret != -EACCES)
2334 return;
2335
2336 dev_dbg(&rt1320->sdw_slave->dev, "%s, Starting to reload DSP FW", __func__);
2337 rt1320_dspfw_load_code(rt1320);
2338 }
2339
rt1320_vc_preset(struct rt1320_sdw_priv * rt1320)2340 static void rt1320_vc_preset(struct rt1320_sdw_priv *rt1320)
2341 {
2342 struct sdw_slave *slave = rt1320->sdw_slave;
2343 unsigned int i, reg, val, delay, retry, tmp;
2344
2345 for (i = 0; i < ARRAY_SIZE(rt1320_vc_blind_write); i++) {
2346 reg = rt1320_vc_blind_write[i].reg;
2347 val = rt1320_vc_blind_write[i].def;
2348 delay = rt1320_vc_blind_write[i].delay_us;
2349
2350 if (reg == 0x3fc2bf83)
2351 rt1320_load_mcu_patch(rt1320);
2352
2353 if ((reg == SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0)) &&
2354 (val == 0x00)) {
2355 retry = 200;
2356 while (retry) {
2357 regmap_read(rt1320->regmap, RT1320_KR0_INT_READY, &tmp);
2358 dev_dbg(&slave->dev, "%s, RT1320_KR0_INT_READY=0x%x\n", __func__, tmp);
2359 if (tmp == 0x1f)
2360 break;
2361 usleep_range(1000, 1500);
2362 retry--;
2363 }
2364 if (!retry)
2365 dev_warn(&slave->dev, "%s MCU is NOT ready!", __func__);
2366 }
2367 regmap_write(rt1320->regmap, reg, val);
2368 if (delay)
2369 usleep_range(delay, delay + 1000);
2370
2371 if (reg == SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0))
2372 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, val);
2373 }
2374 }
2375
rt1321_preset(struct rt1320_sdw_priv * rt1320)2376 static void rt1321_preset(struct rt1320_sdw_priv *rt1320)
2377 {
2378 const struct reg_sequence *blindwrite;
2379 unsigned int i, reg, val, delay;
2380 unsigned int array_size;
2381
2382 switch (rt1320->version_id) {
2383 case RT1321_VA0:
2384 blindwrite = rt1321_blind_write;
2385 array_size = ARRAY_SIZE(rt1321_blind_write);
2386 break;
2387 case RT1321_VA1:
2388 blindwrite = rt1321_va1_blind_write;
2389 array_size = ARRAY_SIZE(rt1321_va1_blind_write);
2390 break;
2391 case RT1321_VA2:
2392 blindwrite = rt1321_va2_blind_write;
2393 array_size = ARRAY_SIZE(rt1321_va2_blind_write);
2394 break;
2395 default:
2396 dev_err(&rt1320->sdw_slave->dev, "%s: Unknown version ID %d\n",
2397 __func__, rt1320->version_id);
2398 return;
2399 }
2400
2401 for (i = 0; i < array_size; i++) {
2402 reg = blindwrite[i].reg;
2403 val = blindwrite[i].def;
2404 delay = blindwrite[i].delay_us;
2405
2406 if (reg == 0x1000cd56)
2407 rt1320_load_mcu_patch(rt1320);
2408
2409 regmap_write(rt1320->regmap, reg, val);
2410
2411 if (delay)
2412 usleep_range(delay, delay + 1000);
2413
2414 if (reg == SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0))
2415 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, val);
2416 }
2417 }
2418
rt1320_io_init(struct device * dev,struct sdw_slave * slave)2419 static int rt1320_io_init(struct device *dev, struct sdw_slave *slave)
2420 {
2421 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev);
2422 unsigned int amp_func_status, val, tmp;
2423
2424 if (rt1320->hw_init)
2425 return 0;
2426
2427 regcache_cache_only(rt1320->regmap, false);
2428 regcache_cache_only(rt1320->mbq_regmap, false);
2429 if (rt1320->first_hw_init) {
2430 regcache_cache_bypass(rt1320->regmap, true);
2431 regcache_cache_bypass(rt1320->mbq_regmap, true);
2432 } else {
2433 /*
2434 * PM runtime status is marked as 'active' only when a Slave reports as Attached
2435 */
2436 /* update count of parent 'active' children */
2437 pm_runtime_set_active(&slave->dev);
2438 }
2439
2440 pm_runtime_get_noresume(&slave->dev);
2441
2442 if (rt1320->version_id < 0) {
2443 regmap_read(rt1320->regmap, RT1320_DEV_VERSION_ID_1, &val);
2444 rt1320->version_id = val;
2445 regmap_read(rt1320->regmap, RT1320_DEV_ID_0, &val);
2446 regmap_read(rt1320->regmap, RT1320_DEV_ID_1, &tmp);
2447 rt1320->dev_id = (val << 8) | tmp;
2448
2449 /* This is a workaround that reads the value twice to obtain the correct result. */
2450 rt1320_pr_read(rt1320, RT1320_HV_DEV_ID_0, &val);
2451 rt1320_pr_read(rt1320, RT1320_HV_DEV_ID_1, &tmp);
2452 rt1320_pr_read(rt1320, RT1320_HV_DEV_ID_0, &val);
2453 rt1320_pr_read(rt1320, RT1320_HV_DEV_ID_1, &tmp);
2454 val = (val << 8) | tmp;
2455
2456 if (rt1320->dev_id == RT1321_DEV_ID) {
2457 if (rt1320->version_id == 0x01)
2458 rt1320->version_id = RT1321_VA2;
2459 else if (val == RT1321_DEV_HV_VA0_ID)
2460 rt1320->version_id = RT1321_VA0;
2461 else if (val == RT1321_DEV_HV_VA1_ID)
2462 rt1320->version_id = RT1321_VA1;
2463 else
2464 dev_err(dev, "%s: Unknown version ID 0x%x for RT1321\n", __func__, rt1320->version_id);
2465 }
2466 }
2467
2468 regmap_read(rt1320->regmap,
2469 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0), &_func_status);
2470 dev_dbg(dev, "%s amp func_status=0x%x\n", __func__, amp_func_status);
2471
2472 /* initialization write */
2473 if ((amp_func_status & FUNCTION_NEEDS_INITIALIZATION) || !rt1320->first_hw_init) {
2474 switch (rt1320->dev_id) {
2475 case RT1320_DEV_ID:
2476 if (rt1320->version_id < RT1320_VC)
2477 rt1320_vab_preset(rt1320);
2478 else
2479 rt1320_vc_preset(rt1320);
2480 break;
2481 case RT1321_DEV_ID:
2482 rt1321_preset(rt1320);
2483 break;
2484 default:
2485 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id);
2486 }
2487
2488 regmap_write(rt1320->regmap,
2489 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0),
2490 FUNCTION_NEEDS_INITIALIZATION);
2491
2492 /* reload DSP FW */
2493 if (rt1320->fw_load_done)
2494 schedule_work(&rt1320->load_dspfw_work);
2495 }
2496 if (!rt1320->first_hw_init && rt1320->version_id == RT1320_VA && rt1320->dev_id == RT1320_DEV_ID) {
2497 regmap_write(rt1320->regmap, SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23,
2498 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0);
2499 regmap_read(rt1320->regmap, RT1320_HIFI_VER_0, &val);
2500 regmap_read(rt1320->regmap, RT1320_HIFI_VER_1, &tmp);
2501 val = (tmp << 8) | val;
2502 regmap_read(rt1320->regmap, RT1320_HIFI_VER_2, &tmp);
2503 val = (tmp << 16) | val;
2504 regmap_read(rt1320->regmap, RT1320_HIFI_VER_3, &tmp);
2505 val = (tmp << 24) | val;
2506 dev_dbg(dev, "%s ROM version=0x%x\n", __func__, val);
2507 /*
2508 * We call the version b which has the new DSP ROM code against version a.
2509 * Therefore, we read the DSP address to check the ID.
2510 */
2511 if (val == RT1320_VER_B_ID)
2512 rt1320->version_id = RT1320_VB;
2513 regmap_write(rt1320->regmap, SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23,
2514 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 3);
2515 }
2516 dev_dbg(dev, "%s version_id=%d, dev_id=0x%x\n", __func__, rt1320->version_id, rt1320->dev_id);
2517
2518 if (rt1320->first_hw_init) {
2519 regcache_cache_bypass(rt1320->regmap, false);
2520 regcache_cache_bypass(rt1320->mbq_regmap, false);
2521 regcache_mark_dirty(rt1320->regmap);
2522 regcache_mark_dirty(rt1320->mbq_regmap);
2523 }
2524
2525 /* Mark Slave initialization complete */
2526 rt1320->first_hw_init = true;
2527 rt1320->hw_init = true;
2528
2529 pm_runtime_put_autosuspend(&slave->dev);
2530
2531 dev_dbg(&slave->dev, "%s hw_init complete\n", __func__);
2532 return 0;
2533 }
2534
rt1320_update_status(struct sdw_slave * slave,enum sdw_slave_status status)2535 static int rt1320_update_status(struct sdw_slave *slave,
2536 enum sdw_slave_status status)
2537 {
2538 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(&slave->dev);
2539
2540 if (status == SDW_SLAVE_UNATTACHED)
2541 rt1320->hw_init = false;
2542
2543 /*
2544 * Perform initialization only if slave status is present and
2545 * hw_init flag is false
2546 */
2547 if (rt1320->hw_init || status != SDW_SLAVE_ATTACHED)
2548 return 0;
2549
2550 /* perform I/O transfers required for Slave initialization */
2551 return rt1320_io_init(&slave->dev, slave);
2552 }
2553
rt1320_pde11_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)2554 static int rt1320_pde11_event(struct snd_soc_dapm_widget *w,
2555 struct snd_kcontrol *kcontrol, int event)
2556 {
2557 struct snd_soc_component *component =
2558 snd_soc_dapm_to_component(w->dapm);
2559 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
2560 unsigned char ps0 = 0x0, ps3 = 0x3;
2561
2562 switch (event) {
2563 case SND_SOC_DAPM_POST_PMU:
2564 regmap_write(rt1320->regmap,
2565 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11,
2566 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps0);
2567 rt1320_pde_transition_delay(rt1320, FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, ps0);
2568 break;
2569 case SND_SOC_DAPM_PRE_PMD:
2570 regmap_write(rt1320->regmap,
2571 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11,
2572 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps3);
2573 rt1320_pde_transition_delay(rt1320, FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, ps3);
2574 break;
2575 default:
2576 break;
2577 }
2578
2579 return 0;
2580 }
2581
rt1320_pde23_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)2582 static int rt1320_pde23_event(struct snd_soc_dapm_widget *w,
2583 struct snd_kcontrol *kcontrol, int event)
2584 {
2585 struct snd_soc_component *component =
2586 snd_soc_dapm_to_component(w->dapm);
2587 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
2588 unsigned char ps0 = 0x0, ps3 = 0x3;
2589
2590 switch (event) {
2591 case SND_SOC_DAPM_POST_PMU:
2592 regmap_write(rt1320->regmap,
2593 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23,
2594 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps0);
2595 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, ps0);
2596 break;
2597 case SND_SOC_DAPM_PRE_PMD:
2598 regmap_write(rt1320->regmap,
2599 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23,
2600 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps3);
2601 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, ps3);
2602 break;
2603 default:
2604 break;
2605 }
2606
2607 return 0;
2608 }
2609
rt1320_set_gain_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2610 static int rt1320_set_gain_put(struct snd_kcontrol *kcontrol,
2611 struct snd_ctl_elem_value *ucontrol)
2612 {
2613 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2614 struct soc_mixer_control *mc =
2615 (struct soc_mixer_control *)kcontrol->private_value;
2616 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
2617 unsigned int gain_l_val, gain_r_val;
2618 unsigned int lvalue, rvalue;
2619 const unsigned int interval_offset = 0xc0;
2620 unsigned int changed = 0, reg_base;
2621 struct rt_sdca_dmic_kctrl_priv *p;
2622 unsigned int regvalue[4], gain_val[4], i;
2623 int err;
2624
2625 if (strstr(ucontrol->id.name, "FU Capture Volume"))
2626 goto _dmic_vol_;
2627
2628 regmap_read(rt1320->mbq_regmap, mc->reg, &lvalue);
2629 regmap_read(rt1320->mbq_regmap, mc->rreg, &rvalue);
2630
2631 /* L Channel */
2632 gain_l_val = ucontrol->value.integer.value[0];
2633 if (gain_l_val > mc->max)
2634 gain_l_val = mc->max;
2635 gain_l_val = 0 - ((mc->max - gain_l_val) * interval_offset);
2636 gain_l_val &= 0xffff;
2637
2638 /* R Channel */
2639 gain_r_val = ucontrol->value.integer.value[1];
2640 if (gain_r_val > mc->max)
2641 gain_r_val = mc->max;
2642 gain_r_val = 0 - ((mc->max - gain_r_val) * interval_offset);
2643 gain_r_val &= 0xffff;
2644
2645 if (lvalue == gain_l_val && rvalue == gain_r_val)
2646 return 0;
2647
2648 /* Lch*/
2649 regmap_write(rt1320->mbq_regmap, mc->reg, gain_l_val);
2650 /* Rch */
2651 regmap_write(rt1320->mbq_regmap, mc->rreg, gain_r_val);
2652 goto _done_;
2653
2654 _dmic_vol_:
2655 p = (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value;
2656
2657 /* check all channels */
2658 for (i = 0; i < p->count; i++) {
2659 switch (rt1320->dev_id) {
2660 case RT1320_DEV_ID:
2661 if (i < 2) {
2662 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
2663 regmap_read(rt1320->mbq_regmap, reg_base + i, ®value[i]);
2664 } else {
2665 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
2666 regmap_read(rt1320->mbq_regmap, reg_base + i - 2, ®value[i]);
2667 }
2668 break;
2669 case RT1321_DEV_ID:
2670 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
2671 regmap_read(rt1320->mbq_regmap, reg_base + i, ®value[i]);
2672 break;
2673 }
2674
2675 gain_val[i] = ucontrol->value.integer.value[i];
2676 if (gain_val[i] > p->max)
2677 gain_val[i] = p->max;
2678
2679 gain_val[i] = 0x1e00 - ((p->max - gain_val[i]) * interval_offset);
2680 gain_val[i] &= 0xffff;
2681 if (regvalue[i] != gain_val[i])
2682 changed = 1;
2683 }
2684
2685 if (!changed)
2686 return 0;
2687
2688 for (i = 0; i < p->count; i++) {
2689 switch (rt1320->dev_id) {
2690 case RT1320_DEV_ID:
2691 if (i < 2) {
2692 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
2693 err = regmap_write(rt1320->mbq_regmap, reg_base + i, gain_val[i]);
2694 } else {
2695 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
2696 err = regmap_write(rt1320->mbq_regmap, reg_base + i - 2, gain_val[i]);
2697 }
2698 break;
2699 case RT1321_DEV_ID:
2700 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
2701 err = regmap_write(rt1320->mbq_regmap, reg_base + i, gain_val[i]);
2702 break;
2703 }
2704
2705 if (err < 0)
2706 dev_err(&rt1320->sdw_slave->dev, "0x%08x can't be set\n", reg_base + i);
2707 }
2708
2709 _done_:
2710 return 1;
2711 }
2712
rt1320_set_gain_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2713 static int rt1320_set_gain_get(struct snd_kcontrol *kcontrol,
2714 struct snd_ctl_elem_value *ucontrol)
2715 {
2716 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2717 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
2718 struct soc_mixer_control *mc =
2719 (struct soc_mixer_control *)kcontrol->private_value;
2720 unsigned int read_l, read_r, ctl_l = 0, ctl_r = 0;
2721 const unsigned int interval_offset = 0xc0;
2722 unsigned int reg_base, regvalue, ctl, i;
2723 struct rt_sdca_dmic_kctrl_priv *p;
2724
2725 if (strstr(ucontrol->id.name, "FU Capture Volume"))
2726 goto _dmic_vol_;
2727
2728 regmap_read(rt1320->mbq_regmap, mc->reg, &read_l);
2729 regmap_read(rt1320->mbq_regmap, mc->rreg, &read_r);
2730
2731 ctl_l = mc->max - (((0 - read_l) & 0xffff) / interval_offset);
2732
2733 if (read_l != read_r)
2734 ctl_r = mc->max - (((0 - read_r) & 0xffff) / interval_offset);
2735 else
2736 ctl_r = ctl_l;
2737
2738 ucontrol->value.integer.value[0] = ctl_l;
2739 ucontrol->value.integer.value[1] = ctl_r;
2740 goto _done_;
2741
2742 _dmic_vol_:
2743 p = (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value;
2744
2745 /* check all channels */
2746 for (i = 0; i < p->count; i++) {
2747 switch (rt1320->dev_id) {
2748 case RT1320_DEV_ID:
2749 if (i < 2) {
2750 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
2751 regmap_read(rt1320->mbq_regmap, reg_base + i, ®value);
2752 } else {
2753 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
2754 regmap_read(rt1320->mbq_regmap, reg_base + i - 2, ®value);
2755 }
2756 break;
2757 case RT1321_DEV_ID:
2758 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
2759 regmap_read(rt1320->mbq_regmap, reg_base + i, ®value);
2760 break;
2761 }
2762
2763 ctl = p->max - (((0x1e00 - regvalue) & 0xffff) / interval_offset);
2764 ucontrol->value.integer.value[i] = ctl;
2765 }
2766 _done_:
2767 return 0;
2768 }
2769
rt1320_set_fu_capture_ctl(struct rt1320_sdw_priv * rt1320)2770 static int rt1320_set_fu_capture_ctl(struct rt1320_sdw_priv *rt1320)
2771 {
2772 int err, i;
2773 unsigned int ch_mute;
2774
2775 for (i = 0; i < ARRAY_SIZE(rt1320->fu_mixer_mute); i++) {
2776 ch_mute = (rt1320->fu_dapm_mute || rt1320->fu_mixer_mute[i]) ? 0x01 : 0x00;
2777
2778 switch (rt1320->dev_id) {
2779 case RT1320_DEV_ID:
2780 if (i < 2)
2781 err = regmap_write(rt1320->regmap,
2782 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113,
2783 RT1320_SDCA_CTL_FU_MUTE, CH_01) + i, ch_mute);
2784 else
2785 err = regmap_write(rt1320->regmap,
2786 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14,
2787 RT1320_SDCA_CTL_FU_MUTE, CH_01) + i - 2, ch_mute);
2788 break;
2789 case RT1321_DEV_ID:
2790 err = regmap_write(rt1320->regmap,
2791 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113,
2792 RT1320_SDCA_CTL_FU_MUTE, CH_01) + i, ch_mute);
2793 break;
2794 default:
2795 dev_err(&rt1320->sdw_slave->dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id);
2796 return -EINVAL;
2797 }
2798 if (err < 0)
2799 return err;
2800 }
2801
2802 return 0;
2803 }
2804
rt1320_dmic_fu_capture_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2805 static int rt1320_dmic_fu_capture_get(struct snd_kcontrol *kcontrol,
2806 struct snd_ctl_elem_value *ucontrol)
2807 {
2808 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2809 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
2810 struct rt_sdca_dmic_kctrl_priv *p =
2811 (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value;
2812 unsigned int i;
2813
2814 for (i = 0; i < p->count; i++)
2815 ucontrol->value.integer.value[i] = !rt1320->fu_mixer_mute[i];
2816
2817 return 0;
2818 }
2819
rt1320_dmic_fu_capture_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2820 static int rt1320_dmic_fu_capture_put(struct snd_kcontrol *kcontrol,
2821 struct snd_ctl_elem_value *ucontrol)
2822 {
2823 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2824 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
2825 struct rt_sdca_dmic_kctrl_priv *p =
2826 (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value;
2827 int err, changed = 0, i;
2828
2829 for (i = 0; i < p->count; i++) {
2830 if (rt1320->fu_mixer_mute[i] != !ucontrol->value.integer.value[i])
2831 changed = 1;
2832 rt1320->fu_mixer_mute[i] = !ucontrol->value.integer.value[i];
2833 }
2834
2835 err = rt1320_set_fu_capture_ctl(rt1320);
2836 if (err < 0)
2837 return err;
2838
2839 return changed;
2840 }
2841
rt1320_dmic_fu_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)2842 static int rt1320_dmic_fu_info(struct snd_kcontrol *kcontrol,
2843 struct snd_ctl_elem_info *uinfo)
2844 {
2845 struct rt_sdca_dmic_kctrl_priv *p =
2846 (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value;
2847
2848 if (p->max == 1)
2849 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2850 else
2851 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2852 uinfo->count = p->count;
2853 uinfo->value.integer.min = 0;
2854 uinfo->value.integer.max = p->max;
2855 return 0;
2856 }
2857
rt1320_dmic_fu_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)2858 static int rt1320_dmic_fu_event(struct snd_soc_dapm_widget *w,
2859 struct snd_kcontrol *kcontrol, int event)
2860 {
2861 struct snd_soc_component *component =
2862 snd_soc_dapm_to_component(w->dapm);
2863 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
2864
2865 switch (event) {
2866 case SND_SOC_DAPM_POST_PMU:
2867 rt1320->fu_dapm_mute = false;
2868 rt1320_set_fu_capture_ctl(rt1320);
2869 break;
2870 case SND_SOC_DAPM_PRE_PMD:
2871 rt1320->fu_dapm_mute = true;
2872 rt1320_set_fu_capture_ctl(rt1320);
2873 break;
2874 }
2875 return 0;
2876 }
2877
2878 static const char * const rt1320_rx_data_ch_select[] = {
2879 "L,R",
2880 "R,L",
2881 "L,L",
2882 "R,R",
2883 "L,L+R",
2884 "R,L+R",
2885 "L+R,L",
2886 "L+R,R",
2887 "L+R,L+R",
2888 };
2889
2890 static SOC_ENUM_SINGLE_DECL(rt1320_rx_data_ch_enum,
2891 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0), 0,
2892 rt1320_rx_data_ch_select);
2893
2894 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6525, 75, 0);
2895 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -1725, 75, 0);
2896
rt1320_r0_load(struct rt1320_sdw_priv * rt1320)2897 static int rt1320_r0_load(struct rt1320_sdw_priv *rt1320)
2898 {
2899 struct device *dev = regmap_get_device(rt1320->regmap);
2900 int dspfw_status;
2901 int ret = 0;
2902
2903 if (!rt1320->r0_l_reg || !rt1320->r0_r_reg)
2904 return -EINVAL;
2905
2906 regmap_write(rt1320->regmap,
2907 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00);
2908 ret = rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x00);
2909 if (ret < 0) {
2910 dev_dbg(dev, "%s, PDE=PS0 is NOT ready\n", __func__);
2911 goto _timeout_;
2912 }
2913
2914 dspfw_status = rt1320_dspfw_status(rt1320);
2915 if (dspfw_status <= 0) {
2916 dev_dbg(dev, "%s, DSP FW is NOT ready\n", __func__);
2917 goto _timeout_;
2918 }
2919
2920 ret = rt1320_check_power_state_ready(rt1320, RT1320_NORMAL_STATE);
2921 if (ret < 0) {
2922 dev_dbg(dev, "%s, DSP FW PS is NOT ready\n", __func__);
2923 goto _timeout_;
2924 }
2925
2926 rt1320_set_advancemode(rt1320);
2927
2928 _timeout_:
2929 regmap_write(rt1320->regmap,
2930 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03);
2931 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x03);
2932
2933 return ret;
2934 }
2935
rt1320_r0_load_mode_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2936 static int rt1320_r0_load_mode_get(struct snd_kcontrol *kcontrol,
2937 struct snd_ctl_elem_value *ucontrol)
2938 {
2939 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2940 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
2941
2942 ucontrol->value.integer.value[0] = rt1320->r0_l_reg;
2943 ucontrol->value.integer.value[1] = rt1320->r0_r_reg;
2944
2945 return 0;
2946 }
2947
rt1320_r0_load_mode_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2948 static int rt1320_r0_load_mode_put(struct snd_kcontrol *kcontrol,
2949 struct snd_ctl_elem_value *ucontrol)
2950 {
2951 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2952 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
2953 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(rt1320->component);
2954 int ret;
2955
2956 if (!rt1320->hw_init)
2957 return 0;
2958
2959 if (ucontrol->value.integer.value[0] == 0 ||
2960 ucontrol->value.integer.value[1] == 0)
2961 return -EINVAL;
2962
2963 ret = pm_runtime_resume(component->dev);
2964 if (ret < 0 && ret != -EACCES)
2965 return ret;
2966
2967 snd_soc_dapm_mutex_lock(dapm);
2968 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF) {
2969 rt1320->r0_l_reg = ucontrol->value.integer.value[0];
2970 rt1320->r0_r_reg = ucontrol->value.integer.value[1];
2971 rt1320_calc_r0(rt1320);
2972 rt1320_r0_load(rt1320);
2973 }
2974 snd_soc_dapm_mutex_unlock(dapm);
2975
2976 return 0;
2977 }
2978
rt1320_t0_r0_load_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)2979 static int rt1320_t0_r0_load_info(struct snd_kcontrol *kcontrol,
2980 struct snd_ctl_elem_info *uinfo)
2981 {
2982 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2983 uinfo->count = 2;
2984 uinfo->value.integer.max = kcontrol->private_value;
2985
2986 return 0;
2987 }
2988
2989 #define RT1320_T0_R0_LOAD(xname, xmax, xhandler_get, xhandler_put) \
2990 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2991 .info = rt1320_t0_r0_load_info, \
2992 .get = xhandler_get, \
2993 .put = xhandler_put, \
2994 .private_value = xmax, \
2995 }
2996
rt1320_dspfw_load_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2997 static int rt1320_dspfw_load_get(struct snd_kcontrol *kcontrol,
2998 struct snd_ctl_elem_value *ucontrol)
2999 {
3000 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
3001 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
3002
3003 ucontrol->value.integer.value[0] = rt1320->fw_load_done;
3004 return 0;
3005 }
3006
rt1320_dspfw_load_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)3007 static int rt1320_dspfw_load_put(struct snd_kcontrol *kcontrol,
3008 struct snd_ctl_elem_value *ucontrol)
3009 {
3010 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
3011 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
3012 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
3013 int ret;
3014
3015 if (!rt1320->hw_init)
3016 return 0;
3017
3018 ret = pm_runtime_resume_and_get(component->dev);
3019 if (ret < 0 && ret != -EACCES)
3020 return ret;
3021
3022 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF &&
3023 ucontrol->value.integer.value[0])
3024 rt1320_dspfw_load_code(rt1320);
3025
3026 if (!ucontrol->value.integer.value[0])
3027 rt1320->fw_load_done = false;
3028
3029 pm_runtime_mark_last_busy(component->dev);
3030 pm_runtime_put_autosuspend(component->dev);
3031 return 0;
3032 }
3033
rt1320_rae_update_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)3034 static int rt1320_rae_update_get(struct snd_kcontrol *kcontrol,
3035 struct snd_ctl_elem_value *ucontrol)
3036 {
3037 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
3038 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
3039
3040 ucontrol->value.integer.value[0] = rt1320->rae_update_done;
3041 return 0;
3042 }
3043
rt1320_rae_update_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)3044 static int rt1320_rae_update_put(struct snd_kcontrol *kcontrol,
3045 struct snd_ctl_elem_value *ucontrol)
3046 {
3047 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
3048 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
3049 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
3050 int ret;
3051
3052 if (!rt1320->hw_init)
3053 return 0;
3054
3055 ret = pm_runtime_resume(component->dev);
3056 if (ret < 0 && ret != -EACCES)
3057 return ret;
3058
3059 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF &&
3060 ucontrol->value.integer.value[0] && rt1320->fw_load_done)
3061 rt1320_rae_load(rt1320);
3062
3063 if (!ucontrol->value.integer.value[0])
3064 rt1320->rae_update_done = false;
3065
3066 return 0;
3067 }
3068
rt1320_brown_out_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)3069 static int rt1320_brown_out_put(struct snd_kcontrol *kcontrol,
3070 struct snd_ctl_elem_value *ucontrol)
3071 {
3072 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
3073 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
3074 int ret, changed = 0;
3075
3076 if (!rt1320->hw_init)
3077 return 0;
3078
3079 ret = pm_runtime_resume(component->dev);
3080 if (ret < 0 && ret != -EACCES)
3081 return ret;
3082
3083 if (rt1320->brown_out != ucontrol->value.integer.value[0]) {
3084 changed = 1;
3085 rt1320->brown_out = ucontrol->value.integer.value[0];
3086 }
3087
3088 if (rt1320->brown_out == 0)
3089 regmap_write(rt1320->regmap, 0xdb03, 0x00);
3090 else
3091 regmap_write(rt1320->regmap, 0xdb03, 0xf0);
3092
3093
3094 return changed;
3095 }
3096
rt1320_brown_out_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)3097 static int rt1320_brown_out_get(struct snd_kcontrol *kcontrol,
3098 struct snd_ctl_elem_value *ucontrol)
3099 {
3100 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
3101 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
3102
3103 ucontrol->value.integer.value[0] = rt1320->brown_out;
3104
3105 return 0;
3106 }
3107
rt1320_r0_temperature_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)3108 static int rt1320_r0_temperature_get(struct snd_kcontrol *kcontrol,
3109 struct snd_ctl_elem_value *ucontrol)
3110 {
3111 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
3112 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
3113
3114 ucontrol->value.integer.value[0] = rt1320->temp_l_calib;
3115 ucontrol->value.integer.value[1] = rt1320->temp_r_calib;
3116 return 0;
3117 }
3118
rt1320_r0_temperature_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)3119 static int rt1320_r0_temperature_put(struct snd_kcontrol *kcontrol,
3120 struct snd_ctl_elem_value *ucontrol)
3121 {
3122 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
3123 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
3124 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(rt1320->component);
3125 int ret;
3126
3127 if (!rt1320->hw_init)
3128 return 0;
3129
3130 ret = pm_runtime_resume(component->dev);
3131 if (ret < 0 && ret != -EACCES)
3132 return ret;
3133
3134 snd_soc_dapm_mutex_lock(dapm);
3135 if ((snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF) &&
3136 ucontrol->value.integer.value[0] && ucontrol->value.integer.value[1])
3137 rt1320_t0_load(rt1320, ucontrol->value.integer.value[0], ucontrol->value.integer.value[1]);
3138 snd_soc_dapm_mutex_unlock(dapm);
3139
3140 return 0;
3141 }
3142
3143 static const struct snd_kcontrol_new rt1320_snd_controls[] = {
3144 SOC_DOUBLE_R_EXT_TLV("FU21 Playback Volume",
3145 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01),
3146 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02),
3147 0, 0x57, 0, rt1320_set_gain_get, rt1320_set_gain_put, out_vol_tlv),
3148 SOC_ENUM("RX Channel Select", rt1320_rx_data_ch_enum),
3149
3150 RT_SDCA_FU_CTRL("FU Capture Switch",
3151 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01),
3152 1, 1, 4, rt1320_dmic_fu_info, rt1320_dmic_fu_capture_get, rt1320_dmic_fu_capture_put),
3153 RT_SDCA_EXT_TLV("FU Capture Volume",
3154 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01),
3155 rt1320_set_gain_get, rt1320_set_gain_put, 4, 0x3f, in_vol_tlv, rt1320_dmic_fu_info),
3156
3157 SOC_SINGLE_EXT("R0 Calibration", SND_SOC_NOPM, 0, 1, 0,
3158 rt1320_r0_cali_get, rt1320_r0_cali_put),
3159 SOC_SINGLE_EXT("DSP FW Update", SND_SOC_NOPM, 0, 1, 0,
3160 rt1320_dspfw_load_get, rt1320_dspfw_load_put),
3161 RT1320_T0_R0_LOAD("R0 Load Mode", 0xffffffff,
3162 rt1320_r0_load_mode_get, rt1320_r0_load_mode_put),
3163 RT1320_T0_R0_LOAD("R0 Temperature", 0xff,
3164 rt1320_r0_temperature_get, rt1320_r0_temperature_put),
3165 SOC_SINGLE_EXT("RAE Update", SND_SOC_NOPM, 0, 1, 0,
3166 rt1320_rae_update_get, rt1320_rae_update_put),
3167 SOC_SINGLE_EXT("Brown Out Switch", SND_SOC_NOPM, 0, 1, 0,
3168 rt1320_brown_out_get, rt1320_brown_out_put),
3169 };
3170
3171 static const struct snd_kcontrol_new rt1320_spk_l_dac =
3172 SOC_DAPM_SINGLE_AUTODISABLE("Switch",
3173 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01),
3174 0, 1, 1);
3175 static const struct snd_kcontrol_new rt1320_spk_r_dac =
3176 SOC_DAPM_SINGLE_AUTODISABLE("Switch",
3177 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02),
3178 0, 1, 1);
3179
3180 static const struct snd_soc_dapm_widget rt1320_dapm_widgets[] = {
3181 /* Audio Interface */
3182 SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0),
3183 SND_SOC_DAPM_AIF_OUT("DP4TX", "DP4 Capture", 0, SND_SOC_NOPM, 0, 0),
3184 SND_SOC_DAPM_AIF_OUT("DP8-10TX", "DP8-10 Capture", 0, SND_SOC_NOPM, 0, 0),
3185
3186 /* Digital Interface */
3187 SND_SOC_DAPM_PGA("FU21", SND_SOC_NOPM, 0, 0, NULL, 0),
3188 SND_SOC_DAPM_SUPPLY("PDE 23", SND_SOC_NOPM, 0, 0,
3189 rt1320_pde23_event,
3190 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
3191 SND_SOC_DAPM_SUPPLY("PDE 11", SND_SOC_NOPM, 0, 0,
3192 rt1320_pde11_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
3193 SND_SOC_DAPM_ADC("FU 113", NULL, SND_SOC_NOPM, 0, 0),
3194 SND_SOC_DAPM_ADC("FU 14", NULL, SND_SOC_NOPM, 0, 0),
3195 SND_SOC_DAPM_PGA_E("FU", SND_SOC_NOPM, 0, 0, NULL, 0,
3196 rt1320_dmic_fu_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
3197
3198 /* Output */
3199 SND_SOC_DAPM_SWITCH("OT23 L", SND_SOC_NOPM, 0, 0, &rt1320_spk_l_dac),
3200 SND_SOC_DAPM_SWITCH("OT23 R", SND_SOC_NOPM, 0, 0, &rt1320_spk_r_dac),
3201 SND_SOC_DAPM_OUTPUT("SPOL"),
3202 SND_SOC_DAPM_OUTPUT("SPOR"),
3203
3204 /* Input */
3205 SND_SOC_DAPM_PGA("AEC Data", SND_SOC_NOPM, 0, 0, NULL, 0),
3206 SND_SOC_DAPM_SIGGEN("AEC Gen"),
3207 SND_SOC_DAPM_INPUT("DMIC1"),
3208 SND_SOC_DAPM_INPUT("DMIC2"),
3209 };
3210
3211 static const struct snd_soc_dapm_route rt1320_dapm_routes[] = {
3212 { "FU21", NULL, "DP1RX" },
3213 { "FU21", NULL, "PDE 23" },
3214 { "OT23 L", "Switch", "FU21" },
3215 { "OT23 R", "Switch", "FU21" },
3216 { "SPOL", NULL, "OT23 L" },
3217 { "SPOR", NULL, "OT23 R" },
3218
3219 { "AEC Data", NULL, "AEC Gen" },
3220 { "DP4TX", NULL, "AEC Data" },
3221
3222 {"DP8-10TX", NULL, "FU"},
3223 {"FU", NULL, "PDE 11"},
3224 {"FU", NULL, "FU 113"},
3225 {"FU", NULL, "FU 14"},
3226 {"FU 113", NULL, "DMIC1"},
3227 {"FU 14", NULL, "DMIC2"},
3228 };
3229
rt1320_set_sdw_stream(struct snd_soc_dai * dai,void * sdw_stream,int direction)3230 static int rt1320_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
3231 int direction)
3232 {
3233 snd_soc_dai_dma_data_set(dai, direction, sdw_stream);
3234 return 0;
3235 }
3236
rt1320_sdw_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)3237 static void rt1320_sdw_shutdown(struct snd_pcm_substream *substream,
3238 struct snd_soc_dai *dai)
3239 {
3240 snd_soc_dai_set_dma_data(dai, substream, NULL);
3241 }
3242
rt1320_sdw_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)3243 static int rt1320_sdw_hw_params(struct snd_pcm_substream *substream,
3244 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
3245 {
3246 struct snd_soc_component *component = dai->component;
3247 struct rt1320_sdw_priv *rt1320 =
3248 snd_soc_component_get_drvdata(component);
3249 struct sdw_stream_config stream_config;
3250 struct sdw_port_config port_config;
3251 struct sdw_port_config dmic_port_config[2];
3252 struct sdw_stream_runtime *sdw_stream;
3253 int retval, num_channels;
3254 unsigned int sampling_rate;
3255
3256 dev_dbg(dai->dev, "%s %s", __func__, dai->name);
3257 sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
3258
3259 if (!sdw_stream)
3260 return -EINVAL;
3261
3262 if (!rt1320->sdw_slave)
3263 return -EINVAL;
3264
3265 /* SoundWire specific configuration */
3266 snd_sdw_params_to_config(substream, params, &stream_config, &port_config);
3267
3268 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
3269 if (dai->id == RT1320_AIF1)
3270 port_config.num = 1;
3271 else
3272 return -EINVAL;
3273 } else {
3274 if (dai->id == RT1320_AIF1)
3275 port_config.num = 4;
3276 else if (dai->id == RT1320_AIF2) {
3277 switch (rt1320->dev_id) {
3278 case RT1320_DEV_ID:
3279 dmic_port_config[0].ch_mask = BIT(0) | BIT(1);
3280 dmic_port_config[0].num = 8;
3281 dmic_port_config[1].ch_mask = BIT(0) | BIT(1);
3282 dmic_port_config[1].num = 10;
3283 break;
3284 case RT1321_DEV_ID:
3285 num_channels = params_channels(params);
3286 dmic_port_config[0].ch_mask = GENMASK(num_channels - 1, 0);
3287 dmic_port_config[0].num = 8;
3288 break;
3289 default:
3290 return -EINVAL;
3291 }
3292 } else
3293 return -EINVAL;
3294 }
3295
3296 if (dai->id == RT1320_AIF1)
3297 retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config,
3298 &port_config, 1, sdw_stream);
3299 else if (dai->id == RT1320_AIF2) {
3300 switch (rt1320->dev_id) {
3301 case RT1320_DEV_ID:
3302 retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config,
3303 dmic_port_config, 2, sdw_stream);
3304 break;
3305 case RT1321_DEV_ID:
3306 retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config,
3307 dmic_port_config, 1, sdw_stream);
3308 break;
3309 default:
3310 dev_err(dai->dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id);
3311 return -EINVAL;
3312 }
3313 } else
3314 return -EINVAL;
3315 if (retval) {
3316 dev_err(dai->dev, "%s: Unable to configure port\n", __func__);
3317 return retval;
3318 }
3319
3320 /* sampling rate configuration */
3321 switch (params_rate(params)) {
3322 case 16000:
3323 sampling_rate = RT1320_SDCA_RATE_16000HZ;
3324 break;
3325 case 32000:
3326 sampling_rate = RT1320_SDCA_RATE_32000HZ;
3327 break;
3328 case 44100:
3329 sampling_rate = RT1320_SDCA_RATE_44100HZ;
3330 break;
3331 case 48000:
3332 sampling_rate = RT1320_SDCA_RATE_48000HZ;
3333 break;
3334 case 96000:
3335 sampling_rate = RT1320_SDCA_RATE_96000HZ;
3336 break;
3337 case 192000:
3338 sampling_rate = RT1320_SDCA_RATE_192000HZ;
3339 break;
3340 default:
3341 dev_err(component->dev, "%s: Rate %d is not supported\n",
3342 __func__, params_rate(params));
3343 return -EINVAL;
3344 }
3345
3346 /* set sampling frequency */
3347 if (dai->id == RT1320_AIF1)
3348 regmap_write(rt1320->regmap,
3349 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0),
3350 sampling_rate);
3351 else {
3352 regmap_write(rt1320->regmap,
3353 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0),
3354 sampling_rate);
3355
3356 if (rt1320->dev_id == RT1320_DEV_ID)
3357 regmap_write(rt1320->regmap,
3358 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0),
3359 sampling_rate);
3360 }
3361
3362 return 0;
3363 }
3364
rt1320_sdw_pcm_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)3365 static int rt1320_sdw_pcm_hw_free(struct snd_pcm_substream *substream,
3366 struct snd_soc_dai *dai)
3367 {
3368 struct snd_soc_component *component = dai->component;
3369 struct rt1320_sdw_priv *rt1320 =
3370 snd_soc_component_get_drvdata(component);
3371 struct sdw_stream_runtime *sdw_stream =
3372 snd_soc_dai_get_dma_data(dai, substream);
3373
3374 if (!rt1320->sdw_slave)
3375 return -EINVAL;
3376
3377 sdw_stream_remove_slave(rt1320->sdw_slave, sdw_stream);
3378 return 0;
3379 }
3380
rt1320_bus_config(struct sdw_slave * slave,struct sdw_bus_params * params)3381 static int rt1320_bus_config(struct sdw_slave *slave,
3382 struct sdw_bus_params *params)
3383 {
3384 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(&slave->dev);
3385 unsigned int clk_base;
3386
3387 regmap_read(rt1320->regmap, 0x004d, &clk_base);
3388 dev_dbg(&rt1320->sdw_slave->dev, "%s clk_base=%x", __func__, clk_base);
3389
3390 switch (clk_base) {
3391 case RT1320_CLK_FREQ_19_2_MHZ:
3392 case RT1320_CLK_FREQ_24MHZ:
3393 regmap_write(rt1320->regmap, 0xc600, 0x04);
3394 regmap_write(rt1320->regmap, 0xc601, 0x83);
3395 regmap_write(rt1320->regmap, 0xc602, 0x1f);
3396 regmap_write(rt1320->regmap, 0xc603, 0x40);
3397 break;
3398 case RT1320_CLK_FREQ_24_576MHZ:
3399 case RT1320_CLK_FREQ_22_5792MHZ:
3400 regmap_write(rt1320->regmap, 0xc600, 0x07);
3401 regmap_write(rt1320->regmap, 0xc601, 0x80);
3402 regmap_write(rt1320->regmap, 0xc602, 0x0f);
3403 regmap_write(rt1320->regmap, 0xc603, 0x40);
3404 break;
3405 default:
3406 return -EINVAL;
3407 }
3408
3409 return 0;
3410 }
3411
3412 /*
3413 * slave_ops: callbacks for get_clock_stop_mode, clock_stop and
3414 * port_prep are not defined for now
3415 */
3416 static const struct sdw_slave_ops rt1320_slave_ops = {
3417 .read_prop = rt1320_read_prop,
3418 .update_status = rt1320_update_status,
3419 .bus_config = rt1320_bus_config,
3420 };
3421
rt1320_sdw_component_probe(struct snd_soc_component * component)3422 static int rt1320_sdw_component_probe(struct snd_soc_component *component)
3423 {
3424 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
3425 int ret;
3426
3427 rt1320->component = component;
3428
3429 if (!rt1320->first_hw_init)
3430 return 0;
3431
3432 ret = pm_runtime_resume(component->dev);
3433 dev_dbg(&rt1320->sdw_slave->dev, "%s pm_runtime_resume, ret=%d", __func__, ret);
3434 if (ret < 0 && ret != -EACCES)
3435 return ret;
3436
3437 /* Apply temperature and calibration data from device property */
3438 if ((rt1320->temp_l_calib <= 0xff) && (rt1320->temp_l_calib > 0) &&
3439 (rt1320->temp_r_calib <= 0xff) && (rt1320->temp_r_calib > 0))
3440 rt1320_t0_load(rt1320, rt1320->temp_l_calib, rt1320->temp_r_calib);
3441
3442 if (rt1320->r0_l_calib && rt1320->r0_r_calib) {
3443 rt1320->r0_l_reg = rt1320->r0_l_calib;
3444 rt1320->r0_r_reg = rt1320->r0_r_calib;
3445 rt1320_calc_r0(rt1320);
3446 rt1320_r0_load(rt1320);
3447 }
3448
3449 return 0;
3450 }
3451
3452 static const struct snd_soc_component_driver soc_component_sdw_rt1320 = {
3453 .probe = rt1320_sdw_component_probe,
3454 .controls = rt1320_snd_controls,
3455 .num_controls = ARRAY_SIZE(rt1320_snd_controls),
3456 .dapm_widgets = rt1320_dapm_widgets,
3457 .num_dapm_widgets = ARRAY_SIZE(rt1320_dapm_widgets),
3458 .dapm_routes = rt1320_dapm_routes,
3459 .num_dapm_routes = ARRAY_SIZE(rt1320_dapm_routes),
3460 .endianness = 1,
3461 };
3462
3463 static const struct snd_soc_dai_ops rt1320_aif_dai_ops = {
3464 .hw_params = rt1320_sdw_hw_params,
3465 .hw_free = rt1320_sdw_pcm_hw_free,
3466 .set_stream = rt1320_set_sdw_stream,
3467 .shutdown = rt1320_sdw_shutdown,
3468 };
3469
3470 #define RT1320_STEREO_RATES (SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
3471 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
3472 #define RT1320_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \
3473 SNDRV_PCM_FMTBIT_S32_LE)
3474
3475 static struct snd_soc_dai_driver rt1320_sdw_dai[] = {
3476 {
3477 .name = "rt1320-aif1",
3478 .id = RT1320_AIF1,
3479 .playback = {
3480 .stream_name = "DP1 Playback",
3481 .channels_min = 1,
3482 .channels_max = 2,
3483 .rates = RT1320_STEREO_RATES,
3484 .formats = RT1320_FORMATS,
3485 },
3486 .capture = {
3487 .stream_name = "DP4 Capture",
3488 .channels_min = 1,
3489 .channels_max = 2,
3490 .rates = RT1320_STEREO_RATES,
3491 .formats = RT1320_FORMATS,
3492 },
3493 .ops = &rt1320_aif_dai_ops,
3494 },
3495 /* DMIC: DP8 2ch + DP10 2ch */
3496 {
3497 .name = "rt1320-aif2",
3498 .id = RT1320_AIF2,
3499 .capture = {
3500 .stream_name = "DP8-10 Capture",
3501 .channels_min = 1,
3502 .channels_max = 4,
3503 .rates = RT1320_STEREO_RATES,
3504 .formats = RT1320_FORMATS,
3505 },
3506 .ops = &rt1320_aif_dai_ops,
3507 },
3508 };
3509
rt1320_parse_dp(struct rt1320_sdw_priv * rt1320,struct device * dev)3510 static int rt1320_parse_dp(struct rt1320_sdw_priv *rt1320, struct device *dev)
3511 {
3512 device_property_read_u32(dev, "realtek,temperature_l_calib",
3513 &rt1320->temp_l_calib);
3514 device_property_read_u32(dev, "realtek,temperature_r_calib",
3515 &rt1320->temp_r_calib);
3516 device_property_read_u32(dev, "realtek,r0_l_calib",
3517 &rt1320->r0_l_calib);
3518 device_property_read_u32(dev, "realtek,r0_r_calib",
3519 &rt1320->r0_r_calib);
3520 device_property_read_string(dev, "realtek,dspfw-name",
3521 &rt1320->dspfw_name);
3522
3523 dev_dbg(dev, "%s: temp_l_calib: %d temp_r_calib: %d r0_l_calib: %d, r0_r_calib: %d",
3524 __func__, rt1320->temp_l_calib, rt1320->temp_r_calib, rt1320->r0_l_calib, rt1320->r0_r_calib);
3525 dev_dbg(dev, "%s: dspfw_name: %s", __func__, rt1320->dspfw_name);
3526
3527 return 0;
3528 }
3529
rt1320_sdw_init(struct device * dev,struct regmap * regmap,struct regmap * mbq_regmap,struct sdw_slave * slave)3530 static int rt1320_sdw_init(struct device *dev, struct regmap *regmap,
3531 struct regmap *mbq_regmap, struct sdw_slave *slave)
3532 {
3533 struct rt1320_sdw_priv *rt1320;
3534 int ret;
3535
3536 rt1320 = devm_kzalloc(dev, sizeof(*rt1320), GFP_KERNEL);
3537 if (!rt1320)
3538 return -ENOMEM;
3539
3540 dev_set_drvdata(dev, rt1320);
3541 rt1320->sdw_slave = slave;
3542 rt1320->mbq_regmap = mbq_regmap;
3543 rt1320->regmap = regmap;
3544
3545 regcache_cache_only(rt1320->regmap, true);
3546 regcache_cache_only(rt1320->mbq_regmap, true);
3547
3548 rt1320_parse_dp(rt1320, dev);
3549
3550 /*
3551 * Mark hw_init to false
3552 * HW init will be performed when device reports present
3553 */
3554 rt1320->hw_init = false;
3555 rt1320->first_hw_init = false;
3556 rt1320->version_id = -1;
3557 rt1320->fu_dapm_mute = true;
3558 rt1320->fu_mixer_mute[0] = rt1320->fu_mixer_mute[1] =
3559 rt1320->fu_mixer_mute[2] = rt1320->fu_mixer_mute[3] = true;
3560 rt1320->brown_out = 1;
3561
3562 INIT_WORK(&rt1320->load_dspfw_work, rt1320_load_dspfw_work);
3563
3564 ret = devm_snd_soc_register_component(dev,
3565 &soc_component_sdw_rt1320,
3566 rt1320_sdw_dai,
3567 ARRAY_SIZE(rt1320_sdw_dai));
3568 if (ret < 0)
3569 return ret;
3570
3571 /* set autosuspend parameters */
3572 pm_runtime_set_autosuspend_delay(dev, 3000);
3573 pm_runtime_use_autosuspend(dev);
3574
3575 /* make sure the device does not suspend immediately */
3576 pm_runtime_mark_last_busy(dev);
3577
3578 pm_runtime_enable(dev);
3579
3580 /* important note: the device is NOT tagged as 'active' and will remain
3581 * 'suspended' until the hardware is enumerated/initialized. This is required
3582 * to make sure the ASoC framework use of pm_runtime_get_sync() does not silently
3583 * fail with -EACCESS because of race conditions between card creation and enumeration
3584 */
3585
3586 dev_dbg(dev, "%s\n", __func__);
3587
3588 return ret;
3589 }
3590
rt1320_sdw_probe(struct sdw_slave * slave,const struct sdw_device_id * id)3591 static int rt1320_sdw_probe(struct sdw_slave *slave,
3592 const struct sdw_device_id *id)
3593 {
3594 struct regmap *regmap, *mbq_regmap;
3595
3596 /* Regmap Initialization */
3597 mbq_regmap = devm_regmap_init_sdw_mbq(slave, &rt1320_mbq_regmap);
3598 if (IS_ERR(mbq_regmap))
3599 return PTR_ERR(mbq_regmap);
3600
3601 regmap = devm_regmap_init_sdw(slave, &rt1320_sdw_regmap);
3602 if (IS_ERR(regmap))
3603 return PTR_ERR(regmap);
3604
3605 return rt1320_sdw_init(&slave->dev, regmap, mbq_regmap, slave);
3606 }
3607
rt1320_sdw_remove(struct sdw_slave * slave)3608 static void rt1320_sdw_remove(struct sdw_slave *slave)
3609 {
3610 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(&slave->dev);
3611
3612 cancel_work_sync(&rt1320->load_dspfw_work);
3613 pm_runtime_disable(&slave->dev);
3614 }
3615
3616 /*
3617 * Version A/B will use the class id 0
3618 * The newer version than A/B will use the class id 1, so add it in advance
3619 */
3620 static const struct sdw_device_id rt1320_id[] = {
3621 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1320, 0x3, 0x0, 0),
3622 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1320, 0x3, 0x1, 0),
3623 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1321, 0x3, 0x1, 0),
3624 {},
3625 };
3626 MODULE_DEVICE_TABLE(sdw, rt1320_id);
3627
rt1320_dev_suspend(struct device * dev)3628 static int rt1320_dev_suspend(struct device *dev)
3629 {
3630 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev);
3631
3632 if (!rt1320->hw_init)
3633 return 0;
3634
3635 regcache_cache_only(rt1320->regmap, true);
3636 regcache_cache_only(rt1320->mbq_regmap, true);
3637 return 0;
3638 }
3639
3640 #define RT1320_PROBE_TIMEOUT 5000
3641
rt1320_dev_resume(struct device * dev)3642 static int rt1320_dev_resume(struct device *dev)
3643 {
3644 struct sdw_slave *slave = dev_to_sdw_dev(dev);
3645 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev);
3646 int ret;
3647
3648 if (!rt1320->first_hw_init)
3649 return 0;
3650
3651 ret = sdw_slave_wait_for_init(slave, RT1320_PROBE_TIMEOUT);
3652 if (ret)
3653 return ret;
3654
3655 regcache_cache_only(rt1320->regmap, false);
3656 ret = regcache_sync(rt1320->regmap);
3657 if (ret)
3658 goto err_sync;
3659
3660 regcache_cache_only(rt1320->mbq_regmap, false);
3661 ret = regcache_sync(rt1320->mbq_regmap);
3662 if (ret)
3663 goto err_sync;
3664
3665 return 0;
3666
3667 err_sync:
3668 regcache_cache_only(rt1320->regmap, true);
3669 regcache_cache_only(rt1320->mbq_regmap, true);
3670 regcache_mark_dirty(rt1320->regmap);
3671 regcache_mark_dirty(rt1320->mbq_regmap);
3672 return ret;
3673 }
3674
3675 static const struct dev_pm_ops rt1320_pm = {
3676 SYSTEM_SLEEP_PM_OPS(rt1320_dev_suspend, rt1320_dev_resume)
3677 RUNTIME_PM_OPS(rt1320_dev_suspend, rt1320_dev_resume, NULL)
3678 };
3679
3680 static struct sdw_driver rt1320_sdw_driver = {
3681 .driver = {
3682 .name = "rt1320-sdca",
3683 .pm = pm_ptr(&rt1320_pm),
3684 },
3685 .probe = rt1320_sdw_probe,
3686 .remove = rt1320_sdw_remove,
3687 .ops = &rt1320_slave_ops,
3688 .id_table = rt1320_id,
3689 };
3690 module_sdw_driver(rt1320_sdw_driver);
3691
3692 MODULE_DESCRIPTION("ASoC RT1320 driver SDCA SDW");
3693 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>");
3694 MODULE_LICENSE("GPL");
3695