1 // SPDX-License-Identifier: GPL-2.0
2
3 #include <media/videobuf2-v4l2.h>
4 #include <media/videobuf2-dma-contig.h>
5 #include <media/v4l2-event.h>
6 #include <media/v4l2-mem2mem.h>
7 #include <linux/module.h>
8
9 #include "mtk_vcodec_dec.h"
10 #include "mtk_vcodec_dec_pm.h"
11 #include "vdec_drv_if.h"
12
13 /**
14 * struct mtk_stateless_control - CID control type
15 * @cfg: control configuration
16 * @codec_type: codec type (V4L2 pixel format) for CID control type
17 */
18 struct mtk_stateless_control {
19 struct v4l2_ctrl_config cfg;
20 int codec_type;
21 };
22
23 static const struct mtk_stateless_control mtk_stateless_controls[] = {
24 {
25 .cfg = {
26 .id = V4L2_CID_STATELESS_H264_SPS,
27 },
28 .codec_type = V4L2_PIX_FMT_H264_SLICE,
29 },
30 {
31 .cfg = {
32 .id = V4L2_CID_STATELESS_H264_PPS,
33 },
34 .codec_type = V4L2_PIX_FMT_H264_SLICE,
35 },
36 {
37 .cfg = {
38 .id = V4L2_CID_STATELESS_H264_SCALING_MATRIX,
39 },
40 .codec_type = V4L2_PIX_FMT_H264_SLICE,
41 },
42 {
43 .cfg = {
44 .id = V4L2_CID_STATELESS_H264_DECODE_PARAMS,
45 },
46 .codec_type = V4L2_PIX_FMT_H264_SLICE,
47 },
48 {
49 .cfg = {
50 .id = V4L2_CID_MPEG_VIDEO_H264_PROFILE,
51 .def = V4L2_MPEG_VIDEO_H264_PROFILE_MAIN,
52 .max = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
53 .menu_skip_mask =
54 BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) |
55 BIT(V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED),
56 },
57 .codec_type = V4L2_PIX_FMT_H264_SLICE,
58 },
59 {
60 .cfg = {
61 .id = V4L2_CID_MPEG_VIDEO_H264_LEVEL,
62 .min = V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
63 .def = V4L2_MPEG_VIDEO_H264_LEVEL_4_1,
64 .max = V4L2_MPEG_VIDEO_H264_LEVEL_4_2,
65 },
66 .codec_type = V4L2_PIX_FMT_H264_SLICE,
67 },
68 {
69 .cfg = {
70 .id = V4L2_CID_STATELESS_H264_DECODE_MODE,
71 .min = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
72 .def = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
73 .max = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
74 },
75 .codec_type = V4L2_PIX_FMT_H264_SLICE,
76 },
77 {
78 .cfg = {
79 .id = V4L2_CID_STATELESS_H264_START_CODE,
80 .min = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
81 .def = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
82 .max = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
83 },
84 .codec_type = V4L2_PIX_FMT_H264_SLICE,
85 },
86 {
87 .cfg = {
88 .id = V4L2_CID_STATELESS_VP8_FRAME,
89 },
90 .codec_type = V4L2_PIX_FMT_VP8_FRAME,
91 },
92 {
93 .cfg = {
94 .id = V4L2_CID_MPEG_VIDEO_VP8_PROFILE,
95 .min = V4L2_MPEG_VIDEO_VP8_PROFILE_0,
96 .def = V4L2_MPEG_VIDEO_VP8_PROFILE_0,
97 .max = V4L2_MPEG_VIDEO_VP8_PROFILE_3,
98 },
99 .codec_type = V4L2_PIX_FMT_VP8_FRAME,
100 },
101 {
102 .cfg = {
103 .id = V4L2_CID_STATELESS_VP9_FRAME,
104 },
105 .codec_type = V4L2_PIX_FMT_VP9_FRAME,
106 },
107 {
108 .cfg = {
109 .id = V4L2_CID_MPEG_VIDEO_VP9_PROFILE,
110 .min = V4L2_MPEG_VIDEO_VP9_PROFILE_0,
111 .def = V4L2_MPEG_VIDEO_VP9_PROFILE_0,
112 .max = V4L2_MPEG_VIDEO_VP9_PROFILE_2,
113 .menu_skip_mask = BIT(V4L2_MPEG_VIDEO_VP9_PROFILE_1),
114 },
115 .codec_type = V4L2_PIX_FMT_VP9_FRAME,
116 },
117 {
118 .cfg = {
119 .id = V4L2_CID_MPEG_VIDEO_VP9_LEVEL,
120 .min = V4L2_MPEG_VIDEO_VP9_LEVEL_1_0,
121 .def = V4L2_MPEG_VIDEO_VP9_LEVEL_4_0,
122 .max = V4L2_MPEG_VIDEO_VP9_LEVEL_4_1,
123 },
124 .codec_type = V4L2_PIX_FMT_VP9_FRAME,
125 },
126 {
127 .cfg = {
128 .id = V4L2_CID_STATELESS_HEVC_SPS,
129 },
130 .codec_type = V4L2_PIX_FMT_HEVC_SLICE,
131 },
132 {
133 .cfg = {
134 .id = V4L2_CID_STATELESS_HEVC_PPS,
135 },
136 .codec_type = V4L2_PIX_FMT_HEVC_SLICE,
137 },
138 {
139 .cfg = {
140 .id = V4L2_CID_STATELESS_HEVC_SCALING_MATRIX,
141 },
142 .codec_type = V4L2_PIX_FMT_HEVC_SLICE,
143 },
144 {
145 .cfg = {
146 .id = V4L2_CID_STATELESS_HEVC_DECODE_PARAMS,
147 },
148 .codec_type = V4L2_PIX_FMT_HEVC_SLICE,
149 },
150 {
151 .cfg = {
152 .id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE,
153 .def = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
154 .max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10,
155 },
156 .codec_type = V4L2_PIX_FMT_HEVC_SLICE,
157 },
158 {
159 .cfg = {
160 .id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
161 .min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
162 .def = V4L2_MPEG_VIDEO_HEVC_LEVEL_4,
163 .max = V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1,
164 },
165 .codec_type = V4L2_PIX_FMT_HEVC_SLICE,
166 },
167
168 {
169 .cfg = {
170 .id = V4L2_CID_STATELESS_HEVC_DECODE_MODE,
171 .min = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
172 .def = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
173 .max = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
174 },
175 .codec_type = V4L2_PIX_FMT_HEVC_SLICE,
176 },
177 {
178 .cfg = {
179 .id = V4L2_CID_STATELESS_HEVC_START_CODE,
180 .min = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
181 .def = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
182 .max = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
183 },
184 .codec_type = V4L2_PIX_FMT_HEVC_SLICE,
185 },
186 {
187 .cfg = {
188 .id = V4L2_CID_STATELESS_AV1_SEQUENCE,
189
190 },
191 .codec_type = V4L2_PIX_FMT_AV1_FRAME,
192 },
193 {
194 .cfg = {
195 .id = V4L2_CID_STATELESS_AV1_FRAME,
196
197 },
198 .codec_type = V4L2_PIX_FMT_AV1_FRAME,
199 },
200 {
201 .cfg = {
202 .id = V4L2_CID_STATELESS_AV1_TILE_GROUP_ENTRY,
203 .dims = { V4L2_AV1_MAX_TILE_COUNT },
204
205 },
206 .codec_type = V4L2_PIX_FMT_AV1_FRAME,
207 },
208 {
209 .cfg = {
210 .id = V4L2_CID_MPEG_VIDEO_AV1_PROFILE,
211 .min = V4L2_MPEG_VIDEO_AV1_PROFILE_MAIN,
212 .def = V4L2_MPEG_VIDEO_AV1_PROFILE_MAIN,
213 .max = V4L2_MPEG_VIDEO_AV1_PROFILE_MAIN,
214 },
215 .codec_type = V4L2_PIX_FMT_AV1_FRAME,
216 },
217 {
218 .cfg = {
219 .id = V4L2_CID_MPEG_VIDEO_AV1_LEVEL,
220 .min = V4L2_MPEG_VIDEO_AV1_LEVEL_2_0,
221 .def = V4L2_MPEG_VIDEO_AV1_LEVEL_4_0,
222 .max = V4L2_MPEG_VIDEO_AV1_LEVEL_5_1,
223 },
224 .codec_type = V4L2_PIX_FMT_AV1_FRAME,
225 },
226 };
227
228 #define NUM_CTRLS ARRAY_SIZE(mtk_stateless_controls)
229
230 static struct mtk_video_fmt mtk_video_formats[9];
231
232 static struct mtk_video_fmt default_out_format;
233 static struct mtk_video_fmt default_cap_format;
234 static unsigned int num_formats;
235
236 static const struct v4l2_frmsize_stepwise stepwise_fhd = {
237 .min_width = MTK_VDEC_MIN_W,
238 .max_width = MTK_VDEC_MAX_W,
239 .step_width = 16,
240 .min_height = MTK_VDEC_MIN_H,
241 .max_height = MTK_VDEC_MAX_H,
242 .step_height = 16
243 };
244
mtk_vcodec_dec_request_release(struct kref * ref)245 static void mtk_vcodec_dec_request_release(struct kref *ref)
246 {
247 struct mtk_vcodec_dec_request *req =
248 container_of(ref, struct mtk_vcodec_dec_request, refcount);
249 media_request_manual_complete(&req->req);
250 }
251
mtk_vdec_stateless_cap_to_disp(struct mtk_vcodec_dec_ctx * ctx,int error,struct media_request * mreq)252 static void mtk_vdec_stateless_cap_to_disp(struct mtk_vcodec_dec_ctx *ctx, int error,
253 struct media_request *mreq)
254 {
255 struct mtk_vcodec_dec_request *req = req_to_dec_req(mreq);
256 struct vb2_v4l2_buffer *dst_buf;
257 enum vb2_buffer_state state;
258
259 if (error)
260 state = VB2_BUF_STATE_ERROR;
261 else
262 state = VB2_BUF_STATE_DONE;
263
264 dst_buf = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
265 v4l2_m2m_buf_done(dst_buf, state);
266 kref_put(&req->refcount, mtk_vcodec_dec_request_release);
267 }
268
vdec_get_cap_buffer(struct mtk_vcodec_dec_ctx * ctx)269 static struct vdec_fb *vdec_get_cap_buffer(struct mtk_vcodec_dec_ctx *ctx)
270 {
271 struct mtk_video_dec_buf *framebuf;
272 struct vb2_v4l2_buffer *vb2_v4l2;
273 struct vb2_buffer *dst_buf;
274 struct vdec_fb *pfb;
275
276 vb2_v4l2 = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
277 if (!vb2_v4l2) {
278 mtk_v4l2_vdec_dbg(1, ctx, "[%d] dst_buf empty!!", ctx->id);
279 return NULL;
280 }
281
282 dst_buf = &vb2_v4l2->vb2_buf;
283 framebuf = container_of(vb2_v4l2, struct mtk_video_dec_buf, m2m_buf.vb);
284
285 pfb = &framebuf->frame_buffer;
286 pfb->base_y.va = vb2_plane_vaddr(dst_buf, 0);
287 pfb->base_y.dma_addr = vb2_dma_contig_plane_dma_addr(dst_buf, 0);
288 pfb->base_y.size = ctx->q_data[MTK_Q_DATA_DST].sizeimage[0];
289
290 if (ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes == 2) {
291 pfb->base_c.va = vb2_plane_vaddr(dst_buf, 1);
292 pfb->base_c.dma_addr =
293 vb2_dma_contig_plane_dma_addr(dst_buf, 1);
294 pfb->base_c.size = ctx->q_data[MTK_Q_DATA_DST].sizeimage[1];
295 }
296 mtk_v4l2_vdec_dbg(1, ctx,
297 "id=%d Framebuf pfb=%p VA=%p Y/C_DMA=%pad_%pad Sz=%zx frame_count = %d",
298 dst_buf->index, pfb, pfb->base_y.va, &pfb->base_y.dma_addr,
299 &pfb->base_c.dma_addr, pfb->base_y.size, ctx->decoded_frame_cnt);
300
301 return pfb;
302 }
303
vb2ops_vdec_buf_request_complete(struct vb2_buffer * vb)304 static void vb2ops_vdec_buf_request_complete(struct vb2_buffer *vb)
305 {
306 struct mtk_vcodec_dec_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
307
308 v4l2_ctrl_request_complete(vb->req_obj.req, &ctx->ctrl_hdl);
309 media_request_manual_complete(vb->req_obj.req);
310 }
311
mtk_vdec_worker(struct work_struct * work)312 static void mtk_vdec_worker(struct work_struct *work)
313 {
314 struct mtk_vcodec_dec_ctx *ctx =
315 container_of(work, struct mtk_vcodec_dec_ctx, decode_work);
316 struct mtk_vcodec_dec_dev *dev = ctx->dev;
317 struct vb2_v4l2_buffer *vb2_v4l2_src;
318 struct vb2_buffer *vb2_src;
319 struct mtk_vcodec_mem *bs_src;
320 struct mtk_video_dec_buf *dec_buf_src;
321 struct media_request *mreq;
322 struct mtk_vcodec_dec_request *req;
323 enum vb2_buffer_state buf_state;
324 bool res_chg = false;
325 int ret;
326
327 vb2_v4l2_src = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
328 if (!vb2_v4l2_src) {
329 v4l2_m2m_job_finish(dev->m2m_dev_dec, ctx->m2m_ctx);
330 mtk_v4l2_vdec_dbg(1, ctx, "[%d] no available source buffer", ctx->id);
331 return;
332 }
333
334 vb2_src = &vb2_v4l2_src->vb2_buf;
335 dec_buf_src = container_of(vb2_v4l2_src, struct mtk_video_dec_buf,
336 m2m_buf.vb);
337 bs_src = &dec_buf_src->bs_buffer;
338
339 mtk_v4l2_vdec_dbg(3, ctx, "[%d] (%d) id=%d, vb=%p", ctx->id,
340 vb2_src->vb2_queue->type, vb2_src->index, vb2_src);
341
342 bs_src->va = vb2_plane_vaddr(vb2_src, 0);
343 bs_src->dma_addr = vb2_dma_contig_plane_dma_addr(vb2_src, 0);
344 bs_src->size = (size_t)vb2_src->planes[0].bytesused;
345 if (!bs_src->va) {
346 v4l2_m2m_job_finish(dev->m2m_dev_dec, ctx->m2m_ctx);
347 mtk_v4l2_vdec_err(ctx, "[%d] id=%d source buffer is NULL", ctx->id,
348 vb2_src->index);
349 return;
350 }
351
352 mtk_v4l2_vdec_dbg(3, ctx, "[%d] Bitstream VA=%p DMA=%pad Size=%zx vb=%p",
353 ctx->id, bs_src->va, &bs_src->dma_addr, bs_src->size, vb2_src);
354 /* Apply request controls. */
355 mreq = vb2_src->req_obj.req;
356 if (WARN_ON(!mreq)) {
357 v4l2_m2m_job_finish(dev->m2m_dev_dec, ctx->m2m_ctx);
358 mtk_v4l2_vdec_err(ctx, "vb2 buffer media request is NULL");
359 return;
360 }
361
362 v4l2_ctrl_request_setup(mreq, &ctx->ctrl_hdl);
363
364 /* Keep a reference so that if the processing completes before this function
365 * ends, we won't accidently update a freshly queued request.
366 */
367 req = req_to_dec_req(mreq);
368 kref_get(&req->refcount);
369
370 ret = vdec_if_decode(ctx, bs_src, NULL, &res_chg);
371 if (ret == -EAGAIN)
372 goto done;
373
374 if (ret) {
375 mtk_v4l2_vdec_err(ctx,
376 "[%d] decode src_buf[%d] sz=0x%zx pts=%llu ret=%d res_chg=%d",
377 ctx->id, vb2_src->index, bs_src->size,
378 vb2_src->timestamp, ret, res_chg);
379 if (ret == -EIO) {
380 mutex_lock(&ctx->lock);
381 dec_buf_src->error = true;
382 mutex_unlock(&ctx->lock);
383 }
384
385 buf_state = VB2_BUF_STATE_ERROR;
386 } else {
387 buf_state = VB2_BUF_STATE_DONE;
388 }
389
390 v4l2_ctrl_request_complete(mreq, &ctx->ctrl_hdl);
391 v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
392 v4l2_m2m_buf_done(vb2_v4l2_src, buf_state);
393
394 if (ret || !IS_VDEC_LAT_ARCH(dev->vdec_pdata->hw_arch) ||
395 ctx->current_codec == V4L2_PIX_FMT_VP8_FRAME)
396 mtk_vdec_stateless_cap_to_disp(ctx, ret, mreq);
397
398 done:
399 kref_put(&req->refcount, mtk_vcodec_dec_request_release);
400 v4l2_m2m_job_finish(dev->m2m_dev_dec, ctx->m2m_ctx);
401 }
402
vb2ops_vdec_stateless_buf_queue(struct vb2_buffer * vb)403 static void vb2ops_vdec_stateless_buf_queue(struct vb2_buffer *vb)
404 {
405 struct mtk_vcodec_dec_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
406 struct vb2_v4l2_buffer *vb2_v4l2 = to_vb2_v4l2_buffer(vb);
407
408 mtk_v4l2_vdec_dbg(3, ctx, "[%d] (%d) id=%d, vb=%p", ctx->id, vb->vb2_queue->type,
409 vb->index, vb);
410
411 mutex_lock(&ctx->lock);
412 v4l2_m2m_buf_queue(ctx->m2m_ctx, vb2_v4l2);
413 mutex_unlock(&ctx->lock);
414 if (vb->vb2_queue->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
415 return;
416
417 /* If an OUTPUT buffer, we may need to update the state */
418 if (ctx->state == MTK_STATE_INIT) {
419 ctx->state = MTK_STATE_HEADER;
420 mtk_v4l2_vdec_dbg(1, ctx, "Init driver from init to header.");
421 } else {
422 mtk_v4l2_vdec_dbg(3, ctx, "[%d] already init driver %d", ctx->id, ctx->state);
423 }
424 }
425
mtk_vdec_flush_decoder(struct mtk_vcodec_dec_ctx * ctx)426 static int mtk_vdec_flush_decoder(struct mtk_vcodec_dec_ctx *ctx)
427 {
428 bool res_chg;
429
430 return vdec_if_decode(ctx, NULL, NULL, &res_chg);
431 }
432
mtk_vcodec_get_pic_info(struct mtk_vcodec_dec_ctx * ctx)433 static int mtk_vcodec_get_pic_info(struct mtk_vcodec_dec_ctx *ctx)
434 {
435 struct mtk_q_data *q_data;
436 int ret = 0;
437
438 q_data = &ctx->q_data[MTK_Q_DATA_DST];
439 if (q_data->fmt->num_planes == 1) {
440 mtk_v4l2_vdec_err(ctx, "[%d]Error!! 10bit mode not support one plane", ctx->id);
441 return -EINVAL;
442 }
443
444 ctx->capture_fourcc = q_data->fmt->fourcc;
445 ret = vdec_if_get_param(ctx, GET_PARAM_PIC_INFO, &ctx->picinfo);
446 if (ret) {
447 mtk_v4l2_vdec_err(ctx, "[%d]Error!! Get GET_PARAM_PICTURE_INFO Fail", ctx->id);
448 return ret;
449 }
450
451 ctx->last_decoded_picinfo = ctx->picinfo;
452
453 q_data->sizeimage[0] = ctx->picinfo.fb_sz[0];
454 q_data->bytesperline[0] = ctx->picinfo.buf_w * 5 / 4;
455
456 q_data->sizeimage[1] = ctx->picinfo.fb_sz[1];
457 q_data->bytesperline[1] = ctx->picinfo.buf_w * 5 / 4;
458
459 q_data->coded_width = ctx->picinfo.buf_w;
460 q_data->coded_height = ctx->picinfo.buf_h;
461 mtk_v4l2_vdec_dbg(1, ctx, "[%d] wxh=%dx%d pic wxh=%dx%d sz[0]=0x%x sz[1]=0x%x",
462 ctx->id, ctx->picinfo.buf_w, ctx->picinfo.buf_h,
463 ctx->picinfo.pic_w, ctx->picinfo.pic_h,
464 q_data->sizeimage[0], q_data->sizeimage[1]);
465
466 return ret;
467 }
468
mtk_vdec_s_ctrl(struct v4l2_ctrl * ctrl)469 static int mtk_vdec_s_ctrl(struct v4l2_ctrl *ctrl)
470 {
471 struct mtk_vcodec_dec_ctx *ctx = ctrl_to_dec_ctx(ctrl);
472 struct v4l2_ctrl_h264_sps *h264;
473 struct v4l2_ctrl_hevc_sps *h265;
474 struct v4l2_ctrl_vp9_frame *frame;
475 struct v4l2_ctrl_av1_sequence *seq;
476 struct v4l2_ctrl *hdr_ctrl;
477 const struct mtk_vcodec_dec_pdata *dec_pdata = ctx->dev->vdec_pdata;
478 const struct mtk_video_fmt *fmt;
479 int i = 0, ret = 0;
480
481 hdr_ctrl = ctrl;
482 if (!hdr_ctrl || !hdr_ctrl->p_new.p)
483 return -EINVAL;
484
485 switch (hdr_ctrl->id) {
486 case V4L2_CID_STATELESS_H264_SPS:
487 h264 = (struct v4l2_ctrl_h264_sps *)hdr_ctrl->p_new.p;
488
489 if (h264->bit_depth_chroma_minus8 == 2 && h264->bit_depth_luma_minus8 == 2) {
490 ctx->is_10bit_bitstream = true;
491 } else if (h264->bit_depth_chroma_minus8 != 0 &&
492 h264->bit_depth_luma_minus8 != 0) {
493 mtk_v4l2_vdec_err(ctx, "H264: chroma_minus8:%d, luma_minus8:%d",
494 h264->bit_depth_chroma_minus8,
495 h264->bit_depth_luma_minus8);
496 return -EINVAL;
497 }
498 break;
499 case V4L2_CID_STATELESS_HEVC_SPS:
500 h265 = (struct v4l2_ctrl_hevc_sps *)hdr_ctrl->p_new.p;
501
502 if (h265->bit_depth_chroma_minus8 == 2 && h265->bit_depth_luma_minus8 == 2) {
503 ctx->is_10bit_bitstream = true;
504 } else if (h265->bit_depth_chroma_minus8 != 0 &&
505 h265->bit_depth_luma_minus8 != 0) {
506 mtk_v4l2_vdec_err(ctx, "HEVC: chroma_minus8:%d, luma_minus8:%d",
507 h265->bit_depth_chroma_minus8,
508 h265->bit_depth_luma_minus8);
509 return -EINVAL;
510 }
511 break;
512 case V4L2_CID_STATELESS_VP9_FRAME:
513 frame = (struct v4l2_ctrl_vp9_frame *)hdr_ctrl->p_new.p;
514
515 if (frame->bit_depth == 10) {
516 ctx->is_10bit_bitstream = true;
517 } else if (frame->bit_depth != 8) {
518 mtk_v4l2_vdec_err(ctx, "VP9: bit_depth:%d", frame->bit_depth);
519 return -EINVAL;
520 }
521
522 if (!(frame->flags & V4L2_VP9_FRAME_FLAG_X_SUBSAMPLING) ||
523 !(frame->flags & V4L2_VP9_FRAME_FLAG_Y_SUBSAMPLING)) {
524 mtk_v4l2_vdec_err(ctx, "VP9: only 420 subsampling is supported");
525 return -EINVAL;
526 }
527 break;
528 case V4L2_CID_STATELESS_AV1_SEQUENCE:
529 seq = (struct v4l2_ctrl_av1_sequence *)hdr_ctrl->p_new.p;
530
531 if (seq->bit_depth == 10) {
532 ctx->is_10bit_bitstream = true;
533 } else if (seq->bit_depth != 8) {
534 mtk_v4l2_vdec_err(ctx, "AV1: bit_depth:%d", seq->bit_depth);
535 return -EINVAL;
536 }
537 break;
538 default:
539 mtk_v4l2_vdec_dbg(3, ctx, "Not supported to set ctrl id: 0x%x\n", hdr_ctrl->id);
540 return ret;
541 }
542
543 if (!ctx->is_10bit_bitstream)
544 return ret;
545
546 for (i = 0; i < *dec_pdata->num_formats; i++) {
547 fmt = &dec_pdata->vdec_formats[i];
548 if (fmt->fourcc == V4L2_PIX_FMT_MT2110R &&
549 hdr_ctrl->id == V4L2_CID_STATELESS_H264_SPS) {
550 ctx->q_data[MTK_Q_DATA_DST].fmt = fmt;
551 break;
552 }
553
554 if (fmt->fourcc == V4L2_PIX_FMT_MT2110T &&
555 (hdr_ctrl->id == V4L2_CID_STATELESS_HEVC_SPS ||
556 hdr_ctrl->id == V4L2_CID_STATELESS_VP9_FRAME ||
557 hdr_ctrl->id == V4L2_CID_STATELESS_AV1_SEQUENCE)) {
558 ctx->q_data[MTK_Q_DATA_DST].fmt = fmt;
559 break;
560 }
561 }
562 ret = mtk_vcodec_get_pic_info(ctx);
563
564 return ret;
565 }
566
567 static const struct v4l2_ctrl_ops mtk_vcodec_dec_ctrl_ops = {
568 .s_ctrl = mtk_vdec_s_ctrl,
569 };
570
mtk_vcodec_dec_fill_h264_level(struct v4l2_ctrl_config * cfg,struct mtk_vcodec_dec_ctx * ctx)571 static void mtk_vcodec_dec_fill_h264_level(struct v4l2_ctrl_config *cfg,
572 struct mtk_vcodec_dec_ctx *ctx)
573 {
574 switch (ctx->dev->chip_name) {
575 case MTK_VDEC_MT8192:
576 case MTK_VDEC_MT8188:
577 cfg->max = V4L2_MPEG_VIDEO_H264_LEVEL_5_2;
578 break;
579 case MTK_VDEC_MT8195:
580 cfg->max = V4L2_MPEG_VIDEO_H264_LEVEL_6_0;
581 break;
582 case MTK_VDEC_MT8183:
583 case MTK_VDEC_MT8186:
584 cfg->max = V4L2_MPEG_VIDEO_H264_LEVEL_4_2;
585 break;
586 default:
587 cfg->max = V4L2_MPEG_VIDEO_H264_LEVEL_4_1;
588 break;
589 }
590 }
591
mtk_vcodec_dec_fill_h264_profile(struct v4l2_ctrl_config * cfg,struct mtk_vcodec_dec_ctx * ctx)592 static void mtk_vcodec_dec_fill_h264_profile(struct v4l2_ctrl_config *cfg,
593 struct mtk_vcodec_dec_ctx *ctx)
594 {
595 switch (ctx->dev->chip_name) {
596 case MTK_VDEC_MT8188:
597 case MTK_VDEC_MT8195:
598 cfg->max = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10;
599 break;
600 default:
601 cfg->max = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH;
602 break;
603 }
604 }
605
mtk_vcodec_dec_fill_h265_level(struct v4l2_ctrl_config * cfg,struct mtk_vcodec_dec_ctx * ctx)606 static void mtk_vcodec_dec_fill_h265_level(struct v4l2_ctrl_config *cfg,
607 struct mtk_vcodec_dec_ctx *ctx)
608 {
609 switch (ctx->dev->chip_name) {
610 case MTK_VDEC_MT8188:
611 cfg->max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1;
612 break;
613 case MTK_VDEC_MT8195:
614 cfg->max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2;
615 break;
616 default:
617 cfg->max = V4L2_MPEG_VIDEO_HEVC_LEVEL_4;
618 break;
619 }
620 }
621
mtk_vcodec_dec_fill_h265_profile(struct v4l2_ctrl_config * cfg,struct mtk_vcodec_dec_ctx * ctx)622 static void mtk_vcodec_dec_fill_h265_profile(struct v4l2_ctrl_config *cfg,
623 struct mtk_vcodec_dec_ctx *ctx)
624 {
625 switch (ctx->dev->chip_name) {
626 case MTK_VDEC_MT8188:
627 case MTK_VDEC_MT8195:
628 cfg->max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10;
629 break;
630 default:
631 cfg->max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE;
632 break;
633 }
634 }
635
mtk_vcodec_dec_fill_vp9_level(struct v4l2_ctrl_config * cfg,struct mtk_vcodec_dec_ctx * ctx)636 static void mtk_vcodec_dec_fill_vp9_level(struct v4l2_ctrl_config *cfg,
637 struct mtk_vcodec_dec_ctx *ctx)
638 {
639 switch (ctx->dev->chip_name) {
640 case MTK_VDEC_MT8192:
641 case MTK_VDEC_MT8188:
642 cfg->max = V4L2_MPEG_VIDEO_VP9_LEVEL_5_1;
643 break;
644 case MTK_VDEC_MT8195:
645 cfg->max = V4L2_MPEG_VIDEO_VP9_LEVEL_5_2;
646 break;
647 case MTK_VDEC_MT8186:
648 cfg->max = V4L2_MPEG_VIDEO_VP9_LEVEL_4_1;
649 break;
650 default:
651 cfg->max = V4L2_MPEG_VIDEO_VP9_LEVEL_4_0;
652 break;
653 }
654 }
655
mtk_vcodec_dec_fill_vp9_profile(struct v4l2_ctrl_config * cfg,struct mtk_vcodec_dec_ctx * ctx)656 static void mtk_vcodec_dec_fill_vp9_profile(struct v4l2_ctrl_config *cfg,
657 struct mtk_vcodec_dec_ctx *ctx)
658 {
659 switch (ctx->dev->chip_name) {
660 case MTK_VDEC_MT8188:
661 case MTK_VDEC_MT8195:
662 cfg->max = V4L2_MPEG_VIDEO_VP9_PROFILE_2;
663 break;
664 default:
665 cfg->max = V4L2_MPEG_VIDEO_VP9_PROFILE_1;
666 break;
667 }
668 }
669
mtk_vcodec_dec_reset_controls(struct v4l2_ctrl_config * cfg,struct mtk_vcodec_dec_ctx * ctx)670 static void mtk_vcodec_dec_reset_controls(struct v4l2_ctrl_config *cfg,
671 struct mtk_vcodec_dec_ctx *ctx)
672 {
673 switch (cfg->id) {
674 case V4L2_CID_MPEG_VIDEO_H264_LEVEL:
675 mtk_vcodec_dec_fill_h264_level(cfg, ctx);
676 mtk_v4l2_vdec_dbg(3, ctx, "h264 supported level: %lld %lld", cfg->max, cfg->def);
677 break;
678 case V4L2_CID_MPEG_VIDEO_HEVC_LEVEL:
679 mtk_vcodec_dec_fill_h265_level(cfg, ctx);
680 mtk_v4l2_vdec_dbg(3, ctx, "h265 supported level: %lld %lld", cfg->max, cfg->def);
681 break;
682 case V4L2_CID_MPEG_VIDEO_VP9_LEVEL:
683 mtk_vcodec_dec_fill_vp9_level(cfg, ctx);
684 mtk_v4l2_vdec_dbg(3, ctx, "vp9 supported level: %lld %lld", cfg->max, cfg->def);
685 break;
686 case V4L2_CID_MPEG_VIDEO_H264_PROFILE:
687 mtk_vcodec_dec_fill_h264_profile(cfg, ctx);
688 mtk_v4l2_vdec_dbg(3, ctx, "h264 supported profile: %lld %lld", cfg->max,
689 cfg->menu_skip_mask);
690 break;
691 case V4L2_CID_MPEG_VIDEO_HEVC_PROFILE:
692 mtk_vcodec_dec_fill_h265_profile(cfg, ctx);
693 mtk_v4l2_vdec_dbg(3, ctx, "h265 supported profile: %lld %lld", cfg->max,
694 cfg->menu_skip_mask);
695 break;
696 case V4L2_CID_MPEG_VIDEO_VP9_PROFILE:
697 mtk_vcodec_dec_fill_vp9_profile(cfg, ctx);
698 mtk_v4l2_vdec_dbg(3, ctx, "vp9 supported profile: %lld %lld", cfg->max,
699 cfg->menu_skip_mask);
700 break;
701 default:
702 break;
703 }
704 }
705
mtk_vcodec_dec_ctrls_setup(struct mtk_vcodec_dec_ctx * ctx)706 static int mtk_vcodec_dec_ctrls_setup(struct mtk_vcodec_dec_ctx *ctx)
707 {
708 unsigned int i;
709
710 v4l2_ctrl_handler_init(&ctx->ctrl_hdl, NUM_CTRLS);
711 if (ctx->ctrl_hdl.error) {
712 mtk_v4l2_vdec_err(ctx, "v4l2_ctrl_handler_init failed\n");
713 return ctx->ctrl_hdl.error;
714 }
715
716 for (i = 0; i < NUM_CTRLS; i++) {
717 struct v4l2_ctrl_config cfg = mtk_stateless_controls[i].cfg;
718 cfg.ops = &mtk_vcodec_dec_ctrl_ops;
719
720 mtk_vcodec_dec_reset_controls(&cfg, ctx);
721 v4l2_ctrl_new_custom(&ctx->ctrl_hdl, &cfg, NULL);
722 if (ctx->ctrl_hdl.error) {
723 mtk_v4l2_vdec_err(ctx, "Adding control %d failed %d", i,
724 ctx->ctrl_hdl.error);
725 return ctx->ctrl_hdl.error;
726 }
727 }
728
729 v4l2_ctrl_handler_setup(&ctx->ctrl_hdl);
730
731 return 0;
732 }
733
fops_media_request_alloc(struct media_device * mdev)734 static struct media_request *fops_media_request_alloc(struct media_device *mdev)
735 {
736 struct mtk_vcodec_dec_request *req;
737
738 req = kzalloc_obj(*req);
739
740 return &req->req;
741 }
742
fops_media_request_free(struct media_request * mreq)743 static void fops_media_request_free(struct media_request *mreq)
744 {
745 struct mtk_vcodec_dec_request *req = req_to_dec_req(mreq);
746
747 kfree(req);
748 }
749
fops_media_request_validate(struct media_request * mreq)750 static int fops_media_request_validate(struct media_request *mreq)
751 {
752 const unsigned int buffer_cnt = vb2_request_buffer_cnt(mreq);
753
754 switch (buffer_cnt) {
755 case 1:
756 /* We expect exactly one buffer with the request */
757 break;
758 case 0:
759 pr_debug(MTK_DBG_VCODEC_STR "No buffer provided with the request.");
760 return -ENOENT;
761 default:
762 pr_debug(MTK_DBG_VCODEC_STR "Too many buffers (%d) provided with the request.",
763 buffer_cnt);
764 return -EINVAL;
765 }
766
767 return vb2_request_validate(mreq);
768 }
769
fops_media_request_queue(struct media_request * mreq)770 static void fops_media_request_queue(struct media_request *mreq)
771 {
772 struct mtk_vcodec_dec_request *req = req_to_dec_req(mreq);
773
774 media_request_mark_manual_completion(mreq);
775 kref_init(&req->refcount);
776 v4l2_m2m_request_queue(mreq);
777 }
778
779 const struct media_device_ops mtk_vcodec_media_ops = {
780 .req_alloc = fops_media_request_alloc,
781 .req_free = fops_media_request_free,
782 .req_validate = fops_media_request_validate,
783 .req_queue = fops_media_request_queue,
784 };
785
mtk_vcodec_add_formats(unsigned int fourcc,struct mtk_vcodec_dec_ctx * ctx)786 static void mtk_vcodec_add_formats(unsigned int fourcc,
787 struct mtk_vcodec_dec_ctx *ctx)
788 {
789 struct mtk_vcodec_dec_dev *dev = ctx->dev;
790 const struct mtk_vcodec_dec_pdata *pdata = dev->vdec_pdata;
791 int count_formats = *pdata->num_formats;
792
793 switch (fourcc) {
794 case V4L2_PIX_FMT_H264_SLICE:
795 case V4L2_PIX_FMT_VP8_FRAME:
796 case V4L2_PIX_FMT_VP9_FRAME:
797 case V4L2_PIX_FMT_HEVC_SLICE:
798 case V4L2_PIX_FMT_AV1_FRAME:
799 mtk_video_formats[count_formats].fourcc = fourcc;
800 mtk_video_formats[count_formats].type = MTK_FMT_DEC;
801 mtk_video_formats[count_formats].num_planes = 1;
802 mtk_video_formats[count_formats].frmsize = stepwise_fhd;
803
804 if (!(ctx->dev->dec_capability & VCODEC_CAPABILITY_4K_DISABLED) &&
805 fourcc != V4L2_PIX_FMT_VP8_FRAME) {
806 mtk_video_formats[count_formats].frmsize.max_width =
807 VCODEC_DEC_4K_CODED_WIDTH;
808 mtk_video_formats[count_formats].frmsize.max_height =
809 VCODEC_DEC_4K_CODED_HEIGHT;
810 }
811 break;
812 case V4L2_PIX_FMT_MM21:
813 case V4L2_PIX_FMT_MT21C:
814 case V4L2_PIX_FMT_MT2110T:
815 case V4L2_PIX_FMT_MT2110R:
816 mtk_video_formats[count_formats].fourcc = fourcc;
817 mtk_video_formats[count_formats].type = MTK_FMT_FRAME;
818 mtk_video_formats[count_formats].num_planes = 2;
819 break;
820 default:
821 mtk_v4l2_vdec_err(ctx, "Can not add unsupported format type");
822 return;
823 }
824
825 num_formats++;
826 mtk_v4l2_vdec_dbg(3, ctx, "num_formats: %d dec_capability: 0x%x",
827 count_formats, ctx->dev->dec_capability);
828 }
829
mtk_vcodec_get_supported_formats(struct mtk_vcodec_dec_ctx * ctx)830 static void mtk_vcodec_get_supported_formats(struct mtk_vcodec_dec_ctx *ctx)
831 {
832 int cap_format_count = 0, out_format_count = 0;
833
834 if (num_formats)
835 return;
836
837 if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_MT21C) {
838 mtk_vcodec_add_formats(V4L2_PIX_FMT_MT21C, ctx);
839 cap_format_count++;
840 }
841 if (ctx->dev->dec_capability & MTK_VDEC_IS_SUPPORT_10BIT) {
842 mtk_vcodec_add_formats(V4L2_PIX_FMT_MT2110T, ctx);
843 cap_format_count++;
844 mtk_vcodec_add_formats(V4L2_PIX_FMT_MT2110R, ctx);
845 cap_format_count++;
846 }
847 if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_MM21) {
848 mtk_vcodec_add_formats(V4L2_PIX_FMT_MM21, ctx);
849 cap_format_count++;
850 }
851 if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_H264_SLICE) {
852 mtk_vcodec_add_formats(V4L2_PIX_FMT_H264_SLICE, ctx);
853 out_format_count++;
854 }
855 if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_VP8_FRAME) {
856 mtk_vcodec_add_formats(V4L2_PIX_FMT_VP8_FRAME, ctx);
857 out_format_count++;
858 }
859 if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_VP9_FRAME) {
860 mtk_vcodec_add_formats(V4L2_PIX_FMT_VP9_FRAME, ctx);
861 out_format_count++;
862 }
863 if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_HEVC_FRAME) {
864 mtk_vcodec_add_formats(V4L2_PIX_FMT_HEVC_SLICE, ctx);
865 out_format_count++;
866 }
867 if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_AV1_FRAME) {
868 mtk_vcodec_add_formats(V4L2_PIX_FMT_AV1_FRAME, ctx);
869 out_format_count++;
870 }
871
872 if (cap_format_count)
873 default_cap_format = mtk_video_formats[cap_format_count - 1];
874 if (out_format_count)
875 default_out_format =
876 mtk_video_formats[cap_format_count + out_format_count - 1];
877 }
878
mtk_init_vdec_params(struct mtk_vcodec_dec_ctx * ctx)879 static void mtk_init_vdec_params(struct mtk_vcodec_dec_ctx *ctx)
880 {
881 struct vb2_queue *src_vq;
882
883 src_vq = v4l2_m2m_get_vq(ctx->m2m_ctx,
884 V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
885
886 if (!ctx->dev->vdec_pdata->is_subdev_supported)
887 ctx->dev->dec_capability |=
888 MTK_VDEC_FORMAT_H264_SLICE | MTK_VDEC_FORMAT_MM21;
889 mtk_vcodec_get_supported_formats(ctx);
890
891 /* Support request api for output plane */
892 src_vq->supports_requests = true;
893 src_vq->requires_requests = true;
894 }
895
vb2ops_vdec_out_buf_validate(struct vb2_buffer * vb)896 static int vb2ops_vdec_out_buf_validate(struct vb2_buffer *vb)
897 {
898 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
899
900 vbuf->field = V4L2_FIELD_NONE;
901 return 0;
902 }
903
904 static const struct vb2_ops mtk_vdec_request_vb2_ops = {
905 .queue_setup = vb2ops_vdec_queue_setup,
906 .start_streaming = vb2ops_vdec_start_streaming,
907 .stop_streaming = vb2ops_vdec_stop_streaming,
908
909 .buf_queue = vb2ops_vdec_stateless_buf_queue,
910 .buf_out_validate = vb2ops_vdec_out_buf_validate,
911 .buf_init = vb2ops_vdec_buf_init,
912 .buf_prepare = vb2ops_vdec_buf_prepare,
913 .buf_finish = vb2ops_vdec_buf_finish,
914 .buf_request_complete = vb2ops_vdec_buf_request_complete,
915 };
916
917 const struct mtk_vcodec_dec_pdata mtk_vdec_8183_pdata = {
918 .init_vdec_params = mtk_init_vdec_params,
919 .ctrls_setup = mtk_vcodec_dec_ctrls_setup,
920 .vdec_vb2_ops = &mtk_vdec_request_vb2_ops,
921 .vdec_formats = mtk_video_formats,
922 .num_formats = &num_formats,
923 .default_out_fmt = &default_out_format,
924 .default_cap_fmt = &default_cap_format,
925 .uses_stateless_api = true,
926 .worker = mtk_vdec_worker,
927 .flush_decoder = mtk_vdec_flush_decoder,
928 .cap_to_disp = mtk_vdec_stateless_cap_to_disp,
929 .get_cap_buffer = vdec_get_cap_buffer,
930 .is_subdev_supported = false,
931 .hw_arch = MTK_VDEC_PURE_SINGLE_CORE,
932 };
933
934 /* This platform data is used for one lat and one core architecture. */
935 const struct mtk_vcodec_dec_pdata mtk_lat_sig_core_pdata = {
936 .init_vdec_params = mtk_init_vdec_params,
937 .ctrls_setup = mtk_vcodec_dec_ctrls_setup,
938 .vdec_vb2_ops = &mtk_vdec_request_vb2_ops,
939 .vdec_formats = mtk_video_formats,
940 .num_formats = &num_formats,
941 .default_out_fmt = &default_out_format,
942 .default_cap_fmt = &default_cap_format,
943 .uses_stateless_api = true,
944 .worker = mtk_vdec_worker,
945 .flush_decoder = mtk_vdec_flush_decoder,
946 .cap_to_disp = mtk_vdec_stateless_cap_to_disp,
947 .get_cap_buffer = vdec_get_cap_buffer,
948 .is_subdev_supported = true,
949 .hw_arch = MTK_VDEC_LAT_SINGLE_CORE,
950 };
951
952 const struct mtk_vcodec_dec_pdata mtk_vdec_single_core_pdata = {
953 .init_vdec_params = mtk_init_vdec_params,
954 .ctrls_setup = mtk_vcodec_dec_ctrls_setup,
955 .vdec_vb2_ops = &mtk_vdec_request_vb2_ops,
956 .vdec_formats = mtk_video_formats,
957 .num_formats = &num_formats,
958 .default_out_fmt = &default_out_format,
959 .default_cap_fmt = &default_cap_format,
960 .uses_stateless_api = true,
961 .worker = mtk_vdec_worker,
962 .flush_decoder = mtk_vdec_flush_decoder,
963 .cap_to_disp = mtk_vdec_stateless_cap_to_disp,
964 .get_cap_buffer = vdec_get_cap_buffer,
965 .is_subdev_supported = true,
966 .hw_arch = MTK_VDEC_PURE_SINGLE_CORE,
967 };
968