1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #ifndef __INTEL_VDSC_REGS_H__ 7 #define __INTEL_VDSC_REGS_H__ 8 9 #include "intel_display_reg_defs.h" 10 11 /* Display Stream Splitter Control */ 12 #define DSS_CTL1 _MMIO(0x67400) 13 #define SPLITTER_ENABLE (1 << 31) 14 #define JOINER_ENABLE (1 << 30) 15 #define DUAL_LINK_MODE_INTERLEAVE (1 << 24) 16 #define DUAL_LINK_MODE_FRONTBACK (0 << 24) 17 #define OVERLAP_PIXELS_MASK (0xf << 16) 18 #define OVERLAP_PIXELS(pixels) ((pixels) << 16) 19 #define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) 20 #define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) 21 #define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0 22 23 #define DSS_CTL2 _MMIO(0x67404) 24 #define VDSC0_ENABLE REG_BIT(31) 25 #define VDSC2_ENABLE REG_BIT(30) 26 #define SMALL_JOINER_CONFIG_3_ENGINES REG_BIT(23) 27 #define VDSC1_ENABLE REG_BIT(15) 28 #define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) 29 #define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) 30 31 #define _ICL_PIPE_DSS_CTL1_PB 0x78200 32 #define _ICL_PIPE_DSS_CTL1_PC 0x78400 33 #define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 34 _ICL_PIPE_DSS_CTL1_PB, \ 35 _ICL_PIPE_DSS_CTL1_PC) 36 #define BIG_JOINER_ENABLE (1 << 29) 37 #define PRIMARY_BIG_JOINER_ENABLE (1 << 28) 38 #define VGA_CENTERING_ENABLE (1 << 27) 39 #define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25) 40 #define SPLITTER_CONFIGURATION_2_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0) 41 #define SPLITTER_CONFIGURATION_4_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1) 42 #define ULTRA_JOINER_ENABLE REG_BIT(23) 43 #define PRIMARY_ULTRA_JOINER_ENABLE REG_BIT(22) 44 #define UNCOMPRESSED_JOINER_PRIMARY (1 << 21) 45 #define UNCOMPRESSED_JOINER_SECONDARY (1 << 20) 46 47 #define _ICL_PIPE_DSS_CTL2_PB 0x78204 48 #define _ICL_PIPE_DSS_CTL2_PC 0x78404 49 #define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 50 _ICL_PIPE_DSS_CTL2_PB, \ 51 _ICL_PIPE_DSS_CTL2_PC) 52 53 /* Icelake Display Stream Compression Registers */ 54 #define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200) 55 #define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00) 56 #define _DSCA_PPS_0 0x6B200 57 #define _DSCC_PPS_0 0x6BA00 58 #define DSCA_PPS(pps) _MMIO(_DSCA_PPS_0 + ((pps) < 12 ? (pps) : (pps) + 12) * 4) 59 #define DSCC_PPS(pps) _MMIO(_DSCC_PPS_0 + ((pps) < 12 ? (pps) : (pps) + 12) * 4) 60 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270 61 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370 62 #define _BMG_DSC2_PICTURE_PARAMETER_SET_0_PB 0x78970 63 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470 64 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC 0x78570 65 #define _BMG_DSC2_PICTURE_PARAMETER_SET_0_PC 0x78A70 66 #define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 67 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \ 68 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC) 69 #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 70 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \ 71 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC) 72 #define _ICL_DSC0_PPS_0(pipe) _PICK_EVEN((pipe) - PIPE_B, \ 73 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \ 74 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC) 75 #define _ICL_DSC1_PPS_0(pipe) _PICK_EVEN((pipe) - PIPE_B, \ 76 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \ 77 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC) 78 #define _BMG_DSC2_PPS_0(pipe) _PICK_EVEN((pipe) - PIPE_B, \ 79 _BMG_DSC2_PICTURE_PARAMETER_SET_0_PB, \ 80 _BMG_DSC2_PICTURE_PARAMETER_SET_0_PC) 81 #define ICL_DSC0_PPS(pipe, pps) _MMIO(_ICL_DSC0_PPS_0(pipe) + ((pps) * 4)) 82 #define ICL_DSC1_PPS(pipe, pps) _MMIO(_ICL_DSC1_PPS_0(pipe) + ((pps) * 4)) 83 #define BMG_DSC2_PPS(pipe, pps) _MMIO(_BMG_DSC2_PPS_0(pipe) + ((pps) * 4)) 84 85 /* PPS 0 */ 86 #define DSC_PPS0_NATIVE_422_ENABLE REG_BIT(23) 87 #define DSC_PPS0_NATIVE_420_ENABLE REG_BIT(22) 88 #define DSC_PPS0_ALT_ICH_SEL REG_BIT(20) 89 #define DSC_PPS0_VBR_ENABLE REG_BIT(19) 90 #define DSC_PPS0_422_ENABLE REG_BIT(18) 91 #define DSC_PPS0_COLOR_SPACE_CONVERSION REG_BIT(17) 92 #define DSC_PPS0_BLOCK_PREDICTION REG_BIT(16) 93 #define DSC_PPS0_LINE_BUF_DEPTH_MASK REG_GENMASK(15, 12) 94 #define DSC_PPS0_LINE_BUF_DEPTH(depth) REG_FIELD_PREP(DSC_PPS0_LINE_BUF_DEPTH_MASK, depth) 95 #define DSC_PPS0_BPC_MASK REG_GENMASK(11, 8) 96 #define DSC_PPS0_BPC(bpc) REG_FIELD_PREP(DSC_PPS0_BPC_MASK, bpc) 97 #define DSC_PPS0_VER_MINOR_MASK REG_GENMASK(7, 4) 98 #define DSC_PPS0_VER_MINOR(minor) REG_FIELD_PREP(DSC_PPS0_VER_MINOR_MASK, minor) 99 #define DSC_PPS0_VER_MAJOR_MASK REG_GENMASK(3, 0) 100 #define DSC_PPS0_VER_MAJOR(major) REG_FIELD_PREP(DSC_PPS0_VER_MAJOR_MASK, major) 101 102 /* PPS 1 */ 103 #define DSC_PPS1_BPP_MASK REG_GENMASK(9, 0) 104 #define DSC_PPS1_BPP(bpp) REG_FIELD_PREP(DSC_PPS1_BPP_MASK, bpp) 105 106 /* PPS 2 */ 107 #define DSC_PPS2_PIC_WIDTH_MASK REG_GENMASK(31, 16) 108 #define DSC_PPS2_PIC_HEIGHT_MASK REG_GENMASK(15, 0) 109 #define DSC_PPS2_PIC_WIDTH(pic_width) REG_FIELD_PREP(DSC_PPS2_PIC_WIDTH_MASK, pic_width) 110 #define DSC_PPS2_PIC_HEIGHT(pic_height) REG_FIELD_PREP(DSC_PPS2_PIC_HEIGHT_MASK, pic_height) 111 112 /* PPS 3 */ 113 #define DSC_PPS3_SLICE_WIDTH_MASK REG_GENMASK(31, 16) 114 #define DSC_PPS3_SLICE_HEIGHT_MASK REG_GENMASK(15, 0) 115 #define DSC_PPS3_SLICE_WIDTH(slice_width) REG_FIELD_PREP(DSC_PPS3_SLICE_WIDTH_MASK, slice_width) 116 #define DSC_PPS3_SLICE_HEIGHT(slice_height) REG_FIELD_PREP(DSC_PPS3_SLICE_HEIGHT_MASK, slice_height) 117 118 /* PPS 4 */ 119 #define DSC_PPS4_INITIAL_DEC_DELAY_MASK REG_GENMASK(31, 16) 120 #define DSC_PPS4_INITIAL_XMIT_DELAY_MASK REG_GENMASK(9, 0) 121 #define DSC_PPS4_INITIAL_DEC_DELAY(dec_delay) REG_FIELD_PREP(DSC_PPS4_INITIAL_DEC_DELAY_MASK, \ 122 dec_delay) 123 #define DSC_PPS4_INITIAL_XMIT_DELAY(xmit_delay) REG_FIELD_PREP(DSC_PPS4_INITIAL_XMIT_DELAY_MASK, \ 124 xmit_delay) 125 126 /* PPS 5 */ 127 #define DSC_PPS5_SCALE_DEC_INT_MASK REG_GENMASK(27, 16) 128 #define DSC_PPS5_SCALE_INC_INT_MASK REG_GENMASK(15, 0) 129 #define DSC_PPS5_SCALE_DEC_INT(scale_dec) REG_FIELD_PREP(DSC_PPS5_SCALE_DEC_INT_MASK, scale_dec) 130 #define DSC_PPS5_SCALE_INC_INT(scale_inc) REG_FIELD_PREP(DSC_PPS5_SCALE_INC_INT_MASK, scale_inc) 131 132 /* PPS 6 */ 133 #define DSC_PPS6_FLATNESS_MAX_QP_MASK REG_GENMASK(28, 24) 134 #define DSC_PPS6_FLATNESS_MIN_QP_MASK REG_GENMASK(20, 16) 135 #define DSC_PPS6_FIRST_LINE_BPG_OFFSET_MASK REG_GENMASK(12, 8) 136 #define DSC_PPS6_INITIAL_SCALE_VALUE_MASK REG_GENMASK(5, 0) 137 #define DSC_PPS6_FLATNESS_MAX_QP(max_qp) REG_FIELD_PREP(DSC_PPS6_FLATNESS_MAX_QP_MASK, max_qp) 138 #define DSC_PPS6_FLATNESS_MIN_QP(min_qp) REG_FIELD_PREP(DSC_PPS6_FLATNESS_MIN_QP_MASK, min_qp) 139 #define DSC_PPS6_FIRST_LINE_BPG_OFFSET(offset) REG_FIELD_PREP(DSC_PPS6_FIRST_LINE_BPG_OFFSET_MASK, \ 140 offset) 141 #define DSC_PPS6_INITIAL_SCALE_VALUE(value) REG_FIELD_PREP(DSC_PPS6_INITIAL_SCALE_VALUE_MASK, \ 142 value) 143 144 /* PPS 7 */ 145 #define DSC_PPS7_NFL_BPG_OFFSET_MASK REG_GENMASK(31, 16) 146 #define DSC_PPS7_SLICE_BPG_OFFSET_MASK REG_GENMASK(15, 0) 147 #define DSC_PPS7_NFL_BPG_OFFSET(bpg_offset) REG_FIELD_PREP(DSC_PPS7_NFL_BPG_OFFSET_MASK, bpg_offset) 148 #define DSC_PPS7_SLICE_BPG_OFFSET(bpg_offset) REG_FIELD_PREP(DSC_PPS7_SLICE_BPG_OFFSET_MASK, \ 149 bpg_offset) 150 /* PPS 8 */ 151 #define DSC_PPS8_INITIAL_OFFSET_MASK REG_GENMASK(31, 16) 152 #define DSC_PPS8_FINAL_OFFSET_MASK REG_GENMASK(15, 0) 153 #define DSC_PPS8_INITIAL_OFFSET(initial_offset) REG_FIELD_PREP(DSC_PPS8_INITIAL_OFFSET_MASK, \ 154 initial_offset) 155 #define DSC_PPS8_FINAL_OFFSET(final_offset) REG_FIELD_PREP(DSC_PPS8_FINAL_OFFSET_MASK, \ 156 final_offset) 157 158 /* PPS 9 */ 159 #define DSC_PPS9_RC_EDGE_FACTOR_MASK REG_GENMASK(19, 16) 160 #define DSC_PPS9_RC_MODEL_SIZE_MASK REG_GENMASK(15, 0) 161 #define DSC_PPS9_RC_EDGE_FACTOR(rc_edge_fact) REG_FIELD_PREP(DSC_PPS9_RC_EDGE_FACTOR_MASK, \ 162 rc_edge_fact) 163 #define DSC_PPS9_RC_MODEL_SIZE(rc_model_size) REG_FIELD_PREP(DSC_PPS9_RC_MODEL_SIZE_MASK, \ 164 rc_model_size) 165 166 /* PPS 10 */ 167 #define DSC_PPS10_RC_TGT_OFF_LOW_MASK REG_GENMASK(23, 20) 168 #define DSC_PPS10_RC_TGT_OFF_HIGH_MASK REG_GENMASK(19, 16) 169 #define DSC_PPS10_RC_QUANT_INC_LIMIT1_MASK REG_GENMASK(12, 8) 170 #define DSC_PPS10_RC_QUANT_INC_LIMIT0_MASK REG_GENMASK(4, 0) 171 #define DSC_PPS10_RC_TARGET_OFF_LOW(rc_tgt_off_low) REG_FIELD_PREP(DSC_PPS10_RC_TGT_OFF_LOW_MASK, \ 172 rc_tgt_off_low) 173 #define DSC_PPS10_RC_TARGET_OFF_HIGH(rc_tgt_off_high) REG_FIELD_PREP(DSC_PPS10_RC_TGT_OFF_HIGH_MASK, \ 174 rc_tgt_off_high) 175 #define DSC_PPS10_RC_QUANT_INC_LIMIT1(lim) REG_FIELD_PREP(DSC_PPS10_RC_QUANT_INC_LIMIT1_MASK, lim) 176 #define DSC_PPS10_RC_QUANT_INC_LIMIT0(lim) REG_FIELD_PREP(DSC_PPS10_RC_QUANT_INC_LIMIT0_MASK, lim) 177 178 /* PPS 16 */ 179 #define DSC_PPS16_SLICE_ROW_PR_FRME_MASK REG_GENMASK(31, 20) 180 #define DSC_PPS16_SLICE_PER_LINE_MASK REG_GENMASK(18, 16) 181 #define DSC_PPS16_SLICE_CHUNK_SIZE_MASK REG_GENMASK(15, 0) 182 #define DSC_PPS16_SLICE_ROW_PER_FRAME(slice_row_per_frame) REG_FIELD_PREP(DSC_PPS16_SLICE_ROW_PR_FRME_MASK, \ 183 slice_row_per_frame) 184 #define DSC_PPS16_SLICE_PER_LINE(slice_per_line) REG_FIELD_PREP(DSC_PPS16_SLICE_PER_LINE_MASK, \ 185 slice_per_line) 186 #define DSC_PPS16_SLICE_CHUNK_SIZE(slice_chunk_size) REG_FIELD_PREP(DSC_PPS16_SLICE_CHUNK_SIZE_MASK, \ 187 slice_chunk_size) 188 189 /* PPS 17 (MTL+) */ 190 #define DSC_PPS17_SL_BPG_OFFSET_MASK REG_GENMASK(31, 27) 191 #define DSC_PPS17_SL_BPG_OFFSET(offset) REG_FIELD_PREP(DSC_PPS17_SL_BPG_OFFSET_MASK, offset) 192 193 /* PPS 18 (MTL+) */ 194 #define DSC_PPS18_NSL_BPG_OFFSET_MASK REG_GENMASK(31, 16) 195 #define DSC_PPS18_SL_OFFSET_ADJ_MASK REG_GENMASK(15, 0) 196 #define DSC_PPS18_NSL_BPG_OFFSET(offset) REG_FIELD_PREP(DSC_PPS18_NSL_BPG_OFFSET_MASK, offset) 197 #define DSC_PPS18_SL_OFFSET_ADJ(offset) REG_FIELD_PREP(DSC_PPS18_SL_OFFSET_ADJ_MASK, offset) 198 199 /* Icelake Rate Control Buffer Threshold Registers */ 200 #define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230) 201 #define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4) 202 #define DSCC_RC_BUF_THRESH_0 _MMIO(0x6BA30) 203 #define DSCC_RC_BUF_THRESH_0_UDW _MMIO(0x6BA30 + 4) 204 #define _ICL_DSC0_RC_BUF_THRESH_0_PB (0x78254) 205 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB (0x78254 + 4) 206 #define _ICL_DSC1_RC_BUF_THRESH_0_PB (0x78354) 207 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB (0x78354 + 4) 208 #define _ICL_DSC0_RC_BUF_THRESH_0_PC (0x78454) 209 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC (0x78454 + 4) 210 #define _ICL_DSC1_RC_BUF_THRESH_0_PC (0x78554) 211 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC (0x78554 + 4) 212 #define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 213 _ICL_DSC0_RC_BUF_THRESH_0_PB, \ 214 _ICL_DSC0_RC_BUF_THRESH_0_PC) 215 #define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 216 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \ 217 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC) 218 #define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 219 _ICL_DSC1_RC_BUF_THRESH_0_PB, \ 220 _ICL_DSC1_RC_BUF_THRESH_0_PC) 221 #define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 222 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \ 223 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC) 224 225 #define DSCA_RC_BUF_THRESH_1 _MMIO(0x6B238) 226 #define DSCA_RC_BUF_THRESH_1_UDW _MMIO(0x6B238 + 4) 227 #define DSCC_RC_BUF_THRESH_1 _MMIO(0x6BA38) 228 #define DSCC_RC_BUF_THRESH_1_UDW _MMIO(0x6BA38 + 4) 229 #define _ICL_DSC0_RC_BUF_THRESH_1_PB (0x7825C) 230 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB (0x7825C + 4) 231 #define _ICL_DSC1_RC_BUF_THRESH_1_PB (0x7835C) 232 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB (0x7835C + 4) 233 #define _ICL_DSC0_RC_BUF_THRESH_1_PC (0x7845C) 234 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC (0x7845C + 4) 235 #define _ICL_DSC1_RC_BUF_THRESH_1_PC (0x7855C) 236 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC (0x7855C + 4) 237 #define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 238 _ICL_DSC0_RC_BUF_THRESH_1_PB, \ 239 _ICL_DSC0_RC_BUF_THRESH_1_PC) 240 #define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 241 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \ 242 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC) 243 #define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 244 _ICL_DSC1_RC_BUF_THRESH_1_PB, \ 245 _ICL_DSC1_RC_BUF_THRESH_1_PC) 246 #define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 247 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \ 248 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC) 249 250 /* Icelake DSC Rate Control Range Parameter Registers */ 251 #define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240) 252 #define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4) 253 #define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40) 254 #define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4) 255 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208) 256 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4) 257 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308) 258 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4) 259 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408) 260 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4) 261 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508) 262 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4) 263 #define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 264 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \ 265 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC) 266 #define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 267 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \ 268 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC) 269 #define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 270 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \ 271 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC) 272 #define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 273 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \ 274 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC) 275 #define RC_BPG_OFFSET_SHIFT 10 276 #define RC_MAX_QP_SHIFT 5 277 #define RC_MIN_QP_SHIFT 0 278 279 #define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248) 280 #define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4) 281 #define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48) 282 #define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4) 283 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210) 284 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4) 285 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310) 286 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4) 287 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410) 288 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4) 289 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510) 290 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4) 291 #define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 292 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \ 293 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC) 294 #define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 295 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \ 296 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC) 297 #define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 298 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \ 299 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC) 300 #define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 301 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \ 302 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC) 303 304 #define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250) 305 #define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4) 306 #define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50) 307 #define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4) 308 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218) 309 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4) 310 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318) 311 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4) 312 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418) 313 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4) 314 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518) 315 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4) 316 #define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 317 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \ 318 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC) 319 #define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 320 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \ 321 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC) 322 #define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 323 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \ 324 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC) 325 #define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 326 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \ 327 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC) 328 329 #define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258) 330 #define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4) 331 #define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58) 332 #define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4) 333 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220) 334 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4) 335 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320) 336 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4) 337 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420) 338 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4) 339 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520) 340 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4) 341 #define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 342 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \ 343 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC) 344 #define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 345 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \ 346 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC) 347 #define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 348 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \ 349 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC) 350 #define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 351 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \ 352 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC) 353 354 #endif /* __INTEL_VDSC_REGS_H__ */ 355