1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rockchip,rk3576-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rockchip,rk3576-power.h> 12#include <dt-bindings/reset/rockchip,rk3576-cru.h> 13#include <dt-bindings/soc/rockchip,boot-mode.h> 14#include <dt-bindings/thermal/thermal.h> 15 16/ { 17 compatible = "rockchip,rk3576"; 18 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 i2c4 = &i2c4; 29 i2c5 = &i2c5; 30 i2c6 = &i2c6; 31 i2c7 = &i2c7; 32 i2c8 = &i2c8; 33 i2c9 = &i2c9; 34 serial0 = &uart0; 35 serial1 = &uart1; 36 serial2 = &uart2; 37 serial3 = &uart3; 38 serial4 = &uart4; 39 serial5 = &uart5; 40 serial6 = &uart6; 41 serial7 = &uart7; 42 serial8 = &uart8; 43 serial9 = &uart9; 44 serial10 = &uart10; 45 serial11 = &uart11; 46 spi0 = &spi0; 47 spi1 = &spi1; 48 spi2 = &spi2; 49 spi3 = &spi3; 50 spi4 = &spi4; 51 }; 52 53 xin32k: clock-xin32k { 54 compatible = "fixed-clock"; 55 clock-frequency = <32768>; 56 clock-output-names = "xin32k"; 57 #clock-cells = <0>; 58 }; 59 60 xin24m: clock-xin24m { 61 compatible = "fixed-clock"; 62 #clock-cells = <0>; 63 clock-frequency = <24000000>; 64 clock-output-names = "xin24m"; 65 }; 66 67 spll: clock-spll { 68 compatible = "fixed-clock"; 69 #clock-cells = <0>; 70 clock-frequency = <702000000>; 71 clock-output-names = "spll"; 72 }; 73 74 cpus { 75 #address-cells = <1>; 76 #size-cells = <0>; 77 78 cpu-map { 79 cluster0 { 80 core0 { 81 cpu = <&cpu_l0>; 82 }; 83 core1 { 84 cpu = <&cpu_l1>; 85 }; 86 core2 { 87 cpu = <&cpu_l2>; 88 }; 89 core3 { 90 cpu = <&cpu_l3>; 91 }; 92 }; 93 cluster1 { 94 core0 { 95 cpu = <&cpu_b0>; 96 }; 97 core1 { 98 cpu = <&cpu_b1>; 99 }; 100 core2 { 101 cpu = <&cpu_b2>; 102 }; 103 core3 { 104 cpu = <&cpu_b3>; 105 }; 106 }; 107 }; 108 109 cpu_l0: cpu@0 { 110 device_type = "cpu"; 111 compatible = "arm,cortex-a53"; 112 reg = <0x0>; 113 enable-method = "psci"; 114 capacity-dmips-mhz = <485>; 115 clocks = <&scmi_clk SCMI_ARMCLK_L>; 116 operating-points-v2 = <&cluster0_opp_table>; 117 dynamic-power-coefficient = <120>; 118 cpu-idle-states = <&CPU_SLEEP>; 119 #cooling-cells = <2>; 120 }; 121 122 cpu_l1: cpu@1 { 123 device_type = "cpu"; 124 compatible = "arm,cortex-a53"; 125 reg = <0x1>; 126 enable-method = "psci"; 127 capacity-dmips-mhz = <485>; 128 clocks = <&scmi_clk SCMI_ARMCLK_L>; 129 operating-points-v2 = <&cluster0_opp_table>; 130 cpu-idle-states = <&CPU_SLEEP>; 131 #cooling-cells = <2>; 132 }; 133 134 cpu_l2: cpu@2 { 135 device_type = "cpu"; 136 compatible = "arm,cortex-a53"; 137 reg = <0x2>; 138 enable-method = "psci"; 139 capacity-dmips-mhz = <485>; 140 clocks = <&scmi_clk SCMI_ARMCLK_L>; 141 operating-points-v2 = <&cluster0_opp_table>; 142 cpu-idle-states = <&CPU_SLEEP>; 143 #cooling-cells = <2>; 144 }; 145 146 cpu_l3: cpu@3 { 147 device_type = "cpu"; 148 compatible = "arm,cortex-a53"; 149 reg = <0x3>; 150 enable-method = "psci"; 151 capacity-dmips-mhz = <485>; 152 clocks = <&scmi_clk SCMI_ARMCLK_L>; 153 operating-points-v2 = <&cluster0_opp_table>; 154 cpu-idle-states = <&CPU_SLEEP>; 155 #cooling-cells = <2>; 156 }; 157 158 cpu_b0: cpu@100 { 159 device_type = "cpu"; 160 compatible = "arm,cortex-a72"; 161 reg = <0x100>; 162 enable-method = "psci"; 163 capacity-dmips-mhz = <1024>; 164 clocks = <&scmi_clk SCMI_ARMCLK_B>; 165 operating-points-v2 = <&cluster1_opp_table>; 166 dynamic-power-coefficient = <320>; 167 cpu-idle-states = <&CPU_SLEEP>; 168 #cooling-cells = <2>; 169 }; 170 171 cpu_b1: cpu@101 { 172 device_type = "cpu"; 173 compatible = "arm,cortex-a72"; 174 reg = <0x101>; 175 enable-method = "psci"; 176 capacity-dmips-mhz = <1024>; 177 clocks = <&scmi_clk SCMI_ARMCLK_B>; 178 operating-points-v2 = <&cluster1_opp_table>; 179 cpu-idle-states = <&CPU_SLEEP>; 180 #cooling-cells = <2>; 181 }; 182 183 cpu_b2: cpu@102 { 184 device_type = "cpu"; 185 compatible = "arm,cortex-a72"; 186 reg = <0x102>; 187 enable-method = "psci"; 188 capacity-dmips-mhz = <1024>; 189 clocks = <&scmi_clk SCMI_ARMCLK_B>; 190 operating-points-v2 = <&cluster1_opp_table>; 191 cpu-idle-states = <&CPU_SLEEP>; 192 #cooling-cells = <2>; 193 }; 194 195 cpu_b3: cpu@103 { 196 device_type = "cpu"; 197 compatible = "arm,cortex-a72"; 198 reg = <0x103>; 199 enable-method = "psci"; 200 capacity-dmips-mhz = <1024>; 201 clocks = <&scmi_clk SCMI_ARMCLK_B>; 202 operating-points-v2 = <&cluster1_opp_table>; 203 cpu-idle-states = <&CPU_SLEEP>; 204 #cooling-cells = <2>; 205 }; 206 207 idle-states { 208 entry-method = "psci"; 209 210 CPU_SLEEP: cpu-sleep { 211 compatible = "arm,idle-state"; 212 arm,psci-suspend-param = <0x0010000>; 213 entry-latency-us = <120>; 214 exit-latency-us = <250>; 215 min-residency-us = <900>; 216 local-timer-stop; 217 }; 218 }; 219 }; 220 221 cluster0_opp_table: opp-table-cluster0 { 222 compatible = "operating-points-v2"; 223 opp-shared; 224 225 opp-408000000 { 226 opp-hz = /bits/ 64 <408000000>; 227 opp-microvolt = <700000 700000 950000>; 228 clock-latency-ns = <40000>; 229 }; 230 231 opp-600000000 { 232 opp-hz = /bits/ 64 <600000000>; 233 opp-microvolt = <700000 700000 950000>; 234 clock-latency-ns = <40000>; 235 }; 236 237 opp-816000000 { 238 opp-hz = /bits/ 64 <816000000>; 239 opp-microvolt = <700000 700000 950000>; 240 clock-latency-ns = <40000>; 241 }; 242 243 opp-1008000000 { 244 opp-hz = /bits/ 64 <1008000000>; 245 opp-microvolt = <700000 700000 950000>; 246 clock-latency-ns = <40000>; 247 }; 248 249 opp-1200000000 { 250 opp-hz = /bits/ 64 <1200000000>; 251 opp-microvolt = <700000 700000 950000>; 252 clock-latency-ns = <40000>; 253 }; 254 255 opp-1416000000 { 256 opp-hz = /bits/ 64 <1416000000>; 257 opp-microvolt = <725000 725000 950000>; 258 clock-latency-ns = <40000>; 259 }; 260 261 opp-1608000000 { 262 opp-hz = /bits/ 64 <1608000000>; 263 opp-microvolt = <750000 750000 950000>; 264 clock-latency-ns = <40000>; 265 }; 266 267 opp-1800000000 { 268 opp-hz = /bits/ 64 <1800000000>; 269 opp-microvolt = <825000 825000 950000>; 270 clock-latency-ns = <40000>; 271 opp-suspend; 272 }; 273 274 opp-2016000000 { 275 opp-hz = /bits/ 64 <2016000000>; 276 opp-microvolt = <900000 900000 950000>; 277 clock-latency-ns = <40000>; 278 }; 279 }; 280 281 cluster1_opp_table: opp-table-cluster1 { 282 compatible = "operating-points-v2"; 283 opp-shared; 284 285 opp-408000000 { 286 opp-hz = /bits/ 64 <408000000>; 287 opp-microvolt = <700000 700000 950000>; 288 clock-latency-ns = <40000>; 289 opp-suspend; 290 }; 291 292 opp-600000000 { 293 opp-hz = /bits/ 64 <600000000>; 294 opp-microvolt = <700000 700000 950000>; 295 clock-latency-ns = <40000>; 296 }; 297 298 opp-816000000 { 299 opp-hz = /bits/ 64 <816000000>; 300 opp-microvolt = <700000 700000 950000>; 301 clock-latency-ns = <40000>; 302 }; 303 304 opp-1008000000 { 305 opp-hz = /bits/ 64 <1008000000>; 306 opp-microvolt = <700000 700000 950000>; 307 clock-latency-ns = <40000>; 308 }; 309 310 opp-1200000000 { 311 opp-hz = /bits/ 64 <1200000000>; 312 opp-microvolt = <700000 700000 950000>; 313 clock-latency-ns = <40000>; 314 }; 315 316 opp-1416000000 { 317 opp-hz = /bits/ 64 <1416000000>; 318 opp-microvolt = <712500 712500 950000>; 319 clock-latency-ns = <40000>; 320 }; 321 322 opp-1608000000 { 323 opp-hz = /bits/ 64 <1608000000>; 324 opp-microvolt = <737500 737500 950000>; 325 clock-latency-ns = <40000>; 326 }; 327 328 opp-1800000000 { 329 opp-hz = /bits/ 64 <1800000000>; 330 opp-microvolt = <800000 800000 950000>; 331 clock-latency-ns = <40000>; 332 }; 333 334 opp-2016000000 { 335 opp-hz = /bits/ 64 <2016000000>; 336 opp-microvolt = <862500 862500 950000>; 337 clock-latency-ns = <40000>; 338 }; 339 340 opp-2208000000 { 341 opp-hz = /bits/ 64 <2208000000>; 342 opp-microvolt = <925000 925000 950000>; 343 clock-latency-ns = <40000>; 344 }; 345 }; 346 347 gpu_opp_table: opp-table-gpu { 348 compatible = "operating-points-v2"; 349 350 opp-300000000 { 351 opp-hz = /bits/ 64 <300000000>; 352 opp-microvolt = <700000 700000 850000>; 353 }; 354 355 opp-400000000 { 356 opp-hz = /bits/ 64 <400000000>; 357 opp-microvolt = <700000 700000 850000>; 358 }; 359 360 opp-500000000 { 361 opp-hz = /bits/ 64 <500000000>; 362 opp-microvolt = <700000 700000 850000>; 363 }; 364 365 opp-600000000 { 366 opp-hz = /bits/ 64 <600000000>; 367 opp-microvolt = <700000 700000 850000>; 368 }; 369 370 opp-700000000 { 371 opp-hz = /bits/ 64 <700000000>; 372 opp-microvolt = <725000 725000 850000>; 373 }; 374 375 opp-800000000 { 376 opp-hz = /bits/ 64 <800000000>; 377 opp-microvolt = <775000 775000 850000>; 378 }; 379 380 opp-900000000 { 381 opp-hz = /bits/ 64 <900000000>; 382 opp-microvolt = <825000 825000 850000>; 383 }; 384 385 opp-950000000 { 386 opp-hz = /bits/ 64 <950000000>; 387 opp-microvolt = <850000 850000 850000>; 388 }; 389 }; 390 391 display_subsystem: display-subsystem { 392 compatible = "rockchip,display-subsystem"; 393 ports = <&vop_out>; 394 }; 395 396 firmware { 397 scmi: scmi { 398 compatible = "arm,scmi-smc"; 399 arm,smc-id = <0x82000010>; 400 shmem = <&scmi_shmem>; 401 #address-cells = <1>; 402 #size-cells = <0>; 403 404 scmi_clk: protocol@14 { 405 reg = <0x14>; 406 #clock-cells = <1>; 407 }; 408 }; 409 }; 410 411 hdmi_sound: hdmi-sound { 412 compatible = "simple-audio-card"; 413 simple-audio-card,name = "HDMI"; 414 simple-audio-card,format = "i2s"; 415 simple-audio-card,mclk-fs = <256>; 416 status = "disabled"; 417 418 simple-audio-card,codec { 419 sound-dai = <&hdmi>; 420 }; 421 422 simple-audio-card,cpu { 423 sound-dai = <&sai6>; 424 }; 425 }; 426 427 pinctrl: pinctrl { 428 compatible = "rockchip,rk3576-pinctrl"; 429 rockchip,grf = <&ioc_grf>; 430 #address-cells = <2>; 431 #size-cells = <2>; 432 ranges; 433 434 gpio0: gpio@27320000 { 435 compatible = "rockchip,gpio-bank"; 436 reg = <0x0 0x27320000 0x0 0x200>; 437 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; 438 gpio-controller; 439 gpio-ranges = <&pinctrl 0 0 32>; 440 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 441 interrupt-controller; 442 #gpio-cells = <2>; 443 #interrupt-cells = <2>; 444 }; 445 446 gpio1: gpio@2ae10000 { 447 compatible = "rockchip,gpio-bank"; 448 reg = <0x0 0x2ae10000 0x0 0x200>; 449 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 450 gpio-controller; 451 gpio-ranges = <&pinctrl 0 32 32>; 452 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 453 interrupt-controller; 454 #gpio-cells = <2>; 455 #interrupt-cells = <2>; 456 }; 457 458 gpio2: gpio@2ae20000 { 459 compatible = "rockchip,gpio-bank"; 460 reg = <0x0 0x2ae20000 0x0 0x200>; 461 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 462 gpio-controller; 463 gpio-ranges = <&pinctrl 0 64 32>; 464 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 465 interrupt-controller; 466 #gpio-cells = <2>; 467 #interrupt-cells = <2>; 468 }; 469 470 gpio3: gpio@2ae30000 { 471 compatible = "rockchip,gpio-bank"; 472 reg = <0x0 0x2ae30000 0x0 0x200>; 473 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 474 gpio-controller; 475 gpio-ranges = <&pinctrl 0 96 32>; 476 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 477 interrupt-controller; 478 #gpio-cells = <2>; 479 #interrupt-cells = <2>; 480 }; 481 482 gpio4: gpio@2ae40000 { 483 compatible = "rockchip,gpio-bank"; 484 reg = <0x0 0x2ae40000 0x0 0x200>; 485 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 486 gpio-controller; 487 gpio-ranges = <&pinctrl 0 128 32>; 488 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 489 interrupt-controller; 490 #gpio-cells = <2>; 491 #interrupt-cells = <2>; 492 }; 493 }; 494 495 pmu_a53: pmu-a53 { 496 compatible = "arm,cortex-a53-pmu"; 497 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 501 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, <&cpu_l3>; 502 }; 503 504 pmu_a72: pmu-a72 { 505 compatible = "arm,cortex-a72-pmu"; 506 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 510 interrupt-affinity = <&cpu_b0>, <&cpu_b1>, <&cpu_b2>, <&cpu_b3>; 511 }; 512 513 psci { 514 compatible = "arm,psci-1.0"; 515 method = "smc"; 516 }; 517 518 thermal_zones: thermal-zones { 519 /* sensor near the center of the SoC */ 520 package_thermal: package-thermal { 521 polling-delay-passive = <0>; 522 polling-delay = <0>; 523 thermal-sensors = <&tsadc 0>; 524 525 trips { 526 package_crit: package-crit { 527 temperature = <115000>; 528 hysteresis = <0>; 529 type = "critical"; 530 }; 531 }; 532 }; 533 534 /* sensor for cluster1 (big Cortex-A72 cores) */ 535 bigcore_thermal: bigcore-thermal { 536 polling-delay-passive = <100>; 537 polling-delay = <0>; 538 thermal-sensors = <&tsadc 1>; 539 540 trips { 541 bigcore_alert: bigcore-alert { 542 temperature = <85000>; 543 hysteresis = <2000>; 544 type = "passive"; 545 }; 546 547 bigcore_crit: bigcore-crit { 548 temperature = <115000>; 549 hysteresis = <0>; 550 type = "critical"; 551 }; 552 }; 553 554 cooling-maps { 555 map0 { 556 trip = <&bigcore_alert>; 557 cooling-device = 558 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 559 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 560 <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 561 <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 562 }; 563 }; 564 }; 565 566 /* sensor for cluster0 (little Cortex-A53 cores) */ 567 littlecore_thermal: littlecore-thermal { 568 polling-delay-passive = <100>; 569 polling-delay = <0>; 570 thermal-sensors = <&tsadc 2>; 571 572 trips { 573 littlecore_alert: littlecore-alert { 574 temperature = <85000>; 575 hysteresis = <2000>; 576 type = "passive"; 577 }; 578 579 littlecore_crit: littlecore-crit { 580 temperature = <115000>; 581 hysteresis = <0>; 582 type = "critical"; 583 }; 584 }; 585 586 cooling-maps { 587 map0 { 588 trip = <&littlecore_alert>; 589 cooling-device = 590 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 591 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 592 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 593 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 594 }; 595 }; 596 }; 597 598 gpu_thermal: gpu-thermal { 599 polling-delay-passive = <100>; 600 polling-delay = <0>; 601 thermal-sensors = <&tsadc 3>; 602 603 trips { 604 gpu_alert: gpu-alert { 605 temperature = <85000>; 606 hysteresis = <2000>; 607 type = "passive"; 608 }; 609 610 gpu_crit: gpu-crit { 611 temperature = <115000>; 612 hysteresis = <0>; 613 type = "critical"; 614 }; 615 }; 616 617 cooling-maps { 618 map0 { 619 trip = <&gpu_alert>; 620 cooling-device = 621 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 622 }; 623 }; 624 }; 625 626 npu_thermal: npu-thermal { 627 polling-delay-passive = <0>; 628 polling-delay = <0>; 629 thermal-sensors = <&tsadc 4>; 630 631 trips { 632 npu_crit: npu-crit { 633 temperature = <115000>; 634 hysteresis = <0>; 635 type = "critical"; 636 }; 637 }; 638 }; 639 640 ddr_thermal: ddr-thermal { 641 polling-delay-passive = <0>; 642 polling-delay = <0>; 643 thermal-sensors = <&tsadc 5>; 644 645 trips { 646 ddr_crit: ddr-crit { 647 temperature = <115000>; 648 hysteresis = <0>; 649 type = "critical"; 650 }; 651 }; 652 }; 653 }; 654 655 timer { 656 compatible = "arm,armv8-timer"; 657 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 658 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 659 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 660 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 661 }; 662 663 soc { 664 compatible = "simple-bus"; 665 #address-cells = <2>; 666 #size-cells = <2>; 667 ranges; 668 669 pcie0: pcie@22000000 { 670 compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie"; 671 reg = <0x0 0x22000000 0x0 0x00400000>, 672 <0x0 0x2a200000 0x0 0x00010000>, 673 <0x0 0x20000000 0x0 0x00100000>; 674 reg-names = "dbi", "apb", "config"; 675 bus-range = <0x0 0xf>; 676 clocks = <&cru ACLK_PCIE0_MST>, <&cru ACLK_PCIE0_SLV>, 677 <&cru ACLK_PCIE0_DBI>, <&cru PCLK_PCIE0>, 678 <&cru CLK_PCIE0_AUX>; 679 clock-names = "aclk_mst", "aclk_slv", 680 "aclk_dbi", "pclk", 681 "aux"; 682 device_type = "pci"; 683 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 685 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>; 689 interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi"; 690 #interrupt-cells = <1>; 691 interrupt-map-mask = <0 0 0 7>; 692 interrupt-map = <0 0 0 1 &pcie0_intc 0>, 693 <0 0 0 2 &pcie0_intc 1>, 694 <0 0 0 3 &pcie0_intc 2>, 695 <0 0 0 4 &pcie0_intc 3>; 696 linux,pci-domain = <0>; 697 max-link-speed = <2>; 698 num-ib-windows = <8>; 699 num-viewport = <8>; 700 num-ob-windows = <2>; 701 num-lanes = <1>; 702 phys = <&combphy0_ps PHY_TYPE_PCIE>; 703 phy-names = "pcie-phy"; 704 power-domains = <&power RK3576_PD_PHP>; 705 ranges = <0x01000000 0x0 0x20100000 0x0 0x20100000 0x0 0x00100000 706 0x02000000 0x0 0x20200000 0x0 0x20200000 0x0 0x00e00000 707 0x03000000 0x9 0x00000000 0x9 0x00000000 0x0 0x80000000>; 708 resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; 709 reset-names = "pwr", "pipe"; 710 #address-cells = <3>; 711 #size-cells = <2>; 712 status = "disabled"; 713 714 pcie0_intc: legacy-interrupt-controller { 715 interrupt-controller; 716 #address-cells = <0>; 717 #interrupt-cells = <1>; 718 interrupt-parent = <&gic>; 719 interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>; 720 }; 721 }; 722 723 pcie1: pcie@22400000 { 724 compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie"; 725 reg = <0x0 0x22400000 0x0 0x00400000>, 726 <0x0 0x2a210000 0x0 0x00010000>, 727 <0x0 0x21000000 0x0 0x00100000>; 728 reg-names = "dbi", "apb", "config"; 729 bus-range = <0x20 0x2f>; 730 clocks = <&cru ACLK_PCIE1_MST>, <&cru ACLK_PCIE1_SLV>, 731 <&cru ACLK_PCIE1_DBI>, <&cru PCLK_PCIE1>, 732 <&cru CLK_PCIE1_AUX>; 733 clock-names = "aclk_mst", "aclk_slv", 734 "aclk_dbi", "pclk", 735 "aux"; 736 device_type = "pci"; 737 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 742 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 743 interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi"; 744 #interrupt-cells = <1>; 745 interrupt-map-mask = <0 0 0 7>; 746 interrupt-map = <0 0 0 1 &pcie1_intc 0>, 747 <0 0 0 2 &pcie1_intc 1>, 748 <0 0 0 3 &pcie1_intc 2>, 749 <0 0 0 4 &pcie1_intc 3>; 750 linux,pci-domain = <1>; 751 max-link-speed = <2>; 752 num-ib-windows = <8>; 753 num-viewport = <8>; 754 num-ob-windows = <2>; 755 num-lanes = <1>; 756 phys = <&combphy1_psu PHY_TYPE_PCIE>; 757 phy-names = "pcie-phy"; 758 power-domains = <&power RK3576_PD_SUBPHP>; 759 ranges = <0x01000000 0x0 0x21100000 0x0 0x21100000 0x0 0x00100000 760 0x02000000 0x0 0x21200000 0x0 0x21200000 0x0 0x00e00000 761 0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x80000000>; 762 resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; 763 reset-names = "pwr", "pipe"; 764 #address-cells = <3>; 765 #size-cells = <2>; 766 status = "disabled"; 767 768 pcie1_intc: legacy-interrupt-controller { 769 interrupt-controller; 770 #address-cells = <0>; 771 #interrupt-cells = <1>; 772 interrupt-parent = <&gic>; 773 interrupts = <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>; 774 }; 775 }; 776 777 usb_drd0_dwc3: usb@23000000 { 778 compatible = "rockchip,rk3576-dwc3", "snps,dwc3"; 779 reg = <0x0 0x23000000 0x0 0x400000>; 780 clocks = <&cru CLK_REF_USB3OTG0>, 781 <&cru CLK_SUSPEND_USB3OTG0>, 782 <&cru ACLK_USB3OTG0>; 783 clock-names = "ref_clk", "suspend_clk", "bus_clk"; 784 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 785 power-domains = <&power RK3576_PD_USB>; 786 resets = <&cru SRST_A_USB3OTG0>; 787 dr_mode = "otg"; 788 phys = <&u2phy0_otg>, <&usbdp_phy PHY_TYPE_USB3>; 789 phy-names = "usb2-phy", "usb3-phy"; 790 phy_type = "utmi_wide"; 791 snps,dis_enblslpm_quirk; 792 snps,dis-u1-entry-quirk; 793 snps,dis-u2-entry-quirk; 794 snps,dis-u2-freeclk-exists-quirk; 795 snps,dis-del-phy-power-chg-quirk; 796 snps,dis-tx-ipgap-linecheck-quirk; 797 snps,parkmode-disable-hs-quirk; 798 snps,parkmode-disable-ss-quirk; 799 status = "disabled"; 800 }; 801 802 usb_drd1_dwc3: usb@23400000 { 803 compatible = "rockchip,rk3576-dwc3", "snps,dwc3"; 804 reg = <0x0 0x23400000 0x0 0x400000>; 805 clocks = <&cru CLK_REF_USB3OTG1>, 806 <&cru CLK_SUSPEND_USB3OTG1>, 807 <&cru ACLK_USB3OTG1>; 808 clock-names = "ref_clk", "suspend_clk", "bus_clk"; 809 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>; 810 power-domains = <&power RK3576_PD_PHP>; 811 resets = <&cru SRST_A_USB3OTG1>; 812 dr_mode = "otg"; 813 phys = <&u2phy1_otg>, <&combphy1_psu PHY_TYPE_USB3>; 814 phy-names = "usb2-phy", "usb3-phy"; 815 phy_type = "utmi_wide"; 816 snps,dis_enblslpm_quirk; 817 snps,dis-u1-entry-quirk; 818 snps,dis-u2-entry-quirk; 819 snps,dis-u2-freeclk-exists-quirk; 820 snps,dis-del-phy-power-chg-quirk; 821 snps,dis-tx-ipgap-linecheck-quirk; 822 snps,dis_rxdet_inp3_quirk; 823 snps,parkmode-disable-hs-quirk; 824 snps,parkmode-disable-ss-quirk; 825 dma-coherent; 826 status = "disabled"; 827 }; 828 829 sys_grf: syscon@2600a000 { 830 compatible = "rockchip,rk3576-sys-grf", "syscon"; 831 reg = <0x0 0x2600a000 0x0 0x2000>; 832 }; 833 834 bigcore_grf: syscon@2600c000 { 835 compatible = "rockchip,rk3576-bigcore-grf", "syscon"; 836 reg = <0x0 0x2600c000 0x0 0x2000>; 837 }; 838 839 litcore_grf: syscon@2600e000 { 840 compatible = "rockchip,rk3576-litcore-grf", "syscon"; 841 reg = <0x0 0x2600e000 0x0 0x2000>; 842 }; 843 844 cci_grf: syscon@26010000 { 845 compatible = "rockchip,rk3576-cci-grf", "syscon"; 846 reg = <0x0 0x26010000 0x0 0x2000>; 847 }; 848 849 gpu_grf: syscon@26016000 { 850 compatible = "rockchip,rk3576-gpu-grf", "syscon"; 851 reg = <0x0 0x26016000 0x0 0x2000>; 852 }; 853 854 npu_grf: syscon@26018000 { 855 compatible = "rockchip,rk3576-npu-grf", "syscon"; 856 reg = <0x0 0x26018000 0x0 0x2000>; 857 }; 858 859 vo0_grf: syscon@2601a000 { 860 compatible = "rockchip,rk3576-vo0-grf", "syscon"; 861 reg = <0x0 0x2601a000 0x0 0x2000>; 862 }; 863 864 usb_grf: syscon@2601e000 { 865 compatible = "rockchip,rk3576-usb-grf", "syscon"; 866 reg = <0x0 0x2601e000 0x0 0x1000>; 867 }; 868 869 php_grf: syscon@26020000 { 870 compatible = "rockchip,rk3576-php-grf", "syscon"; 871 reg = <0x0 0x26020000 0x0 0x2000>; 872 }; 873 874 pmu0_grf: syscon@26024000 { 875 compatible = "rockchip,rk3576-pmu0-grf", "syscon", "simple-mfd"; 876 reg = <0x0 0x26024000 0x0 0x1000>; 877 }; 878 879 pmu1_grf: syscon@26026000 { 880 compatible = "rockchip,rk3576-pmu1-grf", "syscon"; 881 reg = <0x0 0x26026000 0x0 0x1000>; 882 }; 883 884 pipe_phy0_grf: syscon@26028000 { 885 compatible = "rockchip,rk3576-pipe-phy-grf", "syscon"; 886 reg = <0x0 0x26028000 0x0 0x2000>; 887 }; 888 889 pipe_phy1_grf: syscon@2602a000 { 890 compatible = "rockchip,rk3576-pipe-phy-grf", "syscon"; 891 reg = <0x0 0x2602a000 0x0 0x2000>; 892 }; 893 894 usbdpphy_grf: syscon@2602c000 { 895 compatible = "rockchip,rk3576-usbdpphy-grf", "syscon"; 896 reg = <0x0 0x2602c000 0x0 0x2000>; 897 }; 898 899 usb2phy_grf: syscon@2602e000 { 900 compatible = "rockchip,rk3576-usb2phy-grf", "syscon", "simple-mfd"; 901 reg = <0x0 0x2602e000 0x0 0x4000>; 902 #address-cells = <1>; 903 #size-cells = <1>; 904 905 u2phy0: usb2-phy@0 { 906 compatible = "rockchip,rk3576-usb2phy"; 907 reg = <0x0 0x10>; 908 resets = <&cru SRST_OTGPHY_0>, <&cru SRST_P_USBPHY_GRF_0>; 909 reset-names = "phy", "apb"; 910 clocks = <&cru CLK_PHY_REF_SRC>, 911 <&cru ACLK_MMU2>, 912 <&cru ACLK_SLV_MMU2>; 913 clock-names = "phyclk", "aclk", "aclk_slv"; 914 clock-output-names = "usb480m_phy0"; 915 #clock-cells = <0>; 916 status = "disabled"; 917 918 u2phy0_otg: otg-port { 919 #phy-cells = <0>; 920 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 921 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 922 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 923 interrupt-names = "otg-bvalid", "otg-id", "linestate"; 924 status = "disabled"; 925 }; 926 }; 927 928 u2phy1: usb2-phy@2000 { 929 compatible = "rockchip,rk3576-usb2phy"; 930 reg = <0x2000 0x10>; 931 resets = <&cru SRST_OTGPHY_1>, <&cru SRST_P_USBPHY_GRF_1>; 932 reset-names = "phy", "apb"; 933 clocks = <&cru CLK_PHY_REF_SRC>, 934 <&cru ACLK_MMU1>, 935 <&cru ACLK_SLV_MMU1>; 936 clock-names = "phyclk", "aclk", "aclk_slv"; 937 clock-output-names = "usb480m_phy1"; 938 #clock-cells = <0>; 939 status = "disabled"; 940 941 u2phy1_otg: otg-port { 942 #phy-cells = <0>; 943 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 946 interrupt-names = "otg-bvalid", "otg-id", "linestate"; 947 status = "disabled"; 948 }; 949 }; 950 }; 951 952 hdptxphy_grf: syscon@26032000 { 953 compatible = "rockchip,rk3576-hdptxphy-grf", "syscon"; 954 reg = <0x0 0x26032000 0x0 0x100>; 955 }; 956 957 mipidcphy_grf: syscon@26034000 { 958 compatible = "rockchip,rk3576-dcphy-grf", "syscon"; 959 reg = <0x0 0x26034000 0x0 0x2000>; 960 clocks = <&cru PCLK_PMUPHY_ROOT>; 961 }; 962 963 vo1_grf: syscon@26036000 { 964 compatible = "rockchip,rk3576-vo1-grf", "syscon"; 965 reg = <0x0 0x26036000 0x0 0x100>; 966 clocks = <&cru PCLK_VO1_ROOT>; 967 }; 968 969 sdgmac_grf: syscon@26038000 { 970 compatible = "rockchip,rk3576-sdgmac-grf", "syscon"; 971 reg = <0x0 0x26038000 0x0 0x1000>; 972 }; 973 974 ioc_grf: syscon@26040000 { 975 compatible = "rockchip,rk3576-ioc-grf", "syscon", "simple-mfd"; 976 reg = <0x0 0x26040000 0x0 0xc000>; 977 }; 978 979 cru: clock-controller@27200000 { 980 compatible = "rockchip,rk3576-cru"; 981 reg = <0x0 0x27200000 0x0 0x50000>; 982 #clock-cells = <1>; 983 #reset-cells = <1>; 984 985 assigned-clocks = 986 <&cru CLK_AUDIO_FRAC_1_SRC>, 987 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 988 <&cru PLL_AUPLL>, <&cru CLK_UART_FRAC_0>, 989 <&cru CLK_UART_FRAC_1>, <&cru CLK_UART_FRAC_2>, 990 <&cru CLK_AUDIO_FRAC_0>, <&cru CLK_AUDIO_FRAC_1>, 991 <&cru CLK_CPLL_DIV2>, <&cru CLK_CPLL_DIV4>, 992 <&cru CLK_CPLL_DIV10>, <&cru FCLK_DDR_CM0_CORE>, 993 <&cru ACLK_PHP_ROOT>; 994 assigned-clock-parents = <&cru PLL_AUPLL>; 995 assigned-clock-rates = 996 <0>, 997 <1188000000>, <1000000000>, 998 <786432000>, <18432000>, 999 <96000000>, <128000000>, 1000 <45158400>, <49152000>, 1001 <500000000>, <250000000>, 1002 <100000000>, <500000000>, 1003 <250000000>; 1004 }; 1005 1006 i2c0: i2c@27300000 { 1007 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 1008 reg = <0x0 0x27300000 0x0 0x1000>; 1009 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 1010 clock-names = "i2c", "pclk"; 1011 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1012 pinctrl-names = "default"; 1013 pinctrl-0 = <&i2c0m0_xfer>; 1014 #address-cells = <1>; 1015 #size-cells = <0>; 1016 status = "disabled"; 1017 }; 1018 1019 uart1: serial@27310000 { 1020 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 1021 reg = <0x0 0x27310000 0x0 0x100>; 1022 reg-shift = <2>; 1023 reg-io-width = <4>; 1024 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 1025 clock-names = "baudclk", "apb_pclk"; 1026 dmas = <&dmac0 8>, <&dmac0 9>; 1027 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1028 pinctrl-names = "default"; 1029 pinctrl-0 = <&uart1m0_xfer>; 1030 status = "disabled"; 1031 }; 1032 1033 pmu: power-management@27380000 { 1034 compatible = "rockchip,rk3576-pmu", "syscon", "simple-mfd"; 1035 reg = <0x0 0x27380000 0x0 0x800>; 1036 1037 power: power-controller { 1038 compatible = "rockchip,rk3576-power-controller"; 1039 #power-domain-cells = <1>; 1040 #address-cells = <1>; 1041 #size-cells = <0>; 1042 1043 power-domain@RK3576_PD_NPU { 1044 reg = <RK3576_PD_NPU>; 1045 #power-domain-cells = <1>; 1046 #address-cells = <1>; 1047 #size-cells = <0>; 1048 1049 power-domain@RK3576_PD_NPUTOP { 1050 reg = <RK3576_PD_NPUTOP>; 1051 clocks = <&cru ACLK_RKNN0>, 1052 <&cru ACLK_RKNN1>, 1053 <&cru ACLK_RKNN_CBUF>, 1054 <&cru CLK_RKNN_DSU0>, 1055 <&cru HCLK_RKNN_CBUF>, 1056 <&cru HCLK_RKNN_ROOT>, 1057 <&cru HCLK_NPU_CM0_ROOT>, 1058 <&cru PCLK_NPUTOP_ROOT>; 1059 pm_qos = <&qos_npu_mcu>, 1060 <&qos_npu_nsp0>, 1061 <&qos_npu_nsp1>, 1062 <&qos_npu_m0ro>, 1063 <&qos_npu_m1ro>; 1064 #power-domain-cells = <1>; 1065 #address-cells = <1>; 1066 #size-cells = <0>; 1067 1068 power-domain@RK3576_PD_NPU0 { 1069 reg = <RK3576_PD_NPU0>; 1070 clocks = <&cru HCLK_RKNN_ROOT>, 1071 <&cru ACLK_RKNN0>; 1072 pm_qos = <&qos_npu_m0>; 1073 #power-domain-cells = <0>; 1074 }; 1075 power-domain@RK3576_PD_NPU1 { 1076 reg = <RK3576_PD_NPU1>; 1077 clocks = <&cru HCLK_RKNN_ROOT>, 1078 <&cru ACLK_RKNN1>; 1079 pm_qos = <&qos_npu_m1>; 1080 #power-domain-cells = <0>; 1081 }; 1082 }; 1083 }; 1084 1085 power-domain@RK3576_PD_GPU { 1086 reg = <RK3576_PD_GPU>; 1087 clocks = <&cru CLK_GPU>, <&cru PCLK_GPU_ROOT>; 1088 pm_qos = <&qos_gpu>; 1089 #power-domain-cells = <0>; 1090 }; 1091 1092 power-domain@RK3576_PD_NVM { 1093 reg = <RK3576_PD_NVM>; 1094 clocks = <&cru ACLK_EMMC>, <&cru HCLK_EMMC>; 1095 pm_qos = <&qos_emmc>, 1096 <&qos_fspi0>; 1097 #power-domain-cells = <1>; 1098 #address-cells = <1>; 1099 #size-cells = <0>; 1100 1101 power-domain@RK3576_PD_SDGMAC { 1102 reg = <RK3576_PD_SDGMAC>; 1103 clocks = <&cru ACLK_HSGPIO>, 1104 <&cru ACLK_GMAC0>, 1105 <&cru ACLK_GMAC1>, 1106 <&cru CCLK_SRC_SDIO>, 1107 <&cru CCLK_SRC_SDMMC0>, 1108 <&cru HCLK_HSGPIO>, 1109 <&cru HCLK_SDIO>, 1110 <&cru HCLK_SDMMC0>, 1111 <&cru PCLK_SDGMAC_ROOT>; 1112 pm_qos = <&qos_fspi1>, 1113 <&qos_gmac0>, 1114 <&qos_gmac1>, 1115 <&qos_sdio>, 1116 <&qos_sdmmc>, 1117 <&qos_flexbus>; 1118 #power-domain-cells = <0>; 1119 }; 1120 }; 1121 1122 power-domain@RK3576_PD_PHP { 1123 reg = <RK3576_PD_PHP>; 1124 clocks = <&cru ACLK_PHP_ROOT>, 1125 <&cru PCLK_PHP_ROOT>, 1126 <&cru ACLK_MMU0>, 1127 <&cru ACLK_MMU1>; 1128 pm_qos = <&qos_mmu0>, 1129 <&qos_mmu1>; 1130 #power-domain-cells = <1>; 1131 #address-cells = <1>; 1132 #size-cells = <0>; 1133 1134 power-domain@RK3576_PD_SUBPHP { 1135 reg = <RK3576_PD_SUBPHP>; 1136 #power-domain-cells = <0>; 1137 }; 1138 }; 1139 1140 power-domain@RK3576_PD_AUDIO { 1141 reg = <RK3576_PD_AUDIO>; 1142 #power-domain-cells = <0>; 1143 }; 1144 1145 power-domain@RK3576_PD_VEPU1 { 1146 reg = <RK3576_PD_VEPU1>; 1147 clocks = <&cru ACLK_VEPU1>, 1148 <&cru HCLK_VEPU1>; 1149 pm_qos = <&qos_vepu1>; 1150 #power-domain-cells = <0>; 1151 }; 1152 1153 power-domain@RK3576_PD_VPU { 1154 reg = <RK3576_PD_VPU>; 1155 clocks = <&cru ACLK_EBC>, 1156 <&cru HCLK_EBC>, 1157 <&cru ACLK_JPEG>, 1158 <&cru HCLK_JPEG>, 1159 <&cru ACLK_RGA2E_0>, 1160 <&cru HCLK_RGA2E_0>, 1161 <&cru ACLK_RGA2E_1>, 1162 <&cru HCLK_RGA2E_1>, 1163 <&cru ACLK_VDPP>, 1164 <&cru HCLK_VDPP>; 1165 pm_qos = <&qos_ebc>, 1166 <&qos_jpeg>, 1167 <&qos_rga0>, 1168 <&qos_rga1>, 1169 <&qos_vdpp>; 1170 #power-domain-cells = <0>; 1171 }; 1172 1173 power-domain@RK3576_PD_VDEC { 1174 reg = <RK3576_PD_VDEC>; 1175 clocks = <&cru ACLK_RKVDEC_ROOT>, 1176 <&cru HCLK_RKVDEC>; 1177 pm_qos = <&qos_rkvdec>; 1178 #power-domain-cells = <0>; 1179 }; 1180 1181 power-domain@RK3576_PD_VI { 1182 reg = <RK3576_PD_VI>; 1183 clocks = <&cru ACLK_VICAP>, 1184 <&cru HCLK_VICAP>, 1185 <&cru DCLK_VICAP>, 1186 <&cru ACLK_VI_ROOT>, 1187 <&cru HCLK_VI_ROOT>, 1188 <&cru PCLK_VI_ROOT>, 1189 <&cru CLK_ISP_CORE>, 1190 <&cru ACLK_ISP>, 1191 <&cru HCLK_ISP>, 1192 <&cru CLK_CORE_VPSS>, 1193 <&cru ACLK_VPSS>, 1194 <&cru HCLK_VPSS>; 1195 pm_qos = <&qos_isp_mro>, 1196 <&qos_isp_mwo>, 1197 <&qos_vicap_m0>, 1198 <&qos_vpss_mro>, 1199 <&qos_vpss_mwo>; 1200 #power-domain-cells = <1>; 1201 #address-cells = <1>; 1202 #size-cells = <0>; 1203 1204 power-domain@RK3576_PD_VEPU0 { 1205 reg = <RK3576_PD_VEPU0>; 1206 clocks = <&cru ACLK_VEPU0>, 1207 <&cru HCLK_VEPU0>; 1208 pm_qos = <&qos_vepu0>; 1209 #power-domain-cells = <0>; 1210 }; 1211 }; 1212 1213 power-domain@RK3576_PD_VOP { 1214 reg = <RK3576_PD_VOP>; 1215 clocks = <&cru ACLK_VOP>, 1216 <&cru HCLK_VOP>, 1217 <&cru HCLK_VOP_ROOT>, 1218 <&cru PCLK_VOP_ROOT>; 1219 pm_qos = <&qos_vop_m0>, 1220 <&qos_vop_m1ro>; 1221 #power-domain-cells = <1>; 1222 #address-cells = <1>; 1223 #size-cells = <0>; 1224 1225 power-domain@RK3576_PD_USB { 1226 reg = <RK3576_PD_USB>; 1227 clocks = <&cru PCLK_PHP_ROOT>, 1228 <&cru ACLK_USB_ROOT>, 1229 <&cru ACLK_MMU2>, 1230 <&cru ACLK_SLV_MMU2>, 1231 <&cru ACLK_UFS_SYS>; 1232 pm_qos = <&qos_mmu2>, 1233 <&qos_ufshc>; 1234 #power-domain-cells = <0>; 1235 }; 1236 1237 power-domain@RK3576_PD_VO0 { 1238 reg = <RK3576_PD_VO0>; 1239 clocks = <&cru ACLK_HDCP0>, 1240 <&cru HCLK_HDCP0>, 1241 <&cru ACLK_VO0_ROOT>, 1242 <&cru PCLK_VO0_ROOT>, 1243 <&cru HCLK_VOP_ROOT>; 1244 pm_qos = <&qos_hdcp0>; 1245 #power-domain-cells = <0>; 1246 }; 1247 1248 power-domain@RK3576_PD_VO1 { 1249 reg = <RK3576_PD_VO1>; 1250 clocks = <&cru ACLK_HDCP1>, 1251 <&cru HCLK_HDCP1>, 1252 <&cru ACLK_VO1_ROOT>, 1253 <&cru PCLK_VO1_ROOT>, 1254 <&cru HCLK_VOP_ROOT>; 1255 pm_qos = <&qos_hdcp1>; 1256 #power-domain-cells = <0>; 1257 }; 1258 }; 1259 }; 1260 }; 1261 1262 gpu: gpu@27800000 { 1263 compatible = "rockchip,rk3576-mali", "arm,mali-bifrost"; 1264 reg = <0x0 0x27800000 0x0 0x200000>; 1265 assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; 1266 assigned-clock-rates = <198000000>; 1267 clocks = <&cru CLK_GPU>; 1268 clock-names = "core"; 1269 dynamic-power-coefficient = <1625>; 1270 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 1271 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 1272 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 1273 interrupt-names = "job", "mmu", "gpu"; 1274 operating-points-v2 = <&gpu_opp_table>; 1275 power-domains = <&power RK3576_PD_GPU>; 1276 #cooling-cells = <2>; 1277 status = "disabled"; 1278 }; 1279 1280 vop: vop@27d00000 { 1281 compatible = "rockchip,rk3576-vop"; 1282 reg = <0x0 0x27d00000 0x0 0x3000>, <0x0 0x27d05000 0x0 0x1000>; 1283 reg-names = "vop", "gamma-lut"; 1284 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1285 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, 1286 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 1287 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; 1288 interrupt-names = "sys", 1289 "vp0", 1290 "vp1", 1291 "vp2"; 1292 clocks = <&cru ACLK_VOP>, 1293 <&cru HCLK_VOP>, 1294 <&cru DCLK_VP0>, 1295 <&cru DCLK_VP1>, 1296 <&cru DCLK_VP2>, 1297 <&hdptxphy>; 1298 clock-names = "aclk", 1299 "hclk", 1300 "dclk_vp0", 1301 "dclk_vp1", 1302 "dclk_vp2", 1303 "pll_hdmiphy0"; 1304 iommus = <&vop_mmu>; 1305 power-domains = <&power RK3576_PD_VOP>; 1306 rockchip,grf = <&sys_grf>; 1307 rockchip,pmu = <&pmu>; 1308 status = "disabled"; 1309 1310 vop_out: ports { 1311 #address-cells = <1>; 1312 #size-cells = <0>; 1313 1314 vp0: port@0 { 1315 #address-cells = <1>; 1316 #size-cells = <0>; 1317 reg = <0>; 1318 }; 1319 1320 vp1: port@1 { 1321 #address-cells = <1>; 1322 #size-cells = <0>; 1323 reg = <1>; 1324 }; 1325 1326 vp2: port@2 { 1327 #address-cells = <1>; 1328 #size-cells = <0>; 1329 reg = <2>; 1330 }; 1331 }; 1332 }; 1333 1334 vop_mmu: iommu@27d07e00 { 1335 compatible = "rockchip,rk3576-iommu", "rockchip,rk3568-iommu"; 1336 reg = <0x0 0x27d07e00 0x0 0x100>, <0x0 0x27d07f00 0x0 0x100>; 1337 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; 1338 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 1339 clock-names = "aclk", "iface"; 1340 #iommu-cells = <0>; 1341 power-domains = <&power RK3576_PD_VOP>; 1342 status = "disabled"; 1343 }; 1344 1345 sai5: sai@27d40000 { 1346 compatible = "rockchip,rk3576-sai"; 1347 reg = <0x0 0x27d40000 0x0 0x1000>; 1348 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 1349 clocks = <&cru MCLK_SAI5_8CH>, <&cru HCLK_SAI5_8CH>; 1350 clock-names = "mclk", "hclk"; 1351 dmas = <&dmac2 3>; 1352 dma-names = "rx"; 1353 power-domains = <&power RK3576_PD_VO0>; 1354 resets = <&cru SRST_M_SAI5_8CH>, <&cru SRST_H_SAI5_8CH>; 1355 reset-names = "m", "h"; 1356 rockchip,sai-rx-route = <0 1 2 3>; 1357 #sound-dai-cells = <0>; 1358 sound-name-prefix = "SAI5"; 1359 status = "disabled"; 1360 }; 1361 1362 sai6: sai@27d50000 { 1363 compatible = "rockchip,rk3576-sai"; 1364 reg = <0x0 0x27d50000 0x0 0x1000>; 1365 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 1366 clocks = <&cru MCLK_SAI6_8CH>, <&cru HCLK_SAI6_8CH>; 1367 clock-names = "mclk", "hclk"; 1368 dmas = <&dmac2 4>, <&dmac2 5>; 1369 dma-names = "tx", "rx"; 1370 power-domains = <&power RK3576_PD_VO0>; 1371 resets = <&cru SRST_M_SAI6_8CH>, <&cru SRST_H_SAI6_8CH>; 1372 reset-names = "m", "h"; 1373 rockchip,sai-rx-route = <0 1 2 3>; 1374 rockchip,sai-tx-route = <0 1 2 3>; 1375 #sound-dai-cells = <0>; 1376 sound-name-prefix = "SAI6"; 1377 status = "disabled"; 1378 }; 1379 1380 dsi: dsi@27d80000 { 1381 compatible = "rockchip,rk3576-mipi-dsi2"; 1382 reg = <0x0 0x27d80000 0x0 0x10000>; 1383 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 1384 clocks = <&cru PCLK_DSIHOST0>, <&cru CLK_DSIHOST0>; 1385 clock-names = "pclk", "sys"; 1386 power-domains = <&power RK3576_PD_VO0>; 1387 resets = <&cru SRST_P_DSIHOST0>; 1388 reset-names = "apb"; 1389 phys = <&mipidcphy PHY_TYPE_DPHY>; 1390 phy-names = "dcphy"; 1391 rockchip,grf = <&vo0_grf>; 1392 status = "disabled"; 1393 1394 ports { 1395 #address-cells = <1>; 1396 #size-cells = <0>; 1397 1398 dsi_in: port@0 { 1399 reg = <0>; 1400 }; 1401 1402 dsi_out: port@1 { 1403 reg = <1>; 1404 }; 1405 }; 1406 }; 1407 1408 hdmi: hdmi@27da0000 { 1409 compatible = "rockchip,rk3576-dw-hdmi-qp"; 1410 reg = <0x0 0x27da0000 0x0 0x20000>; 1411 clocks = <&cru PCLK_HDMITX0>, 1412 <&cru CLK_HDMITX0_EARC>, 1413 <&cru CLK_HDMITX0_REF>, 1414 <&cru MCLK_SAI6_8CH>, 1415 <&cru CLK_HDMITXHDP>, 1416 <&cru HCLK_VO0_ROOT>; 1417 clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; 1418 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1419 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1420 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1421 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1422 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>; 1423 interrupt-names = "avp", "cec", "earc", "main", "hpd"; 1424 phys = <&hdptxphy>; 1425 pinctrl-names = "default"; 1426 pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda>; 1427 power-domains = <&power RK3576_PD_VO0>; 1428 resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMITXHDP>; 1429 reset-names = "ref", "hdp"; 1430 rockchip,grf = <&ioc_grf>; 1431 rockchip,vo-grf = <&vo0_grf>; 1432 #sound-dai-cells = <0>; 1433 status = "disabled"; 1434 1435 ports { 1436 #address-cells = <1>; 1437 #size-cells = <0>; 1438 1439 hdmi_in: port@0 { 1440 reg = <0>; 1441 }; 1442 1443 hdmi_out: port@1 { 1444 reg = <1>; 1445 }; 1446 }; 1447 }; 1448 1449 sai7: sai@27ed0000 { 1450 compatible = "rockchip,rk3576-sai"; 1451 reg = <0x0 0x27ed0000 0x0 0x1000>; 1452 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 1453 clocks = <&cru MCLK_SAI7_8CH>, <&cru HCLK_SAI7_8CH>; 1454 clock-names = "mclk", "hclk"; 1455 dmas = <&dmac2 19>; 1456 dma-names = "tx"; 1457 power-domains = <&power RK3576_PD_VO1>; 1458 resets = <&cru SRST_M_SAI7_8CH>, <&cru SRST_H_SAI7_8CH>; 1459 reset-names = "m", "h"; 1460 rockchip,sai-tx-route = <0 1 2 3>; 1461 #sound-dai-cells = <0>; 1462 sound-name-prefix = "SAI7"; 1463 status = "disabled"; 1464 }; 1465 1466 sai8: sai@27ee0000 { 1467 compatible = "rockchip,rk3576-sai"; 1468 reg = <0x0 0x27ee0000 0x0 0x1000>; 1469 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1470 clocks = <&cru MCLK_SAI8_8CH>, <&cru HCLK_SAI8_8CH>; 1471 clock-names = "mclk", "hclk"; 1472 dmas = <&dmac1 7>; 1473 dma-names = "tx"; 1474 power-domains = <&power RK3576_PD_VO1>; 1475 resets = <&cru SRST_M_SAI8_8CH>, <&cru SRST_H_SAI8_8CH>; 1476 reset-names = "m", "h"; 1477 rockchip,sai-tx-route = <0 1 2 3>; 1478 #sound-dai-cells = <0>; 1479 sound-name-prefix = "SAI8"; 1480 status = "disabled"; 1481 }; 1482 1483 sai9: sai@27ef0000 { 1484 compatible = "rockchip,rk3576-sai"; 1485 reg = <0x0 0x27ef0000 0x0 0x1000>; 1486 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1487 clocks = <&cru MCLK_SAI9_8CH>, <&cru HCLK_SAI9_8CH>; 1488 clock-names = "mclk", "hclk"; 1489 dmas = <&dmac0 26>; 1490 dma-names = "tx"; 1491 power-domains = <&power RK3576_PD_VO1>; 1492 resets = <&cru SRST_M_SAI9_8CH>, <&cru SRST_H_SAI9_8CH>; 1493 reset-names = "m", "h"; 1494 rockchip,sai-tx-route = <0 1 2 3>; 1495 #sound-dai-cells = <0>; 1496 sound-name-prefix = "SAI9"; 1497 status = "disabled"; 1498 }; 1499 1500 qos_hdcp1: qos@27f02000 { 1501 compatible = "rockchip,rk3576-qos", "syscon"; 1502 reg = <0x0 0x27f02000 0x0 0x20>; 1503 }; 1504 1505 qos_fspi1: qos@27f04000 { 1506 compatible = "rockchip,rk3576-qos", "syscon"; 1507 reg = <0x0 0x27f04000 0x0 0x20>; 1508 }; 1509 1510 qos_gmac0: qos@27f04080 { 1511 compatible = "rockchip,rk3576-qos", "syscon"; 1512 reg = <0x0 0x27f04080 0x0 0x20>; 1513 }; 1514 1515 qos_gmac1: qos@27f04100 { 1516 compatible = "rockchip,rk3576-qos", "syscon"; 1517 reg = <0x0 0x27f04100 0x0 0x20>; 1518 }; 1519 1520 qos_sdio: qos@27f04180 { 1521 compatible = "rockchip,rk3576-qos", "syscon"; 1522 reg = <0x0 0x27f04180 0x0 0x20>; 1523 }; 1524 1525 qos_sdmmc: qos@27f04200 { 1526 compatible = "rockchip,rk3576-qos", "syscon"; 1527 reg = <0x0 0x27f04200 0x0 0x20>; 1528 }; 1529 1530 qos_flexbus: qos@27f04280 { 1531 compatible = "rockchip,rk3576-qos", "syscon"; 1532 reg = <0x0 0x27f04280 0x0 0x20>; 1533 }; 1534 1535 qos_gpu: qos@27f05000 { 1536 compatible = "rockchip,rk3576-qos", "syscon"; 1537 reg = <0x0 0x27f05000 0x0 0x20>; 1538 }; 1539 1540 qos_vepu1: qos@27f06000 { 1541 compatible = "rockchip,rk3576-qos", "syscon"; 1542 reg = <0x0 0x27f06000 0x0 0x20>; 1543 }; 1544 1545 qos_npu_mcu: qos@27f08000 { 1546 compatible = "rockchip,rk3576-qos", "syscon"; 1547 reg = <0x0 0x27f08000 0x0 0x20>; 1548 }; 1549 1550 qos_npu_nsp0: qos@27f08080 { 1551 compatible = "rockchip,rk3576-qos", "syscon"; 1552 reg = <0x0 0x27f08080 0x0 0x20>; 1553 }; 1554 1555 qos_npu_nsp1: qos@27f08100 { 1556 compatible = "rockchip,rk3576-qos", "syscon"; 1557 reg = <0x0 0x27f08100 0x0 0x20>; 1558 }; 1559 1560 qos_emmc: qos@27f09000 { 1561 compatible = "rockchip,rk3576-qos", "syscon"; 1562 reg = <0x0 0x27f09000 0x0 0x20>; 1563 }; 1564 1565 qos_fspi0: qos@27f09080 { 1566 compatible = "rockchip,rk3576-qos", "syscon"; 1567 reg = <0x0 0x27f09080 0x0 0x20>; 1568 }; 1569 1570 qos_mmu0: qos@27f0a000 { 1571 compatible = "rockchip,rk3576-qos", "syscon"; 1572 reg = <0x0 0x27f0a000 0x0 0x20>; 1573 }; 1574 1575 qos_mmu1: qos@27f0a080 { 1576 compatible = "rockchip,rk3576-qos", "syscon"; 1577 reg = <0x0 0x27f0a080 0x0 0x20>; 1578 }; 1579 1580 qos_rkvdec: qos@27f0c000 { 1581 compatible = "rockchip,rk3576-qos", "syscon"; 1582 reg = <0x0 0x27f0c000 0x0 0x20>; 1583 }; 1584 1585 qos_crypto: qos@27f0d000 { 1586 compatible = "rockchip,rk3576-qos", "syscon"; 1587 reg = <0x0 0x27f0d000 0x0 0x20>; 1588 }; 1589 1590 qos_mmu2: qos@27f0e000 { 1591 compatible = "rockchip,rk3576-qos", "syscon"; 1592 reg = <0x0 0x27f0e000 0x0 0x20>; 1593 }; 1594 1595 qos_ufshc: qos@27f0e080 { 1596 compatible = "rockchip,rk3576-qos", "syscon"; 1597 reg = <0x0 0x27f0e080 0x0 0x20>; 1598 }; 1599 1600 qos_vepu0: qos@27f0f000 { 1601 compatible = "rockchip,rk3576-qos", "syscon"; 1602 reg = <0x0 0x27f0f000 0x0 0x20>; 1603 }; 1604 1605 qos_isp_mro: qos@27f10000 { 1606 compatible = "rockchip,rk3576-qos", "syscon"; 1607 reg = <0x0 0x27f10000 0x0 0x20>; 1608 }; 1609 1610 qos_isp_mwo: qos@27f10080 { 1611 compatible = "rockchip,rk3576-qos", "syscon"; 1612 reg = <0x0 0x27f10080 0x0 0x20>; 1613 }; 1614 1615 qos_vicap_m0: qos@27f10100 { 1616 compatible = "rockchip,rk3576-qos", "syscon"; 1617 reg = <0x0 0x27f10100 0x0 0x20>; 1618 }; 1619 1620 qos_vpss_mro: qos@27f10180 { 1621 compatible = "rockchip,rk3576-qos", "syscon"; 1622 reg = <0x0 0x27f10180 0x0 0x20>; 1623 }; 1624 1625 qos_vpss_mwo: qos@27f10200 { 1626 compatible = "rockchip,rk3576-qos", "syscon"; 1627 reg = <0x0 0x27f10200 0x0 0x20>; 1628 }; 1629 1630 qos_hdcp0: qos@27f11000 { 1631 compatible = "rockchip,rk3576-qos", "syscon"; 1632 reg = <0x0 0x27f11000 0x0 0x20>; 1633 }; 1634 1635 qos_vop_m0: qos@27f12800 { 1636 compatible = "rockchip,rk3576-qos", "syscon"; 1637 reg = <0x0 0x27f12800 0x0 0x20>; 1638 }; 1639 1640 qos_vop_m1ro: qos@27f12880 { 1641 compatible = "rockchip,rk3576-qos", "syscon"; 1642 reg = <0x0 0x27f12880 0x0 0x20>; 1643 }; 1644 1645 qos_ebc: qos@27f13000 { 1646 compatible = "rockchip,rk3576-qos", "syscon"; 1647 reg = <0x0 0x27f13000 0x0 0x20>; 1648 }; 1649 1650 qos_rga0: qos@27f13080 { 1651 compatible = "rockchip,rk3576-qos", "syscon"; 1652 reg = <0x0 0x27f13080 0x0 0x20>; 1653 }; 1654 1655 qos_rga1: qos@27f13100 { 1656 compatible = "rockchip,rk3576-qos", "syscon"; 1657 reg = <0x0 0x27f13100 0x0 0x20>; 1658 }; 1659 1660 qos_jpeg: qos@27f13180 { 1661 compatible = "rockchip,rk3576-qos", "syscon"; 1662 reg = <0x0 0x27f13180 0x0 0x20>; 1663 }; 1664 1665 qos_vdpp: qos@27f13200 { 1666 compatible = "rockchip,rk3576-qos", "syscon"; 1667 reg = <0x0 0x27f13200 0x0 0x20>; 1668 }; 1669 1670 qos_npu_m0: qos@27f20000 { 1671 compatible = "rockchip,rk3576-qos", "syscon"; 1672 reg = <0x0 0x27f20000 0x0 0x20>; 1673 }; 1674 1675 qos_npu_m1: qos@27f21000 { 1676 compatible = "rockchip,rk3576-qos", "syscon"; 1677 reg = <0x0 0x27f21000 0x0 0x20>; 1678 }; 1679 1680 qos_npu_m0ro: qos@27f22080 { 1681 compatible = "rockchip,rk3576-qos", "syscon"; 1682 reg = <0x0 0x27f22080 0x0 0x20>; 1683 }; 1684 1685 qos_npu_m1ro: qos@27f22100 { 1686 compatible = "rockchip,rk3576-qos", "syscon"; 1687 reg = <0x0 0x27f22100 0x0 0x20>; 1688 }; 1689 1690 gmac0: ethernet@2a220000 { 1691 compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a"; 1692 reg = <0x0 0x2a220000 0x0 0x10000>; 1693 clocks = <&cru CLK_GMAC0_125M_SRC>, <&cru CLK_GMAC0_RMII_CRU>, 1694 <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>, 1695 <&cru CLK_GMAC0_PTP_REF>; 1696 clock-names = "stmmaceth", "clk_mac_ref", 1697 "pclk_mac", "aclk_mac", 1698 "ptp_ref"; 1699 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1700 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1701 interrupt-names = "macirq", "eth_wake_irq"; 1702 power-domains = <&power RK3576_PD_SDGMAC>; 1703 resets = <&cru SRST_A_GMAC0>; 1704 reset-names = "stmmaceth"; 1705 rockchip,grf = <&sdgmac_grf>; 1706 rockchip,php-grf = <&ioc_grf>; 1707 snps,axi-config = <&gmac0_stmmac_axi_setup>; 1708 snps,mixed-burst; 1709 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; 1710 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; 1711 snps,tso; 1712 status = "disabled"; 1713 1714 mdio0: mdio { 1715 compatible = "snps,dwmac-mdio"; 1716 #address-cells = <0x1>; 1717 #size-cells = <0x0>; 1718 }; 1719 1720 gmac0_stmmac_axi_setup: stmmac-axi-config { 1721 snps,blen = <0 0 0 0 16 8 4>; 1722 snps,rd_osr_lmt = <8>; 1723 snps,wr_osr_lmt = <4>; 1724 }; 1725 1726 gmac0_mtl_rx_setup: rx-queues-config { 1727 snps,rx-queues-to-use = <1>; 1728 queue0 {}; 1729 }; 1730 1731 gmac0_mtl_tx_setup: tx-queues-config { 1732 snps,tx-queues-to-use = <1>; 1733 queue0 {}; 1734 }; 1735 }; 1736 1737 gmac1: ethernet@2a230000 { 1738 compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a"; 1739 reg = <0x0 0x2a230000 0x0 0x10000>; 1740 clocks = <&cru CLK_GMAC1_125M_SRC>, <&cru CLK_GMAC1_RMII_CRU>, 1741 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, 1742 <&cru CLK_GMAC1_PTP_REF>; 1743 clock-names = "stmmaceth", "clk_mac_ref", 1744 "pclk_mac", "aclk_mac", 1745 "ptp_ref"; 1746 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 1747 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 1748 interrupt-names = "macirq", "eth_wake_irq"; 1749 power-domains = <&power RK3576_PD_SDGMAC>; 1750 resets = <&cru SRST_A_GMAC1>; 1751 reset-names = "stmmaceth"; 1752 rockchip,grf = <&sdgmac_grf>; 1753 rockchip,php-grf = <&ioc_grf>; 1754 snps,axi-config = <&gmac1_stmmac_axi_setup>; 1755 snps,mixed-burst; 1756 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 1757 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 1758 snps,tso; 1759 status = "disabled"; 1760 1761 mdio1: mdio { 1762 compatible = "snps,dwmac-mdio"; 1763 #address-cells = <0x1>; 1764 #size-cells = <0x0>; 1765 }; 1766 1767 gmac1_stmmac_axi_setup: stmmac-axi-config { 1768 snps,blen = <0 0 0 0 16 8 4>; 1769 snps,rd_osr_lmt = <8>; 1770 snps,wr_osr_lmt = <4>; 1771 }; 1772 1773 gmac1_mtl_rx_setup: rx-queues-config { 1774 snps,rx-queues-to-use = <1>; 1775 queue0 {}; 1776 }; 1777 1778 gmac1_mtl_tx_setup: tx-queues-config { 1779 snps,tx-queues-to-use = <1>; 1780 queue0 {}; 1781 }; 1782 }; 1783 1784 sata0: sata@2a240000 { 1785 compatible = "rockchip,rk3576-dwc-ahci", "snps,dwc-ahci"; 1786 reg = <0x0 0x2a240000 0x0 0x1000>; 1787 clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, 1788 <&cru CLK_RXOOB0>; 1789 clock-names = "sata", "pmalive", "rxoob"; 1790 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 1791 power-domains = <&power RK3576_PD_SUBPHP>; 1792 phys = <&combphy0_ps PHY_TYPE_SATA>; 1793 phy-names = "sata-phy"; 1794 ports-implemented = <0x1>; 1795 dma-coherent; 1796 status = "disabled"; 1797 }; 1798 1799 sata1: sata@2a250000 { 1800 compatible = "rockchip,rk3576-dwc-ahci", "snps,dwc-ahci"; 1801 reg = <0x0 0x2a250000 0x0 0x1000>; 1802 clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, 1803 <&cru CLK_RXOOB1>; 1804 clock-names = "sata", "pmalive", "rxoob"; 1805 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1806 power-domains = <&power RK3576_PD_SUBPHP>; 1807 phys = <&combphy1_psu PHY_TYPE_SATA>; 1808 phy-names = "sata-phy"; 1809 ports-implemented = <0x1>; 1810 dma-coherent; 1811 status = "disabled"; 1812 }; 1813 1814 ufshc: ufshc@2a2d0000 { 1815 compatible = "rockchip,rk3576-ufshc"; 1816 reg = <0x0 0x2a2d0000 0x0 0x10000>, 1817 <0x0 0x2b040000 0x0 0x10000>, 1818 <0x0 0x2601f000 0x0 0x1000>, 1819 <0x0 0x2603c000 0x0 0x1000>, 1820 <0x0 0x2a2e0000 0x0 0x10000>; 1821 reg-names = "hci", "mphy", "hci_grf", "mphy_grf", "hci_apb"; 1822 clocks = <&cru ACLK_UFS_SYS>, <&cru PCLK_USB_ROOT>, <&cru PCLK_MPHY>, 1823 <&cru CLK_REF_UFS_CLKOUT>; 1824 clock-names = "core", "pclk", "pclk_mphy", "ref_out"; 1825 assigned-clocks = <&cru CLK_REF_OSC_MPHY>; 1826 assigned-clock-parents = <&cru CLK_REF_MPHY_26M>; 1827 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1828 power-domains = <&power RK3576_PD_USB>; 1829 pinctrl-0 = <&ufs_refclk>; 1830 pinctrl-names = "default"; 1831 resets = <&cru SRST_A_UFS_BIU>, <&cru SRST_A_UFS_SYS>, 1832 <&cru SRST_A_UFS>, <&cru SRST_P_UFS_GRF>; 1833 reset-names = "biu", "sys", "ufs", "grf"; 1834 reset-gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_LOW>; 1835 status = "disabled"; 1836 }; 1837 1838 sfc1: spi@2a300000 { 1839 compatible = "rockchip,sfc"; 1840 reg = <0x0 0x2a300000 0x0 0x4000>; 1841 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1842 clocks = <&cru SCLK_FSPI1_X2>, <&cru HCLK_FSPI1>; 1843 clock-names = "clk_sfc", "hclk_sfc"; 1844 power-domains = <&power RK3576_PD_SDGMAC>; 1845 #address-cells = <1>; 1846 #size-cells = <0>; 1847 status = "disabled"; 1848 }; 1849 1850 sdmmc: mmc@2a310000 { 1851 compatible = "rockchip,rk3576-dw-mshc"; 1852 reg = <0x0 0x2a310000 0x0 0x4000>; 1853 clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>; 1854 clock-names = "biu", "ciu"; 1855 fifo-depth = <0x100>; 1856 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; 1857 max-frequency = <200000000>; 1858 pinctrl-names = "default"; 1859 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4 &sdmmc0_pwren>; 1860 power-domains = <&power RK3576_PD_SDGMAC>; 1861 resets = <&cru SRST_H_SDMMC0>; 1862 reset-names = "reset"; 1863 status = "disabled"; 1864 }; 1865 1866 sdio: mmc@2a320000 { 1867 compatible = "rockchip,rk3576-dw-mshc"; 1868 reg = <0x0 0x2a320000 0x0 0x4000>; 1869 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>; 1870 clock-names = "biu", "ciu"; 1871 fifo-depth = <0x100>; 1872 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; 1873 max-frequency = <200000000>; 1874 pinctrl-0 = <&sdmmc1m0_clk &sdmmc1m0_cmd &sdmmc1m0_bus4>; 1875 pinctrl-names = "default"; 1876 power-domains = <&power RK3576_PD_SDGMAC>; 1877 resets = <&cru SRST_H_SDIO>; 1878 reset-names = "reset"; 1879 status = "disabled"; 1880 }; 1881 1882 sdhci: mmc@2a330000 { 1883 compatible = "rockchip,rk3576-dwcmshc", "rockchip,rk3588-dwcmshc"; 1884 reg = <0x0 0x2a330000 0x0 0x10000>; 1885 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_SRC_EMMC>; 1886 assigned-clock-rates = <200000000>, <24000000>, <200000000>; 1887 clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>, 1888 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 1889 <&cru TCLK_EMMC>; 1890 clock-names = "core", "bus", "axi", "block", "timer"; 1891 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; 1892 max-frequency = <200000000>; 1893 pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>, 1894 <&emmc_cmd>, <&emmc_strb>; 1895 pinctrl-names = "default"; 1896 power-domains = <&power RK3576_PD_NVM>; 1897 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, 1898 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, 1899 <&cru SRST_T_EMMC>; 1900 reset-names = "core", "bus", "axi", "block", "timer"; 1901 supports-cqe; 1902 status = "disabled"; 1903 }; 1904 1905 sfc0: spi@2a340000 { 1906 compatible = "rockchip,sfc"; 1907 reg = <0x0 0x2a340000 0x0 0x4000>; 1908 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 1909 clocks = <&cru SCLK_FSPI_X2>, <&cru HCLK_FSPI>; 1910 clock-names = "clk_sfc", "hclk_sfc"; 1911 power-domains = <&power RK3576_PD_NVM>; 1912 #address-cells = <1>; 1913 #size-cells = <0>; 1914 status = "disabled"; 1915 }; 1916 1917 rng: rng@2a410000 { 1918 compatible = "rockchip,rk3576-rng"; 1919 reg = <0x0 0x2a410000 0x0 0x200>; 1920 clocks = <&cru HCLK_TRNG_NS>; 1921 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 1922 resets = <&cru SRST_H_TRNG_NS>; 1923 }; 1924 1925 otp: otp@2a580000 { 1926 compatible = "rockchip,rk3576-otp"; 1927 reg = <0x0 0x2a580000 0x0 0x400>; 1928 #address-cells = <1>; 1929 #size-cells = <1>; 1930 clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, 1931 <&cru CLK_OTP_PHY_G>; 1932 clock-names = "otp", "apb_pclk", "phy"; 1933 resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>; 1934 reset-names = "otp", "apb"; 1935 1936 /* Data cells */ 1937 cpu_code: cpu-code@2 { 1938 reg = <0x02 0x2>; 1939 }; 1940 otp_cpu_version: cpu-version@5 { 1941 reg = <0x05 0x1>; 1942 bits = <3 3>; 1943 }; 1944 otp_id: id@a { 1945 reg = <0x0a 0x10>; 1946 }; 1947 cpub_leakage: cpub-leakage@1e { 1948 reg = <0x1e 0x1>; 1949 }; 1950 cpul_leakage: cpul-leakage@1f { 1951 reg = <0x1f 0x1>; 1952 }; 1953 npu_leakage: npu-leakage@20 { 1954 reg = <0x20 0x1>; 1955 }; 1956 gpu_leakage: gpu-leakage@21 { 1957 reg = <0x21 0x1>; 1958 }; 1959 log_leakage: log-leakage@22 { 1960 reg = <0x22 0x1>; 1961 }; 1962 bigcore_tsadc_trim: bigcore-tsadc-trim@24 { 1963 reg = <0x24 0x2>; 1964 bits = <0 10>; 1965 }; 1966 litcore_tsadc_trim: litcore-tsadc-trim@26 { 1967 reg = <0x26 0x2>; 1968 bits = <0 10>; 1969 }; 1970 ddr_tsadc_trim: ddr-tsadc-trim@28 { 1971 reg = <0x28 0x2>; 1972 bits = <0 10>; 1973 }; 1974 npu_tsadc_trim: npu-tsadc-trim@2a { 1975 reg = <0x2a 0x2>; 1976 bits = <0 10>; 1977 }; 1978 gpu_tsadc_trim: gpu-tsadc-trim@2c { 1979 reg = <0x2c 0x2>; 1980 bits = <0 10>; 1981 }; 1982 soc_tsadc_trim: soc-tsadc-trim@64 { 1983 reg = <0x64 0x2>; 1984 bits = <0 10>; 1985 }; 1986 }; 1987 1988 sai0: sai@2a600000 { 1989 compatible = "rockchip,rk3576-sai"; 1990 reg = <0x0 0x2a600000 0x0 0x1000>; 1991 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1992 clocks = <&cru MCLK_SAI0_8CH>, <&cru HCLK_SAI0_8CH>; 1993 clock-names = "mclk", "hclk"; 1994 dmas = <&dmac0 0>, <&dmac0 1>; 1995 dma-names = "tx", "rx"; 1996 power-domains = <&power RK3576_PD_AUDIO>; 1997 resets = <&cru SRST_M_SAI0_8CH>, <&cru SRST_H_SAI0_8CH>; 1998 reset-names = "m", "h"; 1999 pinctrl-names = "default"; 2000 pinctrl-0 = <&sai0m0_lrck 2001 &sai0m0_sclk 2002 &sai0m0_sdi0 2003 &sai0m0_sdi1 2004 &sai0m0_sdi2 2005 &sai0m0_sdi3 2006 &sai0m0_sdo0 2007 &sai0m0_sdo1 2008 &sai0m0_sdo2 2009 &sai0m0_sdo3>; 2010 #sound-dai-cells = <0>; 2011 sound-name-prefix = "SAI0"; 2012 status = "disabled"; 2013 }; 2014 2015 sai1: sai@2a610000 { 2016 compatible = "rockchip,rk3576-sai"; 2017 reg = <0x0 0x2a610000 0x0 0x1000>; 2018 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 2019 clocks = <&cru MCLK_SAI1_8CH>, <&cru HCLK_SAI1_8CH>; 2020 clock-names = "mclk", "hclk"; 2021 dmas = <&dmac0 2>, <&dmac0 3>; 2022 dma-names = "tx", "rx"; 2023 power-domains = <&power RK3576_PD_AUDIO>; 2024 resets = <&cru SRST_M_SAI1_8CH>, <&cru SRST_H_SAI1_8CH>; 2025 reset-names = "m", "h"; 2026 pinctrl-names = "default"; 2027 pinctrl-0 = <&sai1m0_lrck 2028 &sai1m0_sclk 2029 &sai1m0_sdi0 2030 &sai1m0_sdo0 2031 &sai1m0_sdo1 2032 &sai1m0_sdo2 2033 &sai1m0_sdo3>; 2034 #sound-dai-cells = <0>; 2035 sound-name-prefix = "SAI1"; 2036 status = "disabled"; 2037 }; 2038 2039 sai2: sai@2a620000 { 2040 compatible = "rockchip,rk3576-sai"; 2041 reg = <0x0 0x2a620000 0x0 0x1000>; 2042 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 2043 clocks = <&cru MCLK_SAI2_2CH>, <&cru HCLK_SAI2_2CH>; 2044 clock-names = "mclk", "hclk"; 2045 dmas = <&dmac1 0>, <&dmac1 1>; 2046 dma-names = "tx", "rx"; 2047 power-domains = <&power RK3576_PD_AUDIO>; 2048 resets = <&cru SRST_M_SAI2_2CH>, <&cru SRST_H_SAI2_2CH>; 2049 reset-names = "m", "h"; 2050 pinctrl-names = "default"; 2051 pinctrl-0 = <&sai2m0_lrck 2052 &sai2m0_sclk 2053 &sai2m0_sdi 2054 &sai2m0_sdo>; 2055 #sound-dai-cells = <0>; 2056 sound-name-prefix = "SAI2"; 2057 status = "disabled"; 2058 }; 2059 2060 sai3: sai@2a630000 { 2061 compatible = "rockchip,rk3576-sai"; 2062 reg = <0x0 0x2a630000 0x0 0x1000>; 2063 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 2064 clocks = <&cru MCLK_SAI3_2CH>, <&cru HCLK_SAI3_2CH>; 2065 clock-names = "mclk", "hclk"; 2066 dmas = <&dmac1 2>, <&dmac1 3>; 2067 dma-names = "tx", "rx"; 2068 power-domains = <&power RK3576_PD_AUDIO>; 2069 resets = <&cru SRST_M_SAI3_2CH>, <&cru SRST_H_SAI3_2CH>; 2070 reset-names = "m", "h"; 2071 pinctrl-names = "default"; 2072 pinctrl-0 = <&sai3m0_lrck 2073 &sai3m0_sclk 2074 &sai3m0_sdi 2075 &sai3m0_sdo>; 2076 #sound-dai-cells = <0>; 2077 sound-name-prefix = "SAI3"; 2078 status = "disabled"; 2079 }; 2080 2081 sai4: sai@2a640000 { 2082 compatible = "rockchip,rk3576-sai"; 2083 reg = <0x0 0x2a640000 0x0 0x1000>; 2084 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 2085 clocks = <&cru MCLK_SAI4_2CH>, <&cru HCLK_SAI4_2CH>; 2086 clock-names = "mclk", "hclk"; 2087 dmas = <&dmac2 0>, <&dmac2 1>; 2088 dma-names = "tx", "rx"; 2089 power-domains = <&power RK3576_PD_AUDIO>; 2090 resets = <&cru SRST_M_SAI4_2CH>, <&cru SRST_H_SAI4_2CH>; 2091 reset-names = "m", "h"; 2092 pinctrl-names = "default"; 2093 pinctrl-0 = <&sai4m0_lrck 2094 &sai4m0_sclk 2095 &sai4m0_sdi 2096 &sai4m0_sdo>; 2097 #sound-dai-cells = <0>; 2098 sound-name-prefix = "SAI4"; 2099 status = "disabled"; 2100 }; 2101 2102 gic: interrupt-controller@2a701000 { 2103 compatible = "arm,gic-400"; 2104 reg = <0x0 0x2a701000 0 0x10000>, 2105 <0x0 0x2a702000 0 0x10000>, 2106 <0x0 0x2a704000 0 0x10000>, 2107 <0x0 0x2a706000 0 0x10000>; 2108 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 2109 interrupt-controller; 2110 #interrupt-cells = <3>; 2111 #address-cells = <2>; 2112 #size-cells = <2>; 2113 }; 2114 2115 dmac0: dma-controller@2ab90000 { 2116 compatible = "arm,pl330", "arm,primecell"; 2117 reg = <0x0 0x2ab90000 0x0 0x4000>; 2118 arm,pl330-periph-burst; 2119 clocks = <&cru ACLK_DMAC0>; 2120 clock-names = "apb_pclk"; 2121 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 2122 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 2123 #dma-cells = <1>; 2124 }; 2125 2126 dmac1: dma-controller@2abb0000 { 2127 compatible = "arm,pl330", "arm,primecell"; 2128 reg = <0x0 0x2abb0000 0x0 0x4000>; 2129 arm,pl330-periph-burst; 2130 clocks = <&cru ACLK_DMAC1>; 2131 clock-names = "apb_pclk"; 2132 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 2133 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 2134 #dma-cells = <1>; 2135 }; 2136 2137 dmac2: dma-controller@2abd0000 { 2138 compatible = "arm,pl330", "arm,primecell"; 2139 reg = <0x0 0x2abd0000 0x0 0x4000>; 2140 arm,pl330-periph-burst; 2141 clocks = <&cru ACLK_DMAC2>; 2142 clock-names = "apb_pclk"; 2143 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 2144 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 2145 #dma-cells = <1>; 2146 }; 2147 2148 i2c1: i2c@2ac40000 { 2149 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 2150 reg = <0x0 0x2ac40000 0x0 0x1000>; 2151 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 2152 clock-names = "i2c", "pclk"; 2153 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 2154 pinctrl-names = "default"; 2155 pinctrl-0 = <&i2c1m0_xfer>; 2156 #address-cells = <1>; 2157 #size-cells = <0>; 2158 status = "disabled"; 2159 }; 2160 2161 i2c2: i2c@2ac50000 { 2162 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 2163 reg = <0x0 0x2ac50000 0x0 0x1000>; 2164 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 2165 clock-names = "i2c", "pclk"; 2166 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 2167 pinctrl-names = "default"; 2168 pinctrl-0 = <&i2c2m0_xfer>; 2169 #address-cells = <1>; 2170 #size-cells = <0>; 2171 status = "disabled"; 2172 }; 2173 2174 i2c3: i2c@2ac60000 { 2175 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 2176 reg = <0x0 0x2ac60000 0x0 0x1000>; 2177 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 2178 clock-names = "i2c", "pclk"; 2179 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 2180 pinctrl-names = "default"; 2181 pinctrl-0 = <&i2c3m0_xfer>; 2182 #address-cells = <1>; 2183 #size-cells = <0>; 2184 status = "disabled"; 2185 }; 2186 2187 i2c4: i2c@2ac70000 { 2188 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 2189 reg = <0x0 0x2ac70000 0x0 0x1000>; 2190 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 2191 clock-names = "i2c", "pclk"; 2192 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 2193 pinctrl-names = "default"; 2194 pinctrl-0 = <&i2c4m0_xfer>; 2195 #address-cells = <1>; 2196 #size-cells = <0>; 2197 status = "disabled"; 2198 }; 2199 2200 i2c5: i2c@2ac80000 { 2201 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 2202 reg = <0x0 0x2ac80000 0x0 0x1000>; 2203 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 2204 clock-names = "i2c", "pclk"; 2205 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 2206 pinctrl-names = "default"; 2207 pinctrl-0 = <&i2c5m0_xfer>; 2208 #address-cells = <1>; 2209 #size-cells = <0>; 2210 status = "disabled"; 2211 }; 2212 2213 i2c6: i2c@2ac90000 { 2214 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 2215 reg = <0x0 0x2ac90000 0x0 0x1000>; 2216 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; 2217 clock-names = "i2c", "pclk"; 2218 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 2219 pinctrl-names = "default"; 2220 pinctrl-0 = <&i2c6m0_xfer>; 2221 #address-cells = <1>; 2222 #size-cells = <0>; 2223 status = "disabled"; 2224 }; 2225 2226 i2c7: i2c@2aca0000 { 2227 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 2228 reg = <0x0 0x2aca0000 0x0 0x1000>; 2229 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; 2230 clock-names = "i2c", "pclk"; 2231 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 2232 pinctrl-names = "default"; 2233 pinctrl-0 = <&i2c7m0_xfer>; 2234 #address-cells = <1>; 2235 #size-cells = <0>; 2236 status = "disabled"; 2237 }; 2238 2239 i2c8: i2c@2acb0000 { 2240 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 2241 reg = <0x0 0x2acb0000 0x0 0x1000>; 2242 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; 2243 clock-names = "i2c", "pclk"; 2244 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 2245 pinctrl-names = "default"; 2246 pinctrl-0 = <&i2c8m0_xfer>; 2247 #address-cells = <1>; 2248 #size-cells = <0>; 2249 status = "disabled"; 2250 }; 2251 2252 timer0: timer@2acc0000 { 2253 compatible = "rockchip,rk3576-timer", "rockchip,rk3288-timer"; 2254 reg = <0x0 0x2acc0000 0x0 0x20>; 2255 clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_TIMER0>; 2256 clock-names = "pclk", "timer"; 2257 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2258 }; 2259 2260 wdt: watchdog@2ace0000 { 2261 compatible = "rockchip,rk3576-wdt", "snps,dw-wdt"; 2262 reg = <0x0 0x2ace0000 0x0 0x100>; 2263 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; 2264 clock-names = "tclk", "pclk"; 2265 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 2266 }; 2267 2268 spi0: spi@2acf0000 { 2269 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi"; 2270 reg = <0x0 0x2acf0000 0x0 0x1000>; 2271 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 2272 clock-names = "spiclk", "apb_pclk"; 2273 dmas = <&dmac0 14>, <&dmac0 15>; 2274 dma-names = "tx", "rx"; 2275 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 2276 num-cs = <2>; 2277 pinctrl-names = "default"; 2278 pinctrl-0 = <&spi0m0_csn0 &spi0m0_csn1 &spi0m0_pins>; 2279 #address-cells = <1>; 2280 #size-cells = <0>; 2281 status = "disabled"; 2282 }; 2283 2284 spi1: spi@2ad00000 { 2285 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi"; 2286 reg = <0x0 0x2ad00000 0x0 0x1000>; 2287 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 2288 clock-names = "spiclk", "apb_pclk"; 2289 dmas = <&dmac0 16>, <&dmac0 17>; 2290 dma-names = "tx", "rx"; 2291 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 2292 num-cs = <2>; 2293 pinctrl-names = "default"; 2294 pinctrl-0 = <&spi1m0_csn0 &spi1m0_csn1 &spi1m0_pins>; 2295 #address-cells = <1>; 2296 #size-cells = <0>; 2297 status = "disabled"; 2298 }; 2299 2300 spi2: spi@2ad10000 { 2301 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi"; 2302 reg = <0x0 0x2ad10000 0x0 0x1000>; 2303 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 2304 clock-names = "spiclk", "apb_pclk"; 2305 dmas = <&dmac1 15>, <&dmac1 16>; 2306 dma-names = "tx", "rx"; 2307 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 2308 num-cs = <2>; 2309 pinctrl-names = "default"; 2310 pinctrl-0 = <&spi2m0_csn0 &spi2m0_csn1 &spi2m0_pins>; 2311 #address-cells = <1>; 2312 #size-cells = <0>; 2313 status = "disabled"; 2314 }; 2315 2316 spi3: spi@2ad20000 { 2317 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi"; 2318 reg = <0x0 0x2ad20000 0x0 0x1000>; 2319 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 2320 clock-names = "spiclk", "apb_pclk"; 2321 dmas = <&dmac1 17>, <&dmac1 18>; 2322 dma-names = "tx", "rx"; 2323 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 2324 num-cs = <2>; 2325 pinctrl-names = "default"; 2326 pinctrl-0 = <&spi3m0_csn0 &spi3m0_csn1 &spi3m0_pins>; 2327 #address-cells = <1>; 2328 #size-cells = <0>; 2329 status = "disabled"; 2330 }; 2331 2332 spi4: spi@2ad30000 { 2333 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi"; 2334 reg = <0x0 0x2ad30000 0x0 0x1000>; 2335 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; 2336 clock-names = "spiclk", "apb_pclk"; 2337 dmas = <&dmac2 12>, <&dmac2 13>; 2338 dma-names = "tx", "rx"; 2339 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 2340 num-cs = <2>; 2341 pinctrl-names = "default"; 2342 pinctrl-0 = <&spi4m0_csn0 &spi4m0_csn1 &spi4m0_pins>; 2343 #address-cells = <1>; 2344 #size-cells = <0>; 2345 status = "disabled"; 2346 }; 2347 2348 uart0: serial@2ad40000 { 2349 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2350 reg = <0x0 0x2ad40000 0x0 0x100>; 2351 reg-shift = <2>; 2352 reg-io-width = <4>; 2353 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 2354 clock-names = "baudclk", "apb_pclk"; 2355 dmas = <&dmac0 6>, <&dmac0 7>; 2356 dma-names = "tx", "rx"; 2357 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 2358 pinctrl-0 = <&uart0m0_xfer>; 2359 pinctrl-names = "default"; 2360 status = "disabled"; 2361 }; 2362 2363 uart2: serial@2ad50000 { 2364 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2365 reg = <0x0 0x2ad50000 0x0 0x100>; 2366 reg-shift = <2>; 2367 reg-io-width = <4>; 2368 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 2369 clock-names = "baudclk", "apb_pclk"; 2370 dmas = <&dmac0 10>, <&dmac0 11>; 2371 dma-names = "tx", "rx"; 2372 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 2373 pinctrl-names = "default"; 2374 pinctrl-0 = <&uart2m0_xfer>; 2375 status = "disabled"; 2376 }; 2377 2378 uart3: serial@2ad60000 { 2379 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2380 reg = <0x0 0x2ad60000 0x0 0x100>; 2381 reg-shift = <2>; 2382 reg-io-width = <4>; 2383 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 2384 clock-names = "baudclk", "apb_pclk"; 2385 dmas = <&dmac0 12>, <&dmac0 13>; 2386 dma-names = "tx", "rx"; 2387 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 2388 pinctrl-0 = <&uart3m0_xfer>; 2389 pinctrl-names = "default"; 2390 status = "disabled"; 2391 }; 2392 2393 uart4: serial@2ad70000 { 2394 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2395 reg = <0x0 0x2ad70000 0x0 0x100>; 2396 reg-shift = <2>; 2397 reg-io-width = <4>; 2398 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 2399 clock-names = "baudclk", "apb_pclk"; 2400 dmas = <&dmac1 9>, <&dmac1 10>; 2401 dma-names = "tx", "rx"; 2402 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 2403 pinctrl-0 = <&uart4m0_xfer>; 2404 pinctrl-names = "default"; 2405 status = "disabled"; 2406 }; 2407 2408 uart5: serial@2ad80000 { 2409 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2410 reg = <0x0 0x2ad80000 0x0 0x100>; 2411 reg-shift = <2>; 2412 reg-io-width = <4>; 2413 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 2414 clock-names = "baudclk", "apb_pclk"; 2415 dmas = <&dmac1 11>, <&dmac1 12>; 2416 dma-names = "tx", "rx"; 2417 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 2418 pinctrl-0 = <&uart5m0_xfer>; 2419 pinctrl-names = "default"; 2420 status = "disabled"; 2421 }; 2422 2423 uart6: serial@2ad90000 { 2424 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2425 reg = <0x0 0x2ad90000 0x0 0x100>; 2426 reg-shift = <2>; 2427 reg-io-width = <4>; 2428 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 2429 clock-names = "baudclk", "apb_pclk"; 2430 dmas = <&dmac1 13>, <&dmac1 14>; 2431 dma-names = "tx", "rx"; 2432 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 2433 pinctrl-0 = <&uart6m0_xfer>; 2434 pinctrl-names = "default"; 2435 status = "disabled"; 2436 }; 2437 2438 uart7: serial@2ada0000 { 2439 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2440 reg = <0x0 0x2ada0000 0x0 0x100>; 2441 reg-shift = <2>; 2442 reg-io-width = <4>; 2443 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 2444 clock-names = "baudclk", "apb_pclk"; 2445 dmas = <&dmac2 6>, <&dmac2 7>; 2446 dma-names = "tx", "rx"; 2447 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2448 pinctrl-0 = <&uart7m0_xfer>; 2449 pinctrl-names = "default"; 2450 status = "disabled"; 2451 }; 2452 2453 uart8: serial@2adb0000 { 2454 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2455 reg = <0x0 0x2adb0000 0x0 0x100>; 2456 reg-shift = <2>; 2457 reg-io-width = <4>; 2458 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 2459 clock-names = "baudclk", "apb_pclk"; 2460 dmas = <&dmac2 8>, <&dmac2 9>; 2461 dma-names = "tx", "rx"; 2462 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 2463 pinctrl-0 = <&uart8m0_xfer>; 2464 pinctrl-names = "default"; 2465 status = "disabled"; 2466 }; 2467 2468 uart9: serial@2adc0000 { 2469 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2470 reg = <0x0 0x2adc0000 0x0 0x100>; 2471 reg-shift = <2>; 2472 reg-io-width = <4>; 2473 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 2474 clock-names = "baudclk", "apb_pclk"; 2475 dmas = <&dmac2 10>, <&dmac2 11>; 2476 dma-names = "tx", "rx"; 2477 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 2478 pinctrl-0 = <&uart9m0_xfer>; 2479 pinctrl-names = "default"; 2480 status = "disabled"; 2481 }; 2482 2483 saradc: adc@2ae00000 { 2484 compatible = "rockchip,rk3576-saradc", "rockchip,rk3588-saradc"; 2485 reg = <0x0 0x2ae00000 0x0 0x10000>; 2486 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 2487 clock-names = "saradc", "apb_pclk"; 2488 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 2489 resets = <&cru SRST_P_SARADC>; 2490 reset-names = "saradc-apb"; 2491 #io-channel-cells = <1>; 2492 status = "disabled"; 2493 }; 2494 2495 tsadc: tsadc@2ae70000 { 2496 compatible = "rockchip,rk3576-tsadc"; 2497 reg = <0x0 0x2ae70000 0x0 0x400>; 2498 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 2499 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 2500 clock-names = "tsadc", "apb_pclk"; 2501 assigned-clocks = <&cru CLK_TSADC>; 2502 assigned-clock-rates = <2000000>; 2503 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; 2504 reset-names = "tsadc-apb", "tsadc"; 2505 #thermal-sensor-cells = <1>; 2506 rockchip,hw-tshut-temp = <120000>; 2507 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ 2508 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 2509 #address-cells = <1>; 2510 #size-cells = <0>; 2511 2512 sensor@0 { 2513 reg = <0>; 2514 nvmem-cells = <&soc_tsadc_trim>; 2515 nvmem-cell-names = "trim"; 2516 }; 2517 sensor@1 { 2518 reg = <1>; 2519 nvmem-cells = <&bigcore_tsadc_trim>; 2520 nvmem-cell-names = "trim"; 2521 }; 2522 sensor@2 { 2523 reg = <2>; 2524 nvmem-cells = <&litcore_tsadc_trim>; 2525 nvmem-cell-names = "trim"; 2526 }; 2527 sensor@3 { 2528 reg = <3>; 2529 nvmem-cells = <&ddr_tsadc_trim>; 2530 nvmem-cell-names = "trim"; 2531 }; 2532 sensor@4 { 2533 reg = <4>; 2534 nvmem-cells = <&npu_tsadc_trim>; 2535 nvmem-cell-names = "trim"; 2536 }; 2537 sensor@5 { 2538 reg = <5>; 2539 nvmem-cells = <&gpu_tsadc_trim>; 2540 nvmem-cell-names = "trim"; 2541 }; 2542 }; 2543 2544 i2c9: i2c@2ae80000 { 2545 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 2546 reg = <0x0 0x2ae80000 0x0 0x1000>; 2547 clocks = <&cru CLK_I2C9>, <&cru PCLK_I2C9>; 2548 clock-names = "i2c", "pclk"; 2549 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 2550 pinctrl-names = "default"; 2551 pinctrl-0 = <&i2c9m0_xfer>; 2552 #address-cells = <1>; 2553 #size-cells = <0>; 2554 status = "disabled"; 2555 }; 2556 2557 uart10: serial@2afc0000 { 2558 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2559 reg = <0x0 0x2afc0000 0x0 0x100>; 2560 reg-shift = <2>; 2561 reg-io-width = <4>; 2562 clocks = <&cru SCLK_UART10>, <&cru PCLK_UART10>; 2563 clock-names = "baudclk", "apb_pclk"; 2564 dmas = <&dmac2 21>, <&dmac2 22>; 2565 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 2566 pinctrl-names = "default"; 2567 pinctrl-0 = <&uart10m0_xfer>; 2568 status = "disabled"; 2569 }; 2570 2571 uart11: serial@2afd0000 { 2572 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2573 reg = <0x0 0x2afd0000 0x0 0x100>; 2574 reg-shift = <2>; 2575 reg-io-width = <4>; 2576 clocks = <&cru SCLK_UART11>, <&cru PCLK_UART11>; 2577 clock-names = "baudclk", "apb_pclk"; 2578 dmas = <&dmac2 23>, <&dmac2 24>; 2579 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 2580 pinctrl-names = "default"; 2581 pinctrl-0 = <&uart11m0_xfer>; 2582 status = "disabled"; 2583 }; 2584 2585 mipidcphy: phy@2b020000 { 2586 compatible = "rockchip,rk3576-mipi-dcphy"; 2587 reg = <0x0 0x2b020000 0x0 0x10000>; 2588 clocks = <&cru PCLK_MIPI_DCPHY>, 2589 <&cru CLK_PHY_REF_SRC>; 2590 clock-names = "pclk", "ref"; 2591 resets = <&cru SRST_M_MIPI_DCPHY>, 2592 <&cru SRST_P_MIPI_DCPHY>, 2593 <&cru SRST_P_DCPHY_GRF>, 2594 <&cru SRST_S_MIPI_DCPHY>; 2595 reset-names = "m_phy", "apb", "grf", "s_phy"; 2596 rockchip,grf = <&mipidcphy_grf>; 2597 #phy-cells = <1>; 2598 status = "disabled"; 2599 }; 2600 2601 combphy0_ps: phy@2b050000 { 2602 compatible = "rockchip,rk3576-naneng-combphy"; 2603 reg = <0x0 0x2b050000 0x0 0x100>; 2604 #phy-cells = <1>; 2605 clocks = <&cru CLK_REF_PCIE0_PHY>, 2606 <&cru PCLK_PCIE2_COMBOPHY0>, 2607 <&cru PCLK_PCIE0>; 2608 clock-names = "ref", "apb", "pipe"; 2609 assigned-clocks = <&cru CLK_REF_PCIE0_PHY>; 2610 assigned-clock-rates = <100000000>; 2611 resets = <&cru SRST_PCIE0_PIPE_PHY>, 2612 <&cru SRST_P_PCIE2_COMBOPHY0>; 2613 reset-names = "phy", "apb"; 2614 rockchip,pipe-grf = <&php_grf>; 2615 rockchip,pipe-phy-grf = <&pipe_phy0_grf>; 2616 status = "disabled"; 2617 }; 2618 2619 combphy1_psu: phy@2b060000 { 2620 compatible = "rockchip,rk3576-naneng-combphy"; 2621 reg = <0x0 0x2b060000 0x0 0x100>; 2622 #phy-cells = <1>; 2623 clocks = <&cru CLK_REF_PCIE1_PHY>, 2624 <&cru PCLK_PCIE2_COMBOPHY1>, 2625 <&cru PCLK_PCIE1>; 2626 clock-names = "ref", "apb", "pipe"; 2627 assigned-clocks = <&cru CLK_REF_PCIE1_PHY>; 2628 assigned-clock-rates = <100000000>; 2629 resets = <&cru SRST_PCIE1_PIPE_PHY>, 2630 <&cru SRST_P_PCIE2_COMBOPHY1>; 2631 reset-names = "phy", "apb"; 2632 rockchip,pipe-grf = <&php_grf>; 2633 rockchip,pipe-phy-grf = <&pipe_phy1_grf>; 2634 status = "disabled"; 2635 }; 2636 2637 usbdp_phy: phy@2b010000 { 2638 compatible = "rockchip,rk3576-usbdp-phy"; 2639 reg = <0x0 0x2b010000 0x0 0x10000>; 2640 #phy-cells = <1>; 2641 clocks = <&cru CLK_PHY_REF_SRC >, 2642 <&cru CLK_USBDP_COMBO_PHY_IMMORTAL>, 2643 <&cru PCLK_USBDPPHY>, 2644 <&u2phy0>; 2645 clock-names = "refclk", "immortal", "pclk", "utmi"; 2646 resets = <&cru SRST_USBDP_COMBO_PHY_INIT>, 2647 <&cru SRST_USBDP_COMBO_PHY_CMN>, 2648 <&cru SRST_USBDP_COMBO_PHY_LANE>, 2649 <&cru SRST_USBDP_COMBO_PHY_PCS>, 2650 <&cru SRST_P_USBDPPHY>; 2651 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; 2652 rockchip,u2phy-grf = <&usb2phy_grf>; 2653 rockchip,usb-grf = <&usb_grf>; 2654 rockchip,usbdpphy-grf = <&usbdpphy_grf>; 2655 rockchip,vo-grf = <&vo1_grf>; 2656 status = "disabled"; 2657 }; 2658 2659 hdptxphy: hdmiphy@2b000000 { 2660 compatible = "rockchip,rk3576-hdptx-phy", "rockchip,rk3588-hdptx-phy"; 2661 reg = <0x0 0x2b000000 0x0 0x2000>; 2662 clocks = <&cru CLK_PHY_REF_SRC>, <&cru PCLK_HDPTX_APB>; 2663 clock-names = "ref", "apb"; 2664 #clock-cells = <0>; 2665 resets = <&cru SRST_P_HDPTX_APB>, <&cru SRST_HDPTX_INIT>, 2666 <&cru SRST_HDPTX_CMN>, <&cru SRST_HDPTX_LANE>; 2667 reset-names = "apb", "init", "cmn", "lane"; 2668 rockchip,grf = <&hdptxphy_grf>; 2669 #phy-cells = <0>; 2670 status = "disabled"; 2671 }; 2672 2673 sram: sram@3ff88000 { 2674 compatible = "mmio-sram"; 2675 reg = <0x0 0x3ff88000 0x0 0x78000>; 2676 ranges = <0x0 0x0 0x3ff88000 0x78000>; 2677 #address-cells = <1>; 2678 #size-cells = <1>; 2679 2680 /* start address and size should be 4k align */ 2681 rkvdec_sram: rkvdec-sram@0 { 2682 reg = <0x0 0x78000>; 2683 }; 2684 }; 2685 2686 scmi_shmem: scmi-shmem@4010f000 { 2687 compatible = "arm,scmi-shmem"; 2688 reg = <0x0 0x4010f000 0x0 0x100>; 2689 }; 2690 }; 2691}; 2692 2693#include "rk3576-pinctrl.dtsi" 2694