1 // SPDX-License-Identifier: MIT
2 //
3 // Copyright 2024 Advanced Micro Devices, Inc.
4
5 #include "dm_services.h"
6 #include "dc.h"
7
8 #include "dcn32/dcn32_init.h"
9 #include "dcn401/dcn401_init.h"
10
11 #include "resource.h"
12 #include "include/irq_service_interface.h"
13 #include "dcn401_resource.h"
14
15 #include "dcn20/dcn20_resource.h"
16 #include "dcn30/dcn30_resource.h"
17 #include "dcn32/dcn32_resource.h"
18 #include "dcn321/dcn321_resource.h"
19
20 #include "dcn10/dcn10_ipp.h"
21 #include "dcn401/dcn401_hubbub.h"
22 #include "dcn401/dcn401_mpc.h"
23 #include "dcn401/dcn401_hubp.h"
24 #include "irq/dcn401/irq_service_dcn401.h"
25 #include "dcn401/dcn401_dpp.h"
26 #include "dcn401/dcn401_optc.h"
27 #include "dcn20/dcn20_hwseq.h"
28 #include "dcn30/dcn30_hwseq.h"
29 #include "dce110/dce110_hwseq.h"
30 #include "dcn20/dcn20_opp.h"
31 #include "dcn401/dcn401_dsc.h"
32 #include "dcn30/dcn30_vpg.h"
33 #include "dcn31/dcn31_vpg.h"
34 #include "dcn30/dcn30_afmt.h"
35 #include "dcn30/dcn30_dio_stream_encoder.h"
36 #include "dcn401/dcn401_dio_stream_encoder.h"
37 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
38 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
39 #include "dcn32/dcn32_hpo_dp_link_encoder.h"
40 #include "dcn31/dcn31_apg.h"
41 #include "dcn31/dcn31_dio_link_encoder.h"
42 #include "dcn401/dcn401_dio_link_encoder.h"
43 #include "dcn10/dcn10_link_encoder.h"
44 #include "dcn321/dcn321_dio_link_encoder.h"
45 #include "dce/dce_clock_source.h"
46 #include "dce/dce_audio.h"
47 #include "dce/dce_hwseq.h"
48 #include "clk_mgr.h"
49 #include "virtual/virtual_stream_encoder.h"
50 #include "dml/display_mode_vba.h"
51 #include "dcn401/dcn401_dccg.h"
52 #include "dcn10/dcn10_resource.h"
53 #include "link.h"
54 #include "link_enc_cfg.h"
55 #include "dcn31/dcn31_panel_cntl.h"
56
57 #include "dcn30/dcn30_dwb.h"
58 #include "dcn32/dcn32_mmhubbub.h"
59
60 #include "dcn/dcn_4_1_0_offset.h"
61 #include "dcn/dcn_4_1_0_sh_mask.h"
62 #include "nbif/nbif_6_3_1_offset.h"
63
64 #include "reg_helper.h"
65 #include "dce/dmub_abm.h"
66 #include "dce/dmub_psr.h"
67 #include "dce/dce_aux.h"
68 #include "dce/dce_i2c.h"
69
70 #include "dml/dcn30/display_mode_vba_30.h"
71 #include "vm_helper.h"
72 #include "dcn20/dcn20_vmid.h"
73 #include "dml/dcn401/dcn401_fpu.h"
74
75 #include "dc_state_priv.h"
76
77 #include "dml2/dml2_wrapper.h"
78
79 #include "spl/dc_spl_scl_easf_filters.h"
80 #include "spl/dc_spl_isharp_filters.h"
81
82 #define DC_LOGGER_INIT(logger)
83
84 enum dcn401_clk_src_array_id {
85 DCN401_CLK_SRC_PLL0,
86 DCN401_CLK_SRC_PLL1,
87 DCN401_CLK_SRC_PLL2,
88 DCN401_CLK_SRC_PLL3,
89 //DCN401_CLK_SRC_PLL4,
90 DCN401_CLK_SRC_TOTAL
91 };
92
93 /* begin *********************
94 * macros to expend register list macro defined in HW object header file
95 */
96
97 /* DCN */
98 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
99
100 #define BASE(seg) BASE_INNER(seg)
101
102 #define SR(reg_name)\
103 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
104 reg ## reg_name
105 #define SR_ARR(reg_name, id)\
106 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
107 reg ## reg_name
108 #define SR_ARR_INIT(reg_name, id, value)\
109 REG_STRUCT[id].reg_name = value
110
111 #define SRI(reg_name, block, id)\
112 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
113 reg ## block ## id ## _ ## reg_name
114
115 #define SRI_ARR(reg_name, block, id)\
116 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
117 reg ## block ## id ## _ ## reg_name
118
119 /*
120 * Used when a reg_name would otherwise begin with an integer
121 */
122 #define SRI_ARR_US(reg_name, block, id)\
123 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## reg_name ## _BASE_IDX) + \
124 reg ## block ## id ## reg_name
125 #define SR_ARR_I2C(reg_name, id) \
126 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
127
128 #define SRI_ARR_I2C(reg_name, block, id)\
129 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
130 reg ## block ## id ## _ ## reg_name
131
132 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\
133 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
134 reg ## block ## id ## _ ## reg_name
135
136 #define SRI2(reg_name, block, id)\
137 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
138 reg ## reg_name
139 #define SRI2_ARR(reg_name, block, id)\
140 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
141 reg ## reg_name
142
143 #define SRIR(var_name, reg_name, block, id)\
144 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
145 reg ## block ## id ## _ ## reg_name
146
147 #define SRII(reg_name, block, id)\
148 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
149 reg ## block ## id ## _ ## reg_name
150
151 #define SRII_ARR_2(reg_name, block, id, inst)\
152 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
153 reg ## block ## id ## _ ## reg_name
154
155 #define SRII_MPC_RMU(reg_name, block, id)\
156 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
157 reg ## block ## id ## _ ## reg_name
158
159 #define SRII_DWB(reg_name, temp_name, block, id)\
160 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
161 reg ## block ## id ## _ ## temp_name
162
163 #define DCCG_SRII(reg_name, block, id)\
164 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
165 reg ## block ## id ## _ ## reg_name
166
167 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
168 .field_name = reg_name ## __ ## field_name ## post_fix
169
170 #define VUPDATE_SRII(reg_name, block, id)\
171 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
172 reg ## reg_name ## _ ## block ## id
173
174 /* NBIO */
175 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
176
177 #define NBIO_BASE(seg) \
178 NBIO_BASE_INNER(seg)
179
180 #define NBIO_SR(reg_name)\
181 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
182 regBIF_BX0_ ## reg_name
183 #define NBIO_SR_ARR(reg_name, id)\
184 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
185 regBIF_BX0_ ## reg_name
186
187 #define CTX ctx
188 #define REG(reg_name) \
189 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
190
191 static struct bios_registers bios_regs;
192
193 #define bios_regs_init() \
194 NBIO_SR(BIOS_SCRATCH_3),\
195 NBIO_SR(BIOS_SCRATCH_6)
196
197 #define clk_src_regs_init(index, pllid)\
198 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid)
199
200 static struct dce110_clk_src_regs clk_src_regs[5];
201
202 static const struct dce110_clk_src_shift cs_shift = {
203 CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
204 };
205
206 static const struct dce110_clk_src_mask cs_mask = {
207 CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
208 };
209
210 #define abm_regs_init(id)\
211 ABM_DCN401_REG_LIST_RI(id)
212
213 static struct dce_abm_registers abm_regs[4];
214
215 static const struct dce_abm_shift abm_shift = {
216 ABM_MASK_SH_LIST_DCN401(__SHIFT)
217 };
218
219 static const struct dce_abm_mask abm_mask = {
220 ABM_MASK_SH_LIST_DCN401(_MASK)
221 };
222
223 #define audio_regs_init(id)\
224 AUD_COMMON_REG_LIST_RI(id)
225
226 static struct dce_audio_registers audio_regs[5];
227
228 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
229 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
230 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
231 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
232
233 static const struct dce_audio_shift audio_shift = {
234 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
235 };
236
237 static const struct dce_audio_mask audio_mask = {
238 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
239 };
240
241 #define vpg_regs_init(id)\
242 VPG_DCN401_REG_LIST_RI(id)
243
244 static struct dcn31_vpg_registers vpg_regs[9];
245
246 static const struct dcn31_vpg_shift vpg_shift = {
247 DCN31_VPG_MASK_SH_LIST(__SHIFT)
248 };
249
250 static const struct dcn31_vpg_mask vpg_mask = {
251 DCN31_VPG_MASK_SH_LIST(_MASK)
252 };
253
254 #define afmt_regs_init(id)\
255 AFMT_DCN3_REG_LIST_RI(id)
256
257 static struct dcn30_afmt_registers afmt_regs[5];
258
259 static const struct dcn30_afmt_shift afmt_shift = {
260 DCN3_AFMT_MASK_SH_LIST(__SHIFT)
261 };
262
263 static const struct dcn30_afmt_mask afmt_mask = {
264 DCN3_AFMT_MASK_SH_LIST(_MASK)
265 };
266
267 #define apg_regs_init(id)\
268 APG_DCN31_REG_LIST_RI(id)
269
270 static struct dcn31_apg_registers apg_regs[4];
271
272 static const struct dcn31_apg_shift apg_shift = {
273 DCN31_APG_MASK_SH_LIST(__SHIFT)
274 };
275
276 static const struct dcn31_apg_mask apg_mask = {
277 DCN31_APG_MASK_SH_LIST(_MASK)
278 };
279
280 #define stream_enc_regs_init(id)\
281 SE_DCN4_01_REG_LIST_RI(id)
282
283 static struct dcn10_stream_enc_registers stream_enc_regs[4];
284
285 static const struct dcn10_stream_encoder_shift se_shift = {
286 SE_COMMON_MASK_SH_LIST_DCN401(__SHIFT)
287 };
288
289 static const struct dcn10_stream_encoder_mask se_mask = {
290 SE_COMMON_MASK_SH_LIST_DCN401(_MASK)
291 };
292
293 #define aux_regs_init(id)\
294 DCN2_AUX_REG_LIST_RI(id)
295
296 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5];
297
298 #define hpd_regs_init(id)\
299 HPD_REG_LIST_RI(id)
300
301 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5];
302
303 #define link_regs_init(id, phyid)\
304 LE_DCN401_REG_LIST_RI(id)
305
306 static struct dcn10_link_enc_registers link_enc_regs[4];
307
308
309 static const struct dcn10_link_enc_shift le_shift = {
310 LINK_ENCODER_MASK_SH_LIST_DCN401(__SHIFT)
311 };
312
313
314 static const struct dcn10_link_enc_mask le_mask = {
315 LINK_ENCODER_MASK_SH_LIST_DCN401(_MASK)
316 };
317
318
319 #define hpo_dp_stream_encoder_reg_init(id)\
320 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
321
322 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4];
323
324 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
325 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
326 };
327
328 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
329 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
330 };
331
332
333 #define hpo_dp_link_encoder_reg_init(id)\
334 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id)
335 /*DCN3_1_RDPCSTX_REG_LIST(0),*/
336 /*DCN3_1_RDPCSTX_REG_LIST(1),*/
337 /*DCN3_1_RDPCSTX_REG_LIST(2),*/
338 /*DCN3_1_RDPCSTX_REG_LIST(3),*/
339
340 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[4];
341
342 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
343 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
344 };
345
346 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
347 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
348 };
349
350 #define dpp_regs_init(id)\
351 DPP_REG_LIST_DCN401_COMMON_RI(id)
352
353 static struct dcn401_dpp_registers dpp_regs[4];
354
355 static const struct dcn401_dpp_shift tf_shift = {
356 DPP_REG_LIST_SH_MASK_DCN401_COMMON(__SHIFT)
357 };
358
359 static const struct dcn401_dpp_mask tf_mask = {
360 DPP_REG_LIST_SH_MASK_DCN401_COMMON(_MASK)
361 };
362
363 #define opp_regs_init(id)\
364 OPP_REG_LIST_DCN401_RI(id)
365
366 static struct dcn20_opp_registers opp_regs[4];
367
368 static const struct dcn20_opp_shift opp_shift = {
369 OPP_MASK_SH_LIST_DCN20(__SHIFT)
370 };
371
372 static const struct dcn20_opp_mask opp_mask = {
373 OPP_MASK_SH_LIST_DCN20(_MASK)
374 };
375
376 #define aux_engine_regs_init(id) \
377 AUX_COMMON_REG_LIST0_RI(id), SR_ARR_INIT(AUXN_IMPCAL, id, 0), \
378 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \
379 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \
380 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)
381
382 static struct dce110_aux_registers aux_engine_regs[5];
383
384 static const struct dce110_aux_registers_shift aux_shift = {
385 DCN_AUX_MASK_SH_LIST(__SHIFT)
386 };
387
388 static const struct dce110_aux_registers_mask aux_mask = {
389 DCN_AUX_MASK_SH_LIST(_MASK)
390 };
391
392 #define dwbc_regs_dcn401_init(id)\
393 DWBC_COMMON_REG_LIST_DCN30_RI(id)
394
395 static struct dcn30_dwbc_registers dwbc401_regs[1];
396
397 static const struct dcn30_dwbc_shift dwbc401_shift = {
398 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
399 };
400
401 static const struct dcn30_dwbc_mask dwbc401_mask = {
402 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
403 };
404
405
406 #define mcif_wb_regs_dcn3_init(id)\
407 MCIF_WB_COMMON_REG_LIST_DCN32_RI(id)
408
409 static struct dcn30_mmhubbub_registers mcif_wb30_regs[1];
410
411 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
412 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
413 };
414
415 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
416 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK)
417 };
418
419 #define dsc_regs_init(id)\
420 DSC_REG_LIST_DCN401_RI(id)
421
422 static struct dcn401_dsc_registers dsc_regs[4];
423
424 static const struct dcn401_dsc_shift dsc_shift = {
425 DSC_REG_LIST_SH_MASK_DCN401(__SHIFT)
426 };
427
428 static const struct dcn401_dsc_mask dsc_mask = {
429 DSC_REG_LIST_SH_MASK_DCN401(_MASK)
430 };
431
432 static struct dcn401_mpc_registers mpc_regs;
433
434 #define dcn_mpc_regs_init()\
435 MPC_REG_LIST_DCN4_01_RI(0),\
436 MPC_REG_LIST_DCN4_01_RI(1),\
437 MPC_REG_LIST_DCN4_01_RI(2),\
438 MPC_REG_LIST_DCN4_01_RI(3),\
439 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\
440 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\
441 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\
442 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\
443 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0)
444
445 static const struct dcn401_mpc_shift mpc_shift = {
446 MPC_COMMON_MASK_SH_LIST_DCN4_01(__SHIFT)
447 };
448
449 static const struct dcn401_mpc_mask mpc_mask = {
450 MPC_COMMON_MASK_SH_LIST_DCN4_01(_MASK)
451 };
452
453 #define optc_regs_init(id)\
454 OPTC_COMMON_REG_LIST_DCN401_RI(id)
455
456 static struct dcn_optc_registers optc_regs[4];
457
458 static const struct dcn_optc_shift optc_shift = {
459 OPTC_COMMON_MASK_SH_LIST_DCN401(__SHIFT)
460 };
461
462 static const struct dcn_optc_mask optc_mask = {
463 OPTC_COMMON_MASK_SH_LIST_DCN401(_MASK)
464 };
465
466 #define hubp_regs_init(id)\
467 HUBP_REG_LIST_DCN401_RI(id)
468
469 static struct dcn_hubp2_registers hubp_regs[4];
470
471 static const struct dcn_hubp2_shift hubp_shift = {
472 HUBP_MASK_SH_LIST_DCN401(__SHIFT)
473 };
474
475 static const struct dcn_hubp2_mask hubp_mask = {
476 HUBP_MASK_SH_LIST_DCN401(_MASK)
477 };
478
479 static struct dcn_hubbub_registers hubbub_reg;
480 #define hubbub_reg_init()\
481 HUBBUB_REG_LIST_DCN4_01_RI(0)
482
483 static const struct dcn_hubbub_shift hubbub_shift = {
484 HUBBUB_MASK_SH_LIST_DCN4_01(__SHIFT)
485 };
486
487 static const struct dcn_hubbub_mask hubbub_mask = {
488 HUBBUB_MASK_SH_LIST_DCN4_01(_MASK)
489 };
490
491 static struct dccg_registers dccg_regs;
492
493 #define dccg_regs_init()\
494 DCCG_REG_LIST_DCN401_RI()
495
496 static const struct dccg_shift dccg_shift = {
497 DCCG_MASK_SH_LIST_DCN401(__SHIFT)
498 };
499
500 static const struct dccg_mask dccg_mask = {
501 DCCG_MASK_SH_LIST_DCN401(_MASK)
502 };
503
504 #define SRII2(reg_name_pre, reg_name_post, id)\
505 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
506 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
507 reg ## reg_name_pre ## id ## _ ## reg_name_post
508
509
510 #define HWSEQ_DCN401_REG_LIST()\
511 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
512 SR(DIO_MEM_PWR_CTRL), \
513 SR(ODM_MEM_PWR_CTRL3), \
514 SR(MMHUBBUB_MEM_PWR_CNTL), \
515 SR(DCCG_GATE_DISABLE_CNTL), \
516 SR(DCCG_GATE_DISABLE_CNTL2), \
517 SR(DCFCLK_CNTL),\
518 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
519 SRII(PIXEL_RATE_CNTL, OTG, 0), \
520 SRII(PIXEL_RATE_CNTL, OTG, 1),\
521 SRII(PIXEL_RATE_CNTL, OTG, 2),\
522 SRII(PIXEL_RATE_CNTL, OTG, 3),\
523 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
524 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
525 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
526 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
527 SR(MICROSECOND_TIME_BASE_DIV), \
528 SR(MILLISECOND_TIME_BASE_DIV), \
529 SR(DISPCLK_FREQ_CHANGE_CNTL), \
530 SR(RBBMIF_TIMEOUT_DIS), \
531 SR(RBBMIF_TIMEOUT_DIS_2), \
532 SR(DCHUBBUB_CRC_CTRL), \
533 SR(DPP_TOP0_DPP_CRC_CTRL), \
534 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
535 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
536 SR(MPC_CRC_CTRL), \
537 SR(MPC_CRC_RESULT_GB), \
538 SR(MPC_CRC_RESULT_C), \
539 SR(MPC_CRC_RESULT_AR), \
540 SR(DOMAIN0_PG_CONFIG), \
541 SR(DOMAIN1_PG_CONFIG), \
542 SR(DOMAIN2_PG_CONFIG), \
543 SR(DOMAIN3_PG_CONFIG), \
544 SR(DOMAIN16_PG_CONFIG), \
545 SR(DOMAIN17_PG_CONFIG), \
546 SR(DOMAIN18_PG_CONFIG), \
547 SR(DOMAIN19_PG_CONFIG), \
548 SR(DOMAIN22_PG_CONFIG), \
549 SR(DOMAIN23_PG_CONFIG), \
550 SR(DOMAIN24_PG_CONFIG), \
551 SR(DOMAIN25_PG_CONFIG), \
552 SR(DOMAIN0_PG_STATUS), \
553 SR(DOMAIN1_PG_STATUS), \
554 SR(DOMAIN2_PG_STATUS), \
555 SR(DOMAIN3_PG_STATUS), \
556 SR(DOMAIN16_PG_STATUS), \
557 SR(DOMAIN17_PG_STATUS), \
558 SR(DOMAIN18_PG_STATUS), \
559 SR(DOMAIN19_PG_STATUS), \
560 SR(DOMAIN22_PG_STATUS), \
561 SR(DOMAIN23_PG_STATUS), \
562 SR(DOMAIN24_PG_STATUS), \
563 SR(DOMAIN25_PG_STATUS), \
564 SR(DC_IP_REQUEST_CNTL), \
565 SR(AZALIA_AUDIO_DTO), \
566 SR(HPO_TOP_HW_CONTROL),\
567 SR(AZALIA_CONTROLLER_CLOCK_GATING)
568
569 static struct dce_hwseq_registers hwseq_reg;
570
571 #define hwseq_reg_init()\
572 HWSEQ_DCN401_REG_LIST()
573
574 #define HWSEQ_DCN401_MASK_SH_LIST(mask_sh)\
575 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
576 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
577 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
578 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
579 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
580 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
581 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
582 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
583 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
584 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
585 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
586 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
587 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
588 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
589 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
590 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
591 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
592 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
593 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
594 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
595 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
596 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
597 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
598 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
599 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
600 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
601 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
602 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
603 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
604 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
605 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
606 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
607 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
608 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
609 HWS_SF(, DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
610 HWS_SF(, DOMAIN23_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
611 HWS_SF(, DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
612 HWS_SF(, DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
613 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
614 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
615 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
616 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh), \
617 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
618 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh)
619
620 static const struct dce_hwseq_shift hwseq_shift = {
621 HWSEQ_DCN401_MASK_SH_LIST(__SHIFT)
622 };
623
624 static const struct dce_hwseq_mask hwseq_mask = {
625 HWSEQ_DCN401_MASK_SH_LIST(_MASK)
626 };
627
628 #define vmid_regs_init(id)\
629 DCN20_VMID_REG_LIST_RI(id)
630
631 static struct dcn_vmid_registers vmid_regs[16];
632
633 static const struct dcn20_vmid_shift vmid_shifts = {
634 DCN20_VMID_MASK_SH_LIST(__SHIFT)
635 };
636
637 static const struct dcn20_vmid_mask vmid_masks = {
638 DCN20_VMID_MASK_SH_LIST(_MASK)
639 };
640
641 static const struct resource_caps res_cap_dcn4_01 = {
642 .num_timing_generator = 4,
643 .num_opp = 4,
644 .num_video_plane = 4,
645 .num_audio = 4,
646 .num_stream_encoder = 4,
647 .num_hpo_dp_stream_encoder = 4,
648 .num_hpo_dp_link_encoder = 4,
649 .num_pll = 4,
650 .num_dwb = 1,
651 .num_ddc = 4,
652 .num_vmid = 16,
653 .num_mpc_3dlut = 4,
654 .num_dsc = 4,
655 };
656
657 static const struct dc_plane_cap plane_cap = {
658 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
659 .per_pixel_alpha = true,
660
661 .pixel_format_support = {
662 .argb8888 = true,
663 .nv12 = true,
664 .fp16 = true,
665 .p010 = true,
666 .ayuv = false,
667 },
668
669 .max_upscale_factor = {
670 .argb8888 = 16000,
671 .nv12 = 16000,
672 .fp16 = 16000
673 },
674
675 // 6:1 downscaling ratio: 1000/6 = 166.666
676 .max_downscale_factor = {
677 .argb8888 = 167,
678 .nv12 = 167,
679 .fp16 = 167
680 },
681 64,
682 64
683 };
684
685 static const struct dc_debug_options debug_defaults_drv = {
686 .disable_dmcu = true,
687 .force_abm_enable = false,
688 .clock_trace = true,
689 .disable_pplib_clock_request = false,
690 .pipe_split_policy = MPC_SPLIT_AVOID,
691 .force_single_disp_pipe_split = false,
692 .disable_dcc = DCC_ENABLE,
693 .vsr_support = true,
694 .performance_trace = false,
695 .max_downscale_src_width = 7680,/*upto 8K*/
696 .disable_pplib_wm_range = false,
697 .scl_reset_length10 = true,
698 .sanity_checks = false,
699 .underflow_assert_delay_us = 0xFFFFFFFF,
700 .dwb_fi_phase = -1, // -1 = disable,
701 .dmub_command_table = true,
702 .enable_mem_low_power = {
703 .bits = {
704 .vga = false,
705 .i2c = false,
706 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
707 .dscl = false,
708 .cm = false,
709 .mpc = false,
710 .optc = true,
711 }
712 },
713 .use_max_lb = true,
714 .force_disable_subvp = false,
715 .exit_idle_opt_for_cursor_updates = true,
716 .using_dml2 = true,
717 .using_dml21 = true,
718 .enable_single_display_2to1_odm_policy = true,
719
720 //must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions
721 .enable_double_buffered_dsc_pg_support = true,
722 .enable_dp_dig_pixel_rate_div_policy = 1,
723 .allow_sw_cursor_fallback = false,
724 .alloc_extra_way_for_cursor = true,
725 .min_prefetch_in_strobe_ns = 60000, // 60us
726 .disable_unbounded_requesting = false,
727 .enable_legacy_fast_update = false,
728 .dcc_meta_propagation_delay_us = 10,
729 .fams_version = {
730 .minor = 1,
731 .major = 2,
732 }, //v2.1
733 .fams2_config = {
734 .bits = {
735 .enable = true,
736 .enable_offload_flip = true,
737 .enable_stall_recovery = true,
738 }
739 },
740 .force_cositing = CHROMA_COSITING_NONE + 1,
741 };
742
dcn401_aux_engine_create(struct dc_context * ctx,uint32_t inst)743 static struct dce_aux *dcn401_aux_engine_create(
744 struct dc_context *ctx,
745 uint32_t inst)
746 {
747 struct aux_engine_dce110 *aux_engine =
748 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
749
750 if (!aux_engine)
751 return NULL;
752
753 #undef REG_STRUCT
754 #define REG_STRUCT aux_engine_regs
755 aux_engine_regs_init(0),
756 aux_engine_regs_init(1),
757 aux_engine_regs_init(2),
758 aux_engine_regs_init(3);
759
760 dce110_aux_engine_construct(aux_engine, ctx, inst,
761 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
762 &aux_engine_regs[inst],
763 &aux_mask,
764 &aux_shift,
765 ctx->dc->caps.extended_aux_timeout_support);
766
767 return &aux_engine->base;
768 }
769 #define i2c_inst_regs_init(id)\
770 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)
771
772 static struct dce_i2c_registers i2c_hw_regs[5];
773
774 static const struct dce_i2c_shift i2c_shifts = {
775 I2C_COMMON_MASK_SH_LIST_DCN401(__SHIFT)
776 };
777
778 static const struct dce_i2c_mask i2c_masks = {
779 I2C_COMMON_MASK_SH_LIST_DCN401(_MASK)
780 };
781
dcn401_i2c_hw_create(struct dc_context * ctx,uint32_t inst)782 static struct dce_i2c_hw *dcn401_i2c_hw_create(
783 struct dc_context *ctx,
784 uint32_t inst)
785 {
786 struct dce_i2c_hw *dce_i2c_hw =
787 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
788
789 if (!dce_i2c_hw)
790 return NULL;
791
792 #undef REG_STRUCT
793 #define REG_STRUCT i2c_hw_regs
794 i2c_inst_regs_init(1),
795 i2c_inst_regs_init(2),
796 i2c_inst_regs_init(3),
797 i2c_inst_regs_init(4);
798
799 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
800 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
801
802 return dce_i2c_hw;
803 }
804
dcn401_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)805 static struct clock_source *dcn401_clock_source_create(
806 struct dc_context *ctx,
807 struct dc_bios *bios,
808 enum clock_source_id id,
809 const struct dce110_clk_src_regs *regs,
810 bool dp_clk_src)
811 {
812 struct dce110_clk_src *clk_src =
813 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
814
815 if (!clk_src)
816 return NULL;
817
818 if (dcn401_clk_src_construct(clk_src, ctx, bios, id,
819 regs, &cs_shift, &cs_mask)) {
820 clk_src->base.dp_clk_src = dp_clk_src;
821 return &clk_src->base;
822 }
823
824 kfree(clk_src);
825 BREAK_TO_DEBUGGER();
826 return NULL;
827 }
828
dcn401_hubbub_create(struct dc_context * ctx)829 static struct hubbub *dcn401_hubbub_create(struct dc_context *ctx)
830 {
831 int i;
832
833 struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub),
834 GFP_KERNEL);
835
836 if (!hubbub2)
837 return NULL;
838
839
840 #undef REG_STRUCT
841 #define REG_STRUCT hubbub_reg
842 hubbub_reg_init();
843
844 #undef REG_STRUCT
845 #define REG_STRUCT vmid_regs
846 vmid_regs_init(0),
847 vmid_regs_init(1),
848 vmid_regs_init(2),
849 vmid_regs_init(3),
850 vmid_regs_init(4),
851 vmid_regs_init(5),
852 vmid_regs_init(6),
853 vmid_regs_init(7),
854 vmid_regs_init(8),
855 vmid_regs_init(9),
856 vmid_regs_init(10),
857 vmid_regs_init(11),
858 vmid_regs_init(12),
859 vmid_regs_init(13),
860 vmid_regs_init(14),
861 vmid_regs_init(15);
862
863 hubbub401_construct(hubbub2, ctx,
864 &hubbub_reg,
865 &hubbub_shift,
866 &hubbub_mask,
867 DCN4_01_DEFAULT_DET_SIZE, //nominal (default) detile buffer size in kbytes,
868 8, //dml2 ip_params_st.pixel_chunk_size_kbytes
869 DCN4_01_CRB_SIZE_KB); //dml2 ip_params_st.config_return_buffer_size_in_kbytes
870
871 for (i = 0; i < res_cap_dcn4_01.num_vmid; i++) {
872 struct dcn20_vmid *vmid = &hubbub2->vmid[i];
873
874 vmid->ctx = ctx;
875
876 vmid->regs = &vmid_regs[i];
877 vmid->shifts = &vmid_shifts;
878 vmid->masks = &vmid_masks;
879 }
880
881 return &hubbub2->base;
882 }
883
dcn401_hubp_create(struct dc_context * ctx,uint32_t inst)884 static struct hubp *dcn401_hubp_create(
885 struct dc_context *ctx,
886 uint32_t inst)
887 {
888 struct dcn20_hubp *hubp2 =
889 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
890
891 if (!hubp2)
892 return NULL;
893
894 #undef REG_STRUCT
895 #define REG_STRUCT hubp_regs
896 hubp_regs_init(0),
897 hubp_regs_init(1),
898 hubp_regs_init(2),
899 hubp_regs_init(3);
900
901 if (hubp401_construct(hubp2, ctx, inst,
902 &hubp_regs[inst], &hubp_shift, &hubp_mask))
903 return &hubp2->base;
904
905 BREAK_TO_DEBUGGER();
906 kfree(hubp2);
907 return NULL;
908 }
909
dcn401_dpp_destroy(struct dpp ** dpp)910 static void dcn401_dpp_destroy(struct dpp **dpp)
911 {
912 kfree(TO_DCN401_DPP(*dpp));
913 *dpp = NULL;
914 }
915
dcn401_dpp_create(struct dc_context * ctx,uint32_t inst)916 static struct dpp *dcn401_dpp_create(
917 struct dc_context *ctx,
918 uint32_t inst)
919 {
920 struct dcn401_dpp *dpp401 =
921 kzalloc(sizeof(struct dcn401_dpp), GFP_KERNEL);
922
923 if (!dpp401)
924 return NULL;
925
926 #undef REG_STRUCT
927 #define REG_STRUCT dpp_regs
928 dpp_regs_init(0),
929 dpp_regs_init(1),
930 dpp_regs_init(2),
931 dpp_regs_init(3);
932
933 if (dpp401_construct(dpp401, ctx, inst,
934 &dpp_regs[inst], &tf_shift, &tf_mask))
935 return &dpp401->base;
936
937 BREAK_TO_DEBUGGER();
938 kfree(dpp401);
939 return NULL;
940 }
941
dcn401_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)942 static struct mpc *dcn401_mpc_create(
943 struct dc_context *ctx,
944 int num_mpcc,
945 int num_rmu)
946 {
947 struct dcn401_mpc *mpc401 = kzalloc(sizeof(struct dcn401_mpc),
948 GFP_KERNEL);
949
950 if (!mpc401)
951 return NULL;
952
953 #undef REG_STRUCT
954 #define REG_STRUCT mpc_regs
955 dcn_mpc_regs_init();
956
957 dcn401_mpc_construct(mpc401, ctx,
958 &mpc_regs,
959 &mpc_shift,
960 &mpc_mask,
961 num_mpcc,
962 num_rmu);
963
964 return &mpc401->base;
965 }
966
dcn401_opp_create(struct dc_context * ctx,uint32_t inst)967 static struct output_pixel_processor *dcn401_opp_create(
968 struct dc_context *ctx, uint32_t inst)
969 {
970 struct dcn20_opp *opp4 =
971 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
972
973 if (!opp4) {
974 BREAK_TO_DEBUGGER();
975 return NULL;
976 }
977
978 #undef REG_STRUCT
979 #define REG_STRUCT opp_regs
980 opp_regs_init(0),
981 opp_regs_init(1),
982 opp_regs_init(2),
983 opp_regs_init(3);
984
985 dcn20_opp_construct(opp4, ctx, inst,
986 &opp_regs[inst], &opp_shift, &opp_mask);
987 return &opp4->base;
988 }
989
990
dcn401_timing_generator_create(struct dc_context * ctx,uint32_t instance)991 static struct timing_generator *dcn401_timing_generator_create(
992 struct dc_context *ctx,
993 uint32_t instance)
994 {
995 struct optc *tgn10 =
996 kzalloc(sizeof(struct optc), GFP_KERNEL);
997
998 if (!tgn10)
999 return NULL;
1000 #undef REG_STRUCT
1001 #define REG_STRUCT optc_regs
1002 optc_regs_init(0),
1003 optc_regs_init(1),
1004 optc_regs_init(2),
1005 optc_regs_init(3);
1006
1007 tgn10->base.inst = instance;
1008 tgn10->base.ctx = ctx;
1009
1010 tgn10->tg_regs = &optc_regs[instance];
1011 tgn10->tg_shift = &optc_shift;
1012 tgn10->tg_mask = &optc_mask;
1013
1014 dcn401_timing_generator_init(tgn10);
1015
1016 return &tgn10->base;
1017 }
1018
1019 static const struct encoder_feature_support link_enc_feature = {
1020 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1021 .max_hdmi_pixel_clock = 600000,
1022 .hdmi_ycbcr420_supported = true,
1023 .dp_ycbcr420_supported = true,
1024 .fec_supported = true,
1025 .flags.bits.IS_HBR2_CAPABLE = true,
1026 .flags.bits.IS_HBR3_CAPABLE = true,
1027 .flags.bits.IS_TPS3_CAPABLE = true,
1028 .flags.bits.IS_TPS4_CAPABLE = true
1029 };
1030
dcn401_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)1031 static struct link_encoder *dcn401_link_encoder_create(
1032 struct dc_context *ctx,
1033 const struct encoder_init_data *enc_init_data)
1034 {
1035 struct dcn20_link_encoder *enc20 =
1036 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1037
1038 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
1039 return NULL;
1040
1041 #undef REG_STRUCT
1042 #define REG_STRUCT link_enc_aux_regs
1043 aux_regs_init(0),
1044 aux_regs_init(1),
1045 aux_regs_init(2),
1046 aux_regs_init(3);
1047
1048 #undef REG_STRUCT
1049 #define REG_STRUCT link_enc_hpd_regs
1050 hpd_regs_init(0),
1051 hpd_regs_init(1),
1052 hpd_regs_init(2),
1053 hpd_regs_init(3);
1054 #undef REG_STRUCT
1055 #define REG_STRUCT link_enc_regs
1056 link_regs_init(0, A),
1057 link_regs_init(1, B),
1058 link_regs_init(2, C),
1059 link_regs_init(3, D);
1060
1061 dcn401_link_encoder_construct(enc20,
1062 enc_init_data,
1063 &link_enc_feature,
1064 &link_enc_regs[enc_init_data->transmitter],
1065 &link_enc_aux_regs[enc_init_data->channel - 1],
1066 &link_enc_hpd_regs[enc_init_data->hpd_source],
1067 &le_shift,
1068 &le_mask);
1069 return &enc20->enc10.base;
1070 }
1071
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1072 static void read_dce_straps(
1073 struct dc_context *ctx,
1074 struct resource_straps *straps)
1075 {
1076 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS,
1077 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1078
1079 }
1080
dcn401_create_audio(struct dc_context * ctx,unsigned int inst)1081 static struct audio *dcn401_create_audio(
1082 struct dc_context *ctx, unsigned int inst)
1083 {
1084
1085 #undef REG_STRUCT
1086 #define REG_STRUCT audio_regs
1087 audio_regs_init(0),
1088 audio_regs_init(1),
1089 audio_regs_init(2),
1090 audio_regs_init(3),
1091 audio_regs_init(4);
1092
1093 return dce_audio_create(ctx, inst,
1094 &audio_regs[inst], &audio_shift, &audio_mask);
1095 }
1096
dcn401_vpg_create(struct dc_context * ctx,uint32_t inst)1097 static struct vpg *dcn401_vpg_create(
1098 struct dc_context *ctx,
1099 uint32_t inst)
1100 {
1101 struct dcn31_vpg *vpg4 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);
1102
1103 if (!vpg4)
1104 return NULL;
1105
1106
1107 #undef REG_STRUCT
1108 #define REG_STRUCT vpg_regs
1109 vpg_regs_init(0),
1110 vpg_regs_init(1),
1111 vpg_regs_init(2),
1112 vpg_regs_init(3),
1113 vpg_regs_init(4),
1114 vpg_regs_init(5),
1115 vpg_regs_init(6),
1116 vpg_regs_init(7),
1117 vpg_regs_init(8);
1118
1119 vpg31_construct(vpg4, ctx, inst,
1120 &vpg_regs[inst],
1121 &vpg_shift,
1122 &vpg_mask);
1123
1124 return &vpg4->base;
1125 }
1126
dcn401_afmt_create(struct dc_context * ctx,uint32_t inst)1127 static struct afmt *dcn401_afmt_create(
1128 struct dc_context *ctx,
1129 uint32_t inst)
1130 {
1131 struct dcn30_afmt *afmt401 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
1132
1133 if (!afmt401)
1134 return NULL;
1135
1136 #undef REG_STRUCT
1137 #define REG_STRUCT afmt_regs
1138 afmt_regs_init(0),
1139 afmt_regs_init(1),
1140 afmt_regs_init(2),
1141 afmt_regs_init(3),
1142 afmt_regs_init(4);
1143
1144 afmt3_construct(afmt401, ctx, inst,
1145 &afmt_regs[inst],
1146 &afmt_shift,
1147 &afmt_mask);
1148
1149 return &afmt401->base;
1150 }
1151
dcn401_apg_create(struct dc_context * ctx,uint32_t inst)1152 static struct apg *dcn401_apg_create(
1153 struct dc_context *ctx,
1154 uint32_t inst)
1155 {
1156 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1157
1158 if (!apg31)
1159 return NULL;
1160
1161 #undef REG_STRUCT
1162 #define REG_STRUCT apg_regs
1163 apg_regs_init(0),
1164 apg_regs_init(1),
1165 apg_regs_init(2),
1166 apg_regs_init(3);
1167
1168 apg31_construct(apg31, ctx, inst,
1169 &apg_regs[inst],
1170 &apg_shift,
1171 &apg_mask);
1172
1173 return &apg31->base;
1174 }
1175
dcn401_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1176 static struct stream_encoder *dcn401_stream_encoder_create(
1177 enum engine_id eng_id,
1178 struct dc_context *ctx)
1179 {
1180 struct dcn10_stream_encoder *enc1;
1181 struct vpg *vpg;
1182 struct afmt *afmt;
1183 int vpg_inst;
1184 int afmt_inst;
1185
1186 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1187 if (eng_id <= ENGINE_ID_DIGF) {
1188 vpg_inst = eng_id;
1189 afmt_inst = eng_id;
1190 } else
1191 return NULL;
1192
1193 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1194 vpg = dcn401_vpg_create(ctx, vpg_inst);
1195 afmt = dcn401_afmt_create(ctx, afmt_inst);
1196
1197 if (!enc1 || !vpg || !afmt || eng_id >= ARRAY_SIZE(stream_enc_regs)) {
1198 kfree(enc1);
1199 kfree(vpg);
1200 kfree(afmt);
1201 return NULL;
1202 }
1203 #undef REG_STRUCT
1204 #define REG_STRUCT stream_enc_regs
1205 stream_enc_regs_init(0),
1206 stream_enc_regs_init(1),
1207 stream_enc_regs_init(2),
1208 stream_enc_regs_init(3);
1209 //stream_enc_regs_init(4);
1210
1211 dcn401_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1212 eng_id, vpg, afmt,
1213 &stream_enc_regs[eng_id],
1214 &se_shift, &se_mask);
1215 return &enc1->base;
1216 }
1217
dcn401_hpo_dp_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1218 static struct hpo_dp_stream_encoder *dcn401_hpo_dp_stream_encoder_create(
1219 enum engine_id eng_id,
1220 struct dc_context *ctx)
1221 {
1222 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1223 struct vpg *vpg;
1224 struct apg *apg;
1225 uint32_t hpo_dp_inst;
1226 uint32_t vpg_inst;
1227 uint32_t apg_inst;
1228
1229 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1230 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1231
1232 /* Mapping of VPG register blocks to HPO DP block instance:
1233 * VPG[6] -> HPO_DP[0]
1234 * VPG[7] -> HPO_DP[1]
1235 * VPG[8] -> HPO_DP[2]
1236 * VPG[9] -> HPO_DP[3]
1237 */
1238 vpg_inst = hpo_dp_inst + 5;
1239
1240 /* Mapping of APG register blocks to HPO DP block instance:
1241 * APG[0] -> HPO_DP[0]
1242 * APG[1] -> HPO_DP[1]
1243 * APG[2] -> HPO_DP[2]
1244 * APG[3] -> HPO_DP[3]
1245 */
1246 apg_inst = hpo_dp_inst;
1247
1248 /* allocate HPO stream encoder and create VPG sub-block */
1249 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1250 vpg = dcn401_vpg_create(ctx, vpg_inst);
1251 apg = dcn401_apg_create(ctx, apg_inst);
1252
1253 if (!hpo_dp_enc31 || !vpg || !apg) {
1254 kfree(hpo_dp_enc31);
1255 kfree(vpg);
1256 kfree(apg);
1257 return NULL;
1258 }
1259
1260 #undef REG_STRUCT
1261 #define REG_STRUCT hpo_dp_stream_enc_regs
1262 hpo_dp_stream_encoder_reg_init(0),
1263 hpo_dp_stream_encoder_reg_init(1),
1264 hpo_dp_stream_encoder_reg_init(2),
1265 hpo_dp_stream_encoder_reg_init(3);
1266
1267 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1268 hpo_dp_inst, eng_id, vpg, apg,
1269 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1270 &hpo_dp_se_shift, &hpo_dp_se_mask);
1271
1272 return &hpo_dp_enc31->base;
1273 }
1274
dcn401_hpo_dp_link_encoder_create(uint8_t inst,struct dc_context * ctx)1275 static struct hpo_dp_link_encoder *dcn401_hpo_dp_link_encoder_create(
1276 uint8_t inst,
1277 struct dc_context *ctx)
1278 {
1279 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1280
1281 /* allocate HPO link encoder */
1282 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1283 if (!hpo_dp_enc31)
1284 return NULL; /* out of memory */
1285
1286 #undef REG_STRUCT
1287 #define REG_STRUCT hpo_dp_link_enc_regs
1288 hpo_dp_link_encoder_reg_init(0),
1289 hpo_dp_link_encoder_reg_init(1),
1290 hpo_dp_link_encoder_reg_init(2),
1291 hpo_dp_link_encoder_reg_init(3);
1292
1293 hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst,
1294 &hpo_dp_link_enc_regs[inst],
1295 &hpo_dp_le_shift, &hpo_dp_le_mask);
1296
1297 return &hpo_dp_enc31->base;
1298 }
1299
dcn401_calc_num_avail_chans_for_mall(struct dc * dc,unsigned int num_chans)1300 static unsigned int dcn401_calc_num_avail_chans_for_mall(struct dc *dc, unsigned int num_chans)
1301 {
1302 unsigned int num_available_chans = 1;
1303
1304 /* channels for MALL must be a power of 2 */
1305 while (num_chans > 1) {
1306 num_available_chans = (num_available_chans << 1);
1307 num_chans = (num_chans >> 1);
1308 }
1309
1310 /* cannot be odd */
1311 num_available_chans &= ~1;
1312
1313 /* clamp to max available channels for MALL per ASIC */
1314 if (ASICREV_IS_GC_12_0_0_A0(dc->ctx->asic_id.hw_internal_rev)) {
1315 num_available_chans = num_available_chans > 16 ? 16 : num_available_chans;
1316 } else if (ASICREV_IS_GC_12_0_1_A0(dc->ctx->asic_id.hw_internal_rev)) {
1317 num_available_chans = num_available_chans > 8 ? 8 : num_available_chans;
1318 }
1319
1320 return num_available_chans;
1321 }
1322
dcn401_hwseq_create(struct dc_context * ctx)1323 static struct dce_hwseq *dcn401_hwseq_create(
1324 struct dc_context *ctx)
1325 {
1326 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1327
1328 #undef REG_STRUCT
1329 #define REG_STRUCT hwseq_reg
1330 hwseq_reg_init();
1331
1332 if (hws) {
1333 hws->ctx = ctx;
1334 hws->regs = &hwseq_reg;
1335 hws->shifts = &hwseq_shift;
1336 hws->masks = &hwseq_mask;
1337 }
1338
1339 return hws;
1340 }
1341 static const struct resource_create_funcs res_create_funcs = {
1342 .read_dce_straps = read_dce_straps,
1343 .create_audio = dcn401_create_audio,
1344 .create_stream_encoder = dcn401_stream_encoder_create,
1345 .create_hpo_dp_stream_encoder = dcn401_hpo_dp_stream_encoder_create,
1346 .create_hpo_dp_link_encoder = dcn401_hpo_dp_link_encoder_create,
1347 .create_hwseq = dcn401_hwseq_create,
1348 };
1349
dcn401_dsc_destroy(struct display_stream_compressor ** dsc)1350 static void dcn401_dsc_destroy(struct display_stream_compressor **dsc)
1351 {
1352 kfree(container_of(*dsc, struct dcn401_dsc, base));
1353 *dsc = NULL;
1354 }
1355
dcn401_resource_destruct(struct dcn401_resource_pool * pool)1356 static void dcn401_resource_destruct(struct dcn401_resource_pool *pool)
1357 {
1358 unsigned int i;
1359
1360 for (i = 0; i < pool->base.stream_enc_count; i++) {
1361 if (pool->base.stream_enc[i] != NULL) {
1362 if (pool->base.stream_enc[i]->vpg != NULL) {
1363 kfree(DCN31_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1364 pool->base.stream_enc[i]->vpg = NULL;
1365 }
1366 if (pool->base.stream_enc[i]->afmt != NULL) {
1367 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1368 pool->base.stream_enc[i]->afmt = NULL;
1369 }
1370 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1371 pool->base.stream_enc[i] = NULL;
1372 }
1373 }
1374
1375 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1376 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1377 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1378 kfree(DCN31_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1379 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1380 }
1381 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1382 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1383 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1384 }
1385 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1386 pool->base.hpo_dp_stream_enc[i] = NULL;
1387 }
1388 }
1389
1390 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1391 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1392 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1393 pool->base.hpo_dp_link_enc[i] = NULL;
1394 }
1395 }
1396
1397 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1398 if (pool->base.dscs[i] != NULL)
1399 dcn401_dsc_destroy(&pool->base.dscs[i]);
1400 }
1401
1402 if (pool->base.mpc != NULL) {
1403 kfree(TO_DCN20_MPC(pool->base.mpc));
1404 pool->base.mpc = NULL;
1405 }
1406 if (pool->base.hubbub != NULL) {
1407 kfree(TO_DCN20_HUBBUB(pool->base.hubbub));
1408 pool->base.hubbub = NULL;
1409 }
1410 for (i = 0; i < pool->base.pipe_count; i++) {
1411 if (pool->base.dpps[i] != NULL)
1412 dcn401_dpp_destroy(&pool->base.dpps[i]);
1413
1414 if (pool->base.ipps[i] != NULL)
1415 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1416
1417 if (pool->base.hubps[i] != NULL) {
1418 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1419 pool->base.hubps[i] = NULL;
1420 }
1421
1422 if (pool->base.irqs != NULL) {
1423 dal_irq_service_destroy(&pool->base.irqs);
1424 }
1425 }
1426
1427 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1428 if (pool->base.engines[i] != NULL)
1429 dce110_engine_destroy(&pool->base.engines[i]);
1430 if (pool->base.hw_i2cs[i] != NULL) {
1431 kfree(pool->base.hw_i2cs[i]);
1432 pool->base.hw_i2cs[i] = NULL;
1433 }
1434 if (pool->base.sw_i2cs[i] != NULL) {
1435 kfree(pool->base.sw_i2cs[i]);
1436 pool->base.sw_i2cs[i] = NULL;
1437 }
1438 }
1439
1440 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1441 if (pool->base.opps[i] != NULL)
1442 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1443 }
1444
1445 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1446 if (pool->base.timing_generators[i] != NULL) {
1447 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1448 pool->base.timing_generators[i] = NULL;
1449 }
1450 }
1451
1452 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1453 if (pool->base.dwbc[i] != NULL) {
1454 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1455 pool->base.dwbc[i] = NULL;
1456 }
1457 if (pool->base.mcif_wb[i] != NULL) {
1458 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1459 pool->base.mcif_wb[i] = NULL;
1460 }
1461 }
1462
1463 for (i = 0; i < pool->base.audio_count; i++) {
1464 if (pool->base.audios[i])
1465 dce_aud_destroy(&pool->base.audios[i]);
1466 }
1467
1468 for (i = 0; i < pool->base.clk_src_count; i++) {
1469 if (pool->base.clock_sources[i] != NULL) {
1470 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1471 pool->base.clock_sources[i] = NULL;
1472 }
1473 }
1474
1475 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1476 if (pool->base.mpc_lut[i] != NULL) {
1477 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1478 pool->base.mpc_lut[i] = NULL;
1479 }
1480 if (pool->base.mpc_shaper[i] != NULL) {
1481 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1482 pool->base.mpc_shaper[i] = NULL;
1483 }
1484 }
1485
1486 if (pool->base.dp_clock_source != NULL) {
1487 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1488 pool->base.dp_clock_source = NULL;
1489 }
1490
1491 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1492 if (pool->base.multiple_abms[i] != NULL)
1493 dce_abm_destroy(&pool->base.multiple_abms[i]);
1494 }
1495
1496 if (pool->base.psr != NULL)
1497 dmub_psr_destroy(&pool->base.psr);
1498
1499 if (pool->base.dccg != NULL)
1500 dcn_dccg_destroy(&pool->base.dccg);
1501
1502 if (pool->base.oem_device != NULL) {
1503 struct dc *dc = pool->base.oem_device->ctx->dc;
1504
1505 dc->link_srv->destroy_ddc_service(&pool->base.oem_device);
1506 }
1507 }
1508
1509
dcn401_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)1510 static bool dcn401_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1511 {
1512 int i;
1513 uint32_t dwb_count = pool->res_cap->num_dwb;
1514
1515 for (i = 0; i < dwb_count; i++) {
1516 struct dcn30_dwbc *dwbc401 = kzalloc(sizeof(struct dcn30_dwbc),
1517 GFP_KERNEL);
1518
1519 if (!dwbc401) {
1520 dm_error("DC: failed to create dwbc401!\n");
1521 return false;
1522 }
1523
1524
1525 #undef REG_STRUCT
1526 #define REG_STRUCT dwbc401_regs
1527 dwbc_regs_dcn401_init(0);
1528
1529 dcn30_dwbc_construct(dwbc401, ctx,
1530 &dwbc401_regs[i],
1531 &dwbc401_shift,
1532 &dwbc401_mask,
1533 i);
1534
1535 pool->dwbc[i] = &dwbc401->base;
1536
1537 }
1538 return true;
1539 }
1540
dcn401_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)1541 static bool dcn401_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1542 {
1543 int i;
1544 uint32_t dwb_count = pool->res_cap->num_dwb;
1545
1546 for (i = 0; i < dwb_count; i++) {
1547 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1548 GFP_KERNEL);
1549
1550 if (!mcif_wb30) {
1551 dm_error("DC: failed to create mcif_wb30!\n");
1552 return false;
1553 }
1554
1555 #undef REG_STRUCT
1556 #define REG_STRUCT mcif_wb30_regs
1557 mcif_wb_regs_dcn3_init(0);
1558
1559 dcn32_mmhubbub_construct(mcif_wb30, ctx,
1560 &mcif_wb30_regs[i],
1561 &mcif_wb30_shift,
1562 &mcif_wb30_mask,
1563 i);
1564
1565 pool->mcif_wb[i] = &mcif_wb30->base;
1566 }
1567 return true;
1568 }
1569
dcn401_dsc_create(struct dc_context * ctx,uint32_t inst)1570 static struct display_stream_compressor *dcn401_dsc_create(
1571 struct dc_context *ctx, uint32_t inst)
1572 {
1573 struct dcn401_dsc *dsc =
1574 kzalloc(sizeof(struct dcn401_dsc), GFP_KERNEL);
1575
1576 if (!dsc) {
1577 BREAK_TO_DEBUGGER();
1578 return NULL;
1579 }
1580
1581 #undef REG_STRUCT
1582 #define REG_STRUCT dsc_regs
1583 dsc_regs_init(0),
1584 dsc_regs_init(1),
1585 dsc_regs_init(2),
1586 dsc_regs_init(3);
1587
1588 dsc401_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1589 dsc401_set_fgcg(dsc,
1590 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);
1591
1592 //dsc->max_image_width = 6016;
1593 dsc->max_image_width = 5760;
1594
1595 return &dsc->base;
1596 }
1597
dcn401_destroy_resource_pool(struct resource_pool ** pool)1598 static void dcn401_destroy_resource_pool(struct resource_pool **pool)
1599 {
1600 struct dcn401_resource_pool *dcn401_pool = TO_DCN401_RES_POOL(*pool);
1601
1602 dcn401_resource_destruct(dcn401_pool);
1603 kfree(dcn401_pool);
1604 *pool = NULL;
1605 }
1606
1607 static struct dc_cap_funcs cap_funcs = {
1608 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap,
1609 .get_subvp_en = dcn32_subvp_in_use,
1610 };
1611
dcn401_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)1612 static void dcn401_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1613 {
1614 struct dml2_configuration_options *dml2_opt = &dc->dml2_tmp;
1615
1616 memcpy(dml2_opt, &dc->dml2_options, sizeof(dc->dml2_options));
1617
1618 /* re-calculate the available MALL size if required */
1619 if (bw_params->num_channels > 0) {
1620 dc->caps.max_cab_allocation_bytes = dcn401_calc_num_avail_chans_for_mall(
1621 dc, bw_params->num_channels) *
1622 dc->caps.mall_size_per_mem_channel * 1024 * 1024;
1623 dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes;
1624 }
1625
1626 DC_FP_START();
1627
1628 dcn401_update_bw_bounding_box_fpu(dc, bw_params);
1629
1630 dml2_opt->use_clock_dc_limits = false;
1631 if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2)
1632 dml2_reinit(dc, dml2_opt, &dc->current_state->bw_ctx.dml2);
1633
1634 dml2_opt->use_clock_dc_limits = true;
1635 if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2_dc_power_source)
1636 dml2_reinit(dc, dml2_opt, &dc->current_state->bw_ctx.dml2_dc_power_source);
1637
1638 DC_FP_END();
1639 }
1640
dcn401_patch_unknown_plane_state(struct dc_plane_state * plane_state)1641 enum dc_status dcn401_patch_unknown_plane_state(struct dc_plane_state *plane_state)
1642 {
1643 plane_state->tiling_info.gfxversion = DcGfxAddr3;
1644 plane_state->tiling_info.gfx_addr3.swizzle = DC_ADDR3_SW_64KB_2D;
1645 return DC_OK;
1646 }
1647
dcn401_validate_bandwidth(struct dc * dc,struct dc_state * context,bool fast_validate)1648 bool dcn401_validate_bandwidth(struct dc *dc,
1649 struct dc_state *context,
1650 bool fast_validate)
1651 {
1652 bool out = false;
1653 if (dc->debug.using_dml2)
1654 out = dml2_validate(dc, context,
1655 context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,
1656 fast_validate);
1657 return out;
1658 }
1659
dcn401_prepare_mcache_programming(struct dc * dc,struct dc_state * context)1660 void dcn401_prepare_mcache_programming(struct dc *dc,
1661 struct dc_state *context)
1662 {
1663 if (dc->debug.using_dml21)
1664 dml2_prepare_mcache_programming(dc, context,
1665 context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2);
1666 }
1667
dcn401_build_pipe_pix_clk_params(struct pipe_ctx * pipe_ctx)1668 static void dcn401_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx)
1669 {
1670 const struct dc_stream_state *stream = pipe_ctx->stream;
1671 struct dc_link *link = stream->link;
1672 struct link_encoder *link_enc = NULL;
1673 struct pixel_clk_params *pixel_clk_params = &pipe_ctx->stream_res.pix_clk_params;
1674
1675 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
1676
1677 link_enc = link_enc_cfg_get_link_enc(link);
1678 if (link_enc)
1679 pixel_clk_params->encoder_object_id = link_enc->id;
1680
1681 pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1682 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1683 /* TODO: un-hardcode*/
1684
1685 /* TODO - DP2.0 HW: calculate requested_sym_clk for UHBR rates */
1686
1687 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
1688 LINK_RATE_REF_FREQ_IN_KHZ;
1689 pixel_clk_params->flags.ENABLE_SS = 0;
1690 pixel_clk_params->color_depth =
1691 stream->timing.display_color_depth;
1692 pixel_clk_params->flags.DISPLAY_BLANKED = 1;
1693 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
1694
1695 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1696 pixel_clk_params->color_depth = COLOR_DEPTH_888;
1697
1698 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1699 pixel_clk_params->requested_pix_clk_100hz *= 2;
1700 if (dc_is_tmds_signal(stream->signal) &&
1701 stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1702 pixel_clk_params->requested_pix_clk_100hz /= 2;
1703
1704 pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1705 pipe_ctx->clock_source,
1706 &pipe_ctx->stream_res.pix_clk_params,
1707 &pipe_ctx->pll_settings);
1708
1709 pixel_clk_params->dio_se_pix_per_cycle = 1;
1710 if (dc_is_tmds_signal(stream->signal) &&
1711 stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
1712 pixel_clk_params->dio_se_pix_per_cycle = 2;
1713 } else if (dc_is_dp_signal(stream->signal)) {
1714 /* round up to nearest power of 2, or max at 8 pixels per cycle */
1715 if (pixel_clk_params->requested_pix_clk_100hz > 4 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) {
1716 pixel_clk_params->dio_se_pix_per_cycle = 8;
1717 } else if (pixel_clk_params->requested_pix_clk_100hz > 2 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) {
1718 pixel_clk_params->dio_se_pix_per_cycle = 4;
1719 } else if (pixel_clk_params->requested_pix_clk_100hz > stream->ctx->dc->clk_mgr->dprefclk_khz * 10) {
1720 pixel_clk_params->dio_se_pix_per_cycle = 2;
1721 } else {
1722 pixel_clk_params->dio_se_pix_per_cycle = 1;
1723 }
1724 }
1725 }
1726
dcn401_get_power_profile(const struct dc_state * context)1727 static int dcn401_get_power_profile(const struct dc_state *context)
1728 {
1729 int uclk_mhz = context->bw_ctx.bw.dcn.clk.dramclk_khz / 1000;
1730 int dpm_level = 0;
1731
1732 for (int i = 0; i < context->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; i++) {
1733 if (context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz == 0 ||
1734 uclk_mhz < context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz)
1735 break;
1736 if (uclk_mhz > context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz)
1737 dpm_level++;
1738 }
1739
1740 return dpm_level;
1741 }
1742
dcn401_get_vstartup_for_pipe(struct pipe_ctx * pipe_ctx)1743 static unsigned int dcn401_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx)
1744 {
1745 return pipe_ctx->global_sync.dcn4x.vstartup_lines;
1746 }
1747
1748 static struct resource_funcs dcn401_res_pool_funcs = {
1749 .destroy = dcn401_destroy_resource_pool,
1750 .link_enc_create = dcn401_link_encoder_create,
1751 .link_enc_create_minimal = NULL,
1752 .panel_cntl_create = dcn32_panel_cntl_create,
1753 .validate_bandwidth = dcn401_validate_bandwidth,
1754 .calculate_wm_and_dlg = NULL,
1755 .populate_dml_pipes = NULL,
1756 .acquire_free_pipe_as_secondary_dpp_pipe = dcn32_acquire_free_pipe_as_secondary_dpp_pipe,
1757 .acquire_free_pipe_as_secondary_opp_head = dcn32_acquire_free_pipe_as_secondary_opp_head,
1758 .release_pipe = dcn20_release_pipe,
1759 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1760 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1761 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1762 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1763 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1764 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1765 .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut,
1766 .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut,
1767 .update_bw_bounding_box = dcn401_update_bw_bounding_box,
1768 .patch_unknown_plane_state = dcn401_patch_unknown_plane_state,
1769 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
1770 .add_phantom_pipes = dcn32_add_phantom_pipes,
1771 .prepare_mcache_programming = dcn401_prepare_mcache_programming,
1772 .build_pipe_pix_clk_params = dcn401_build_pipe_pix_clk_params,
1773 .calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes,
1774 .get_power_profile = dcn401_get_power_profile,
1775 .get_vstartup_for_pipe = dcn401_get_vstartup_for_pipe
1776 };
1777
read_pipe_fuses(struct dc_context * ctx)1778 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1779 {
1780 uint32_t value = REG_READ(CC_DC_PIPE_DIS);
1781 /* DCN401 support max 4 pipes */
1782 value = value & 0xf;
1783 return value;
1784 }
1785
1786
dcn401_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn401_resource_pool * pool)1787 static bool dcn401_resource_construct(
1788 uint8_t num_virtual_links,
1789 struct dc *dc,
1790 struct dcn401_resource_pool *pool)
1791 {
1792 int i, j;
1793 struct dc_context *ctx = dc->ctx;
1794 struct irq_service_init_data init_data;
1795 struct ddc_service_init_data ddc_init_data = {0};
1796 uint32_t pipe_fuses = 0;
1797 uint32_t num_pipes = 4;
1798
1799 #undef REG_STRUCT
1800 #define REG_STRUCT bios_regs
1801 bios_regs_init();
1802
1803 #undef REG_STRUCT
1804 #define REG_STRUCT clk_src_regs
1805 clk_src_regs_init(0, A),
1806 clk_src_regs_init(1, B),
1807 clk_src_regs_init(2, C),
1808 clk_src_regs_init(3, D);
1809
1810 #undef REG_STRUCT
1811 #define REG_STRUCT abm_regs
1812 abm_regs_init(0),
1813 abm_regs_init(1),
1814 abm_regs_init(2),
1815 abm_regs_init(3);
1816
1817 #undef REG_STRUCT
1818 #define REG_STRUCT dccg_regs
1819 dccg_regs_init();
1820
1821 ctx->dc_bios->regs = &bios_regs;
1822
1823 pool->base.res_cap = &res_cap_dcn4_01;
1824
1825 /* max number of pipes for ASIC before checking for pipe fuses */
1826 num_pipes = pool->base.res_cap->num_timing_generator;
1827 pipe_fuses = read_pipe_fuses(ctx);
1828
1829 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++)
1830 if (pipe_fuses & 1 << i)
1831 num_pipes--;
1832
1833 if (pipe_fuses & 1)
1834 ASSERT(0); //Unexpected - Pipe 0 should always be fully functional!
1835
1836 if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK)
1837 ASSERT(0); //Entire DCN is harvested!
1838
1839 pool->base.funcs = &dcn401_res_pool_funcs;
1840
1841 /*************************************************
1842 * Resource + asic cap harcoding *
1843 *************************************************/
1844 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1845 pool->base.timing_generator_count = num_pipes;
1846 pool->base.pipe_count = num_pipes;
1847 pool->base.mpcc_count = num_pipes;
1848 dc->caps.max_downscale_ratio = 600;
1849 dc->caps.i2c_speed_in_khz = 95;
1850 dc->caps.i2c_speed_in_khz_hdcp = 95; /*1.4 w/a applied by default*/
1851 /* TODO: Bring max cursor size back to 256 after subvp cursor corruption is fixed*/
1852 dc->caps.max_cursor_size = 64;
1853 dc->caps.cursor_not_scaled = true;
1854 dc->caps.min_horizontal_blanking_period = 80;
1855 dc->caps.dmdata_alloc_size = 2048;
1856 dc->caps.mall_size_per_mem_channel = 4;
1857 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
1858 dc->caps.cache_line_size = 64;
1859 dc->caps.cache_num_ways = 16;
1860
1861 /* Calculate the available MALL space */
1862 dc->caps.max_cab_allocation_bytes = dcn401_calc_num_avail_chans_for_mall(
1863 dc, dc->ctx->dc_bios->vram_info.num_chans) *
1864 dc->caps.mall_size_per_mem_channel * 1024 * 1024;
1865 dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes;
1866
1867 dc->caps.subvp_fw_processing_delay_us = 15;
1868 dc->caps.subvp_drr_max_vblank_margin_us = 40;
1869 dc->caps.subvp_prefetch_end_to_mall_start_us = 15;
1870 dc->caps.subvp_swath_height_margin_lines = 16;
1871 dc->caps.subvp_pstate_allow_width_us = 20;
1872 dc->caps.subvp_vertical_int_margin_us = 30;
1873 dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin
1874
1875 dc->caps.max_slave_planes = 2;
1876 dc->caps.max_slave_yuv_planes = 2;
1877 dc->caps.max_slave_rgb_planes = 2;
1878 dc->caps.post_blend_color_processing = true;
1879 dc->caps.force_dp_tps4_for_cp2520 = true;
1880 dc->caps.dp_hpo = true;
1881 dc->caps.dp_hdmi21_pcon_support = true;
1882 dc->caps.edp_dsc_support = true;
1883 dc->caps.extended_aux_timeout_support = true;
1884 dc->caps.dmcub_support = true;
1885 dc->caps.max_v_total = (1 << 15) - 1;
1886 dc->caps.vtotal_limited_by_fp2 = true;
1887
1888 if (ASICREV_IS_GC_12_0_1_A0(dc->ctx->asic_id.hw_internal_rev))
1889 dc->caps.dcc_plane_width_limit = 7680;
1890
1891 /* Color pipeline capabilities */
1892 dc->caps.color.dpp.dcn_arch = 1;
1893 dc->caps.color.dpp.input_lut_shared = 0;
1894 dc->caps.color.dpp.icsc = 1;
1895 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1896 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1897 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1898 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1899 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1900 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1901 dc->caps.color.dpp.post_csc = 1;
1902 dc->caps.color.dpp.gamma_corr = 1;
1903 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1904
1905 dc->caps.color.dpp.hw_3d_lut = 1;
1906 dc->caps.color.dpp.ogam_ram = 1;
1907 // no OGAM ROM on DCN2 and later ASICs
1908 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1909 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1910 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1911 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1912 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1913 dc->caps.color.dpp.ocsc = 0;
1914
1915 dc->caps.color.mpc.gamut_remap = 1;
1916 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC
1917 dc->caps.color.mpc.ogam_ram = 1;
1918 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1919 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1920 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1921 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1922 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1923 dc->caps.color.mpc.ocsc = 1;
1924 dc->config.use_spl = true;
1925 dc->config.prefer_easf = true;
1926 dc->config.dc_mode_clk_limit_support = true;
1927 dc->config.enable_windowed_mpo_odm = true;
1928 dc->config.set_pipe_unlock_order = true; /* Need to ensure DET gets freed before allocating */
1929 /* read VBIOS LTTPR caps */
1930 {
1931 if (ctx->dc_bios->funcs->get_lttpr_caps) {
1932 enum bp_result bp_query_result;
1933 uint8_t is_vbios_lttpr_enable = 0;
1934
1935 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1936 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1937 }
1938
1939 /* interop bit is implicit */
1940 {
1941 dc->caps.vbios_lttpr_aware = true;
1942 }
1943 }
1944
1945 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1946 dc->debug = debug_defaults_drv;
1947
1948 // Init the vm_helper
1949 if (dc->vm_helper)
1950 vm_helper_init(dc->vm_helper, 16);
1951
1952 /*************************************************
1953 * Create resources *
1954 *************************************************/
1955
1956 /* Clock Sources for Pixel Clock*/
1957 pool->base.clock_sources[DCN401_CLK_SRC_PLL0] =
1958 dcn401_clock_source_create(ctx, ctx->dc_bios,
1959 CLOCK_SOURCE_COMBO_PHY_PLL0,
1960 &clk_src_regs[0], false);
1961 pool->base.clock_sources[DCN401_CLK_SRC_PLL1] =
1962 dcn401_clock_source_create(ctx, ctx->dc_bios,
1963 CLOCK_SOURCE_COMBO_PHY_PLL1,
1964 &clk_src_regs[1], false);
1965 pool->base.clock_sources[DCN401_CLK_SRC_PLL2] =
1966 dcn401_clock_source_create(ctx, ctx->dc_bios,
1967 CLOCK_SOURCE_COMBO_PHY_PLL2,
1968 &clk_src_regs[2], false);
1969 pool->base.clock_sources[DCN401_CLK_SRC_PLL3] =
1970 dcn401_clock_source_create(ctx, ctx->dc_bios,
1971 CLOCK_SOURCE_COMBO_PHY_PLL3,
1972 &clk_src_regs[3], false);
1973 // pool->base.clock_sources[DCN401_CLK_SRC_PLL4] =
1974 // dcn401_clock_source_create(ctx, ctx->dc_bios,
1975 // CLOCK_SOURCE_COMBO_PHY_PLL4,
1976 // &clk_src_regs[4], false);
1977
1978 pool->base.clk_src_count = DCN401_CLK_SRC_TOTAL;
1979
1980 /* todo: not reuse phy_pll registers */
1981 pool->base.dp_clock_source =
1982 dcn401_clock_source_create(ctx, ctx->dc_bios,
1983 CLOCK_SOURCE_ID_DP_DTO,
1984 &clk_src_regs[0], true);
1985
1986 for (i = 0; i < pool->base.clk_src_count; i++) {
1987 if (pool->base.clock_sources[i] == NULL) {
1988 dm_error("DC: failed to create clock sources!\n");
1989 BREAK_TO_DEBUGGER();
1990 goto create_fail;
1991 }
1992 }
1993
1994 /* DCCG */
1995 pool->base.dccg = dccg401_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1996 if (pool->base.dccg == NULL) {
1997 dm_error("DC: failed to create dccg!\n");
1998 BREAK_TO_DEBUGGER();
1999 goto create_fail;
2000 }
2001
2002 /* IRQ Service */
2003 init_data.ctx = dc->ctx;
2004 pool->base.irqs = dal_irq_service_dcn401_create(&init_data);
2005 if (!pool->base.irqs)
2006 goto create_fail;
2007
2008 /* HUBBUB */
2009 pool->base.hubbub = dcn401_hubbub_create(ctx);
2010 if (pool->base.hubbub == NULL) {
2011 BREAK_TO_DEBUGGER();
2012 dm_error("DC: failed to create hubbub!\n");
2013 goto create_fail;
2014 }
2015
2016 /* HUBPs, DPPs, OPPs, TGs, ABMs */
2017 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2018
2019 /* if pipe is disabled, skip instance of HW pipe,
2020 * i.e, skip ASIC register instance
2021 */
2022 if (pipe_fuses & 1 << i)
2023 continue;
2024
2025 pool->base.hubps[j] = dcn401_hubp_create(ctx, i);
2026 if (pool->base.hubps[j] == NULL) {
2027 BREAK_TO_DEBUGGER();
2028 dm_error(
2029 "DC: failed to create hubps!\n");
2030 goto create_fail;
2031 }
2032
2033 pool->base.dpps[j] = dcn401_dpp_create(ctx, i);
2034 if (pool->base.dpps[j] == NULL) {
2035 BREAK_TO_DEBUGGER();
2036 dm_error(
2037 "DC: failed to create dpps!\n");
2038 goto create_fail;
2039 }
2040
2041 pool->base.opps[j] = dcn401_opp_create(ctx, i);
2042 if (pool->base.opps[j] == NULL) {
2043 BREAK_TO_DEBUGGER();
2044 dm_error(
2045 "DC: failed to create output pixel processor!\n");
2046 goto create_fail;
2047 }
2048
2049 pool->base.timing_generators[j] = dcn401_timing_generator_create(
2050 ctx, i);
2051 if (pool->base.timing_generators[j] == NULL) {
2052 BREAK_TO_DEBUGGER();
2053 dm_error("DC: failed to create tg!\n");
2054 goto create_fail;
2055 }
2056
2057 pool->base.multiple_abms[j] = dmub_abm_create(ctx,
2058 &abm_regs[i],
2059 &abm_shift,
2060 &abm_mask);
2061 if (pool->base.multiple_abms[j] == NULL) {
2062 dm_error("DC: failed to create abm for pipe %d!\n", i);
2063 BREAK_TO_DEBUGGER();
2064 goto create_fail;
2065 }
2066
2067 /* index for resource pool arrays for next valid pipe */
2068 j++;
2069 }
2070
2071 /* PSR */
2072 pool->base.psr = dmub_psr_create(ctx);
2073 if (pool->base.psr == NULL) {
2074 dm_error("DC: failed to create psr obj!\n");
2075 BREAK_TO_DEBUGGER();
2076 goto create_fail;
2077 }
2078
2079 /* MPCCs */
2080 pool->base.mpc = dcn401_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut);
2081 if (pool->base.mpc == NULL) {
2082 BREAK_TO_DEBUGGER();
2083 dm_error("DC: failed to create mpc!\n");
2084 goto create_fail;
2085 }
2086
2087 /* DSCs */
2088 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2089 pool->base.dscs[i] = dcn401_dsc_create(ctx, i);
2090 if (pool->base.dscs[i] == NULL) {
2091 BREAK_TO_DEBUGGER();
2092 dm_error("DC: failed to create display stream compressor %d!\n", i);
2093 goto create_fail;
2094 }
2095 }
2096
2097 /* DWB */
2098 if (!dcn401_dwbc_create(ctx, &pool->base)) {
2099 BREAK_TO_DEBUGGER();
2100 dm_error("DC: failed to create dwbc!\n");
2101 goto create_fail;
2102 }
2103
2104 /* MMHUBBUB */
2105 if (!dcn401_mmhubbub_create(ctx, &pool->base)) {
2106 BREAK_TO_DEBUGGER();
2107 dm_error("DC: failed to create mcif_wb!\n");
2108 goto create_fail;
2109 }
2110
2111 /* AUX and I2C */
2112 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2113 pool->base.engines[i] = dcn401_aux_engine_create(ctx, i);
2114 if (pool->base.engines[i] == NULL) {
2115 BREAK_TO_DEBUGGER();
2116 dm_error(
2117 "DC:failed to create aux engine!!\n");
2118 goto create_fail;
2119 }
2120 pool->base.hw_i2cs[i] = dcn401_i2c_hw_create(ctx, i);
2121 if (pool->base.hw_i2cs[i] == NULL) {
2122 BREAK_TO_DEBUGGER();
2123 dm_error(
2124 "DC:failed to create hw i2c!!\n");
2125 goto create_fail;
2126 }
2127 pool->base.sw_i2cs[i] = NULL;
2128 }
2129
2130 /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2131 if (!resource_construct(num_virtual_links, dc, &pool->base,
2132 &res_create_funcs))
2133 goto create_fail;
2134
2135 /* HW Sequencer init functions and Plane caps */
2136 dcn401_hw_sequencer_init_functions(dc);
2137
2138 dc->caps.max_planes = pool->base.pipe_count;
2139
2140 for (i = 0; i < dc->caps.max_planes; ++i)
2141 dc->caps.planes[i] = plane_cap;
2142
2143 dc->cap_funcs = cap_funcs;
2144
2145 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
2146 ddc_init_data.ctx = dc->ctx;
2147 ddc_init_data.link = NULL;
2148 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
2149 ddc_init_data.id.enum_id = 0;
2150 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
2151 pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);
2152 } else {
2153 pool->base.oem_device = NULL;
2154 }
2155
2156 //For now enable SDPIF_REQUEST_RATE_LIMIT on DCN4_01 when vram_info.num_chans provided
2157 if (dc->config.sdpif_request_limit_words_per_umc == 0)
2158 dc->config.sdpif_request_limit_words_per_umc = 16;
2159
2160 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;
2161 dc->dml2_options.use_native_pstate_optimization = false;
2162 dc->dml2_options.use_native_soc_bb_construction = true;
2163 dc->dml2_options.minimize_dispclk_using_odm = true;
2164 dc->dml2_options.map_dc_pipes_with_callbacks = true;
2165 dc->dml2_options.force_tdlut_enable = true;
2166
2167 resource_init_common_dml2_callbacks(dc, &dc->dml2_options);
2168 dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;
2169 dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc;
2170 dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = pool->base.funcs->calculate_mall_ways_from_bytes;
2171
2172 dc->dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc->caps.subvp_fw_processing_delay_us;
2173 dc->dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc->caps.subvp_prefetch_end_to_mall_start_us;
2174 dc->dml2_options.svp_pstate.subvp_pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us;
2175 dc->dml2_options.svp_pstate.subvp_swath_height_margin_lines = dc->caps.subvp_swath_height_margin_lines;
2176
2177 dc->dml2_options.svp_pstate.force_disable_subvp = dc->debug.force_disable_subvp;
2178 dc->dml2_options.svp_pstate.force_enable_subvp = dc->debug.force_subvp_mclk_switch;
2179
2180 dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size;
2181 dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways;
2182 dc->dml2_options.mall_cfg.max_cab_allocation_bytes = dc->caps.max_cab_allocation_bytes;
2183 dc->dml2_options.mall_cfg.mblk_height_4bpe_pixels = DCN3_2_MBLK_HEIGHT_4BPE;
2184 dc->dml2_options.mall_cfg.mblk_height_8bpe_pixels = DCN3_2_MBLK_HEIGHT_8BPE;
2185 dc->dml2_options.mall_cfg.mblk_size_bytes = DCN3_2_MALL_MBLK_SIZE_BYTES;
2186 dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH;
2187
2188 dc->dml2_options.max_segments_per_hubp = 20;
2189 dc->dml2_options.det_segment_size = DCN4_01_CRB_SEGMENT_SIZE_KB;
2190
2191 /* SPL */
2192 spl_init_easf_filter_coeffs();
2193 spl_init_blur_scale_coeffs();
2194 dc->caps.scl_caps.sharpener_support = true;
2195
2196 return true;
2197
2198 create_fail:
2199
2200 dcn401_resource_destruct(pool);
2201
2202 return false;
2203 }
2204
dcn401_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2205 struct resource_pool *dcn401_create_resource_pool(
2206 const struct dc_init_data *init_data,
2207 struct dc *dc)
2208 {
2209 struct dcn401_resource_pool *pool =
2210 kzalloc(sizeof(struct dcn401_resource_pool), GFP_KERNEL);
2211
2212 if (!pool)
2213 return NULL;
2214
2215 if (dcn401_resource_construct(init_data->num_virtual_links, dc, pool))
2216 return &pool->base;
2217
2218 BREAK_TO_DEBUGGER();
2219 kfree(pool);
2220 return NULL;
2221 }
2222