1 /*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27 #include "dcn35_clk_mgr.h"
28
29 #include "dccg.h"
30 #include "clk_mgr_internal.h"
31
32 // For dce12_get_dp_ref_freq_khz
33 #include "dce100/dce_clk_mgr.h"
34
35 // For dcn20_update_clocks_update_dpp_dto
36 #include "dcn20/dcn20_clk_mgr.h"
37
38
39 #include "reg_helper.h"
40 #include "core_types.h"
41 #include "dcn35_smu.h"
42 #include "dm_helpers.h"
43
44 #include "dcn31/dcn31_clk_mgr.h"
45
46 #include "dc_dmub_srv.h"
47 #include "link.h"
48 #include "logger_types.h"
49
50 #undef DC_LOGGER
51 #define DC_LOGGER \
52 clk_mgr->base.base.ctx->logger
53
54 #define DCN_BASE__INST0_SEG1 0x000000C0
55 #define mmCLK1_CLK_PLL_REQ 0x16E37
56
57 #define mmCLK1_CLK0_DFS_CNTL 0x16E69
58 #define mmCLK1_CLK1_DFS_CNTL 0x16E6C
59 #define mmCLK1_CLK2_DFS_CNTL 0x16E6F
60 #define mmCLK1_CLK3_DFS_CNTL 0x16E72
61 #define mmCLK1_CLK4_DFS_CNTL 0x16E75
62 #define mmCLK1_CLK5_DFS_CNTL 0x16E78
63
64 #define mmCLK1_CLK0_CURRENT_CNT 0x16EFB
65 #define mmCLK1_CLK1_CURRENT_CNT 0x16EFC
66 #define mmCLK1_CLK2_CURRENT_CNT 0x16EFD
67 #define mmCLK1_CLK3_CURRENT_CNT 0x16EFE
68 #define mmCLK1_CLK4_CURRENT_CNT 0x16EFF
69 #define mmCLK1_CLK5_CURRENT_CNT 0x16F00
70
71 #define mmCLK1_CLK0_BYPASS_CNTL 0x16E8A
72 #define mmCLK1_CLK1_BYPASS_CNTL 0x16E93
73 #define mmCLK1_CLK2_BYPASS_CNTL 0x16E9C
74 #define mmCLK1_CLK3_BYPASS_CNTL 0x16EA5
75 #define mmCLK1_CLK4_BYPASS_CNTL 0x16EAE
76 #define mmCLK1_CLK5_BYPASS_CNTL 0x16EB7
77
78 #define mmCLK1_CLK0_DS_CNTL 0x16E83
79 #define mmCLK1_CLK1_DS_CNTL 0x16E8C
80 #define mmCLK1_CLK2_DS_CNTL 0x16E95
81 #define mmCLK1_CLK3_DS_CNTL 0x16E9E
82 #define mmCLK1_CLK4_DS_CNTL 0x16EA7
83 #define mmCLK1_CLK5_DS_CNTL 0x16EB0
84
85 #define mmCLK1_CLK0_ALLOW_DS 0x16E84
86 #define mmCLK1_CLK1_ALLOW_DS 0x16E8D
87 #define mmCLK1_CLK2_ALLOW_DS 0x16E96
88 #define mmCLK1_CLK3_ALLOW_DS 0x16E9F
89 #define mmCLK1_CLK4_ALLOW_DS 0x16EA8
90 #define mmCLK1_CLK5_ALLOW_DS 0x16EB1
91
92 #define mmCLK5_spll_field_8 0x1B24B
93 #define mmDENTIST_DISPCLK_CNTL 0x0124
94 #define regDENTIST_DISPCLK_CNTL 0x0064
95 #define regDENTIST_DISPCLK_CNTL_BASE_IDX 1
96
97 #define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
98 #define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc
99 #define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
100 #define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
101 #define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L
102 #define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
103
104 #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK 0x00000007L
105 #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV_MASK 0x000F0000L
106 // DENTIST_DISPCLK_CNTL
107 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0
108 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8
109 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13
110 #define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE__SHIFT 0x14
111 #define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER__SHIFT 0x18
112 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x0000007FL
113 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x00007F00L
114 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x00080000L
115 #define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE_MASK 0x00100000L
116 #define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER_MASK 0x7F000000L
117
118 #define CLK5_spll_field_8__spll_ssc_en_MASK 0x00002000L
119
120 #define SMU_VER_THRESHOLD 0x5D4A00 //93.74.0
121 #undef FN
122 #define FN(reg_name, field_name) \
123 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
124
125 #define REG(reg) \
126 (clk_mgr->regs->reg)
127
128 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
129
130 #define BASE(seg) BASE_INNER(seg)
131
132 #define SR(reg_name)\
133 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
134 reg ## reg_name
135
136 #define CLK_SR_DCN35(reg_name)\
137 .reg_name = mm ## reg_name
138
139 static const struct clk_mgr_registers clk_mgr_regs_dcn35 = {
140 CLK_REG_LIST_DCN35()
141 };
142
143 static const struct clk_mgr_shift clk_mgr_shift_dcn35 = {
144 CLK_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
145 };
146
147 static const struct clk_mgr_mask clk_mgr_mask_dcn35 = {
148 CLK_COMMON_MASK_SH_LIST_DCN32(_MASK)
149 };
150
151 #define TO_CLK_MGR_DCN35(clk_mgr)\
152 container_of(clk_mgr, struct clk_mgr_dcn35, base)
153
dcn35_get_active_display_cnt_wa(struct dc * dc,struct dc_state * context,int * all_active_disps)154 static int dcn35_get_active_display_cnt_wa(
155 struct dc *dc,
156 struct dc_state *context,
157 int *all_active_disps)
158 {
159 int i, display_count = 0;
160 bool tmds_present = false;
161
162 for (i = 0; i < context->stream_count; i++) {
163 const struct dc_stream_state *stream = context->streams[i];
164
165 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
166 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
167 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
168 tmds_present = true;
169 }
170
171 for (i = 0; i < dc->link_count; i++) {
172 const struct dc_link *link = dc->links[i];
173
174 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
175 if (link->link_enc && link->link_enc->funcs->is_dig_enabled &&
176 link->link_enc->funcs->is_dig_enabled(link->link_enc))
177 display_count++;
178 }
179 if (all_active_disps != NULL)
180 *all_active_disps = display_count;
181 /* WA for hang on HDMI after display off back on*/
182 if (display_count == 0 && tmds_present)
183 display_count = 1;
184
185 return display_count;
186 }
dcn35_disable_otg_wa(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower,bool disable)187 static void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context,
188 bool safe_to_lower, bool disable)
189 {
190 struct dc *dc = clk_mgr_base->ctx->dc;
191 int i;
192
193 if (dc->ctx->dce_environment == DCE_ENV_DIAG)
194 return;
195
196 for (i = 0; i < dc->res_pool->pipe_count; ++i) {
197 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
198 struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];
199 struct clk_mgr_internal *clk_mgr_internal = TO_CLK_MGR_INTERNAL(clk_mgr_base);
200 struct dccg *dccg = clk_mgr_internal->dccg;
201 struct pipe_ctx *pipe = safe_to_lower
202 ? &context->res_ctx.pipe_ctx[i]
203 : &dc->current_state->res_ctx.pipe_ctx[i];
204 bool stream_changed_otg_dig_on = false;
205 if (pipe->top_pipe || pipe->prev_odm_pipe)
206 continue;
207 stream_changed_otg_dig_on = old_pipe->stream && new_pipe->stream &&
208 old_pipe->stream != new_pipe->stream &&
209 old_pipe->stream_res.tg == new_pipe->stream_res.tg &&
210 new_pipe->stream->link_enc && !new_pipe->stream->dpms_off &&
211 new_pipe->stream->link_enc->funcs->is_dig_enabled &&
212 new_pipe->stream->link_enc->funcs->is_dig_enabled(
213 new_pipe->stream->link_enc) &&
214 new_pipe->stream_res.stream_enc &&
215 new_pipe->stream_res.stream_enc->funcs->is_fifo_enabled &&
216 new_pipe->stream_res.stream_enc->funcs->is_fifo_enabled(new_pipe->stream_res.stream_enc);
217
218 bool has_active_hpo = false;
219
220 if (old_pipe->stream && new_pipe->stream && old_pipe->stream == new_pipe->stream) {
221 has_active_hpo = dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(old_pipe) &&
222 dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(new_pipe);
223
224 }
225
226
227 if (!has_active_hpo && !dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe) &&
228 (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal) ||
229 !pipe->stream->link_enc) && !stream_changed_otg_dig_on)) {
230
231
232 /* This w/a should not trigger when we have a dig active */
233 if (disable) {
234 if (pipe->stream_res.tg && pipe->stream_res.tg->funcs->immediate_disable_crtc)
235 pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
236
237 reset_sync_context_for_pipe(dc, context, i);
238 } else {
239 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
240 }
241 }
242 }
243 }
244
dcn35_update_clocks_update_dtb_dto(struct clk_mgr_internal * clk_mgr,struct dc_state * context,int ref_dtbclk_khz)245 static void dcn35_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr,
246 struct dc_state *context,
247 int ref_dtbclk_khz)
248 {
249 struct dccg *dccg = clk_mgr->dccg;
250 uint32_t tg_mask = 0;
251 int i;
252
253 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
254 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
255 struct dtbclk_dto_params dto_params = {0};
256
257 /* use mask to program DTO once per tg */
258 if (pipe_ctx->stream_res.tg &&
259 !(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) {
260 tg_mask |= (1 << pipe_ctx->stream_res.tg->inst);
261
262 dto_params.otg_inst = pipe_ctx->stream_res.tg->inst;
263 dto_params.ref_dtbclk_khz = ref_dtbclk_khz;
264
265 dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params);
266 //dccg->funcs->set_audio_dtbclk_dto(clk_mgr->dccg, &dto_params);
267 }
268 }
269 }
270
dcn35_update_clocks_update_dpp_dto(struct clk_mgr_internal * clk_mgr,struct dc_state * context,bool safe_to_lower)271 static void dcn35_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
272 struct dc_state *context, bool safe_to_lower)
273 {
274 int i;
275 bool dppclk_active[MAX_PIPES] = {0};
276
277
278 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;
279 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
280 int dpp_inst = 0, dppclk_khz, prev_dppclk_khz;
281
282 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
283
284 if (context->res_ctx.pipe_ctx[i].plane_res.dpp)
285 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
286 else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {
287 /* dpp == NULL && dppclk_khz == 0 is valid because of pipe harvesting.
288 * In this case just continue in loop
289 */
290 continue;
291 } else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {
292 /* The software state is not valid if dpp resource is NULL and
293 * dppclk_khz > 0.
294 */
295 ASSERT(false);
296 continue;
297 }
298
299 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];
300
301 if (safe_to_lower || prev_dppclk_khz < dppclk_khz)
302 clk_mgr->dccg->funcs->update_dpp_dto(
303 clk_mgr->dccg, dpp_inst, dppclk_khz);
304 dppclk_active[dpp_inst] = true;
305 }
306 if (safe_to_lower)
307 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
308 struct dpp *old_dpp = clk_mgr->base.ctx->dc->current_state->res_ctx.pipe_ctx[i].plane_res.dpp;
309
310 if (old_dpp && !dppclk_active[old_dpp->inst])
311 clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, old_dpp->inst, 0);
312 }
313 }
314
get_lowest_dpia_index(const struct dc_link * link)315 static uint8_t get_lowest_dpia_index(const struct dc_link *link)
316 {
317 const struct dc *dc_struct = link->dc;
318 uint8_t idx = 0xFF;
319 int i;
320
321 for (i = 0; i < MAX_PIPES * 2; ++i) {
322 if (!dc_struct->links[i] || dc_struct->links[i]->ep_type != DISPLAY_ENDPOINT_USB4_DPIA)
323 continue;
324
325 if (idx > dc_struct->links[i]->link_index)
326 idx = dc_struct->links[i]->link_index;
327 }
328
329 return idx;
330 }
331
dcn35_notify_host_router_bw(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)332 static void dcn35_notify_host_router_bw(struct clk_mgr *clk_mgr_base, struct dc_state *context,
333 bool safe_to_lower)
334 {
335 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
336 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
337 uint32_t host_router_bw_kbps[MAX_HOST_ROUTERS_NUM] = { 0 };
338 int i;
339 for (i = 0; i < context->stream_count; ++i) {
340 const struct dc_stream_state *stream = context->streams[i];
341 const struct dc_link *link = stream->link;
342 uint8_t lowest_dpia_index = 0;
343 unsigned int hr_index = 0;
344
345 if (!link)
346 continue;
347
348 lowest_dpia_index = get_lowest_dpia_index(link);
349 if (link->link_index < lowest_dpia_index)
350 continue;
351
352 hr_index = (link->link_index - lowest_dpia_index) / 2;
353 if (hr_index >= MAX_HOST_ROUTERS_NUM)
354 continue;
355 host_router_bw_kbps[hr_index] += dc_bandwidth_in_kbps_from_timing(
356 &stream->timing, dc_link_get_highest_encoding_format(link));
357 }
358
359 for (i = 0; i < MAX_HOST_ROUTERS_NUM; ++i) {
360 new_clocks->host_router_bw_kbps[i] = host_router_bw_kbps[i];
361 if (should_set_clock(safe_to_lower, new_clocks->host_router_bw_kbps[i], clk_mgr_base->clks.host_router_bw_kbps[i])) {
362 clk_mgr_base->clks.host_router_bw_kbps[i] = new_clocks->host_router_bw_kbps[i];
363 dcn35_smu_notify_host_router_bw(clk_mgr, i, new_clocks->host_router_bw_kbps[i]);
364 }
365 }
366 }
367
dcn35_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)368 void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,
369 struct dc_state *context,
370 bool safe_to_lower)
371 {
372 union dmub_rb_cmd cmd;
373 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
374 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
375 struct dc *dc = clk_mgr_base->ctx->dc;
376 int display_count = 0;
377 bool update_dppclk = false;
378 bool update_dispclk = false;
379 bool dpp_clock_lowered = false;
380 int all_active_disps = 0;
381
382 if (dc->work_arounds.skip_clock_update)
383 return;
384
385 display_count = dcn35_get_active_display_cnt_wa(dc, context, &all_active_disps);
386 if (new_clocks->dtbclk_en && !new_clocks->ref_dtbclk_khz)
387 new_clocks->ref_dtbclk_khz = 600000;
388
389 /*
390 * if it is safe to lower, but we are already in the lower state, we don't have to do anything
391 * also if safe to lower is false, we just go in the higher state
392 */
393 if (safe_to_lower) {
394 if (new_clocks->zstate_support != DCN_ZSTATE_SUPPORT_DISALLOW &&
395 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) {
396 dcn35_smu_set_zstate_support(clk_mgr, new_clocks->zstate_support);
397 dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, true);
398 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
399 }
400
401 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) {
402 if (clk_mgr->base.ctx->dc->config.allow_0_dtb_clk)
403 dcn35_smu_set_dtbclk(clk_mgr, false);
404
405 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
406 }
407 /* check that we're not already in lower */
408 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
409 /* if we can go lower, go lower */
410 if (display_count == 0)
411 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
412 }
413 } else {
414 if (new_clocks->zstate_support == DCN_ZSTATE_SUPPORT_DISALLOW &&
415 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) {
416 dcn35_smu_set_zstate_support(clk_mgr, DCN_ZSTATE_SUPPORT_DISALLOW);
417 dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, false);
418 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
419 }
420
421 if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) {
422 int actual_dtbclk = 0;
423
424 dcn35_update_clocks_update_dtb_dto(clk_mgr, context, new_clocks->ref_dtbclk_khz);
425 dcn35_smu_set_dtbclk(clk_mgr, true);
426
427 actual_dtbclk = REG_READ(CLK1_CLK4_CURRENT_CNT);
428
429 if (actual_dtbclk) {
430 clk_mgr_base->clks.ref_dtbclk_khz = new_clocks->ref_dtbclk_khz;
431 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
432 }
433 }
434
435 /* check that we're not already in D0 */
436 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
437 union display_idle_optimization_u idle_info = { 0 };
438
439 dcn35_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
440 /* update power state */
441 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
442 }
443 }
444 if (dc->debug.force_min_dcfclk_mhz > 0)
445 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
446 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
447
448 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
449 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
450 dcn35_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
451 }
452
453 if (should_set_clock(safe_to_lower,
454 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
455 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
456 dcn35_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
457 }
458
459 // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
460 if (new_clocks->dppclk_khz < 100000)
461 new_clocks->dppclk_khz = 100000;
462
463 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
464 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
465 dpp_clock_lowered = true;
466 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
467 update_dppclk = true;
468 }
469
470 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
471 dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true);
472
473 if (dc->debug.min_disp_clk_khz > 0 && new_clocks->dispclk_khz < dc->debug.min_disp_clk_khz)
474 new_clocks->dispclk_khz = dc->debug.min_disp_clk_khz;
475
476 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
477 dcn35_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
478 dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false);
479
480 update_dispclk = true;
481 }
482
483 /* clock limits are received with MHz precision, divide by 1000 to prevent setting clocks at every call */
484 if (!dc->debug.disable_dtb_ref_clk_switch &&
485 should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000,
486 clk_mgr_base->clks.ref_dtbclk_khz / 1000)) {
487 dcn35_update_clocks_update_dtb_dto(clk_mgr, context, new_clocks->ref_dtbclk_khz);
488 clk_mgr_base->clks.ref_dtbclk_khz = new_clocks->ref_dtbclk_khz;
489 }
490
491 if (dpp_clock_lowered) {
492 // increase per DPP DTO before lowering global dppclk
493 dcn35_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
494 dcn35_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
495 } else {
496 // increase global DPPCLK before lowering per DPP DTO
497 if (update_dppclk || update_dispclk)
498 dcn35_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
499 dcn35_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
500 }
501
502 // notify PMFW of bandwidth per DPIA tunnel
503 if (dc->debug.notify_dpia_hr_bw)
504 dcn35_notify_host_router_bw(clk_mgr_base, context, safe_to_lower);
505
506 // notify DMCUB of latest clocks
507 memset(&cmd, 0, sizeof(cmd));
508 cmd.notify_clocks.header.type = DMUB_CMD__CLK_MGR;
509 cmd.notify_clocks.header.sub_type = DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS;
510 cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz;
511 cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz =
512 clk_mgr_base->clks.dcfclk_deep_sleep_khz;
513 cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz;
514 cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz;
515
516 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
517 }
518
get_vco_frequency_from_reg(struct clk_mgr_internal * clk_mgr)519 static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
520 {
521 /* get FbMult value */
522 struct fixed31_32 pll_req;
523 unsigned int fbmult_frac_val = 0;
524 unsigned int fbmult_int_val = 0;
525
526 /*
527 * Register value of fbmult is in 8.16 format, we are converting to 314.32
528 * to leverage the fix point operations available in driver
529 */
530
531 REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
532 REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
533
534 pll_req = dc_fixpt_from_int(fbmult_int_val);
535
536 /*
537 * since fractional part is only 16 bit in register definition but is 32 bit
538 * in our fix point definiton, need to shift left by 16 to obtain correct value
539 */
540 pll_req.value |= fbmult_frac_val << 16;
541
542 /* multiply by REFCLK period */
543 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
544
545 /* integer part is now VCO frequency in kHz */
546 return dc_fixpt_floor(pll_req);
547 }
548
dcn35_enable_pme_wa(struct clk_mgr * clk_mgr_base)549 static void dcn35_enable_pme_wa(struct clk_mgr *clk_mgr_base)
550 {
551 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
552
553 dcn35_smu_enable_pme_wa(clk_mgr);
554 }
555
556
dcn35_are_clock_states_equal(struct dc_clocks * a,struct dc_clocks * b)557 bool dcn35_are_clock_states_equal(struct dc_clocks *a,
558 struct dc_clocks *b)
559 {
560 if (a->dispclk_khz != b->dispclk_khz)
561 return false;
562 else if (a->dppclk_khz != b->dppclk_khz)
563 return false;
564 else if (a->dcfclk_khz != b->dcfclk_khz)
565 return false;
566 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
567 return false;
568 else if (a->zstate_support != b->zstate_support)
569 return false;
570 else if (a->dtbclk_en != b->dtbclk_en)
571 return false;
572
573 return true;
574 }
575
dcn35_dump_clk_registers(struct clk_state_registers_and_bypass * regs_and_bypass,struct clk_mgr_dcn35 * clk_mgr)576 static void dcn35_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
577 struct clk_mgr_dcn35 *clk_mgr)
578 {
579 }
580
dcn35_is_spll_ssc_enabled(struct clk_mgr * clk_mgr_base)581 static bool dcn35_is_spll_ssc_enabled(struct clk_mgr *clk_mgr_base)
582 {
583 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
584
585 uint32_t ssc_enable;
586
587 ssc_enable = REG_READ(CLK5_spll_field_8) & CLK5_spll_field_8__spll_ssc_en_MASK;
588
589 return ssc_enable != 0;
590 }
591
init_clk_states(struct clk_mgr * clk_mgr)592 static void init_clk_states(struct clk_mgr *clk_mgr)
593 {
594 uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz;
595
596 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
597
598 clk_mgr->clks.ref_dtbclk_khz = ref_dtbclk; // restore ref_dtbclk
599 clk_mgr->clks.p_state_change_support = true;
600 clk_mgr->clks.prev_p_state_change_support = true;
601 clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
602 clk_mgr->clks.zstate_support = DCN_ZSTATE_SUPPORT_UNKNOWN;
603 }
604
dcn35_init_clocks(struct clk_mgr * clk_mgr)605 void dcn35_init_clocks(struct clk_mgr *clk_mgr)
606 {
607 struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);
608
609 init_clk_states(clk_mgr);
610
611 // to adjust dp_dto reference clock if ssc is enable otherwise to apply dprefclk
612 if (dcn35_is_spll_ssc_enabled(clk_mgr))
613 clk_mgr->dp_dto_source_clock_in_khz =
614 dce_adjust_dp_ref_freq_for_ss(clk_mgr_int, clk_mgr->dprefclk_khz);
615 else
616 clk_mgr->dp_dto_source_clock_in_khz = clk_mgr->dprefclk_khz;
617
618 }
619 static struct clk_bw_params dcn35_bw_params = {
620 .vram_type = Ddr4MemType,
621 .num_channels = 1,
622 .clk_table = {
623 .num_entries = 4,
624 },
625
626 };
627
628 static struct wm_table ddr5_wm_table = {
629 .entries = {
630 {
631 .wm_inst = WM_A,
632 .wm_type = WM_TYPE_PSTATE_CHG,
633 .pstate_latency_us = 11.72,
634 .sr_exit_time_us = 28.0,
635 .sr_enter_plus_exit_time_us = 30.0,
636 .valid = true,
637 },
638 {
639 .wm_inst = WM_B,
640 .wm_type = WM_TYPE_PSTATE_CHG,
641 .pstate_latency_us = 11.72,
642 .sr_exit_time_us = 28.0,
643 .sr_enter_plus_exit_time_us = 30.0,
644 .valid = true,
645 },
646 {
647 .wm_inst = WM_C,
648 .wm_type = WM_TYPE_PSTATE_CHG,
649 .pstate_latency_us = 11.72,
650 .sr_exit_time_us = 28.0,
651 .sr_enter_plus_exit_time_us = 30.0,
652 .valid = true,
653 },
654 {
655 .wm_inst = WM_D,
656 .wm_type = WM_TYPE_PSTATE_CHG,
657 .pstate_latency_us = 11.72,
658 .sr_exit_time_us = 28.0,
659 .sr_enter_plus_exit_time_us = 30.0,
660 .valid = true,
661 },
662 }
663 };
664
665 static struct wm_table lpddr5_wm_table = {
666 .entries = {
667 {
668 .wm_inst = WM_A,
669 .wm_type = WM_TYPE_PSTATE_CHG,
670 .pstate_latency_us = 11.65333,
671 .sr_exit_time_us = 28.0,
672 .sr_enter_plus_exit_time_us = 30.0,
673 .valid = true,
674 },
675 {
676 .wm_inst = WM_B,
677 .wm_type = WM_TYPE_PSTATE_CHG,
678 .pstate_latency_us = 11.65333,
679 .sr_exit_time_us = 28.0,
680 .sr_enter_plus_exit_time_us = 30.0,
681 .valid = true,
682 },
683 {
684 .wm_inst = WM_C,
685 .wm_type = WM_TYPE_PSTATE_CHG,
686 .pstate_latency_us = 11.65333,
687 .sr_exit_time_us = 28.0,
688 .sr_enter_plus_exit_time_us = 30.0,
689 .valid = true,
690 },
691 {
692 .wm_inst = WM_D,
693 .wm_type = WM_TYPE_PSTATE_CHG,
694 .pstate_latency_us = 11.65333,
695 .sr_exit_time_us = 28.0,
696 .sr_enter_plus_exit_time_us = 30.0,
697 .valid = true,
698 },
699 }
700 };
701
702 static DpmClocks_t_dcn35 dummy_clocks;
703 static DpmClocks_t_dcn351 dummy_clocks_dcn351;
704
705 static struct dcn35_watermarks dummy_wms = { 0 };
706
707 static struct dcn35_ss_info_table ss_info_table = {
708 .ss_divider = 1000,
709 .ss_percentage = {0, 0, 375, 375, 375}
710 };
711
dcn35_read_ss_info_from_lut(struct clk_mgr_internal * clk_mgr)712 static void dcn35_read_ss_info_from_lut(struct clk_mgr_internal *clk_mgr)
713 {
714 uint32_t clock_source = 0;
715
716 clock_source = REG_READ(CLK1_CLK2_BYPASS_CNTL) & CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK;
717
718 // If it's DFS mode, clock_source is 0.
719 if (dcn35_is_spll_ssc_enabled(&clk_mgr->base) && (clock_source < ARRAY_SIZE(ss_info_table.ss_percentage))) {
720 clk_mgr->dprefclk_ss_percentage = ss_info_table.ss_percentage[clock_source];
721
722 if (clk_mgr->dprefclk_ss_percentage != 0) {
723 clk_mgr->ss_on_dprefclk = true;
724 clk_mgr->dprefclk_ss_divider = ss_info_table.ss_divider;
725 }
726 }
727 }
728
dcn35_build_watermark_ranges(struct clk_bw_params * bw_params,struct dcn35_watermarks * table)729 static void dcn35_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn35_watermarks *table)
730 {
731 int i, num_valid_sets;
732
733 num_valid_sets = 0;
734
735 for (i = 0; i < WM_SET_COUNT; i++) {
736 /* skip empty entries, the smu array has no holes*/
737 if (!bw_params->wm_table.entries[i].valid)
738 continue;
739
740 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
741 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
742 /* We will not select WM based on fclk, so leave it as unconstrained */
743 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
744 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
745
746 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
747 if (i == 0)
748 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
749 else {
750 /* add 1 to make it non-overlapping with next lvl */
751 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
752 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
753 }
754 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
755 bw_params->clk_table.entries[i].dcfclk_mhz;
756
757 } else {
758 /* unconstrained for memory retraining */
759 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
760 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
761
762 /* Modify previous watermark range to cover up to max */
763 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
764 }
765 num_valid_sets++;
766 }
767
768 ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
769
770 /* modify the min and max to make sure we cover the whole range*/
771 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;
772 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;
773 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;
774 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
775
776 /* This is for writeback only, does not matter currently as no writeback support*/
777 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
778 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;
779 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;
780 table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;
781 table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;
782 }
783
dcn35_notify_wm_ranges(struct clk_mgr * clk_mgr_base)784 static void dcn35_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
785 {
786 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
787 struct clk_mgr_dcn35 *clk_mgr_dcn35 = TO_CLK_MGR_DCN35(clk_mgr);
788 struct dcn35_watermarks *table = clk_mgr_dcn35->smu_wm_set.wm_set;
789
790 if (!clk_mgr->smu_ver)
791 return;
792
793 if (!table || clk_mgr_dcn35->smu_wm_set.mc_address.quad_part == 0)
794 return;
795
796 memset(table, 0, sizeof(*table));
797
798 dcn35_build_watermark_ranges(clk_mgr_base->bw_params, table);
799
800 dcn35_smu_set_dram_addr_high(clk_mgr,
801 clk_mgr_dcn35->smu_wm_set.mc_address.high_part);
802 dcn35_smu_set_dram_addr_low(clk_mgr,
803 clk_mgr_dcn35->smu_wm_set.mc_address.low_part);
804 dcn35_smu_transfer_wm_table_dram_2_smu(clk_mgr);
805 }
806
dcn35_get_dpm_table_from_smu(struct clk_mgr_internal * clk_mgr,struct dcn35_smu_dpm_clks * smu_dpm_clks)807 static void dcn35_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
808 struct dcn35_smu_dpm_clks *smu_dpm_clks)
809 {
810 DpmClocks_t_dcn35 *table = smu_dpm_clks->dpm_clks;
811
812 if (!clk_mgr->smu_ver)
813 return;
814
815 if (!table || smu_dpm_clks->mc_address.quad_part == 0)
816 return;
817
818 memset(table, 0, sizeof(*table));
819
820 dcn35_smu_set_dram_addr_high(clk_mgr,
821 smu_dpm_clks->mc_address.high_part);
822 dcn35_smu_set_dram_addr_low(clk_mgr,
823 smu_dpm_clks->mc_address.low_part);
824 dcn35_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
825 }
826
dcn351_get_dpm_table_from_smu(struct clk_mgr_internal * clk_mgr,struct dcn351_smu_dpm_clks * smu_dpm_clks)827 static void dcn351_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
828 struct dcn351_smu_dpm_clks *smu_dpm_clks)
829 {
830 DpmClocks_t_dcn351 *table = smu_dpm_clks->dpm_clks;
831
832 if (!clk_mgr->smu_ver)
833 return;
834 if (!table || smu_dpm_clks->mc_address.quad_part == 0)
835 return;
836 memset(table, 0, sizeof(*table));
837 dcn35_smu_set_dram_addr_high(clk_mgr,
838 smu_dpm_clks->mc_address.high_part);
839 dcn35_smu_set_dram_addr_low(clk_mgr,
840 smu_dpm_clks->mc_address.low_part);
841 dcn35_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
842 }
find_max_clk_value(const uint32_t clocks[],uint32_t num_clocks)843 static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks)
844 {
845 uint32_t max = 0;
846 int i;
847
848 for (i = 0; i < num_clocks; ++i) {
849 if (clocks[i] > max)
850 max = clocks[i];
851 }
852
853 return max;
854 }
855
is_valid_clock_value(uint32_t clock_value)856 static inline bool is_valid_clock_value(uint32_t clock_value)
857 {
858 return clock_value > 1 && clock_value < 100000;
859 }
860
convert_wck_ratio(uint8_t wck_ratio)861 static unsigned int convert_wck_ratio(uint8_t wck_ratio)
862 {
863 switch (wck_ratio) {
864 case WCK_RATIO_1_2:
865 return 2;
866
867 case WCK_RATIO_1_4:
868 return 4;
869 /* Find lowest DPM, FCLK is filled in reverse order*/
870
871 default:
872 break;
873 }
874
875 return 1;
876 }
877
calc_dram_speed_mts(const MemPstateTable_t * entry)878 static inline uint32_t calc_dram_speed_mts(const MemPstateTable_t *entry)
879 {
880 return entry->UClk * convert_wck_ratio(entry->WckRatio) * 2;
881 }
882
dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal * clk_mgr,struct integrated_info * bios_info,DpmClocks_t_dcn35 * clock_table)883 static void dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk_mgr,
884 struct integrated_info *bios_info,
885 DpmClocks_t_dcn35 *clock_table)
886 {
887 struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
888 struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entries - 1];
889 uint32_t max_fclk = 0, min_pstate = 0, max_dispclk = 0, max_dppclk = 0;
890 uint32_t max_pstate = 0, max_dram_speed_mts = 0, min_dram_speed_mts = 0;
891 uint32_t num_memps, num_fclk, num_dcfclk;
892 int i;
893
894 /* Determine min/max p-state values. */
895 num_memps = (clock_table->NumMemPstatesEnabled > NUM_MEM_PSTATE_LEVELS) ? NUM_MEM_PSTATE_LEVELS :
896 clock_table->NumMemPstatesEnabled;
897 for (i = 0; i < num_memps; i++) {
898 uint32_t dram_speed_mts = calc_dram_speed_mts(&clock_table->MemPstateTable[i]);
899
900 if (is_valid_clock_value(dram_speed_mts) && dram_speed_mts > max_dram_speed_mts) {
901 max_dram_speed_mts = dram_speed_mts;
902 max_pstate = i;
903 }
904 }
905
906 min_dram_speed_mts = max_dram_speed_mts;
907 min_pstate = max_pstate;
908
909 for (i = 0; i < num_memps; i++) {
910 uint32_t dram_speed_mts = calc_dram_speed_mts(&clock_table->MemPstateTable[i]);
911
912 if (is_valid_clock_value(dram_speed_mts) && dram_speed_mts < min_dram_speed_mts) {
913 min_dram_speed_mts = dram_speed_mts;
914 min_pstate = i;
915 }
916 }
917
918 /* We expect the table to contain at least one valid P-state entry. */
919 ASSERT(clock_table->NumMemPstatesEnabled &&
920 is_valid_clock_value(max_dram_speed_mts) &&
921 is_valid_clock_value(min_dram_speed_mts));
922
923 /* dispclk and dppclk can be max at any voltage, same number of levels for both */
924 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS &&
925 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) {
926 max_dispclk = find_max_clk_value(clock_table->DispClocks,
927 clock_table->NumDispClkLevelsEnabled);
928 max_dppclk = find_max_clk_value(clock_table->DppClocks,
929 clock_table->NumDispClkLevelsEnabled);
930 } else {
931 /* Invalid number of entries in the table from PMFW. */
932 ASSERT(0);
933 }
934
935 /* Base the clock table on dcfclk, need at least one entry regardless of pmfw table */
936 ASSERT(clock_table->NumDcfClkLevelsEnabled > 0);
937
938 num_fclk = (clock_table->NumFclkLevelsEnabled > NUM_FCLK_DPM_LEVELS) ? NUM_FCLK_DPM_LEVELS :
939 clock_table->NumFclkLevelsEnabled;
940 max_fclk = find_max_clk_value(clock_table->FclkClocks_Freq, num_fclk);
941
942 num_dcfclk = (clock_table->NumDcfClkLevelsEnabled > NUM_DCFCLK_DPM_LEVELS) ? NUM_DCFCLK_DPM_LEVELS :
943 clock_table->NumDcfClkLevelsEnabled;
944 for (i = 0; i < num_dcfclk; i++) {
945 int j;
946
947 /* First search defaults for the clocks we don't read using closest lower or equal default dcfclk */
948 for (j = bw_params->clk_table.num_entries - 1; j > 0; j--)
949 if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i])
950 break;
951
952 bw_params->clk_table.entries[i].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz;
953 bw_params->clk_table.entries[i].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz;
954 bw_params->clk_table.entries[i].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz;
955
956 /* Now update clocks we do read */
957 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemPstateTable[min_pstate].MemClk;
958 bw_params->clk_table.entries[i].voltage = clock_table->MemPstateTable[min_pstate].Voltage;
959 bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i];
960 bw_params->clk_table.entries[i].socclk_mhz = clock_table->SocClocks[i];
961 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
962 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
963 bw_params->clk_table.entries[i].wck_ratio =
964 convert_wck_ratio(clock_table->MemPstateTable[min_pstate].WckRatio);
965
966 /* Dcfclk and Fclk are tied, but at a different ratio */
967 bw_params->clk_table.entries[i].fclk_mhz = min(max_fclk, 2 * clock_table->DcfClocks[i]);
968 }
969
970 /* Make sure to include at least one entry at highest pstate */
971 if (max_pstate != min_pstate || i == 0) {
972 if (i > MAX_NUM_DPM_LVL - 1)
973 i = MAX_NUM_DPM_LVL - 1;
974
975 bw_params->clk_table.entries[i].fclk_mhz = max_fclk;
976 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemPstateTable[max_pstate].MemClk;
977 bw_params->clk_table.entries[i].voltage = clock_table->MemPstateTable[max_pstate].Voltage;
978 bw_params->clk_table.entries[i].dcfclk_mhz =
979 find_max_clk_value(clock_table->DcfClocks, NUM_DCFCLK_DPM_LEVELS);
980 bw_params->clk_table.entries[i].socclk_mhz =
981 find_max_clk_value(clock_table->SocClocks, NUM_SOCCLK_DPM_LEVELS);
982 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
983 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
984 bw_params->clk_table.entries[i].wck_ratio = convert_wck_ratio(
985 clock_table->MemPstateTable[max_pstate].WckRatio);
986 i++;
987 }
988 bw_params->clk_table.num_entries = i--;
989
990 /* Make sure all highest clocks are included*/
991 bw_params->clk_table.entries[i].socclk_mhz =
992 find_max_clk_value(clock_table->SocClocks, NUM_SOCCLK_DPM_LEVELS);
993 bw_params->clk_table.entries[i].dispclk_mhz =
994 find_max_clk_value(clock_table->DispClocks, NUM_DISPCLK_DPM_LEVELS);
995 bw_params->clk_table.entries[i].dppclk_mhz =
996 find_max_clk_value(clock_table->DppClocks, NUM_DPPCLK_DPM_LEVELS);
997 bw_params->clk_table.entries[i].fclk_mhz =
998 find_max_clk_value(clock_table->FclkClocks_Freq, NUM_FCLK_DPM_LEVELS);
999 ASSERT(clock_table->DcfClocks[i] == find_max_clk_value(clock_table->DcfClocks, NUM_DCFCLK_DPM_LEVELS));
1000 bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz;
1001 bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz;
1002 bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz;
1003 bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels = clock_table->NumDcfClkLevelsEnabled;
1004 bw_params->clk_table.num_entries_per_clk.num_dispclk_levels = clock_table->NumDispClkLevelsEnabled;
1005 bw_params->clk_table.num_entries_per_clk.num_dppclk_levels = clock_table->NumDispClkLevelsEnabled;
1006 bw_params->clk_table.num_entries_per_clk.num_fclk_levels = clock_table->NumFclkLevelsEnabled;
1007 bw_params->clk_table.num_entries_per_clk.num_memclk_levels = clock_table->NumMemPstatesEnabled;
1008 bw_params->clk_table.num_entries_per_clk.num_socclk_levels = clock_table->NumSocClkLevelsEnabled;
1009
1010 /*
1011 * Set any 0 clocks to max default setting. Not an issue for
1012 * power since we aren't doing switching in such case anyway
1013 */
1014 for (i = 0; i < bw_params->clk_table.num_entries; i++) {
1015 if (!bw_params->clk_table.entries[i].fclk_mhz) {
1016 bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz;
1017 bw_params->clk_table.entries[i].memclk_mhz = def_max.memclk_mhz;
1018 bw_params->clk_table.entries[i].voltage = def_max.voltage;
1019 }
1020 if (!bw_params->clk_table.entries[i].dcfclk_mhz)
1021 bw_params->clk_table.entries[i].dcfclk_mhz = def_max.dcfclk_mhz;
1022 if (!bw_params->clk_table.entries[i].socclk_mhz)
1023 bw_params->clk_table.entries[i].socclk_mhz = def_max.socclk_mhz;
1024 if (!bw_params->clk_table.entries[i].dispclk_mhz)
1025 bw_params->clk_table.entries[i].dispclk_mhz = def_max.dispclk_mhz;
1026 if (!bw_params->clk_table.entries[i].dppclk_mhz)
1027 bw_params->clk_table.entries[i].dppclk_mhz = def_max.dppclk_mhz;
1028 if (!bw_params->clk_table.entries[i].fclk_mhz)
1029 bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz;
1030 if (!bw_params->clk_table.entries[i].phyclk_mhz)
1031 bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz;
1032 if (!bw_params->clk_table.entries[i].phyclk_d18_mhz)
1033 bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz;
1034 if (!bw_params->clk_table.entries[i].dtbclk_mhz)
1035 bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz;
1036 }
1037 ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz);
1038 bw_params->vram_type = bios_info->memory_type;
1039 bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4;
1040 bw_params->num_channels = bios_info->ma_channel_number ? bios_info->ma_channel_number : 4;
1041
1042 for (i = 0; i < WM_SET_COUNT; i++) {
1043 bw_params->wm_table.entries[i].wm_inst = i;
1044
1045 if (i >= bw_params->clk_table.num_entries) {
1046 bw_params->wm_table.entries[i].valid = false;
1047 continue;
1048 }
1049
1050 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
1051 bw_params->wm_table.entries[i].valid = true;
1052 }
1053 }
1054
dcn35_set_low_power_state(struct clk_mgr * clk_mgr_base)1055 static void dcn35_set_low_power_state(struct clk_mgr *clk_mgr_base)
1056 {
1057 int display_count;
1058 struct dc *dc = clk_mgr_base->ctx->dc;
1059 struct dc_state *context = dc->current_state;
1060
1061 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
1062 display_count = dcn35_get_active_display_cnt_wa(dc, context, NULL);
1063 /* if we can go lower, go lower */
1064 if (display_count == 0)
1065 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
1066 }
1067 }
1068
dcn35_exit_low_power_state(struct clk_mgr * clk_mgr_base)1069 static void dcn35_exit_low_power_state(struct clk_mgr *clk_mgr_base)
1070 {
1071 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1072
1073 //SMU optimization is performed part of low power state exit.
1074 dcn35_smu_exit_low_power_state(clk_mgr);
1075
1076 }
1077
dcn35_is_ips_supported(struct clk_mgr * clk_mgr_base)1078 static bool dcn35_is_ips_supported(struct clk_mgr *clk_mgr_base)
1079 {
1080 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1081
1082 return dcn35_smu_get_ips_supported(clk_mgr) ? true : false;
1083 }
1084
dcn35_init_clocks_fpga(struct clk_mgr * clk_mgr)1085 static void dcn35_init_clocks_fpga(struct clk_mgr *clk_mgr)
1086 {
1087 init_clk_states(clk_mgr);
1088
1089 /* TODO: Implement the functions and remove the ifndef guard */
1090 }
1091
dcn35_update_clocks_fpga(struct clk_mgr * clk_mgr,struct dc_state * context,bool safe_to_lower)1092 static void dcn35_update_clocks_fpga(struct clk_mgr *clk_mgr,
1093 struct dc_state *context,
1094 bool safe_to_lower)
1095 {
1096 struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);
1097 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
1098 int fclk_adj = new_clocks->fclk_khz;
1099
1100 /* TODO: remove this after correctly set by DML */
1101 new_clocks->dcfclk_khz = 400000;
1102 new_clocks->socclk_khz = 400000;
1103
1104 /* Min fclk = 1.2GHz since all the extra scemi logic seems to run off of it */
1105 //int fclk_adj = new_clocks->fclk_khz > 1200000 ? new_clocks->fclk_khz : 1200000;
1106 new_clocks->fclk_khz = 4320000;
1107
1108 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr->clks.phyclk_khz)) {
1109 clk_mgr->clks.phyclk_khz = new_clocks->phyclk_khz;
1110 }
1111
1112 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr->clks.dcfclk_khz)) {
1113 clk_mgr->clks.dcfclk_khz = new_clocks->dcfclk_khz;
1114 }
1115
1116 if (should_set_clock(safe_to_lower,
1117 new_clocks->dcfclk_deep_sleep_khz, clk_mgr->clks.dcfclk_deep_sleep_khz)) {
1118 clk_mgr->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
1119 }
1120
1121 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr->clks.socclk_khz)) {
1122 clk_mgr->clks.socclk_khz = new_clocks->socclk_khz;
1123 }
1124
1125 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr->clks.dramclk_khz)) {
1126 clk_mgr->clks.dramclk_khz = new_clocks->dramclk_khz;
1127 }
1128
1129 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->clks.dppclk_khz)) {
1130 clk_mgr->clks.dppclk_khz = new_clocks->dppclk_khz;
1131 }
1132
1133 if (should_set_clock(safe_to_lower, fclk_adj, clk_mgr->clks.fclk_khz)) {
1134 clk_mgr->clks.fclk_khz = fclk_adj;
1135 }
1136
1137 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr->clks.dispclk_khz)) {
1138 clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz;
1139 }
1140
1141 /* Both fclk and ref_dppclk run on the same scemi clock.
1142 * So take the higher value since the DPP DTO is typically programmed
1143 * such that max dppclk is 1:1 with ref_dppclk.
1144 */
1145 if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz)
1146 clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz;
1147 if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz)
1148 clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz;
1149
1150 // Both fclk and ref_dppclk run on the same scemi clock.
1151 clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz;
1152
1153 /* TODO: set dtbclk in correct place */
1154 clk_mgr->clks.dtbclk_en = true;
1155 dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks);
1156 dcn35_update_clocks_update_dpp_dto(clk_mgr_int, context, safe_to_lower);
1157
1158 dcn35_update_clocks_update_dtb_dto(clk_mgr_int, context, clk_mgr->clks.ref_dtbclk_khz);
1159 }
1160
1161 static struct clk_mgr_funcs dcn35_funcs = {
1162 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
1163 .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
1164 .update_clocks = dcn35_update_clocks,
1165 .init_clocks = dcn35_init_clocks,
1166 .enable_pme_wa = dcn35_enable_pme_wa,
1167 .are_clock_states_equal = dcn35_are_clock_states_equal,
1168 .notify_wm_ranges = dcn35_notify_wm_ranges,
1169 .set_low_power_state = dcn35_set_low_power_state,
1170 .exit_low_power_state = dcn35_exit_low_power_state,
1171 .is_ips_supported = dcn35_is_ips_supported,
1172 };
1173
1174 struct clk_mgr_funcs dcn35_fpga_funcs = {
1175 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
1176 .update_clocks = dcn35_update_clocks_fpga,
1177 .init_clocks = dcn35_init_clocks_fpga,
1178 .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
1179 };
1180
translate_to_DpmClocks_t_dcn35(struct dcn351_smu_dpm_clks * smu_dpm_clks_a,struct dcn35_smu_dpm_clks * smu_dpm_clks_b)1181 static void translate_to_DpmClocks_t_dcn35(struct dcn351_smu_dpm_clks *smu_dpm_clks_a,
1182 struct dcn35_smu_dpm_clks *smu_dpm_clks_b)
1183 {
1184 /*translate two structures and only take need clock tables*/
1185 uint8_t i;
1186
1187 if (smu_dpm_clks_a == NULL || smu_dpm_clks_b == NULL ||
1188 smu_dpm_clks_a->dpm_clks == NULL || smu_dpm_clks_b->dpm_clks == NULL)
1189 return;
1190
1191 for (i = 0; i < NUM_DCFCLK_DPM_LEVELS; i++)
1192 smu_dpm_clks_b->dpm_clks->DcfClocks[i] = smu_dpm_clks_a->dpm_clks->DcfClocks[i];
1193
1194 for (i = 0; i < NUM_DISPCLK_DPM_LEVELS; i++)
1195 smu_dpm_clks_b->dpm_clks->DispClocks[i] = smu_dpm_clks_a->dpm_clks->DispClocks[i];
1196
1197 for (i = 0; i < NUM_DPPCLK_DPM_LEVELS; i++)
1198 smu_dpm_clks_b->dpm_clks->DppClocks[i] = smu_dpm_clks_a->dpm_clks->DppClocks[i];
1199
1200 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
1201 smu_dpm_clks_b->dpm_clks->FclkClocks_Freq[i] = smu_dpm_clks_a->dpm_clks->FclkClocks_Freq[i];
1202 smu_dpm_clks_b->dpm_clks->FclkClocks_Voltage[i] = smu_dpm_clks_a->dpm_clks->FclkClocks_Voltage[i];
1203 }
1204 for (i = 0; i < NUM_MEM_PSTATE_LEVELS; i++) {
1205 smu_dpm_clks_b->dpm_clks->MemPstateTable[i].MemClk =
1206 smu_dpm_clks_a->dpm_clks->MemPstateTable[i].MemClk;
1207 smu_dpm_clks_b->dpm_clks->MemPstateTable[i].UClk =
1208 smu_dpm_clks_a->dpm_clks->MemPstateTable[i].UClk;
1209 smu_dpm_clks_b->dpm_clks->MemPstateTable[i].Voltage =
1210 smu_dpm_clks_a->dpm_clks->MemPstateTable[i].Voltage;
1211 smu_dpm_clks_b->dpm_clks->MemPstateTable[i].WckRatio =
1212 smu_dpm_clks_a->dpm_clks->MemPstateTable[i].WckRatio;
1213 }
1214 smu_dpm_clks_b->dpm_clks->MaxGfxClk = smu_dpm_clks_a->dpm_clks->MaxGfxClk;
1215 smu_dpm_clks_b->dpm_clks->MinGfxClk = smu_dpm_clks_a->dpm_clks->MinGfxClk;
1216 smu_dpm_clks_b->dpm_clks->NumDcfClkLevelsEnabled =
1217 smu_dpm_clks_a->dpm_clks->NumDcfClkLevelsEnabled;
1218 smu_dpm_clks_b->dpm_clks->NumDispClkLevelsEnabled =
1219 smu_dpm_clks_a->dpm_clks->NumDispClkLevelsEnabled;
1220 smu_dpm_clks_b->dpm_clks->NumFclkLevelsEnabled =
1221 smu_dpm_clks_a->dpm_clks->NumFclkLevelsEnabled;
1222 smu_dpm_clks_b->dpm_clks->NumMemPstatesEnabled =
1223 smu_dpm_clks_a->dpm_clks->NumMemPstatesEnabled;
1224 smu_dpm_clks_b->dpm_clks->NumSocClkLevelsEnabled =
1225 smu_dpm_clks_a->dpm_clks->NumSocClkLevelsEnabled;
1226
1227 for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++) {
1228 smu_dpm_clks_b->dpm_clks->SocClocks[i] = smu_dpm_clks_a->dpm_clks->SocClocks[i];
1229 smu_dpm_clks_b->dpm_clks->SocVoltage[i] = smu_dpm_clks_a->dpm_clks->SocVoltage[i];
1230 }
1231 }
dcn35_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_dcn35 * clk_mgr,struct pp_smu_funcs * pp_smu,struct dccg * dccg)1232 void dcn35_clk_mgr_construct(
1233 struct dc_context *ctx,
1234 struct clk_mgr_dcn35 *clk_mgr,
1235 struct pp_smu_funcs *pp_smu,
1236 struct dccg *dccg)
1237 {
1238 struct dcn35_smu_dpm_clks smu_dpm_clks = { 0 };
1239 struct dcn351_smu_dpm_clks smu_dpm_clks_dcn351 = { 0 };
1240 clk_mgr->base.base.ctx = ctx;
1241 clk_mgr->base.base.funcs = &dcn35_funcs;
1242
1243 clk_mgr->base.pp_smu = pp_smu;
1244
1245 clk_mgr->base.dccg = dccg;
1246 clk_mgr->base.dfs_bypass_disp_clk = 0;
1247
1248 clk_mgr->base.dprefclk_ss_percentage = 0;
1249 clk_mgr->base.dprefclk_ss_divider = 1000;
1250 clk_mgr->base.ss_on_dprefclk = false;
1251 clk_mgr->base.dfs_ref_freq_khz = 48000;
1252 if (ctx->dce_version == DCN_VERSION_3_5) {
1253 clk_mgr->base.regs = &clk_mgr_regs_dcn35;
1254 clk_mgr->base.clk_mgr_shift = &clk_mgr_shift_dcn35;
1255 clk_mgr->base.clk_mgr_mask = &clk_mgr_mask_dcn35;
1256 }
1257
1258
1259 clk_mgr->smu_wm_set.wm_set = (struct dcn35_watermarks *)dm_helpers_allocate_gpu_mem(
1260 clk_mgr->base.base.ctx,
1261 DC_MEM_ALLOC_TYPE_GART,
1262 sizeof(struct dcn35_watermarks),
1263 &clk_mgr->smu_wm_set.mc_address.quad_part);
1264
1265 if (!clk_mgr->smu_wm_set.wm_set) {
1266 clk_mgr->smu_wm_set.wm_set = &dummy_wms;
1267 clk_mgr->smu_wm_set.mc_address.quad_part = 0;
1268 }
1269 ASSERT(clk_mgr->smu_wm_set.wm_set);
1270
1271 smu_dpm_clks.dpm_clks = (DpmClocks_t_dcn35 *)dm_helpers_allocate_gpu_mem(
1272 clk_mgr->base.base.ctx,
1273 DC_MEM_ALLOC_TYPE_GART,
1274 sizeof(DpmClocks_t_dcn35),
1275 &smu_dpm_clks.mc_address.quad_part);
1276 if (smu_dpm_clks.dpm_clks == NULL) {
1277 smu_dpm_clks.dpm_clks = &dummy_clocks;
1278 smu_dpm_clks.mc_address.quad_part = 0;
1279 }
1280 ASSERT(smu_dpm_clks.dpm_clks);
1281
1282 if (ctx->dce_version == DCN_VERSION_3_51) {
1283 smu_dpm_clks_dcn351.dpm_clks = (DpmClocks_t_dcn351 *)dm_helpers_allocate_gpu_mem(
1284 clk_mgr->base.base.ctx,
1285 DC_MEM_ALLOC_TYPE_GART,
1286 sizeof(DpmClocks_t_dcn351),
1287 &smu_dpm_clks_dcn351.mc_address.quad_part);
1288 if (smu_dpm_clks_dcn351.dpm_clks == NULL) {
1289 smu_dpm_clks_dcn351.dpm_clks = &dummy_clocks_dcn351;
1290 smu_dpm_clks_dcn351.mc_address.quad_part = 0;
1291 }
1292 }
1293
1294 clk_mgr->base.smu_ver = dcn35_smu_get_smu_version(&clk_mgr->base);
1295
1296 if (clk_mgr->base.smu_ver)
1297 clk_mgr->base.smu_present = true;
1298
1299 /* TODO: Check we get what we expect during bringup */
1300 clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base);
1301
1302 if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
1303 dcn35_bw_params.wm_table = lpddr5_wm_table;
1304 } else {
1305 dcn35_bw_params.wm_table = ddr5_wm_table;
1306 }
1307 /* Saved clocks configured at boot for debug purposes */
1308 dcn35_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, clk_mgr);
1309
1310 clk_mgr->base.base.dprefclk_khz = dcn35_smu_get_dprefclk(&clk_mgr->base);
1311 clk_mgr->base.base.clks.ref_dtbclk_khz = 600000;
1312
1313 dce_clock_read_ss_info(&clk_mgr->base);
1314 /*when clk src is from FCH, it could have ss, same clock src as DPREF clk*/
1315
1316 dcn35_read_ss_info_from_lut(&clk_mgr->base);
1317
1318 clk_mgr->base.base.bw_params = &dcn35_bw_params;
1319
1320 if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {
1321 int i;
1322 if (ctx->dce_version == DCN_VERSION_3_51) {
1323 dcn351_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks_dcn351);
1324 translate_to_DpmClocks_t_dcn35(&smu_dpm_clks_dcn351, &smu_dpm_clks);
1325 } else
1326 dcn35_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
1327 DC_LOG_SMU("NumDcfClkLevelsEnabled: %d\n"
1328 "NumDispClkLevelsEnabled: %d\n"
1329 "NumSocClkLevelsEnabled: %d\n"
1330 "VcnClkLevelsEnabled: %d\n"
1331 "FClkLevelsEnabled: %d\n"
1332 "NumMemPstatesEnabled: %d\n"
1333 "MinGfxClk: %d\n"
1334 "MaxGfxClk: %d\n",
1335 smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled,
1336 smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled,
1337 smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled,
1338 smu_dpm_clks.dpm_clks->VcnClkLevelsEnabled,
1339 smu_dpm_clks.dpm_clks->NumFclkLevelsEnabled,
1340 smu_dpm_clks.dpm_clks->NumMemPstatesEnabled,
1341 smu_dpm_clks.dpm_clks->MinGfxClk,
1342 smu_dpm_clks.dpm_clks->MaxGfxClk);
1343 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled; i++) {
1344 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DcfClocks[%d] = %d\n",
1345 i,
1346 smu_dpm_clks.dpm_clks->DcfClocks[i]);
1347 }
1348 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) {
1349 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DispClocks[%d] = %d\n",
1350 i, smu_dpm_clks.dpm_clks->DispClocks[i]);
1351 }
1352 for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++) {
1353 DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocClocks[%d] = %d\n",
1354 i, smu_dpm_clks.dpm_clks->SocClocks[i]);
1355 }
1356 for (i = 0; i < smu_dpm_clks.dpm_clks->NumFclkLevelsEnabled; i++) {
1357 DC_LOG_SMU("smu_dpm_clks.dpm_clks->FclkClocks_Freq[%d] = %d\n",
1358 i, smu_dpm_clks.dpm_clks->FclkClocks_Freq[i]);
1359 DC_LOG_SMU("smu_dpm_clks.dpm_clks->FclkClocks_Voltage[%d] = %d\n",
1360 i, smu_dpm_clks.dpm_clks->FclkClocks_Voltage[i]);
1361 }
1362 for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++)
1363 DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocVoltage[%d] = %d\n",
1364 i, smu_dpm_clks.dpm_clks->SocVoltage[i]);
1365
1366 for (i = 0; i < smu_dpm_clks.dpm_clks->NumMemPstatesEnabled; i++) {
1367 DC_LOG_SMU("smu_dpm_clks.dpm_clks.MemPstateTable[%d].UClk = %d\n"
1368 "smu_dpm_clks.dpm_clks->MemPstateTable[%d].MemClk= %d\n"
1369 "smu_dpm_clks.dpm_clks->MemPstateTable[%d].Voltage = %d\n",
1370 i, smu_dpm_clks.dpm_clks->MemPstateTable[i].UClk,
1371 i, smu_dpm_clks.dpm_clks->MemPstateTable[i].MemClk,
1372 i, smu_dpm_clks.dpm_clks->MemPstateTable[i].Voltage);
1373 }
1374
1375 if (ctx->dc_bios->integrated_info && ctx->dc->config.use_default_clock_table == false) {
1376 dcn35_clk_mgr_helper_populate_bw_params(
1377 &clk_mgr->base,
1378 ctx->dc_bios->integrated_info,
1379 smu_dpm_clks.dpm_clks);
1380 }
1381 }
1382
1383 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
1384 dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_GART,
1385 smu_dpm_clks.dpm_clks);
1386
1387 if (smu_dpm_clks_dcn351.dpm_clks && smu_dpm_clks_dcn351.mc_address.quad_part != 0)
1388 dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_GART,
1389 smu_dpm_clks_dcn351.dpm_clks);
1390
1391 if (ctx->dc->config.disable_ips != DMUB_IPS_DISABLE_ALL) {
1392 bool ips_support = false;
1393
1394 /*avoid call pmfw at init*/
1395 ips_support = dcn35_smu_get_ips_supported(&clk_mgr->base);
1396 if (ips_support) {
1397 ctx->dc->debug.ignore_pg = false;
1398 ctx->dc->debug.disable_dpp_power_gate = false;
1399 ctx->dc->debug.disable_hubp_power_gate = false;
1400 ctx->dc->debug.disable_dsc_power_gate = false;
1401
1402 /* Disable dynamic IPS2 in older PMFW (93.12) for Z8 interop. */
1403 if (ctx->dc->config.disable_ips == DMUB_IPS_ENABLE &&
1404 ctx->dce_version == DCN_VERSION_3_5 &&
1405 ((clk_mgr->base.smu_ver & 0x00FFFFFF) <= 0x005d0c00))
1406 ctx->dc->config.disable_ips = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;
1407 } else {
1408 /*let's reset the config control flag*/
1409 ctx->dc->config.disable_ips = DMUB_IPS_DISABLE_ALL; /*pmfw not support it, disable it all*/
1410 }
1411 }
1412 }
1413
dcn35_clk_mgr_destroy(struct clk_mgr_internal * clk_mgr_int)1414 void dcn35_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)
1415 {
1416 struct clk_mgr_dcn35 *clk_mgr = TO_CLK_MGR_DCN35(clk_mgr_int);
1417
1418 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0)
1419 dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
1420 clk_mgr->smu_wm_set.wm_set);
1421 }
1422