1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright 2019 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #include "dm_services.h"
28 #include "dc.h"
29
30 #include "dcn32/dcn32_init.h"
31
32 #include "resource.h"
33 #include "include/irq_service_interface.h"
34 #include "basics/conversion.h"
35 #include "dcn32/dcn32_resource.h"
36 #include "dcn321_resource.h"
37
38 #include "dcn20/dcn20_resource.h"
39 #include "dcn30/dcn30_resource.h"
40
41 #include "dml/dcn321/dcn321_fpu.h"
42
43 #include "dcn10/dcn10_ipp.h"
44 #include "dcn30/dcn30_hubbub.h"
45 #include "dcn31/dcn31_hubbub.h"
46 #include "dcn32/dcn32_hubbub.h"
47 #include "dcn32/dcn32_mpc.h"
48 #include "dcn32/dcn32_hubp.h"
49 #include "irq/dcn32/irq_service_dcn32.h"
50 #include "dcn32/dcn32_dpp.h"
51 #include "dcn32/dcn32_optc.h"
52 #include "dcn20/dcn20_hwseq.h"
53 #include "dcn30/dcn30_hwseq.h"
54 #include "dce110/dce110_hwseq.h"
55 #include "dcn30/dcn30_opp.h"
56 #include "dcn20/dcn20_dsc.h"
57 #include "dcn30/dcn30_vpg.h"
58 #include "dcn30/dcn30_afmt.h"
59 #include "dcn30/dcn30_dio_stream_encoder.h"
60 #include "dcn32/dcn32_dio_stream_encoder.h"
61 #include "dcn30/dcn30_hpo_frl_stream_encoder.h"
62 #include "dcn30/dcn30_hpo_frl_link_encoder.h"
63 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
64 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
65 #include "dcn32/dcn32_hpo_dp_link_encoder.h"
66 #include "dcn31/dcn31_apg.h"
67 #include "dcn31/dcn31_dio_link_encoder.h"
68 #include "dcn32/dcn32_dio_link_encoder.h"
69 #include "dcn321/dcn321_dio_link_encoder.h"
70 #include "dce/dce_clock_source.h"
71 #include "dce/dce_audio.h"
72 #include "dce/dce_hwseq.h"
73 #include "clk_mgr.h"
74 #include "dio/virtual/virtual_stream_encoder.h"
75 #include "dio/dcn10/dcn10_dio.h"
76 #include "dml/display_mode_vba.h"
77 #include "dcn32/dcn32_dccg.h"
78 #include "dcn10/dcn10_resource.h"
79 #include "link_service.h"
80 #include "dcn31/dcn31_panel_cntl.h"
81
82 #include "dcn30/dcn30_dwb.h"
83 #include "dcn32/dcn32_mmhubbub.h"
84
85 #include "dcn/dcn_3_2_1_offset.h"
86 #include "dcn/dcn_3_2_1_sh_mask.h"
87 #include "nbio/nbio_4_3_0_offset.h"
88
89 #include "reg_helper.h"
90 #include "dce/dmub_abm.h"
91 #include "dce/dmub_psr.h"
92 #include "dce/dce_aux.h"
93 #include "dce/dce_i2c.h"
94
95 #include "dml/dcn30/display_mode_vba_30.h"
96 #include "vm_helper.h"
97 #include "dcn20/dcn20_vmid.h"
98
99 #include "dc_state_priv.h"
100
101 #define DC_LOGGER_INIT(logger)
102
103 enum dcn321_clk_src_array_id {
104 DCN321_CLK_SRC_PLL0,
105 DCN321_CLK_SRC_PLL1,
106 DCN321_CLK_SRC_PLL2,
107 DCN321_CLK_SRC_PLL3,
108 DCN321_CLK_SRC_PLL4,
109 DCN321_CLK_SRC_TOTAL
110 };
111
112 /* begin *********************
113 * macros to expend register list macro defined in HW object header file
114 */
115
116 /* DCN */
117 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
118
119 #define BASE(seg) BASE_INNER(seg)
120
121 #define SR(reg_name)\
122 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
123 reg ## reg_name
124 #define SR_ARR(reg_name, id)\
125 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
126 reg ## reg_name
127 #define SR_ARR_INIT(reg_name, id, value)\
128 REG_STRUCT[id].reg_name = value
129
130 #define SRI(reg_name, block, id)\
131 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
132 reg ## block ## id ## _ ## reg_name
133
134 #define SRI_ARR(reg_name, block, id)\
135 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
136 reg ## block ## id ## _ ## reg_name
137
138 #define SR_ARR_I2C(reg_name, id) \
139 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
140
141 #define SRI_ARR_I2C(reg_name, block, id)\
142 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
143 reg ## block ## id ## _ ## reg_name
144
145 #define SRI_ARR_DME(reg_name, block, id, offset)\
146 REG_STRUCT[id - offset].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
147 reg ## block ## id ## _ ## reg_name
148
149 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\
150 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
151 reg ## block ## id ## _ ## reg_name
152
153 #define SRI2(reg_name, block, id)\
154 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
155 reg ## reg_name
156 #define SRI2_ARR(reg_name, block, id)\
157 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
158 reg ## reg_name
159
160 #define SRIR(var_name, reg_name, block, id)\
161 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
162 reg ## block ## id ## _ ## reg_name
163
164 #define SRII(reg_name, block, id)\
165 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
166 reg ## block ## id ## _ ## reg_name
167
168 #define SRII_ARR_2(reg_name, block, id, inst)\
169 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
170 reg ## block ## id ## _ ## reg_name
171
172 #define SRII_MPC_RMU(reg_name, block, id)\
173 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
174 reg ## block ## id ## _ ## reg_name
175
176 #define SRII_DWB(reg_name, temp_name, block, id)\
177 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
178 reg ## block ## id ## _ ## temp_name
179
180 #define DCCG_SRII(reg_name, block, id)\
181 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
182 reg ## block ## id ## _ ## reg_name
183
184 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
185 .field_name = reg_name ## __ ## field_name ## post_fix
186
187 #define VUPDATE_SRII(reg_name, block, id)\
188 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
189 reg ## reg_name ## _ ## block ## id
190
191 /* NBIO */
192 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
193
194 #define NBIO_BASE(seg) \
195 NBIO_BASE_INNER(seg)
196
197 #define NBIO_SR(reg_name)\
198 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
199 regBIF_BX0_ ## reg_name
200 #define NBIO_SR_ARR(reg_name, id)\
201 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
202 regBIF_BX0_ ## reg_name
203
204 #define CTX ctx
205 #define REG(reg_name) \
206 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
207
208 static struct bios_registers bios_regs;
209
210 #define bios_regs_init() \
211 ( \
212 NBIO_SR(BIOS_SCRATCH_3),\
213 NBIO_SR(BIOS_SCRATCH_6)\
214 )
215
216 #define clk_src_regs_init(index, pllid)\
217 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid)
218
219 static struct dce110_clk_src_regs clk_src_regs[5];
220
221 static const struct dce110_clk_src_shift cs_shift = {
222 CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
223 };
224
225 static const struct dce110_clk_src_mask cs_mask = {
226 CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
227 };
228
229 #define abm_regs_init(id)\
230 ABM_DCN32_REG_LIST_RI(id)
231
232 static struct dce_abm_registers abm_regs[4];
233
234 static const struct dce_abm_shift abm_shift = {
235 ABM_MASK_SH_LIST_DCN32(__SHIFT)
236 };
237
238 static const struct dce_abm_mask abm_mask = {
239 ABM_MASK_SH_LIST_DCN32(_MASK)
240 };
241
242 #define audio_regs_init(id)\
243 AUD_COMMON_REG_LIST_RI(id)
244
245 static struct dce_audio_registers audio_regs[5];
246
247 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
248 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
249 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
250 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
251
252 static const struct dce_audio_shift audio_shift = {
253 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
254 };
255
256 static const struct dce_audio_mask audio_mask = {
257 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
258 };
259
260 #define vpg_regs_init(id)\
261 VPG_DCN3_REG_LIST_RI(id)
262
263 static struct dcn30_vpg_registers vpg_regs[10];
264
265 static const struct dcn30_vpg_shift vpg_shift = {
266 DCN3_VPG_MASK_SH_LIST(__SHIFT)
267 };
268
269 static const struct dcn30_vpg_mask vpg_mask = {
270 DCN3_VPG_MASK_SH_LIST(_MASK)
271 };
272
273 #define afmt_regs_init(id)\
274 AFMT_DCN3_REG_LIST_RI(id)
275
276 static struct dcn30_afmt_registers afmt_regs[6];
277
278 static const struct dcn30_afmt_shift afmt_shift = {
279 DCN3_AFMT_MASK_SH_LIST(__SHIFT)
280 };
281
282 static const struct dcn30_afmt_mask afmt_mask = {
283 DCN3_AFMT_MASK_SH_LIST(_MASK)
284 };
285
286 #define apg_regs_init(id)\
287 APG_DCN31_REG_LIST_RI(id)
288
289 static struct dcn31_apg_registers apg_regs[4];
290
291 static const struct dcn31_apg_shift apg_shift = {
292 DCN31_APG_MASK_SH_LIST(__SHIFT)
293 };
294
295 static const struct dcn31_apg_mask apg_mask = {
296 DCN31_APG_MASK_SH_LIST(_MASK)
297 };
298
299 #define stream_enc_regs_init(id)\
300 SE_DCN32_REG_LIST_RI(id)
301
302 static struct dcn10_stream_enc_registers stream_enc_regs[5];
303
304 static const struct dcn10_stream_encoder_shift se_shift = {
305 SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
306 };
307
308 static const struct dcn10_stream_encoder_mask se_mask = {
309 SE_COMMON_MASK_SH_LIST_DCN32(_MASK)
310 };
311
312
313 #define aux_regs_init(id)\
314 DCN2_AUX_REG_LIST_RI(id)
315
316 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5];
317
318 #define hpd_regs_init(id)\
319 HPD_REG_LIST_RI(id)
320
321 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5];
322
323 #define link_regs_init(id, phyid)\
324 ( \
325 LE_DCN31_REG_LIST_RI(id), \
326 UNIPHY_DCN2_REG_LIST_RI(id, phyid)\
327 )
328 /*DPCS_DCN31_REG_LIST(id),*/ \
329
330 static struct dcn10_link_enc_registers link_enc_regs[5];
331
332 static const struct dcn10_link_enc_shift le_shift = {
333 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
334 // DPCS_DCN31_MASK_SH_LIST(__SHIFT)
335 };
336
337 static const struct dcn10_link_enc_mask le_mask = {
338 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
339 // DPCS_DCN31_MASK_SH_LIST(_MASK)
340 };
341
342 #define hpo_frl_stream_encoder_reg_list(id)\
343 DCN3_0_HPO_FRL_STREAM_ENC_REG_LIST_RI(id)
344
345 #define hpo_frl_stream_encoder_dme_reg_list(id)\
346 DCN3_0_HPO_STREAM_ENC_DME_REG_LIST_RI(id, 6)
347
348 static struct dcn30_hpo_frl_stream_enc_registers hpo_frl_stream_enc_regs[2];
349
350 static const struct dcn30_hpo_frl_stream_encoder_shift hpo_se_shift = {
351 DCN3_0_HPO_STREAM_ENC_MASK_SH_LIST(__SHIFT)
352 };
353
354 static const struct dcn30_hpo_frl_stream_encoder_mask hpo_se_mask = {
355 DCN3_0_HPO_STREAM_ENC_MASK_SH_LIST(_MASK)
356 };
357
358 #define hpo_frl_link_encoder_reg_list(id)\
359 DCN3_0_HPO_FRL_LINK_ENC_REG_LIST_RI(id)
360
361 static struct dcn30_hpo_frl_link_encoder_registers hpo_frl_link_enc_regs[1];
362
363 static const struct dcn30_hpo_frl_link_encoder_shift hpo_le_shift = {
364 DCN3_0_HPO_FRL_LINK_ENC_MASK_SH_LIST(__SHIFT)
365 };
366
367 static const struct dcn30_hpo_frl_link_encoder_mask hpo_le_mask = {
368 DCN3_0_HPO_FRL_LINK_ENC_MASK_SH_LIST(_MASK)
369 };
370
371 #define hpo_dp_stream_encoder_reg_init(id)\
372 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
373
374 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4];
375
376 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
377 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
378 };
379
380 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
381 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
382 };
383
384
385 #define hpo_dp_link_encoder_reg_init(id)\
386 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id)
387 /*DCN3_1_RDPCSTX_REG_LIST(0),*/
388 /*DCN3_1_RDPCSTX_REG_LIST(1),*/
389 /*DCN3_1_RDPCSTX_REG_LIST(2),*/
390 /*DCN3_1_RDPCSTX_REG_LIST(3),*/
391
392 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2];
393
394 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
395 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
396 };
397
398 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
399 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
400 };
401
402 #define dpp_regs_init(id)\
403 DPP_REG_LIST_DCN30_COMMON_RI(id)
404
405 static struct dcn3_dpp_registers dpp_regs[4];
406
407 static const struct dcn3_dpp_shift tf_shift = {
408 DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT)
409 };
410
411 static const struct dcn3_dpp_mask tf_mask = {
412 DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK)
413 };
414
415
416 #define opp_regs_init(id)\
417 OPP_REG_LIST_DCN30_RI(id)
418
419 static struct dcn20_opp_registers opp_regs[4];
420
421 static const struct dcn20_opp_shift opp_shift = {
422 OPP_MASK_SH_LIST_DCN20(__SHIFT)
423 };
424
425 static const struct dcn20_opp_mask opp_mask = {
426 OPP_MASK_SH_LIST_DCN20(_MASK)
427 };
428
429 #define aux_engine_regs_init(id) \
430 ( \
431 AUX_COMMON_REG_LIST0_RI(id), SR_ARR_INIT(AUXN_IMPCAL, id, 0), \
432 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \
433 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \
434 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)\
435 )
436
437 static struct dce110_aux_registers aux_engine_regs[5];
438
439 static const struct dce110_aux_registers_shift aux_shift = {
440 DCN_AUX_MASK_SH_LIST(__SHIFT)
441 };
442
443 static const struct dce110_aux_registers_mask aux_mask = {
444 DCN_AUX_MASK_SH_LIST(_MASK)
445 };
446
447 #define dwbc_regs_dcn3_init(id)\
448 DWBC_COMMON_REG_LIST_DCN30_RI(id)
449
450 static struct dcn30_dwbc_registers dwbc30_regs[1];
451
452 static const struct dcn30_dwbc_shift dwbc30_shift = {
453 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
454 };
455
456 static const struct dcn30_dwbc_mask dwbc30_mask = {
457 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
458 };
459
460 #define mcif_wb_regs_dcn3_init(id)\
461 MCIF_WB_COMMON_REG_LIST_DCN32_RI(id)
462
463 static struct dcn30_mmhubbub_registers mcif_wb30_regs[1];
464
465 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
466 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
467 };
468
469 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
470 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK)
471 };
472
473 #define dsc_regsDCN20_init(id)\
474 DSC_REG_LIST_DCN20_RI(id)
475
476 static struct dcn20_dsc_registers dsc_regs[4];
477
478 static const struct dcn20_dsc_shift dsc_shift = {
479 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
480 };
481
482 static const struct dcn20_dsc_mask dsc_mask = {
483 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
484 };
485
486 static struct dcn30_mpc_registers mpc_regs;
487 #define dcn_mpc_regs_init()\
488 MPC_REG_LIST_DCN3_2_RI(0),\
489 MPC_REG_LIST_DCN3_2_RI(1),\
490 MPC_REG_LIST_DCN3_2_RI(2),\
491 MPC_REG_LIST_DCN3_2_RI(3),\
492 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\
493 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\
494 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\
495 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\
496 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0)
497
498 static const struct dcn30_mpc_shift mpc_shift = {
499 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
500 };
501
502 static const struct dcn30_mpc_mask mpc_mask = {
503 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)
504 };
505
506 #define optc_regs_init(id)\
507 OPTC_COMMON_REG_LIST_DCN3_2_RI(id)
508
509 static struct dcn_optc_registers optc_regs[4];
510
511 static const struct dcn_optc_shift optc_shift = {
512 OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
513 };
514
515 static const struct dcn_optc_mask optc_mask = {
516 OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
517 };
518
519 #define hubp_regs_init(id) \
520 HUBP_REG_LIST_DCN32_RI(id)
521
522 static struct dcn_hubp2_registers hubp_regs[4];
523
524 static const struct dcn_hubp2_shift hubp_shift = {
525 HUBP_MASK_SH_LIST_DCN32(__SHIFT)
526 };
527
528 static const struct dcn_hubp2_mask hubp_mask = {
529 HUBP_MASK_SH_LIST_DCN32(_MASK)
530 };
531
532 static struct dcn_hubbub_registers hubbub_reg;
533 #define hubbub_reg_init()\
534 HUBBUB_REG_LIST_DCN32_RI(0)
535
536 static const struct dcn_hubbub_shift hubbub_shift = {
537 HUBBUB_MASK_SH_LIST_DCN32(__SHIFT)
538 };
539
540 static const struct dcn_hubbub_mask hubbub_mask = {
541 HUBBUB_MASK_SH_LIST_DCN32(_MASK)
542 };
543
544 static struct dccg_registers dccg_regs;
545
546 #define dccg_regs_init()\
547 DCCG_REG_LIST_DCN32_RI()
548
549 static const struct dccg_shift dccg_shift = {
550 DCCG_MASK_SH_LIST_DCN32(__SHIFT)
551 };
552
553 static const struct dccg_mask dccg_mask = {
554 DCCG_MASK_SH_LIST_DCN32(_MASK)
555 };
556
557
558 #define SRII2(reg_name_pre, reg_name_post, id)\
559 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
560 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
561 reg ## reg_name_pre ## id ## _ ## reg_name_post
562
563
564 #define HWSEQ_DCN32_REG_LIST()\
565 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
566 SR(DIO_MEM_PWR_CTRL), \
567 SR(ODM_MEM_PWR_CTRL3), \
568 SR(MMHUBBUB_MEM_PWR_CNTL), \
569 SR(DCCG_GATE_DISABLE_CNTL), \
570 SR(DCCG_GATE_DISABLE_CNTL2), \
571 SR(DCFCLK_CNTL),\
572 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
573 SRII(PIXEL_RATE_CNTL, OTG, 0), \
574 SRII(PIXEL_RATE_CNTL, OTG, 1),\
575 SRII(PIXEL_RATE_CNTL, OTG, 2),\
576 SRII(PIXEL_RATE_CNTL, OTG, 3),\
577 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
578 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
579 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
580 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
581 SR(MICROSECOND_TIME_BASE_DIV), \
582 SR(MILLISECOND_TIME_BASE_DIV), \
583 SR(DISPCLK_FREQ_CHANGE_CNTL), \
584 SR(RBBMIF_TIMEOUT_DIS), \
585 SR(RBBMIF_TIMEOUT_DIS_2), \
586 SR(DCHUBBUB_CRC_CTRL), \
587 SR(DPP_TOP0_DPP_CRC_CTRL), \
588 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
589 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
590 SR(MPC_CRC_CTRL), \
591 SR(MPC_CRC_RESULT_GB), \
592 SR(MPC_CRC_RESULT_C), \
593 SR(MPC_CRC_RESULT_AR), \
594 SR(DOMAIN0_PG_CONFIG), \
595 SR(DOMAIN1_PG_CONFIG), \
596 SR(DOMAIN2_PG_CONFIG), \
597 SR(DOMAIN3_PG_CONFIG), \
598 SR(DOMAIN16_PG_CONFIG), \
599 SR(DOMAIN17_PG_CONFIG), \
600 SR(DOMAIN18_PG_CONFIG), \
601 SR(DOMAIN19_PG_CONFIG), \
602 SR(DOMAIN0_PG_STATUS), \
603 SR(DOMAIN1_PG_STATUS), \
604 SR(DOMAIN2_PG_STATUS), \
605 SR(DOMAIN3_PG_STATUS), \
606 SR(DOMAIN16_PG_STATUS), \
607 SR(DOMAIN17_PG_STATUS), \
608 SR(DOMAIN18_PG_STATUS), \
609 SR(DOMAIN19_PG_STATUS), \
610 SR(D1VGA_CONTROL), \
611 SR(D2VGA_CONTROL), \
612 SR(D3VGA_CONTROL), \
613 SR(D4VGA_CONTROL), \
614 SR(D5VGA_CONTROL), \
615 SR(D6VGA_CONTROL), \
616 SR(DC_IP_REQUEST_CNTL), \
617 SR(AZALIA_AUDIO_DTO), \
618 SR(AZALIA_CONTROLLER_CLOCK_GATING)
619
620 static struct dce_hwseq_registers hwseq_reg;
621
622 #define hwseq_reg_init()\
623 HWSEQ_DCN32_REG_LIST()
624
625 #define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\
626 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
627 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
628 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
629 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
630 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
631 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
632 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
633 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
634 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
635 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
636 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
637 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
638 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
639 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
640 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
641 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
642 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
643 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
644 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
645 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
646 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
647 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
648 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
649 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
650 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
651 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
652 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
653 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
654 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
655 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
656 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
657 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh)
658
659 static const struct dce_hwseq_shift hwseq_shift = {
660 HWSEQ_DCN32_MASK_SH_LIST(__SHIFT)
661 };
662
663 static const struct dce_hwseq_mask hwseq_mask = {
664 HWSEQ_DCN32_MASK_SH_LIST(_MASK)
665 };
666 #define vmid_regs_init(id)\
667 DCN20_VMID_REG_LIST_RI(id)
668
669 static struct dcn_vmid_registers vmid_regs[16];
670
671 static const struct dcn20_vmid_shift vmid_shifts = {
672 DCN20_VMID_MASK_SH_LIST(__SHIFT)
673 };
674
675 static const struct dcn20_vmid_mask vmid_masks = {
676 DCN20_VMID_MASK_SH_LIST(_MASK)
677 };
678
679 static struct dcn_dio_registers dio_regs;
680
681 #define DIO_MASK_SH_LIST(mask_sh)\
682 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh)
683
684 static const struct dcn_dio_shift dio_shift = {
685 DIO_MASK_SH_LIST(__SHIFT)
686 };
687
688 static const struct dcn_dio_mask dio_mask = {
689 DIO_MASK_SH_LIST(_MASK)
690 };
691
692 static const struct resource_caps res_cap_dcn321 = {
693 .num_timing_generator = 4,
694 .num_opp = 4,
695 .num_video_plane = 4,
696 .num_audio = 5,
697 .num_stream_encoder = 5,
698 .num_hpo_frl = 1,
699 .num_hpo_dp_stream_encoder = 4,
700 .num_hpo_dp_link_encoder = 2,
701 .num_pll = 5,
702 .num_dwb = 1,
703 .num_ddc = 5,
704 .num_vmid = 16,
705 .num_mpc_3dlut = 4,
706 .num_dsc = 4,
707 };
708
709 static const struct dc_plane_cap plane_cap = {
710 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
711 .per_pixel_alpha = true,
712
713 .pixel_format_support = {
714 .argb8888 = true,
715 .nv12 = true,
716 .fp16 = true,
717 .p010 = true,
718 .ayuv = false,
719 },
720
721 .max_upscale_factor = {
722 .argb8888 = 16000,
723 .nv12 = 16000,
724 .fp16 = 16000
725 },
726
727 // 6:1 downscaling ratio: 1000/6 = 166.666
728 .max_downscale_factor = {
729 .argb8888 = 167,
730 .nv12 = 167,
731 .fp16 = 167
732 },
733 64,
734 64
735 };
736
737 static const struct dc_debug_options debug_defaults_drv = {
738 .limit_ffe = 3,
739 .disable_dmcu = true,
740 .force_abm_enable = false,
741 .clock_trace = true,
742 .disable_pplib_clock_request = false,
743 .pipe_split_policy = MPC_SPLIT_AVOID,
744 .force_single_disp_pipe_split = false,
745 .disable_dcc = DCC_ENABLE,
746 .vsr_support = true,
747 .performance_trace = false,
748 .max_downscale_src_width = 7680,/*upto 8K*/
749 .disable_pplib_wm_range = false,
750 .scl_reset_length10 = true,
751 .sanity_checks = false,
752 .underflow_assert_delay_us = 0xFFFFFFFF,
753 .dwb_fi_phase = -1, // -1 = disable,
754 .dmub_command_table = true,
755 .enable_mem_low_power = {
756 .bits = {
757 .vga = false,
758 .i2c = false,
759 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
760 .dscl = false,
761 .cm = false,
762 .mpc = false,
763 .optc = true,
764 }
765 },
766 .use_max_lb = true,
767 .force_disable_subvp = false,
768 .exit_idle_opt_for_cursor_updates = true,
769 .enable_single_display_2to1_odm_policy = true,
770
771 /*must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions*/
772 .enable_double_buffered_dsc_pg_support = true,
773 .enable_dp_dig_pixel_rate_div_policy = 1,
774 .allow_sw_cursor_fallback = false, // Linux can't do SW cursor "fallback"
775 .alloc_extra_way_for_cursor = true,
776 .min_prefetch_in_strobe_ns = 60000, // 60us
777 .disable_unbounded_requesting = false,
778 .override_dispclk_programming = true,
779 .disable_fpo_optimizations = false,
780 .fpo_vactive_margin_us = 2000, // 2000us
781 .disable_fpo_vactive = false,
782 .disable_boot_optimizations = false,
783 .disable_subvp_high_refresh = false,
784 .fpo_vactive_min_active_margin_us = 200,
785 .fpo_vactive_max_blank_us = 1000,
786 .disable_dc_mode_overwrite = true,
787 .using_dml2 = false,
788 };
789
790 static const struct dc_check_config config_defaults = {
791 .enable_legacy_fast_update = false,
792 };
793
dcn321_aux_engine_create(struct dc_context * ctx,uint32_t inst)794 static struct dce_aux *dcn321_aux_engine_create(
795 struct dc_context *ctx,
796 uint32_t inst)
797 {
798 struct aux_engine_dce110 *aux_engine =
799 kzalloc_obj(struct aux_engine_dce110);
800
801 if (!aux_engine)
802 return NULL;
803
804 #undef REG_STRUCT
805 #define REG_STRUCT aux_engine_regs
806 aux_engine_regs_init(0),
807 aux_engine_regs_init(1),
808 aux_engine_regs_init(2),
809 aux_engine_regs_init(3),
810 aux_engine_regs_init(4);
811
812 dce110_aux_engine_construct(aux_engine, ctx, inst,
813 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
814 &aux_engine_regs[inst],
815 &aux_mask,
816 &aux_shift,
817 ctx->dc->caps.extended_aux_timeout_support);
818
819 return &aux_engine->base;
820 }
821 #define i2c_inst_regs_init(id)\
822 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)
823
824 static struct dce_i2c_registers i2c_hw_regs[5];
825
826 static const struct dce_i2c_shift i2c_shifts = {
827 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
828 };
829
830 static const struct dce_i2c_mask i2c_masks = {
831 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
832 };
833
dcn321_i2c_hw_create(struct dc_context * ctx,uint32_t inst)834 static struct dce_i2c_hw *dcn321_i2c_hw_create(
835 struct dc_context *ctx,
836 uint32_t inst)
837 {
838 struct dce_i2c_hw *dce_i2c_hw =
839 kzalloc_obj(struct dce_i2c_hw);
840
841 if (!dce_i2c_hw)
842 return NULL;
843
844 #undef REG_STRUCT
845 #define REG_STRUCT i2c_hw_regs
846 i2c_inst_regs_init(1),
847 i2c_inst_regs_init(2),
848 i2c_inst_regs_init(3),
849 i2c_inst_regs_init(4),
850 i2c_inst_regs_init(5);
851
852 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
853 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
854
855 return dce_i2c_hw;
856 }
857
dcn321_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)858 static struct clock_source *dcn321_clock_source_create(
859 struct dc_context *ctx,
860 struct dc_bios *bios,
861 enum clock_source_id id,
862 const struct dce110_clk_src_regs *regs,
863 bool dp_clk_src)
864 {
865 struct dce110_clk_src *clk_src =
866 kzalloc_obj(struct dce110_clk_src);
867
868 if (!clk_src)
869 return NULL;
870
871 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
872 regs, &cs_shift, &cs_mask)) {
873 clk_src->base.dp_clk_src = dp_clk_src;
874 return &clk_src->base;
875 }
876
877 kfree(clk_src);
878 BREAK_TO_DEBUGGER();
879 return NULL;
880 }
881
dcn321_dio_create(struct dc_context * ctx)882 static struct dio *dcn321_dio_create(struct dc_context *ctx)
883 {
884 struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio);
885
886 if (!dio10)
887 return NULL;
888
889 #undef REG_STRUCT
890 #define REG_STRUCT dio_regs
891 DIO_REG_LIST_DCN10();
892
893 dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask);
894
895 return &dio10->base;
896 }
897
dcn321_hubbub_create(struct dc_context * ctx)898 static struct hubbub *dcn321_hubbub_create(struct dc_context *ctx)
899 {
900 int i;
901
902 struct dcn20_hubbub *hubbub2 = kzalloc_obj(struct dcn20_hubbub);
903
904 if (!hubbub2)
905 return NULL;
906
907 #undef REG_STRUCT
908 #define REG_STRUCT hubbub_reg
909 hubbub_reg_init();
910
911 #undef REG_STRUCT
912 #define REG_STRUCT vmid_regs
913 vmid_regs_init(0),
914 vmid_regs_init(1),
915 vmid_regs_init(2),
916 vmid_regs_init(3),
917 vmid_regs_init(4),
918 vmid_regs_init(5),
919 vmid_regs_init(6),
920 vmid_regs_init(7),
921 vmid_regs_init(8),
922 vmid_regs_init(9),
923 vmid_regs_init(10),
924 vmid_regs_init(11),
925 vmid_regs_init(12),
926 vmid_regs_init(13),
927 vmid_regs_init(14),
928 vmid_regs_init(15);
929
930 hubbub32_construct(hubbub2, ctx,
931 &hubbub_reg,
932 &hubbub_shift,
933 &hubbub_mask,
934 ctx->dc->dml.ip.det_buffer_size_kbytes,
935 ctx->dc->dml.ip.pixel_chunk_size_kbytes,
936 ctx->dc->dml.ip.config_return_buffer_size_in_kbytes);
937
938
939 for (i = 0; i < res_cap_dcn321.num_vmid; i++) {
940 struct dcn20_vmid *vmid = &hubbub2->vmid[i];
941
942 vmid->ctx = ctx;
943
944 vmid->regs = &vmid_regs[i];
945 vmid->shifts = &vmid_shifts;
946 vmid->masks = &vmid_masks;
947 }
948
949 return &hubbub2->base;
950 }
951
dcn321_hubp_create(struct dc_context * ctx,uint32_t inst)952 static struct hubp *dcn321_hubp_create(
953 struct dc_context *ctx,
954 uint32_t inst)
955 {
956 struct dcn20_hubp *hubp2 =
957 kzalloc_obj(struct dcn20_hubp);
958
959 if (!hubp2)
960 return NULL;
961
962 #undef REG_STRUCT
963 #define REG_STRUCT hubp_regs
964 hubp_regs_init(0),
965 hubp_regs_init(1),
966 hubp_regs_init(2),
967 hubp_regs_init(3);
968
969 if (hubp32_construct(hubp2, ctx, inst,
970 &hubp_regs[inst], &hubp_shift, &hubp_mask))
971 return &hubp2->base;
972
973 BREAK_TO_DEBUGGER();
974 kfree(hubp2);
975 return NULL;
976 }
977
dcn321_dpp_destroy(struct dpp ** dpp)978 static void dcn321_dpp_destroy(struct dpp **dpp)
979 {
980 kfree(TO_DCN30_DPP(*dpp));
981 *dpp = NULL;
982 }
983
dcn321_dpp_create(struct dc_context * ctx,uint32_t inst)984 static struct dpp *dcn321_dpp_create(
985 struct dc_context *ctx,
986 uint32_t inst)
987 {
988 struct dcn3_dpp *dpp3 =
989 kzalloc_obj(struct dcn3_dpp);
990
991 if (!dpp3)
992 return NULL;
993
994 #undef REG_STRUCT
995 #define REG_STRUCT dpp_regs
996 dpp_regs_init(0),
997 dpp_regs_init(1),
998 dpp_regs_init(2),
999 dpp_regs_init(3);
1000
1001 if (dpp32_construct(dpp3, ctx, inst,
1002 &dpp_regs[inst], &tf_shift, &tf_mask))
1003 return &dpp3->base;
1004
1005 BREAK_TO_DEBUGGER();
1006 kfree(dpp3);
1007 return NULL;
1008 }
1009
dcn321_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)1010 static struct mpc *dcn321_mpc_create(
1011 struct dc_context *ctx,
1012 int num_mpcc,
1013 int num_rmu)
1014 {
1015 struct dcn30_mpc *mpc30 = kzalloc_obj(struct dcn30_mpc);
1016
1017 if (!mpc30)
1018 return NULL;
1019
1020 #undef REG_STRUCT
1021 #define REG_STRUCT mpc_regs
1022 dcn_mpc_regs_init();
1023
1024 dcn32_mpc_construct(mpc30, ctx,
1025 &mpc_regs,
1026 &mpc_shift,
1027 &mpc_mask,
1028 num_mpcc,
1029 num_rmu);
1030
1031 return &mpc30->base;
1032 }
1033
dcn321_opp_create(struct dc_context * ctx,uint32_t inst)1034 static struct output_pixel_processor *dcn321_opp_create(
1035 struct dc_context *ctx, uint32_t inst)
1036 {
1037 struct dcn20_opp *opp2 =
1038 kzalloc_obj(struct dcn20_opp);
1039
1040 if (!opp2) {
1041 BREAK_TO_DEBUGGER();
1042 return NULL;
1043 }
1044
1045 #undef REG_STRUCT
1046 #define REG_STRUCT opp_regs
1047 opp_regs_init(0),
1048 opp_regs_init(1),
1049 opp_regs_init(2),
1050 opp_regs_init(3);
1051
1052 dcn20_opp_construct(opp2, ctx, inst,
1053 &opp_regs[inst], &opp_shift, &opp_mask);
1054 return &opp2->base;
1055 }
1056
1057
dcn321_timing_generator_create(struct dc_context * ctx,uint32_t instance)1058 static struct timing_generator *dcn321_timing_generator_create(
1059 struct dc_context *ctx,
1060 uint32_t instance)
1061 {
1062 struct optc *tgn10 =
1063 kzalloc_obj(struct optc);
1064
1065 if (!tgn10)
1066 return NULL;
1067
1068 #undef REG_STRUCT
1069 #define REG_STRUCT optc_regs
1070 optc_regs_init(0),
1071 optc_regs_init(1),
1072 optc_regs_init(2),
1073 optc_regs_init(3);
1074
1075 tgn10->base.inst = instance;
1076 tgn10->base.ctx = ctx;
1077
1078 tgn10->tg_regs = &optc_regs[instance];
1079 tgn10->tg_shift = &optc_shift;
1080 tgn10->tg_mask = &optc_mask;
1081
1082 dcn32_timing_generator_init(tgn10);
1083
1084 return &tgn10->base;
1085 }
1086
1087 static const struct encoder_feature_support link_enc_feature = {
1088 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1089 .max_hdmi_pixel_clock = 600000,
1090 .hdmi_ycbcr420_supported = true,
1091 .dp_ycbcr420_supported = true,
1092 .fec_supported = true,
1093 .flags.bits.IS_HBR2_CAPABLE = true,
1094 .flags.bits.IS_HBR3_CAPABLE = true,
1095 .flags.bits.IS_TPS3_CAPABLE = true,
1096 .flags.bits.IS_TPS4_CAPABLE = true
1097 };
1098
dcn321_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)1099 static struct link_encoder *dcn321_link_encoder_create(
1100 struct dc_context *ctx,
1101 const struct encoder_init_data *enc_init_data)
1102 {
1103 struct dcn20_link_encoder *enc20 =
1104 kzalloc_obj(struct dcn20_link_encoder);
1105
1106 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
1107 return NULL;
1108
1109 #undef REG_STRUCT
1110 #define REG_STRUCT link_enc_aux_regs
1111 aux_regs_init(0),
1112 aux_regs_init(1),
1113 aux_regs_init(2),
1114 aux_regs_init(3),
1115 aux_regs_init(4);
1116
1117 #undef REG_STRUCT
1118 #define REG_STRUCT link_enc_hpd_regs
1119 hpd_regs_init(0),
1120 hpd_regs_init(1),
1121 hpd_regs_init(2),
1122 hpd_regs_init(3),
1123 hpd_regs_init(4);
1124
1125 #undef REG_STRUCT
1126 #define REG_STRUCT link_enc_regs
1127 link_regs_init(0, A),
1128 link_regs_init(1, B),
1129 link_regs_init(2, C),
1130 link_regs_init(3, D),
1131 link_regs_init(4, E);
1132
1133 dcn321_link_encoder_construct(enc20,
1134 enc_init_data,
1135 &link_enc_feature,
1136 &link_enc_regs[enc_init_data->transmitter],
1137 &link_enc_aux_regs[enc_init_data->channel - 1],
1138 &link_enc_hpd_regs[enc_init_data->hpd_source],
1139 &le_shift,
1140 &le_mask);
1141
1142 return &enc20->enc10.base;
1143 }
1144
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1145 static void read_dce_straps(
1146 struct dc_context *ctx,
1147 struct resource_straps *straps)
1148 {
1149 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS,
1150 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1151
1152 }
1153
dcn321_create_audio(struct dc_context * ctx,unsigned int inst)1154 static struct audio *dcn321_create_audio(
1155 struct dc_context *ctx, unsigned int inst)
1156 {
1157
1158 #undef REG_STRUCT
1159 #define REG_STRUCT audio_regs
1160 audio_regs_init(0),
1161 audio_regs_init(1),
1162 audio_regs_init(2),
1163 audio_regs_init(3),
1164 audio_regs_init(4);
1165
1166 return dce_audio_create(ctx, inst,
1167 &audio_regs[inst], &audio_shift, &audio_mask);
1168 }
1169
dcn321_vpg_create(struct dc_context * ctx,uint32_t inst)1170 static struct vpg *dcn321_vpg_create(
1171 struct dc_context *ctx,
1172 uint32_t inst)
1173 {
1174 struct dcn30_vpg *vpg3 = kzalloc_obj(struct dcn30_vpg);
1175
1176 if (!vpg3)
1177 return NULL;
1178
1179 #undef REG_STRUCT
1180 #define REG_STRUCT vpg_regs
1181 vpg_regs_init(0),
1182 vpg_regs_init(1),
1183 vpg_regs_init(2),
1184 vpg_regs_init(3),
1185 vpg_regs_init(4),
1186 vpg_regs_init(5),
1187 vpg_regs_init(6),
1188 vpg_regs_init(7),
1189 vpg_regs_init(8),
1190 vpg_regs_init(9);
1191
1192 vpg3_construct(vpg3, ctx, inst,
1193 &vpg_regs[inst],
1194 &vpg_shift,
1195 &vpg_mask);
1196
1197 return &vpg3->base;
1198 }
1199
dcn321_afmt_create(struct dc_context * ctx,uint32_t inst)1200 static struct afmt *dcn321_afmt_create(
1201 struct dc_context *ctx,
1202 uint32_t inst)
1203 {
1204 struct dcn30_afmt *afmt3 = kzalloc_obj(struct dcn30_afmt);
1205
1206 if (!afmt3)
1207 return NULL;
1208
1209 #undef REG_STRUCT
1210 #define REG_STRUCT afmt_regs
1211 afmt_regs_init(0),
1212 afmt_regs_init(1),
1213 afmt_regs_init(2),
1214 afmt_regs_init(3),
1215 afmt_regs_init(4),
1216 afmt_regs_init(5);
1217
1218 afmt3_construct(afmt3, ctx, inst,
1219 &afmt_regs[inst],
1220 &afmt_shift,
1221 &afmt_mask);
1222
1223 return &afmt3->base;
1224 }
1225
dcn321_apg_create(struct dc_context * ctx,uint32_t inst)1226 static struct apg *dcn321_apg_create(
1227 struct dc_context *ctx,
1228 uint32_t inst)
1229 {
1230 struct dcn31_apg *apg31 = kzalloc_obj(struct dcn31_apg);
1231
1232 if (!apg31)
1233 return NULL;
1234
1235 #undef REG_STRUCT
1236 #define REG_STRUCT apg_regs
1237 apg_regs_init(0),
1238 apg_regs_init(1),
1239 apg_regs_init(2),
1240 apg_regs_init(3);
1241
1242 apg31_construct(apg31, ctx, inst,
1243 &apg_regs[inst],
1244 &apg_shift,
1245 &apg_mask);
1246
1247 return &apg31->base;
1248 }
1249
dcn321_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1250 static struct stream_encoder *dcn321_stream_encoder_create(
1251 enum engine_id eng_id,
1252 struct dc_context *ctx)
1253 {
1254 struct dcn10_stream_encoder *enc1;
1255 struct vpg *vpg;
1256 struct afmt *afmt;
1257 int vpg_inst;
1258 int afmt_inst;
1259
1260 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1261 if (eng_id < 0 || eng_id >= ARRAY_SIZE(stream_enc_regs))
1262 return NULL;
1263
1264 vpg_inst = eng_id;
1265 afmt_inst = eng_id;
1266
1267 enc1 = kzalloc_obj(struct dcn10_stream_encoder);
1268 vpg = dcn321_vpg_create(ctx, vpg_inst);
1269 afmt = dcn321_afmt_create(ctx, afmt_inst);
1270
1271 if (!enc1 || !vpg || !afmt) {
1272 kfree(enc1);
1273 kfree(vpg);
1274 kfree(afmt);
1275 return NULL;
1276 }
1277
1278 #undef REG_STRUCT
1279 #define REG_STRUCT stream_enc_regs
1280 stream_enc_regs_init(0),
1281 stream_enc_regs_init(1),
1282 stream_enc_regs_init(2),
1283 stream_enc_regs_init(3),
1284 stream_enc_regs_init(4);
1285
1286 dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1287 eng_id, vpg, afmt,
1288 &stream_enc_regs[eng_id],
1289 &se_shift, &se_mask);
1290
1291 return &enc1->base;
1292 }
1293
dcn321_hpo_frl_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1294 static struct hpo_frl_stream_encoder *dcn321_hpo_frl_stream_encoder_create(enum engine_id eng_id,
1295 struct dc_context *ctx)
1296 {
1297 struct dcn30_hpo_frl_stream_encoder *hpo_enc3;
1298 struct afmt *afmt;
1299 struct vpg *vpg;
1300 int afmt_inst;
1301 int vpg_inst;
1302
1303 #undef REG_STRUCT
1304 #define REG_STRUCT hpo_frl_stream_enc_regs
1305 hpo_frl_stream_encoder_reg_list(0),
1306 hpo_frl_stream_encoder_dme_reg_list(6);
1307
1308 /* Mapping of VPG, AFMT, DME register blocks to HPO block instance */
1309 if (eng_id == ENGINE_ID_HPO_0) {
1310 vpg_inst = 5;
1311 afmt_inst = 5;
1312 } else {
1313 return NULL;
1314 }
1315
1316 /* allocate HPO stream encoder and create VPG, AFMT sub-blocks */
1317 hpo_enc3 = kzalloc_obj(struct dcn30_hpo_frl_stream_encoder);
1318 vpg = dcn321_vpg_create(ctx, vpg_inst);
1319 afmt = dcn321_afmt_create(ctx, afmt_inst);
1320
1321 if (!hpo_enc3 || !vpg || !afmt) {
1322 kfree(hpo_enc3);
1323 kfree(vpg);
1324 kfree(afmt);
1325 return NULL;
1326 }
1327
1328 dcn30_hpo_frl_stream_encoder_construct(hpo_enc3,
1329 ctx,
1330 ctx->dc_bios,
1331 eng_id,
1332 vpg,
1333 afmt,
1334 &hpo_frl_stream_enc_regs[eng_id - ENGINE_ID_HPO_0],
1335 &hpo_se_shift,
1336 &hpo_se_mask);
1337
1338 return &hpo_enc3->base;
1339 }
1340
dcn321_hpo_frl_link_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1341 static struct hpo_frl_link_encoder *dcn321_hpo_frl_link_encoder_create(enum engine_id eng_id,
1342 struct dc_context *ctx)
1343 {
1344 struct dcn30_hpo_frl_link_encoder *hpo_enc3;
1345
1346 ASSERT((eng_id == ENGINE_ID_HPO_0) || (eng_id == ENGINE_ID_HPO_1));
1347
1348 #undef REG_STRUCT
1349 #define REG_STRUCT hpo_frl_link_enc_regs
1350 hpo_frl_link_encoder_reg_list(0);
1351
1352 /* allocate HPO link encoder */
1353 hpo_enc3 = kzalloc_obj(struct dcn30_hpo_frl_link_encoder);
1354 if (!hpo_enc3)
1355 return NULL; /* out of memory */
1356
1357 hpo_frl_link_encoder3_construct(hpo_enc3,
1358 ctx,
1359 eng_id - ENGINE_ID_HPO_0,
1360 &hpo_frl_link_enc_regs[eng_id - ENGINE_ID_HPO_0],
1361 &hpo_le_shift,
1362 &hpo_le_mask);
1363
1364 return &hpo_enc3->base;
1365 }
1366
dcn321_hpo_dp_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1367 static struct hpo_dp_stream_encoder *dcn321_hpo_dp_stream_encoder_create(
1368 enum engine_id eng_id,
1369 struct dc_context *ctx)
1370 {
1371 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1372 struct vpg *vpg;
1373 struct apg *apg;
1374 uint32_t hpo_dp_inst;
1375 uint32_t vpg_inst;
1376 uint32_t apg_inst;
1377
1378 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1379 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1380
1381 /* Mapping of VPG register blocks to HPO DP block instance:
1382 * VPG[6] -> HPO_DP[0]
1383 * VPG[7] -> HPO_DP[1]
1384 * VPG[8] -> HPO_DP[2]
1385 * VPG[9] -> HPO_DP[3]
1386 */
1387 vpg_inst = hpo_dp_inst + 6;
1388
1389 /* Mapping of APG register blocks to HPO DP block instance:
1390 * APG[0] -> HPO_DP[0]
1391 * APG[1] -> HPO_DP[1]
1392 * APG[2] -> HPO_DP[2]
1393 * APG[3] -> HPO_DP[3]
1394 */
1395 apg_inst = hpo_dp_inst;
1396
1397 /* allocate HPO stream encoder and create VPG sub-block */
1398 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_stream_encoder);
1399 vpg = dcn321_vpg_create(ctx, vpg_inst);
1400 apg = dcn321_apg_create(ctx, apg_inst);
1401
1402 if (!hpo_dp_enc31 || !vpg || !apg) {
1403 kfree(hpo_dp_enc31);
1404 kfree(vpg);
1405 kfree(apg);
1406 return NULL;
1407 }
1408
1409 #undef REG_STRUCT
1410 #define REG_STRUCT hpo_dp_stream_enc_regs
1411 hpo_dp_stream_encoder_reg_init(0),
1412 hpo_dp_stream_encoder_reg_init(1),
1413 hpo_dp_stream_encoder_reg_init(2),
1414 hpo_dp_stream_encoder_reg_init(3);
1415
1416 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1417 hpo_dp_inst, eng_id, vpg, apg,
1418 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1419 &hpo_dp_se_shift, &hpo_dp_se_mask);
1420
1421 return &hpo_dp_enc31->base;
1422 }
1423
dcn321_hpo_dp_link_encoder_create(uint8_t inst,struct dc_context * ctx)1424 static struct hpo_dp_link_encoder *dcn321_hpo_dp_link_encoder_create(
1425 uint8_t inst,
1426 struct dc_context *ctx)
1427 {
1428 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1429
1430 /* allocate HPO link encoder */
1431 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_link_encoder);
1432 if (!hpo_dp_enc31)
1433 return NULL; /* out of memory */
1434
1435 #undef REG_STRUCT
1436 #define REG_STRUCT hpo_dp_link_enc_regs
1437 hpo_dp_link_encoder_reg_init(0),
1438 hpo_dp_link_encoder_reg_init(1);
1439
1440 hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst,
1441 &hpo_dp_link_enc_regs[inst],
1442 &hpo_dp_le_shift, &hpo_dp_le_mask);
1443
1444 return &hpo_dp_enc31->base;
1445 }
1446
dcn321_hwseq_create(struct dc_context * ctx)1447 static struct dce_hwseq *dcn321_hwseq_create(
1448 struct dc_context *ctx)
1449 {
1450 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);
1451
1452 #undef REG_STRUCT
1453 #define REG_STRUCT hwseq_reg
1454 hwseq_reg_init();
1455
1456 if (hws) {
1457 hws->ctx = ctx;
1458 hws->regs = &hwseq_reg;
1459 hws->shifts = &hwseq_shift;
1460 hws->masks = &hwseq_mask;
1461 }
1462 return hws;
1463 }
1464 static const struct resource_create_funcs res_create_funcs = {
1465 .read_dce_straps = read_dce_straps,
1466 .create_audio = dcn321_create_audio,
1467 .create_stream_encoder = dcn321_stream_encoder_create,
1468 .create_hpo_frl_stream_encoder = dcn321_hpo_frl_stream_encoder_create,
1469 .create_hpo_dp_stream_encoder = dcn321_hpo_dp_stream_encoder_create,
1470 .create_hpo_dp_link_encoder = dcn321_hpo_dp_link_encoder_create,
1471 .create_hwseq = dcn321_hwseq_create,
1472 };
1473
dcn321_resource_destruct(struct dcn321_resource_pool * pool)1474 static void dcn321_resource_destruct(struct dcn321_resource_pool *pool)
1475 {
1476 unsigned int i;
1477
1478 for (i = 0; i < pool->base.stream_enc_count; i++) {
1479 if (pool->base.stream_enc[i] != NULL) {
1480 if (pool->base.stream_enc[i]->vpg != NULL) {
1481 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1482 pool->base.stream_enc[i]->vpg = NULL;
1483 }
1484 if (pool->base.stream_enc[i]->afmt != NULL) {
1485 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1486 pool->base.stream_enc[i]->afmt = NULL;
1487 }
1488 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1489 pool->base.stream_enc[i] = NULL;
1490 }
1491 }
1492
1493 for (i = 0; i < pool->base.hpo_frl_stream_enc_count; i++) {
1494 if (pool->base.hpo_frl_stream_enc[i] != NULL) {
1495 if (pool->base.hpo_frl_stream_enc[i]->vpg != NULL) {
1496 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_frl_stream_enc[i]->vpg));
1497 pool->base.hpo_frl_stream_enc[i]->vpg = NULL;
1498 }
1499
1500 if (pool->base.hpo_frl_stream_enc[i]->afmt != NULL) {
1501 kfree(DCN30_AFMT_FROM_AFMT(pool->base.hpo_frl_stream_enc[i]->afmt));
1502 pool->base.hpo_frl_stream_enc[i]->afmt = NULL;
1503 }
1504
1505 kfree(DCN30_HPO_FRL_STRENC_FROM_HPO_FRL_STRENC(pool->base.hpo_frl_stream_enc[i]));
1506 pool->base.hpo_frl_stream_enc[i] = NULL;
1507 }
1508 }
1509
1510 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1511 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1512 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1513 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1514 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1515 }
1516 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1517 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1518 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1519 }
1520 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1521 pool->base.hpo_dp_stream_enc[i] = NULL;
1522 }
1523 }
1524
1525 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1526 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1527 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1528 pool->base.hpo_dp_link_enc[i] = NULL;
1529 }
1530 }
1531
1532 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
1533 if (pool->base.dscs[i] != NULL)
1534 dcn20_dsc_destroy(&pool->base.dscs[i]);
1535 }
1536
1537 if (pool->base.mpc != NULL) {
1538 kfree(TO_DCN20_MPC(pool->base.mpc));
1539 pool->base.mpc = NULL;
1540 }
1541 if (pool->base.hubbub != NULL) {
1542 kfree(TO_DCN20_HUBBUB(pool->base.hubbub));
1543 pool->base.hubbub = NULL;
1544 }
1545 for (i = 0; i < pool->base.pipe_count; i++) {
1546 if (pool->base.dpps[i] != NULL)
1547 dcn321_dpp_destroy(&pool->base.dpps[i]);
1548
1549 if (pool->base.ipps[i] != NULL)
1550 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1551
1552 if (pool->base.hubps[i] != NULL) {
1553 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1554 pool->base.hubps[i] = NULL;
1555 }
1556
1557 if (pool->base.irqs != NULL)
1558 dal_irq_service_destroy(&pool->base.irqs);
1559 }
1560
1561 for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
1562 if (pool->base.engines[i] != NULL)
1563 dce110_engine_destroy(&pool->base.engines[i]);
1564 if (pool->base.hw_i2cs[i] != NULL) {
1565 kfree(pool->base.hw_i2cs[i]);
1566 pool->base.hw_i2cs[i] = NULL;
1567 }
1568 if (pool->base.sw_i2cs[i] != NULL) {
1569 kfree(pool->base.sw_i2cs[i]);
1570 pool->base.sw_i2cs[i] = NULL;
1571 }
1572 }
1573
1574 for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
1575 if (pool->base.opps[i] != NULL)
1576 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1577 }
1578
1579 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
1580 if (pool->base.timing_generators[i] != NULL) {
1581 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1582 pool->base.timing_generators[i] = NULL;
1583 }
1584 }
1585
1586 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
1587 if (pool->base.dwbc[i] != NULL) {
1588 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1589 pool->base.dwbc[i] = NULL;
1590 }
1591 if (pool->base.mcif_wb[i] != NULL) {
1592 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1593 pool->base.mcif_wb[i] = NULL;
1594 }
1595 }
1596
1597 for (i = 0; i < pool->base.audio_count; i++) {
1598 if (pool->base.audios[i])
1599 dce_aud_destroy(&pool->base.audios[i]);
1600 }
1601
1602 for (i = 0; i < pool->base.clk_src_count; i++) {
1603 if (pool->base.clock_sources[i] != NULL) {
1604 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1605 pool->base.clock_sources[i] = NULL;
1606 }
1607 }
1608
1609 for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) {
1610 if (pool->base.mpc_lut[i] != NULL) {
1611 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1612 pool->base.mpc_lut[i] = NULL;
1613 }
1614 if (pool->base.mpc_shaper[i] != NULL) {
1615 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1616 pool->base.mpc_shaper[i] = NULL;
1617 }
1618 }
1619
1620 if (pool->base.dp_clock_source != NULL) {
1621 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1622 pool->base.dp_clock_source = NULL;
1623 }
1624
1625 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
1626 if (pool->base.multiple_abms[i] != NULL)
1627 dce_abm_destroy(&pool->base.multiple_abms[i]);
1628 }
1629
1630 if (pool->base.psr != NULL)
1631 dmub_psr_destroy(&pool->base.psr);
1632
1633 if (pool->base.dccg != NULL)
1634 dcn_dccg_destroy(&pool->base.dccg);
1635
1636 if (pool->base.dio != NULL) {
1637 kfree(TO_DCN10_DIO(pool->base.dio));
1638 pool->base.dio = NULL;
1639 }
1640
1641 if (pool->base.oem_device != NULL) {
1642 struct dc *dc = pool->base.oem_device->ctx->dc;
1643
1644 dc->link_srv->destroy_ddc_service(&pool->base.oem_device);
1645 }
1646 }
1647
1648
dcn321_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)1649 static bool dcn321_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1650 {
1651 unsigned int i;
1652 uint32_t dwb_count = pool->res_cap->num_dwb;
1653
1654 for (i = 0; i < dwb_count; i++) {
1655 struct dcn30_dwbc *dwbc30 = kzalloc_obj(struct dcn30_dwbc);
1656
1657 if (!dwbc30) {
1658 dm_error("DC: failed to create dwbc30!\n");
1659 return false;
1660 }
1661
1662 #undef REG_STRUCT
1663 #define REG_STRUCT dwbc30_regs
1664 dwbc_regs_dcn3_init(0);
1665
1666 dcn30_dwbc_construct(dwbc30, ctx,
1667 &dwbc30_regs[i],
1668 &dwbc30_shift,
1669 &dwbc30_mask,
1670 i);
1671
1672 pool->dwbc[i] = &dwbc30->base;
1673 }
1674 return true;
1675 }
1676
dcn321_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)1677 static bool dcn321_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1678 {
1679 unsigned int i;
1680 uint32_t dwb_count = pool->res_cap->num_dwb;
1681
1682 for (i = 0; i < dwb_count; i++) {
1683 struct dcn30_mmhubbub *mcif_wb30 = kzalloc_obj(struct dcn30_mmhubbub);
1684
1685 if (!mcif_wb30) {
1686 dm_error("DC: failed to create mcif_wb30!\n");
1687 return false;
1688 }
1689
1690 #undef REG_STRUCT
1691 #define REG_STRUCT mcif_wb30_regs
1692 mcif_wb_regs_dcn3_init(0);
1693
1694 dcn32_mmhubbub_construct(mcif_wb30, ctx,
1695 &mcif_wb30_regs[i],
1696 &mcif_wb30_shift,
1697 &mcif_wb30_mask,
1698 i);
1699
1700 pool->mcif_wb[i] = &mcif_wb30->base;
1701 }
1702 return true;
1703 }
1704
dcn321_dsc_create(struct dc_context * ctx,uint32_t inst)1705 static struct display_stream_compressor *dcn321_dsc_create(
1706 struct dc_context *ctx, uint32_t inst)
1707 {
1708 struct dcn20_dsc *dsc =
1709 kzalloc_obj(struct dcn20_dsc);
1710
1711 if (!dsc) {
1712 BREAK_TO_DEBUGGER();
1713 return NULL;
1714 }
1715
1716 #undef REG_STRUCT
1717 #define REG_STRUCT dsc_regs
1718 dsc_regsDCN20_init(0),
1719 dsc_regsDCN20_init(1),
1720 dsc_regsDCN20_init(2),
1721 dsc_regsDCN20_init(3);
1722
1723 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1724
1725 dsc->max_image_width = 6016;
1726
1727 return &dsc->base;
1728 }
1729
dcn321_destroy_resource_pool(struct resource_pool ** pool)1730 static void dcn321_destroy_resource_pool(struct resource_pool **pool)
1731 {
1732 struct dcn321_resource_pool *dcn321_pool = TO_DCN321_RES_POOL(*pool);
1733
1734 dcn321_resource_destruct(dcn321_pool);
1735 kfree(dcn321_pool);
1736 *pool = NULL;
1737 }
1738
1739 static struct dc_cap_funcs cap_funcs = {
1740 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap,
1741 .get_subvp_en = dcn32_subvp_in_use,
1742 };
1743
dcn321_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)1744 static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1745 {
1746 DC_FP_START();
1747
1748 dcn321_update_bw_bounding_box_fpu(dc, bw_params);
1749
1750 if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2)
1751 dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2);
1752
1753 if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2_dc_power_source)
1754 dml2_reinit(dc, &dc->dml2_dc_power_options, &dc->current_state->bw_ctx.dml2_dc_power_source);
1755
1756 DC_FP_END();
1757 }
1758
1759 static struct resource_funcs dcn321_res_pool_funcs = {
1760 .destroy = dcn321_destroy_resource_pool,
1761 .link_enc_create = dcn321_link_encoder_create,
1762 .link_enc_create_minimal = NULL,
1763 .hpo_frl_link_enc_create = dcn321_hpo_frl_link_encoder_create,
1764 .panel_cntl_create = dcn32_panel_cntl_create,
1765 .validate_bandwidth = dcn32_validate_bandwidth,
1766 .calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg,
1767 .populate_dml_pipes = dcn32_populate_dml_pipes_from_context,
1768 .acquire_free_pipe_as_secondary_dpp_pipe = dcn32_acquire_free_pipe_as_secondary_dpp_pipe,
1769 .acquire_free_pipe_as_secondary_opp_head = dcn32_acquire_free_pipe_as_secondary_opp_head,
1770 .release_pipe = dcn20_release_pipe,
1771 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1772 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1773 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1774 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1775 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1776 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1777 .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut,
1778 .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut,
1779 .update_bw_bounding_box = dcn321_update_bw_bounding_box,
1780 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1781 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
1782 .add_phantom_pipes = dcn32_add_phantom_pipes,
1783 .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params,
1784 .calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes,
1785 .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
1786 .get_max_hw_cursor_size = dcn32_get_max_hw_cursor_size,
1787 .get_default_tiling_info = dcn10_get_default_tiling_info,
1788 };
1789
read_pipe_fuses(struct dc_context * ctx)1790 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1791 {
1792 uint32_t value = REG_READ(CC_DC_PIPE_DIS);
1793 /* DCN321 support max 4 pipes */
1794 value = value & 0xf;
1795 return value;
1796 }
1797
1798
dcn321_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn321_resource_pool * pool)1799 static bool dcn321_resource_construct(
1800 uint8_t num_virtual_links,
1801 struct dc *dc,
1802 struct dcn321_resource_pool *pool)
1803 {
1804 int i, j;
1805 struct dc_context *ctx = dc->ctx;
1806 struct irq_service_init_data init_data;
1807 struct ddc_service_init_data ddc_init_data = {0};
1808 uint32_t pipe_fuses = 0;
1809 uint32_t num_pipes = 4;
1810
1811 #undef REG_STRUCT
1812 #define REG_STRUCT bios_regs
1813 bios_regs_init();
1814
1815 #undef REG_STRUCT
1816 #define REG_STRUCT clk_src_regs
1817 clk_src_regs_init(0, A),
1818 clk_src_regs_init(1, B),
1819 clk_src_regs_init(2, C),
1820 clk_src_regs_init(3, D),
1821 clk_src_regs_init(4, E);
1822
1823 #undef REG_STRUCT
1824 #define REG_STRUCT abm_regs
1825 abm_regs_init(0),
1826 abm_regs_init(1),
1827 abm_regs_init(2),
1828 abm_regs_init(3);
1829
1830 #undef REG_STRUCT
1831 #define REG_STRUCT dccg_regs
1832 dccg_regs_init();
1833
1834
1835 ctx->dc_bios->regs = &bios_regs;
1836
1837 pool->base.res_cap = &res_cap_dcn321;
1838 /* max number of pipes for ASIC before checking for pipe fuses */
1839 num_pipes = pool->base.res_cap->num_timing_generator;
1840 pipe_fuses = read_pipe_fuses(ctx);
1841
1842 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++)
1843 if (pipe_fuses & 1 << i)
1844 num_pipes--;
1845
1846 if (pipe_fuses & 1)
1847 ASSERT(0); //Unexpected - Pipe 0 should always be fully functional!
1848
1849 if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK)
1850 ASSERT(0); //Entire DCN is harvested!
1851
1852 /* within dml lib, initial value is hard coded, if ASIC pipe is fused, the
1853 * value will be changed, update max_num_dpp and max_num_otg for dml.
1854 */
1855 dcn3_21_ip.max_num_dpp = num_pipes;
1856 dcn3_21_ip.max_num_otg = num_pipes;
1857
1858 pool->base.funcs = &dcn321_res_pool_funcs;
1859
1860 /*************************************************
1861 * Resource + asic cap harcoding *
1862 *************************************************/
1863 pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
1864 pool->base.timing_generator_count = num_pipes;
1865 pool->base.pipe_count = num_pipes;
1866 pool->base.mpcc_count = num_pipes;
1867 dc->caps.max_downscale_ratio = 600;
1868 dc->caps.i2c_speed_in_khz = 100;
1869 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/
1870 /* TODO: Bring max cursor size back to 256 after subvp cursor corruption is fixed*/
1871 dc->caps.max_cursor_size = 64;
1872 dc->caps.max_buffered_cursor_size = 64; // sqrt(16 * 1024 / 4)
1873 dc->caps.min_horizontal_blanking_period = 80;
1874 dc->caps.dmdata_alloc_size = 2048;
1875 dc->caps.mall_size_per_mem_channel = 4;
1876 /* total size = mall per channel * num channels * 1024 * 1024 */
1877 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;
1878
1879 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
1880 dc->caps.cache_line_size = 64;
1881 dc->caps.cache_num_ways = 16;
1882
1883 /* Calculate the available MALL space */
1884 dc->caps.max_cab_allocation_bytes = dcn32_calc_num_avail_chans_for_mall(
1885 dc, dc->ctx->dc_bios->vram_info.num_chans) *
1886 dc->caps.mall_size_per_mem_channel * 1024 * 1024;
1887 dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes;
1888
1889 dc->caps.subvp_fw_processing_delay_us = 15;
1890 dc->caps.subvp_drr_max_vblank_margin_us = 40;
1891 dc->caps.subvp_prefetch_end_to_mall_start_us = 15;
1892 dc->caps.subvp_swath_height_margin_lines = 16;
1893 dc->caps.subvp_pstate_allow_width_us = 20;
1894 dc->caps.subvp_vertical_int_margin_us = 30;
1895 dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin
1896 dc->caps.max_slave_planes = 2;
1897 dc->caps.max_slave_yuv_planes = 2;
1898 dc->caps.max_slave_rgb_planes = 2;
1899 dc->caps.post_blend_color_processing = true;
1900 dc->caps.force_dp_tps4_for_cp2520 = true;
1901 dc->caps.hdmi_hpo = true;
1902 dc->caps.dp_hpo = true;
1903 dc->caps.dp_hdmi21_pcon_support = true;
1904 dc->caps.edp_dsc_support = true;
1905 dc->caps.extended_aux_timeout_support = true;
1906 dc->caps.dmcub_support = true;
1907 dc->caps.max_v_total = (1 << 15) - 1;
1908 dc->caps.vtotal_limited_by_fp2 = true;
1909
1910 /* Color pipeline capabilities */
1911 dc->caps.color.dpp.dcn_arch = 1;
1912 dc->caps.color.dpp.input_lut_shared = 0;
1913 dc->caps.color.dpp.icsc = 1;
1914 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1915 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1916 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1917 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1918 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1919 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1920 dc->caps.color.dpp.post_csc = 1;
1921 dc->caps.color.dpp.gamma_corr = 1;
1922 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1923 dc->caps.color.dpp.upsp_pre_scaler = 0;
1924
1925 dc->caps.color.dpp.hw_3d_lut = 0;
1926 dc->caps.color.dpp.ogam_ram = 0;
1927 // no OGAM ROM on DCN2 and later ASICs
1928 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1929 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1930 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1931 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1932 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1933 dc->caps.color.dpp.ocsc = 0;
1934
1935 dc->caps.color.mpc.gamut_remap = 1;
1936 dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC
1937 dc->caps.color.mpc.ogam_ram = 1;
1938 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1939 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1940 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1941 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1942 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1943 dc->caps.color.mpc.ocsc = 1;
1944 dc->caps.color.mpc.preblend = true;
1945 dc->caps.color.mpc.max_gamut_remap_coeff = dc_fixpt_from_fraction(S3D12_MAX, DIVIDER);
1946 /* HACK: Force FRL support until BIOS is ready. */
1947 dc->config.force_hdmi21_frl_enc_enable = true;
1948
1949 /* Use pipe context based otg sync logic */
1950 dc->config.use_pipe_ctx_sync_logic = true;
1951
1952 dc->config.dc_mode_clk_limit_support = true;
1953 dc->config.enable_windowed_mpo_odm = true;
1954 dc->config.disable_hbr_audio_dp2 = true;
1955 /* read VBIOS LTTPR caps */
1956 {
1957 if (ctx->dc_bios->funcs->get_lttpr_caps) {
1958 enum bp_result bp_query_result;
1959 uint8_t is_vbios_lttpr_enable = 0;
1960
1961 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1962 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1963 }
1964
1965 /* interop bit is implicit */
1966 {
1967 dc->caps.vbios_lttpr_aware = true;
1968 }
1969 }
1970 dc->check_config = config_defaults;
1971
1972 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1973 dc->debug = debug_defaults_drv;
1974
1975 // Init the vm_helper
1976 if (dc->vm_helper)
1977 vm_helper_init(dc->vm_helper, 16);
1978
1979 /*************************************************
1980 * Create resources *
1981 *************************************************/
1982
1983 /* Clock Sources for Pixel Clock*/
1984 pool->base.clock_sources[DCN321_CLK_SRC_PLL0] =
1985 dcn321_clock_source_create(ctx, ctx->dc_bios,
1986 CLOCK_SOURCE_COMBO_PHY_PLL0,
1987 &clk_src_regs[0], false);
1988 pool->base.clock_sources[DCN321_CLK_SRC_PLL1] =
1989 dcn321_clock_source_create(ctx, ctx->dc_bios,
1990 CLOCK_SOURCE_COMBO_PHY_PLL1,
1991 &clk_src_regs[1], false);
1992 pool->base.clock_sources[DCN321_CLK_SRC_PLL2] =
1993 dcn321_clock_source_create(ctx, ctx->dc_bios,
1994 CLOCK_SOURCE_COMBO_PHY_PLL2,
1995 &clk_src_regs[2], false);
1996 pool->base.clock_sources[DCN321_CLK_SRC_PLL3] =
1997 dcn321_clock_source_create(ctx, ctx->dc_bios,
1998 CLOCK_SOURCE_COMBO_PHY_PLL3,
1999 &clk_src_regs[3], false);
2000 pool->base.clock_sources[DCN321_CLK_SRC_PLL4] =
2001 dcn321_clock_source_create(ctx, ctx->dc_bios,
2002 CLOCK_SOURCE_COMBO_PHY_PLL4,
2003 &clk_src_regs[4], false);
2004
2005 pool->base.clk_src_count = DCN321_CLK_SRC_TOTAL;
2006
2007 /* todo: not reuse phy_pll registers */
2008 pool->base.dp_clock_source =
2009 dcn321_clock_source_create(ctx, ctx->dc_bios,
2010 CLOCK_SOURCE_ID_DP_DTO,
2011 &clk_src_regs[0], true);
2012
2013 for (i = 0; i < (int)pool->base.clk_src_count; i++) {
2014 if (pool->base.clock_sources[i] == NULL) {
2015 dm_error("DC: failed to create clock sources!\n");
2016 BREAK_TO_DEBUGGER();
2017 goto create_fail;
2018 }
2019 }
2020
2021 /* DCCG */
2022 pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2023 if (pool->base.dccg == NULL) {
2024 dm_error("DC: failed to create dccg!\n");
2025 BREAK_TO_DEBUGGER();
2026 goto create_fail;
2027 }
2028
2029 /* DML */
2030 dml_init_instance(&dc->dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32);
2031
2032 /* IRQ Service */
2033 init_data.ctx = dc->ctx;
2034 pool->base.irqs = dal_irq_service_dcn32_create(&init_data);
2035 if (!pool->base.irqs)
2036 goto create_fail;
2037
2038 /* HUBBUB */
2039 pool->base.hubbub = dcn321_hubbub_create(ctx);
2040 if (pool->base.hubbub == NULL) {
2041 BREAK_TO_DEBUGGER();
2042 dm_error("DC: failed to create hubbub!\n");
2043 goto create_fail;
2044 }
2045
2046 /* DIO */
2047 pool->base.dio = dcn321_dio_create(ctx);
2048 if (pool->base.dio == NULL) {
2049 BREAK_TO_DEBUGGER();
2050 dm_error("DC: failed to create dio!\n");
2051 goto create_fail;
2052 }
2053
2054 /* HUBPs, DPPs, OPPs, TGs, ABMs */
2055 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2056
2057 /* if pipe is disabled, skip instance of HW pipe,
2058 * i.e, skip ASIC register instance
2059 */
2060 if (pipe_fuses & 1 << i)
2061 continue;
2062
2063 pool->base.hubps[j] = dcn321_hubp_create(ctx, i);
2064 if (pool->base.hubps[j] == NULL) {
2065 BREAK_TO_DEBUGGER();
2066 dm_error(
2067 "DC: failed to create hubps!\n");
2068 goto create_fail;
2069 }
2070
2071 pool->base.dpps[j] = dcn321_dpp_create(ctx, i);
2072 if (pool->base.dpps[j] == NULL) {
2073 BREAK_TO_DEBUGGER();
2074 dm_error(
2075 "DC: failed to create dpps!\n");
2076 goto create_fail;
2077 }
2078
2079 pool->base.opps[j] = dcn321_opp_create(ctx, i);
2080 if (pool->base.opps[j] == NULL) {
2081 BREAK_TO_DEBUGGER();
2082 dm_error(
2083 "DC: failed to create output pixel processor!\n");
2084 goto create_fail;
2085 }
2086
2087 pool->base.timing_generators[j] = dcn321_timing_generator_create(
2088 ctx, i);
2089 if (pool->base.timing_generators[j] == NULL) {
2090 BREAK_TO_DEBUGGER();
2091 dm_error("DC: failed to create tg!\n");
2092 goto create_fail;
2093 }
2094
2095 pool->base.multiple_abms[j] = dmub_abm_create(ctx,
2096 &abm_regs[i],
2097 &abm_shift,
2098 &abm_mask);
2099 if (pool->base.multiple_abms[j] == NULL) {
2100 dm_error("DC: failed to create abm for pipe %d!\n", i);
2101 BREAK_TO_DEBUGGER();
2102 goto create_fail;
2103 }
2104
2105 /* index for resource pool arrays for next valid pipe */
2106 j++;
2107 }
2108
2109 /* PSR */
2110 pool->base.psr = dmub_psr_create(ctx);
2111 if (pool->base.psr == NULL) {
2112 dm_error("DC: failed to create psr obj!\n");
2113 BREAK_TO_DEBUGGER();
2114 goto create_fail;
2115 }
2116
2117 /* MPCCs */
2118 pool->base.mpc = dcn321_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut);
2119 if (pool->base.mpc == NULL) {
2120 BREAK_TO_DEBUGGER();
2121 dm_error("DC: failed to create mpc!\n");
2122 goto create_fail;
2123 }
2124
2125 /* DSCs */
2126 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2127 pool->base.dscs[i] = dcn321_dsc_create(ctx, i);
2128 if (pool->base.dscs[i] == NULL) {
2129 BREAK_TO_DEBUGGER();
2130 dm_error("DC: failed to create display stream compressor %d!\n", i);
2131 goto create_fail;
2132 }
2133 }
2134
2135 /* DWB */
2136 if (!dcn321_dwbc_create(ctx, &pool->base)) {
2137 BREAK_TO_DEBUGGER();
2138 dm_error("DC: failed to create dwbc!\n");
2139 goto create_fail;
2140 }
2141
2142 /* MMHUBBUB */
2143 if (!dcn321_mmhubbub_create(ctx, &pool->base)) {
2144 BREAK_TO_DEBUGGER();
2145 dm_error("DC: failed to create mcif_wb!\n");
2146 goto create_fail;
2147 }
2148
2149 /* AUX and I2C */
2150 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2151 pool->base.engines[i] = dcn321_aux_engine_create(ctx, i);
2152 if (pool->base.engines[i] == NULL) {
2153 BREAK_TO_DEBUGGER();
2154 dm_error(
2155 "DC:failed to create aux engine!!\n");
2156 goto create_fail;
2157 }
2158 pool->base.hw_i2cs[i] = dcn321_i2c_hw_create(ctx, i);
2159 if (pool->base.hw_i2cs[i] == NULL) {
2160 BREAK_TO_DEBUGGER();
2161 dm_error(
2162 "DC:failed to create hw i2c!!\n");
2163 goto create_fail;
2164 }
2165 pool->base.sw_i2cs[i] = NULL;
2166 }
2167
2168 /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2169 if (!resource_construct(num_virtual_links, dc, &pool->base,
2170 &res_create_funcs))
2171 goto create_fail;
2172
2173 /* HW Sequencer init functions and Plane caps */
2174 dcn32_hw_sequencer_init_functions(dc);
2175
2176 dc->caps.max_planes = pool->base.pipe_count;
2177
2178 for (i = 0; i < (int)dc->caps.max_planes; ++i)
2179 dc->caps.planes[i] = plane_cap;
2180
2181 dc->caps.max_odm_combine_factor = 4;
2182
2183 dc->cap_funcs = cap_funcs;
2184
2185 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
2186 ddc_init_data.ctx = dc->ctx;
2187 ddc_init_data.link = NULL;
2188 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
2189 ddc_init_data.id.enum_id = 0;
2190 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
2191 pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);
2192 } else {
2193 pool->base.oem_device = NULL;
2194 }
2195
2196 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;
2197 dc->dml2_options.use_native_soc_bb_construction = true;
2198 dc->dml2_options.minimize_dispclk_using_odm = true;
2199
2200 resource_init_common_dml2_callbacks(dc, &dc->dml2_options);
2201 dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;
2202 dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc;
2203 dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = pool->base.funcs->calculate_mall_ways_from_bytes;
2204
2205 dc->dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc->caps.subvp_fw_processing_delay_us;
2206 dc->dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc->caps.subvp_prefetch_end_to_mall_start_us;
2207 dc->dml2_options.svp_pstate.subvp_pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us;
2208 dc->dml2_options.svp_pstate.subvp_swath_height_margin_lines = dc->caps.subvp_swath_height_margin_lines;
2209
2210 dc->dml2_options.svp_pstate.force_disable_subvp = dc->debug.force_disable_subvp;
2211 dc->dml2_options.svp_pstate.force_enable_subvp = dc->debug.force_subvp_mclk_switch;
2212
2213 dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size;
2214 dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways;
2215 dc->dml2_options.mall_cfg.max_cab_allocation_bytes = dc->caps.max_cab_allocation_bytes;
2216 dc->dml2_options.mall_cfg.mblk_height_4bpe_pixels = DCN3_2_MBLK_HEIGHT_4BPE;
2217 dc->dml2_options.mall_cfg.mblk_height_8bpe_pixels = DCN3_2_MBLK_HEIGHT_8BPE;
2218 dc->dml2_options.mall_cfg.mblk_size_bytes = DCN3_2_MALL_MBLK_SIZE_BYTES;
2219 dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH;
2220
2221 dc->dml2_options.max_segments_per_hubp = 18;
2222 dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;
2223
2224 /* init DC limited DML2 options */
2225 memcpy(&dc->dml2_dc_power_options, &dc->dml2_options, sizeof(struct dml2_configuration_options));
2226 dc->dml2_dc_power_options.use_clock_dc_limits = true;
2227
2228 return true;
2229
2230 create_fail:
2231
2232 dcn321_resource_destruct(pool);
2233
2234 return false;
2235 }
2236
dcn321_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2237 struct resource_pool *dcn321_create_resource_pool(
2238 const struct dc_init_data *init_data,
2239 struct dc *dc)
2240 {
2241 struct dcn321_resource_pool *pool =
2242 kzalloc_obj(struct dcn321_resource_pool);
2243
2244 if (!pool)
2245 return NULL;
2246
2247 if (dcn321_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
2248 return &pool->base;
2249
2250 BREAK_TO_DEBUGGER();
2251 kfree(pool);
2252 return NULL;
2253 }
2254