1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright 2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27
28
29 #include "dcn314_clk_mgr.h"
30
31 #include "dccg.h"
32 #include "clk_mgr_internal.h"
33
34 // For dce12_get_dp_ref_freq_khz
35 #include "dce100/dce_clk_mgr.h"
36
37 // For dcn20_update_clocks_update_dpp_dto
38 #include "dcn20/dcn20_clk_mgr.h"
39
40
41
42 #include "reg_helper.h"
43 #include "core_types.h"
44 #include "dm_helpers.h"
45
46 /* TODO: remove this include once we ported over remaining clk mgr functions*/
47 #include "dcn30/dcn30_clk_mgr.h"
48 #include "dcn31/dcn31_clk_mgr.h"
49
50 #include "dc_dmub_srv.h"
51 #include "link_service.h"
52 #include "dcn314_smu.h"
53
54
55 #include "logger_types.h"
56
57
58 #define MAX_INSTANCE 7
59 #define MAX_SEGMENT 8
60
61 struct IP_BASE_INSTANCE {
62 unsigned int segment[MAX_SEGMENT];
63 };
64
65 struct IP_BASE {
66 struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
67 };
68
69 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0, 0, 0 } },
70 { { 0x00016E00, 0x02401C00, 0, 0, 0, 0, 0, 0 } },
71 { { 0x00017000, 0x02402000, 0, 0, 0, 0, 0, 0 } },
72 { { 0x00017200, 0x02402400, 0, 0, 0, 0, 0, 0 } },
73 { { 0x0001B000, 0x0242D800, 0, 0, 0, 0, 0, 0 } },
74 { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0, 0, 0 } },
75 { { 0x0001B400, 0x0242E000, 0, 0, 0, 0, 0, 0 } } } };
76
77 #undef DC_LOGGER
78 #define DC_LOGGER \
79 clk_mgr->base.base.ctx->logger
80 #define regCLK1_CLK_PLL_REQ 0x0237
81 #define regCLK1_CLK_PLL_REQ_BASE_IDX 0
82
83 #define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
84 #define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc
85 #define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
86 #define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
87 #define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L
88 #define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
89
90 #define regCLK1_CLK2_BYPASS_CNTL 0x029c
91 #define regCLK1_CLK2_BYPASS_CNTL_BASE_IDX 0
92
93 #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL__SHIFT 0x0
94 #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV__SHIFT 0x10
95 #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK 0x00000007L
96 #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV_MASK 0x000F0000L
97
98 #define regCLK6_0_CLK6_spll_field_8 0x464b
99 #define regCLK6_0_CLK6_spll_field_8_BASE_IDX 0
100
101 #define CLK6_0_CLK6_spll_field_8__spll_ssc_en__SHIFT 0xd
102 #define CLK6_0_CLK6_spll_field_8__spll_ssc_en_MASK 0x00002000L
103
104 #define REG(reg_name) \
105 (CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
106
107 #define TO_CLK_MGR_DCN314(clk_mgr)\
108 container_of(clk_mgr, struct clk_mgr_dcn314, base)
109
dcn314_get_active_display_cnt_wa(struct dc * dc,struct dc_state * context)110 static int dcn314_get_active_display_cnt_wa(
111 struct dc *dc,
112 struct dc_state *context)
113 {
114 int i, display_count;
115 bool tmds_present = false;
116
117 display_count = 0;
118 for (i = 0; i < context->stream_count; i++) {
119 const struct dc_stream_state *stream = context->streams[i];
120
121 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
122 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
123 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
124 tmds_present = true;
125
126 /* Checking stream / link detection ensuring that PHY is active*/
127 if (dc_is_dp_signal(stream->signal) && !stream->dpms_off)
128 display_count++;
129
130 /* FRL can't be tracked by DIG enablement */
131 if (dc_is_hdmi_frl_signal(stream->signal))
132 display_count++;
133 }
134
135 for (i = 0; i < dc->link_count; i++) {
136 const struct dc_link *link = dc->links[i];
137
138 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
139 if (link->link_enc && link->link_enc->funcs->is_dig_enabled &&
140 link->link_enc->funcs->is_dig_enabled(link->link_enc))
141 display_count++;
142 }
143
144 /* WA for hang on HDMI after display off back on*/
145 if (display_count == 0 && tmds_present)
146 display_count = 1;
147
148 return display_count;
149 }
150
dcn314_disable_otg_wa(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower,bool disable)151 static void dcn314_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context,
152 bool safe_to_lower, bool disable)
153 {
154 struct dc *dc = clk_mgr_base->ctx->dc;
155 uint8_t i;
156
157 for (i = 0; i < dc->res_pool->pipe_count; ++i) {
158 struct pipe_ctx *pipe = safe_to_lower
159 ? &context->res_ctx.pipe_ctx[i]
160 : &dc->current_state->res_ctx.pipe_ctx[i];
161
162 if (pipe->top_pipe || pipe->prev_odm_pipe)
163 continue;
164 if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))) {
165 if (disable) {
166 if (pipe->stream_res.tg && pipe->stream_res.tg->funcs->immediate_disable_crtc)
167 pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
168
169 reset_sync_context_for_pipe(dc, context, i);
170 } else {
171 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
172 }
173 }
174 }
175 }
176
dcn314_is_spll_ssc_enabled(struct clk_mgr * clk_mgr_base)177 bool dcn314_is_spll_ssc_enabled(struct clk_mgr *clk_mgr_base)
178 {
179 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
180 uint32_t ssc_enable;
181
182 REG_GET(CLK6_0_CLK6_spll_field_8, spll_ssc_en, &ssc_enable);
183
184 return ssc_enable == 1;
185 }
186
dcn314_init_clocks(struct clk_mgr * clk_mgr)187 void dcn314_init_clocks(struct clk_mgr *clk_mgr)
188 {
189 struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);
190 uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz;
191
192 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
193 // Assumption is that boot state always supports pstate
194 clk_mgr->clks.ref_dtbclk_khz = ref_dtbclk; // restore ref_dtbclk
195 clk_mgr->clks.p_state_change_support = true;
196 clk_mgr->clks.prev_p_state_change_support = true;
197 clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
198 clk_mgr->clks.zstate_support = DCN_ZSTATE_SUPPORT_UNKNOWN;
199
200 // to adjust dp_dto reference clock if ssc is enable otherwise to apply dprefclk
201 if (dcn314_is_spll_ssc_enabled(clk_mgr))
202 clk_mgr->dp_dto_source_clock_in_khz =
203 dce_adjust_dp_ref_freq_for_ss(clk_mgr_int, clk_mgr->dprefclk_khz);
204 else
205 clk_mgr->dp_dto_source_clock_in_khz = clk_mgr->dprefclk_khz;
206 }
207
dcn314_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)208 void dcn314_update_clocks(struct clk_mgr *clk_mgr_base,
209 struct dc_state *context,
210 bool safe_to_lower)
211 {
212 union dmub_rb_cmd cmd;
213 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
214 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
215 struct dc *dc = clk_mgr_base->ctx->dc;
216 int display_count = 0;
217 bool update_dppclk = false;
218 bool update_dispclk = false;
219 bool dpp_clock_lowered = false;
220
221 if (dc->work_arounds.skip_clock_update)
222 return;
223
224 display_count = dcn314_get_active_display_cnt_wa(dc, context);
225 /*
226 * if it is safe to lower, but we are already in the lower state, we don't have to do anything
227 * also if safe to lower is false, we just go in the higher state
228 */
229 if (safe_to_lower) {
230 if (new_clocks->zstate_support != DCN_ZSTATE_SUPPORT_DISALLOW &&
231 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) {
232 dcn314_smu_set_zstate_support(clk_mgr, new_clocks->zstate_support);
233 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
234 }
235
236 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) {
237 dcn314_smu_set_dtbclk(clk_mgr, false);
238 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
239 }
240 /* check that we're not already in lower */
241 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
242 /* if we can go lower, go lower */
243 if (display_count == 0) {
244 union display_idle_optimization_u idle_info = { 0 };
245 idle_info.idle_info.df_request_disabled = 1;
246 idle_info.idle_info.phy_ref_clk_off = 1;
247 idle_info.idle_info.s0i2_rdy = 1;
248 dcn314_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
249 /* update power state */
250 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
251 }
252 }
253 } else {
254 if (new_clocks->zstate_support == DCN_ZSTATE_SUPPORT_DISALLOW &&
255 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) {
256 dcn314_smu_set_zstate_support(clk_mgr, DCN_ZSTATE_SUPPORT_DISALLOW);
257 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
258 }
259
260 if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) {
261 dcn314_smu_set_dtbclk(clk_mgr, true);
262 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
263 }
264
265 /* check that we're not already in D0 */
266 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
267 union display_idle_optimization_u idle_info = { 0 };
268
269 dcn314_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
270 /* update power state */
271 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
272 }
273 }
274
275 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
276 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
277 dcn314_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
278 }
279
280 if (should_set_clock(safe_to_lower,
281 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
282 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
283 dcn314_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
284 }
285
286 // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
287 if (new_clocks->dppclk_khz < 100000)
288 new_clocks->dppclk_khz = 100000;
289
290 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
291 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
292 dpp_clock_lowered = true;
293 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
294 update_dppclk = true;
295 }
296
297 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) &&
298 (new_clocks->dispclk_khz > 0 || (safe_to_lower && display_count == 0))) {
299 uint32_t requested_dispclk_khz = new_clocks->dispclk_khz;
300
301 dcn314_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true);
302
303 /* Clamp the requested clock to PMFW based on their limit. */
304 if (dc->debug.min_disp_clk_khz > 0 && requested_dispclk_khz < dc->debug.min_disp_clk_khz)
305 requested_dispclk_khz = dc->debug.min_disp_clk_khz;
306
307 dcn314_smu_set_dispclk(clk_mgr, requested_dispclk_khz);
308 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
309 dcn314_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false);
310
311 update_dispclk = true;
312 }
313
314 if (dpp_clock_lowered) {
315 // increase per DPP DTO before lowering global dppclk
316 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
317 dcn314_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
318 } else {
319 // increase global DPPCLK before lowering per DPP DTO
320 if (update_dppclk || update_dispclk)
321 dcn314_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
322 // always update dtos unless clock is lowered and not safe to lower
323 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
324 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
325 }
326
327 // notify DMCUB of latest clocks
328 memset(&cmd, 0, sizeof(cmd));
329 cmd.notify_clocks.header.type = DMUB_CMD__CLK_MGR;
330 cmd.notify_clocks.header.sub_type = DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS;
331 cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz;
332 cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz =
333 clk_mgr_base->clks.dcfclk_deep_sleep_khz;
334 cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz;
335 cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz;
336
337 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
338 }
339
get_vco_frequency_from_reg(struct clk_mgr_internal * clk_mgr)340 static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
341 {
342 /* get FbMult value */
343 struct fixed31_32 pll_req;
344 unsigned int fbmult_frac_val = 0;
345 unsigned int fbmult_int_val = 0;
346
347 /*
348 * Register value of fbmult is in 8.16 format, we are converting to 314.32
349 * to leverage the fix point operations available in driver
350 */
351
352 REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
353 REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
354
355 pll_req = dc_fixpt_from_int(fbmult_int_val);
356
357 /*
358 * since fractional part is only 16 bit in register definition but is 32 bit
359 * in our fix point definiton, need to shift left by 16 to obtain correct value
360 */
361 pll_req.value |= fbmult_frac_val << 16;
362
363 /* multiply by REFCLK period */
364 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
365
366 /* integer part is now VCO frequency in kHz */
367 return dc_fixpt_floor(pll_req);
368 }
369
dcn314_enable_pme_wa(struct clk_mgr * clk_mgr_base)370 static void dcn314_enable_pme_wa(struct clk_mgr *clk_mgr_base)
371 {
372 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
373
374 dcn314_smu_enable_pme_wa(clk_mgr);
375 }
376
dcn314_are_clock_states_equal(struct dc_clocks * a,struct dc_clocks * b)377 bool dcn314_are_clock_states_equal(struct dc_clocks *a,
378 struct dc_clocks *b)
379 {
380 if (a->dispclk_khz != b->dispclk_khz)
381 return false;
382 else if (a->dppclk_khz != b->dppclk_khz)
383 return false;
384 else if (a->dcfclk_khz != b->dcfclk_khz)
385 return false;
386 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
387 return false;
388 else if (a->zstate_support != b->zstate_support)
389 return false;
390 else if (a->dtbclk_en != b->dtbclk_en)
391 return false;
392
393 return true;
394 }
395
dcn314_dump_clk_registers(struct clk_state_registers_and_bypass * regs_and_bypass,struct clk_mgr * clk_mgr_base,struct clk_log_info * log_info)396 static void dcn314_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
397 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
398 {
399 (void)regs_and_bypass;
400 (void)clk_mgr_base;
401 (void)log_info;
402 return;
403 }
404
405 static struct clk_bw_params dcn314_bw_params = {
406 .vram_type = Ddr4MemType,
407 .num_channels = 1,
408 .clk_table = {
409 .num_entries = 4,
410 },
411
412 };
413
414 static struct wm_table ddr5_wm_table = {
415 .entries = {
416 {
417 .wm_inst = WM_A,
418 .wm_type = WM_TYPE_PSTATE_CHG,
419 .pstate_latency_us = 11.72,
420 .sr_exit_time_us = 12.5,
421 .sr_enter_plus_exit_time_us = 14.5,
422 .valid = true,
423 },
424 {
425 .wm_inst = WM_B,
426 .wm_type = WM_TYPE_PSTATE_CHG,
427 .pstate_latency_us = 11.72,
428 .sr_exit_time_us = 12.5,
429 .sr_enter_plus_exit_time_us = 14.5,
430 .valid = true,
431 },
432 {
433 .wm_inst = WM_C,
434 .wm_type = WM_TYPE_PSTATE_CHG,
435 .pstate_latency_us = 11.72,
436 .sr_exit_time_us = 12.5,
437 .sr_enter_plus_exit_time_us = 14.5,
438 .valid = true,
439 },
440 {
441 .wm_inst = WM_D,
442 .wm_type = WM_TYPE_PSTATE_CHG,
443 .pstate_latency_us = 11.72,
444 .sr_exit_time_us = 12.5,
445 .sr_enter_plus_exit_time_us = 14.5,
446 .valid = true,
447 },
448 }
449 };
450
451 static struct wm_table lpddr5_wm_table = {
452 .entries = {
453 {
454 .wm_inst = WM_A,
455 .wm_type = WM_TYPE_PSTATE_CHG,
456 .pstate_latency_us = 11.65333,
457 .sr_exit_time_us = 30.0,
458 .sr_enter_plus_exit_time_us = 32.0,
459 .valid = true,
460 },
461 {
462 .wm_inst = WM_B,
463 .wm_type = WM_TYPE_PSTATE_CHG,
464 .pstate_latency_us = 11.65333,
465 .sr_exit_time_us = 30.0,
466 .sr_enter_plus_exit_time_us = 32.0,
467 .valid = true,
468 },
469 {
470 .wm_inst = WM_C,
471 .wm_type = WM_TYPE_PSTATE_CHG,
472 .pstate_latency_us = 11.65333,
473 .sr_exit_time_us = 30.0,
474 .sr_enter_plus_exit_time_us = 32.0,
475 .valid = true,
476 },
477 {
478 .wm_inst = WM_D,
479 .wm_type = WM_TYPE_PSTATE_CHG,
480 .pstate_latency_us = 11.65333,
481 .sr_exit_time_us = 30.0,
482 .sr_enter_plus_exit_time_us = 32.0,
483 .valid = true,
484 },
485 }
486 };
487
488 static DpmClocks314_t dummy_clocks;
489
490 static struct dcn314_watermarks dummy_wms = { 0 };
491
492 static struct dcn314_ss_info_table ss_info_table = {
493 .ss_divider = 1000,
494 .ss_percentage = {0, 0, 375, 375, 375}
495 };
496
dcn314_build_watermark_ranges(struct clk_bw_params * bw_params,struct dcn314_watermarks * table)497 static void dcn314_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn314_watermarks *table)
498 {
499 uint8_t i, num_valid_sets;
500
501 num_valid_sets = 0;
502
503 for (i = 0; i < WM_SET_COUNT; i++) {
504 /* skip empty entries, the smu array has no holes*/
505 if (!bw_params->wm_table.entries[i].valid)
506 continue;
507
508 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting =
509 (uint8_t)bw_params->wm_table.entries[i].wm_inst;
510 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType =
511 (uint8_t)bw_params->wm_table.entries[i].wm_type;
512 /* We will not select WM based on fclk, so leave it as unconstrained */
513 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
514 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
515
516 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
517 if (i == 0)
518 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
519 else {
520 /* add 1 to make it non-overlapping with next lvl */
521 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
522 (uint16_t)(bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1);
523 }
524 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
525 (uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz;
526
527 } else {
528 /* unconstrained for memory retraining */
529 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
530 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
531
532 /* Modify previous watermark range to cover up to max */
533 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
534 }
535 num_valid_sets++;
536 }
537
538 ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
539
540 /* modify the min and max to make sure we cover the whole range*/
541 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;
542 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;
543 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;
544 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
545
546 /* This is for writeback only, does not matter currently as no writeback support*/
547 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
548 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;
549 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;
550 table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;
551 table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;
552 }
553
dcn314_notify_wm_ranges(struct clk_mgr * clk_mgr_base)554 static void dcn314_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
555 {
556 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
557 struct clk_mgr_dcn314 *clk_mgr_dcn314 = TO_CLK_MGR_DCN314(clk_mgr);
558 struct dcn314_watermarks *table = clk_mgr_dcn314->smu_wm_set.wm_set;
559
560 if (!clk_mgr->smu_ver)
561 return;
562
563 if (!table || clk_mgr_dcn314->smu_wm_set.mc_address.quad_part == 0)
564 return;
565
566 memset(table, 0, sizeof(*table));
567
568 dcn314_build_watermark_ranges(clk_mgr_base->bw_params, table);
569
570 dcn314_smu_set_dram_addr_high(clk_mgr,
571 clk_mgr_dcn314->smu_wm_set.mc_address.high_part);
572 dcn314_smu_set_dram_addr_low(clk_mgr,
573 clk_mgr_dcn314->smu_wm_set.mc_address.low_part);
574 dcn314_smu_transfer_wm_table_dram_2_smu(clk_mgr);
575 }
576
dcn314_get_dpm_table_from_smu(struct clk_mgr_internal * clk_mgr,struct dcn314_smu_dpm_clks * smu_dpm_clks)577 static void dcn314_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
578 struct dcn314_smu_dpm_clks *smu_dpm_clks)
579 {
580 DpmClocks314_t *table = smu_dpm_clks->dpm_clks;
581
582 if (!clk_mgr->smu_ver)
583 return;
584
585 if (!table || smu_dpm_clks->mc_address.quad_part == 0)
586 return;
587
588 memset(table, 0, sizeof(*table));
589
590 dcn314_smu_set_dram_addr_high(clk_mgr,
591 smu_dpm_clks->mc_address.high_part);
592 dcn314_smu_set_dram_addr_low(clk_mgr,
593 smu_dpm_clks->mc_address.low_part);
594 dcn314_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
595 }
596
is_valid_clock_value(uint32_t clock_value)597 static inline bool is_valid_clock_value(uint32_t clock_value)
598 {
599 return clock_value > 1 && clock_value < 100000;
600 }
601
convert_wck_ratio(uint8_t wck_ratio)602 static unsigned int convert_wck_ratio(uint8_t wck_ratio)
603 {
604 switch (wck_ratio) {
605 case WCK_RATIO_1_2:
606 return 2;
607
608 case WCK_RATIO_1_4:
609 return 4;
610
611 default:
612 break;
613 }
614 return 1;
615 }
616
find_max_clk_value(const uint32_t clocks[],uint32_t num_clocks)617 static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks)
618 {
619 uint32_t max = 0;
620 uint32_t i;
621
622 for (i = 0; i < num_clocks; ++i) {
623 if (clocks[i] > max)
624 max = clocks[i];
625 }
626
627 return max;
628 }
629
dcn314_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal * clk_mgr,struct integrated_info * bios_info,const DpmClocks314_t * clock_table)630 static void dcn314_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk_mgr,
631 struct integrated_info *bios_info,
632 const DpmClocks314_t *clock_table)
633 {
634 struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
635 struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entries - 1];
636 uint32_t max_pstate = 0, max_fclk = 0, min_pstate = 0, max_dispclk = 0, max_dppclk = 0;
637 int i;
638 unsigned int entry_idx;
639
640 /* Find highest valid fclk pstate */
641 for (i = 0; i < clock_table->NumDfPstatesEnabled; i++) {
642 if (is_valid_clock_value(clock_table->DfPstateTable[i].FClk) &&
643 clock_table->DfPstateTable[i].FClk > max_fclk) {
644 max_fclk = clock_table->DfPstateTable[i].FClk;
645 max_pstate = i;
646 }
647 }
648
649 /* We expect the table to contain at least one valid fclk entry. */
650 ASSERT(is_valid_clock_value(max_fclk));
651
652 /* Dispclk and dppclk can be max at any voltage, same number of levels for both */
653 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS &&
654 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) {
655 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled);
656 max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled);
657 } else {
658 /* Invalid number of entries in the table from PMFW. */
659 ASSERT(0);
660 }
661
662 /* Base the clock table on dcfclk, need at least one entry regardless of pmfw table */
663 for (i = 0; i < clock_table->NumDcfClkLevelsEnabled; i++) {
664 uint32_t min_fclk = clock_table->DfPstateTable[0].FClk;
665 int j;
666
667 for (j = 1; j < clock_table->NumDfPstatesEnabled; j++) {
668 if (is_valid_clock_value(clock_table->DfPstateTable[j].FClk) &&
669 clock_table->DfPstateTable[j].FClk < min_fclk &&
670 clock_table->DfPstateTable[j].Voltage <= clock_table->SocVoltage[i]) {
671 min_fclk = clock_table->DfPstateTable[j].FClk;
672 min_pstate = j;
673 }
674 }
675
676 /* First search defaults for the clocks we don't read using closest lower or equal default dcfclk */
677 for (j = bw_params->clk_table.num_entries - 1; j > 0; j--)
678 if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i])
679 break;
680
681 bw_params->clk_table.entries[i].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz;
682 bw_params->clk_table.entries[i].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz;
683 bw_params->clk_table.entries[i].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz;
684
685 /* Now update clocks we do read */
686 bw_params->clk_table.entries[i].fclk_mhz = min_fclk;
687 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[min_pstate].MemClk;
688 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[min_pstate].Voltage;
689 bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i];
690 bw_params->clk_table.entries[i].socclk_mhz = clock_table->SocClocks[i];
691 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
692 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
693 bw_params->clk_table.entries[i].wck_ratio = convert_wck_ratio(
694 clock_table->DfPstateTable[min_pstate].WckRatio);
695 }
696
697 /* Make sure to include at least one entry at highest pstate */
698 if (max_pstate != min_pstate || i == 0) {
699 if (i > MAX_NUM_DPM_LVL - 1)
700 i = MAX_NUM_DPM_LVL - 1;
701
702 bw_params->clk_table.entries[i].fclk_mhz = max_fclk;
703 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[max_pstate].MemClk;
704 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[max_pstate].Voltage;
705 bw_params->clk_table.entries[i].dcfclk_mhz = find_max_clk_value(clock_table->DcfClocks, NUM_DCFCLK_DPM_LEVELS);
706 bw_params->clk_table.entries[i].socclk_mhz = find_max_clk_value(clock_table->SocClocks, NUM_SOCCLK_DPM_LEVELS);
707 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
708 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
709 bw_params->clk_table.entries[i].wck_ratio = convert_wck_ratio(
710 clock_table->DfPstateTable[max_pstate].WckRatio);
711 i++;
712 }
713 bw_params->clk_table.num_entries = i--;
714
715 /* Make sure all highest clocks are included*/
716 bw_params->clk_table.entries[i].socclk_mhz = find_max_clk_value(clock_table->SocClocks, NUM_SOCCLK_DPM_LEVELS);
717 bw_params->clk_table.entries[i].dispclk_mhz = find_max_clk_value(clock_table->DispClocks, NUM_DISPCLK_DPM_LEVELS);
718 bw_params->clk_table.entries[i].dppclk_mhz = find_max_clk_value(clock_table->DppClocks, NUM_DPPCLK_DPM_LEVELS);
719 ASSERT(clock_table->DcfClocks[i] == find_max_clk_value(clock_table->DcfClocks, NUM_DCFCLK_DPM_LEVELS));
720 bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz;
721 bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz;
722 bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz;
723
724 /*
725 * Set any 0 clocks to max default setting. Not an issue for
726 * power since we aren't doing switching in such case anyway
727 */
728 for (entry_idx = 0; entry_idx < bw_params->clk_table.num_entries; entry_idx++) {
729 if (!bw_params->clk_table.entries[entry_idx].fclk_mhz) {
730 bw_params->clk_table.entries[entry_idx].fclk_mhz = def_max.fclk_mhz;
731 bw_params->clk_table.entries[entry_idx].memclk_mhz = def_max.memclk_mhz;
732 bw_params->clk_table.entries[entry_idx].voltage = def_max.voltage;
733 }
734 if (!bw_params->clk_table.entries[entry_idx].dcfclk_mhz)
735 bw_params->clk_table.entries[entry_idx].dcfclk_mhz = def_max.dcfclk_mhz;
736 if (!bw_params->clk_table.entries[entry_idx].socclk_mhz)
737 bw_params->clk_table.entries[entry_idx].socclk_mhz = def_max.socclk_mhz;
738 if (!bw_params->clk_table.entries[entry_idx].dispclk_mhz)
739 bw_params->clk_table.entries[entry_idx].dispclk_mhz = def_max.dispclk_mhz;
740 if (!bw_params->clk_table.entries[entry_idx].dppclk_mhz)
741 bw_params->clk_table.entries[entry_idx].dppclk_mhz = def_max.dppclk_mhz;
742 if (!bw_params->clk_table.entries[entry_idx].phyclk_mhz)
743 bw_params->clk_table.entries[entry_idx].phyclk_mhz = def_max.phyclk_mhz;
744 if (!bw_params->clk_table.entries[entry_idx].phyclk_d18_mhz)
745 bw_params->clk_table.entries[entry_idx].phyclk_d18_mhz = def_max.phyclk_d18_mhz;
746 if (!bw_params->clk_table.entries[entry_idx].dtbclk_mhz)
747 bw_params->clk_table.entries[entry_idx].dtbclk_mhz = def_max.dtbclk_mhz;
748 }
749 ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz);
750 bw_params->vram_type = bios_info->memory_type;
751
752 bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4;
753 bw_params->num_channels = bios_info->ma_channel_number ? bios_info->ma_channel_number : 4;
754
755 for (entry_idx = 0; entry_idx < (unsigned int)WM_SET_COUNT; entry_idx++) {
756 bw_params->wm_table.entries[entry_idx].wm_inst = entry_idx;
757
758 if (entry_idx >= bw_params->clk_table.num_entries) {
759 bw_params->wm_table.entries[entry_idx].valid = false;
760 continue;
761 }
762
763 bw_params->wm_table.entries[entry_idx].wm_type = WM_TYPE_PSTATE_CHG;
764 bw_params->wm_table.entries[entry_idx].valid = true;
765 }
766 }
767
768 static struct clk_mgr_funcs dcn314_funcs = {
769 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
770 .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
771 .update_clocks = dcn314_update_clocks,
772 .init_clocks = dcn314_init_clocks,
773 .enable_pme_wa = dcn314_enable_pme_wa,
774 .are_clock_states_equal = dcn314_are_clock_states_equal,
775 .notify_wm_ranges = dcn314_notify_wm_ranges
776 };
777 extern struct clk_mgr_funcs dcn3_fpga_funcs;
778
dcn314_read_ss_info_from_lut(struct clk_mgr_internal * clk_mgr)779 static void dcn314_read_ss_info_from_lut(struct clk_mgr_internal *clk_mgr)
780 {
781 uint32_t clock_source;
782 //uint32_t ssc_enable;
783
784 REG_GET(CLK1_CLK2_BYPASS_CNTL, CLK2_BYPASS_SEL, &clock_source);
785 //REG_GET(CLK6_0_CLK6_spll_field_8, spll_ssc_en, &ssc_enable);
786
787 if (dcn314_is_spll_ssc_enabled(&clk_mgr->base) && (clock_source < ARRAY_SIZE(ss_info_table.ss_percentage))) {
788 clk_mgr->dprefclk_ss_percentage = ss_info_table.ss_percentage[clock_source];
789
790 if (clk_mgr->dprefclk_ss_percentage != 0) {
791 clk_mgr->ss_on_dprefclk = true;
792 clk_mgr->dprefclk_ss_divider = ss_info_table.ss_divider;
793 }
794 }
795 }
796
dcn314_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_dcn314 * clk_mgr,struct pp_smu_funcs * pp_smu,struct dccg * dccg)797 void dcn314_clk_mgr_construct(
798 struct dc_context *ctx,
799 struct clk_mgr_dcn314 *clk_mgr,
800 struct pp_smu_funcs *pp_smu,
801 struct dccg *dccg)
802 {
803 struct dcn314_smu_dpm_clks smu_dpm_clks = { 0 };
804 struct clk_log_info log_info = {0};
805
806 clk_mgr->base.base.ctx = ctx;
807 clk_mgr->base.base.funcs = &dcn314_funcs;
808
809 clk_mgr->base.pp_smu = pp_smu;
810
811 clk_mgr->base.dccg = dccg;
812 clk_mgr->base.dfs_bypass_disp_clk = 0;
813
814 clk_mgr->base.dprefclk_ss_percentage = 0;
815 clk_mgr->base.dprefclk_ss_divider = 1000;
816 clk_mgr->base.ss_on_dprefclk = false;
817 clk_mgr->base.dfs_ref_freq_khz = 48000;
818
819 clk_mgr->smu_wm_set.wm_set = (struct dcn314_watermarks *)dm_helpers_allocate_gpu_mem(
820 clk_mgr->base.base.ctx,
821 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
822 sizeof(struct dcn314_watermarks),
823 &clk_mgr->smu_wm_set.mc_address.quad_part);
824
825 if (!clk_mgr->smu_wm_set.wm_set) {
826 clk_mgr->smu_wm_set.wm_set = &dummy_wms;
827 clk_mgr->smu_wm_set.mc_address.quad_part = 0;
828 }
829 ASSERT(clk_mgr->smu_wm_set.wm_set);
830
831 smu_dpm_clks.dpm_clks = (DpmClocks314_t *)dm_helpers_allocate_gpu_mem(
832 clk_mgr->base.base.ctx,
833 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
834 sizeof(DpmClocks314_t),
835 &smu_dpm_clks.mc_address.quad_part);
836
837 if (smu_dpm_clks.dpm_clks == NULL) {
838 smu_dpm_clks.dpm_clks = &dummy_clocks;
839 smu_dpm_clks.mc_address.quad_part = 0;
840 }
841
842 ASSERT(smu_dpm_clks.dpm_clks);
843
844 clk_mgr->base.smu_ver = dcn314_smu_get_smu_version(&clk_mgr->base);
845
846 if (clk_mgr->base.smu_ver)
847 clk_mgr->base.smu_present = true;
848
849 /* TODO: Check we get what we expect during bringup */
850 clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base);
851
852 if (ctx->dc_bios->integrated_info &&
853 ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType)
854 dcn314_bw_params.wm_table = lpddr5_wm_table;
855 else
856 dcn314_bw_params.wm_table = ddr5_wm_table;
857
858 /* Saved clocks configured at boot for debug purposes */
859 dcn314_dump_clk_registers(&clk_mgr->base.base.boot_snapshot,
860 &clk_mgr->base.base, &log_info);
861
862 clk_mgr->base.base.dprefclk_khz = 600000;
863 clk_mgr->base.base.clks.ref_dtbclk_khz = 600000;
864 dce_clock_read_ss_info(&clk_mgr->base);
865 dcn314_read_ss_info_from_lut(&clk_mgr->base);
866 /*if bios enabled SS, driver needs to adjust dtb clock, only enable with correct bios*/
867
868 clk_mgr->base.base.bw_params = &dcn314_bw_params;
869
870 if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {
871 int i;
872
873 dcn314_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
874 DC_LOG_SMU("NumDcfClkLevelsEnabled: %d\n"
875 "NumDispClkLevelsEnabled: %d\n"
876 "NumSocClkLevelsEnabled: %d\n"
877 "VcnClkLevelsEnabled: %d\n"
878 "NumDfPst atesEnabled: %d\n"
879 "MinGfxClk: %d\n"
880 "MaxGfxClk: %d\n",
881 smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled,
882 smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled,
883 smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled,
884 smu_dpm_clks.dpm_clks->VcnClkLevelsEnabled,
885 smu_dpm_clks.dpm_clks->NumDfPstatesEnabled,
886 smu_dpm_clks.dpm_clks->MinGfxClk,
887 smu_dpm_clks.dpm_clks->MaxGfxClk);
888 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled; i++) {
889 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DcfClocks[%d] = %d\n",
890 i,
891 smu_dpm_clks.dpm_clks->DcfClocks[i]);
892 }
893 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) {
894 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DispClocks[%d] = %d\n",
895 i, smu_dpm_clks.dpm_clks->DispClocks[i]);
896 }
897 for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++) {
898 DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocClocks[%d] = %d\n",
899 i, smu_dpm_clks.dpm_clks->SocClocks[i]);
900 }
901 for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++)
902 DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocVoltage[%d] = %d\n",
903 i, smu_dpm_clks.dpm_clks->SocVoltage[i]);
904
905 for (i = 0; i < NUM_DF_PSTATE_LEVELS; i++) {
906 DC_LOG_SMU("smu_dpm_clks.dpm_clks.DfPstateTable[%d].FClk = %d\n"
907 "smu_dpm_clks.dpm_clks->DfPstateTable[%d].MemClk= %d\n"
908 "smu_dpm_clks.dpm_clks->DfPstateTable[%d].Voltage = %d\n",
909 i, smu_dpm_clks.dpm_clks->DfPstateTable[i].FClk,
910 i, smu_dpm_clks.dpm_clks->DfPstateTable[i].MemClk,
911 i, smu_dpm_clks.dpm_clks->DfPstateTable[i].Voltage);
912 }
913
914 if (ctx->dc_bios->integrated_info && ctx->dc->config.use_default_clock_table == false) {
915 dcn314_clk_mgr_helper_populate_bw_params(
916 &clk_mgr->base,
917 ctx->dc_bios->integrated_info,
918 smu_dpm_clks.dpm_clks);
919 }
920 }
921
922 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
923 dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
924 smu_dpm_clks.dpm_clks);
925 }
926
dcn314_clk_mgr_destroy(struct clk_mgr_internal * clk_mgr_int)927 void dcn314_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)
928 {
929 struct clk_mgr_dcn314 *clk_mgr = TO_CLK_MGR_DCN314(clk_mgr_int);
930
931 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0)
932 dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
933 clk_mgr->smu_wm_set.wm_set);
934 }
935