1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27 #include "dm_services.h"
28 #include "dc.h"
29
30 #include "dcn30/dcn30_init.h"
31
32 #include "resource.h"
33 #include "include/irq_service_interface.h"
34 #include "dcn20/dcn20_resource.h"
35
36 #include "dcn30_resource.h"
37
38 #include "dcn10/dcn10_ipp.h"
39 #include "dcn30/dcn30_hubbub.h"
40 #include "dcn30/dcn30_mpc.h"
41 #include "dcn30/dcn30_hubp.h"
42 #include "irq/dcn30/irq_service_dcn30.h"
43 #include "dcn30/dcn30_dpp.h"
44 #include "dcn30/dcn30_optc.h"
45 #include "dcn20/dcn20_hwseq.h"
46 #include "dcn30/dcn30_hwseq.h"
47 #include "dce110/dce110_hwseq.h"
48 #include "dcn30/dcn30_opp.h"
49 #include "dcn20/dcn20_dsc.h"
50 #include "dcn30/dcn30_vpg.h"
51 #include "dcn30/dcn30_afmt.h"
52 #include "dcn30/dcn30_dio_stream_encoder.h"
53 #include "dcn30/dcn30_dio_link_encoder.h"
54 #include "dce/dce_clock_source.h"
55 #include "dce/dce_audio.h"
56 #include "dce/dce_hwseq.h"
57 #include "clk_mgr.h"
58 #include "virtual/virtual_stream_encoder.h"
59 #include "dce110/dce110_resource.h"
60 #include "dml/display_mode_vba.h"
61 #include "dcn30/dcn30_dccg.h"
62 #include "dcn10/dcn10_resource.h"
63 #include "link.h"
64 #include "dce/dce_panel_cntl.h"
65
66 #include "dcn30/dcn30_dwb.h"
67 #include "dcn30/dcn30_mmhubbub.h"
68
69 #include "sienna_cichlid_ip_offset.h"
70 #include "dcn/dcn_3_0_0_offset.h"
71 #include "dcn/dcn_3_0_0_sh_mask.h"
72
73 #include "nbio/nbio_7_4_offset.h"
74
75 #include "dpcs/dpcs_3_0_0_offset.h"
76 #include "dpcs/dpcs_3_0_0_sh_mask.h"
77
78 #include "mmhub/mmhub_2_0_0_offset.h"
79 #include "mmhub/mmhub_2_0_0_sh_mask.h"
80
81 #include "reg_helper.h"
82 #include "dce/dmub_abm.h"
83 #include "dce/dmub_psr.h"
84 #include "dce/dce_aux.h"
85 #include "dce/dce_i2c.h"
86
87 #include "dml/dcn30/dcn30_fpu.h"
88 #include "dml/dcn30/display_mode_vba_30.h"
89 #include "vm_helper.h"
90 #include "dcn20/dcn20_vmid.h"
91 #include "amdgpu_socbb.h"
92 #include "dc_dmub_srv.h"
93
94 #define DC_LOGGER \
95 dc->ctx->logger
96 #define DC_LOGGER_INIT(logger)
97
98 enum dcn30_clk_src_array_id {
99 DCN30_CLK_SRC_PLL0,
100 DCN30_CLK_SRC_PLL1,
101 DCN30_CLK_SRC_PLL2,
102 DCN30_CLK_SRC_PLL3,
103 DCN30_CLK_SRC_PLL4,
104 DCN30_CLK_SRC_PLL5,
105 DCN30_CLK_SRC_TOTAL
106 };
107
108 /* begin *********************
109 * macros to expend register list macro defined in HW object header file
110 */
111
112 /* DCN */
113 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
114
115 #define BASE(seg) BASE_INNER(seg)
116
117 #define SR(reg_name)\
118 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
119 mm ## reg_name
120
121 #define SRI(reg_name, block, id)\
122 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
123 mm ## block ## id ## _ ## reg_name
124
125 #define SRI2(reg_name, block, id)\
126 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
127 mm ## reg_name
128
129 #define SRIR(var_name, reg_name, block, id)\
130 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
131 mm ## block ## id ## _ ## reg_name
132
133 #define SRII(reg_name, block, id)\
134 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
135 mm ## block ## id ## _ ## reg_name
136
137 #define SRII_MPC_RMU(reg_name, block, id)\
138 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
139 mm ## block ## id ## _ ## reg_name
140
141 #define SRII_DWB(reg_name, temp_name, block, id)\
142 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
143 mm ## block ## id ## _ ## temp_name
144
145 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
146 .field_name = reg_name ## __ ## field_name ## post_fix
147
148 #define DCCG_SRII(reg_name, block, id)\
149 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
150 mm ## block ## id ## _ ## reg_name
151
152 #define VUPDATE_SRII(reg_name, block, id)\
153 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
154 mm ## reg_name ## _ ## block ## id
155
156 /* NBIO */
157 #define NBIO_BASE_INNER(seg) \
158 NBIO_BASE__INST0_SEG ## seg
159
160 #define NBIO_BASE(seg) \
161 NBIO_BASE_INNER(seg)
162
163 #define NBIO_SR(reg_name)\
164 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
165 mm ## reg_name
166
167 /* MMHUB */
168 #define MMHUB_BASE_INNER(seg) \
169 MMHUB_BASE__INST0_SEG ## seg
170
171 #define MMHUB_BASE(seg) \
172 MMHUB_BASE_INNER(seg)
173
174 #define MMHUB_SR(reg_name)\
175 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
176 mmMM ## reg_name
177
178 /* CLOCK */
179 #define CLK_BASE_INNER(seg) \
180 CLK_BASE__INST0_SEG ## seg
181
182 #define CLK_BASE(seg) \
183 CLK_BASE_INNER(seg)
184
185 #define CLK_SRI(reg_name, block, inst)\
186 .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
187 mm ## block ## _ ## inst ## _ ## reg_name
188
189
190 static const struct bios_registers bios_regs = {
191 NBIO_SR(BIOS_SCRATCH_3),
192 NBIO_SR(BIOS_SCRATCH_6)
193 };
194
195 #define clk_src_regs(index, pllid)\
196 [index] = {\
197 CS_COMMON_REG_LIST_DCN2_0(index, pllid),\
198 }
199
200 static const struct dce110_clk_src_regs clk_src_regs[] = {
201 clk_src_regs(0, A),
202 clk_src_regs(1, B),
203 clk_src_regs(2, C),
204 clk_src_regs(3, D),
205 clk_src_regs(4, E),
206 clk_src_regs(5, F)
207 };
208
209 static const struct dce110_clk_src_shift cs_shift = {
210 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
211 };
212
213 static const struct dce110_clk_src_mask cs_mask = {
214 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
215 };
216
217 #define abm_regs(id)\
218 [id] = {\
219 ABM_DCN30_REG_LIST(id)\
220 }
221
222 static const struct dce_abm_registers abm_regs[] = {
223 abm_regs(0),
224 abm_regs(1),
225 abm_regs(2),
226 abm_regs(3),
227 abm_regs(4),
228 abm_regs(5),
229 };
230
231 static const struct dce_abm_shift abm_shift = {
232 ABM_MASK_SH_LIST_DCN30(__SHIFT)
233 };
234
235 static const struct dce_abm_mask abm_mask = {
236 ABM_MASK_SH_LIST_DCN30(_MASK)
237 };
238
239
240
241 #define audio_regs(id)\
242 [id] = {\
243 AUD_COMMON_REG_LIST(id)\
244 }
245
246 static const struct dce_audio_registers audio_regs[] = {
247 audio_regs(0),
248 audio_regs(1),
249 audio_regs(2),
250 audio_regs(3),
251 audio_regs(4),
252 audio_regs(5),
253 audio_regs(6)
254 };
255
256 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
257 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
258 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
259 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
260
261 static const struct dce_audio_shift audio_shift = {
262 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
263 };
264
265 static const struct dce_audio_mask audio_mask = {
266 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
267 };
268
269 #define vpg_regs(id)\
270 [id] = {\
271 VPG_DCN3_REG_LIST(id)\
272 }
273
274 static const struct dcn30_vpg_registers vpg_regs[] = {
275 vpg_regs(0),
276 vpg_regs(1),
277 vpg_regs(2),
278 vpg_regs(3),
279 vpg_regs(4),
280 vpg_regs(5),
281 vpg_regs(6),
282 };
283
284 static const struct dcn30_vpg_shift vpg_shift = {
285 DCN3_VPG_MASK_SH_LIST(__SHIFT)
286 };
287
288 static const struct dcn30_vpg_mask vpg_mask = {
289 DCN3_VPG_MASK_SH_LIST(_MASK)
290 };
291
292 #define afmt_regs(id)\
293 [id] = {\
294 AFMT_DCN3_REG_LIST(id)\
295 }
296
297 static const struct dcn30_afmt_registers afmt_regs[] = {
298 afmt_regs(0),
299 afmt_regs(1),
300 afmt_regs(2),
301 afmt_regs(3),
302 afmt_regs(4),
303 afmt_regs(5),
304 afmt_regs(6),
305 };
306
307 static const struct dcn30_afmt_shift afmt_shift = {
308 DCN3_AFMT_MASK_SH_LIST(__SHIFT)
309 };
310
311 static const struct dcn30_afmt_mask afmt_mask = {
312 DCN3_AFMT_MASK_SH_LIST(_MASK)
313 };
314
315 #define stream_enc_regs(id)\
316 [id] = {\
317 SE_DCN3_REG_LIST(id)\
318 }
319
320 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
321 stream_enc_regs(0),
322 stream_enc_regs(1),
323 stream_enc_regs(2),
324 stream_enc_regs(3),
325 stream_enc_regs(4),
326 stream_enc_regs(5)
327 };
328
329 static const struct dcn10_stream_encoder_shift se_shift = {
330 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
331 };
332
333 static const struct dcn10_stream_encoder_mask se_mask = {
334 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
335 };
336
337
338 #define aux_regs(id)\
339 [id] = {\
340 DCN2_AUX_REG_LIST(id)\
341 }
342
343 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
344 aux_regs(0),
345 aux_regs(1),
346 aux_regs(2),
347 aux_regs(3),
348 aux_regs(4),
349 aux_regs(5)
350 };
351
352 #define hpd_regs(id)\
353 [id] = {\
354 HPD_REG_LIST(id)\
355 }
356
357 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
358 hpd_regs(0),
359 hpd_regs(1),
360 hpd_regs(2),
361 hpd_regs(3),
362 hpd_regs(4),
363 hpd_regs(5)
364 };
365
366 #define link_regs(id, phyid)\
367 [id] = {\
368 LE_DCN3_REG_LIST(id), \
369 UNIPHY_DCN2_REG_LIST(phyid), \
370 DPCS_DCN2_REG_LIST(id), \
371 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
372 }
373
374 static const struct dce110_aux_registers_shift aux_shift = {
375 DCN_AUX_MASK_SH_LIST(__SHIFT)
376 };
377
378 static const struct dce110_aux_registers_mask aux_mask = {
379 DCN_AUX_MASK_SH_LIST(_MASK)
380 };
381
382 static const struct dcn10_link_enc_registers link_enc_regs[] = {
383 link_regs(0, A),
384 link_regs(1, B),
385 link_regs(2, C),
386 link_regs(3, D),
387 link_regs(4, E),
388 link_regs(5, F)
389 };
390
391 static const struct dcn10_link_enc_shift le_shift = {
392 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT),\
393 DPCS_DCN2_MASK_SH_LIST(__SHIFT)
394 };
395
396 static const struct dcn10_link_enc_mask le_mask = {
397 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK),\
398 DPCS_DCN2_MASK_SH_LIST(_MASK)
399 };
400
401
402 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
403 { DCN_PANEL_CNTL_REG_LIST() }
404 };
405
406 static const struct dce_panel_cntl_shift panel_cntl_shift = {
407 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
408 };
409
410 static const struct dce_panel_cntl_mask panel_cntl_mask = {
411 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
412 };
413
414 #define dpp_regs(id)\
415 [id] = {\
416 DPP_REG_LIST_DCN30(id),\
417 }
418
419 static const struct dcn3_dpp_registers dpp_regs[] = {
420 dpp_regs(0),
421 dpp_regs(1),
422 dpp_regs(2),
423 dpp_regs(3),
424 dpp_regs(4),
425 dpp_regs(5),
426 };
427
428 static const struct dcn3_dpp_shift tf_shift = {
429 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
430 };
431
432 static const struct dcn3_dpp_mask tf_mask = {
433 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
434 };
435
436 #define opp_regs(id)\
437 [id] = {\
438 OPP_REG_LIST_DCN30(id),\
439 }
440
441 static const struct dcn20_opp_registers opp_regs[] = {
442 opp_regs(0),
443 opp_regs(1),
444 opp_regs(2),
445 opp_regs(3),
446 opp_regs(4),
447 opp_regs(5)
448 };
449
450 static const struct dcn20_opp_shift opp_shift = {
451 OPP_MASK_SH_LIST_DCN20(__SHIFT)
452 };
453
454 static const struct dcn20_opp_mask opp_mask = {
455 OPP_MASK_SH_LIST_DCN20(_MASK)
456 };
457
458 #define aux_engine_regs(id)\
459 [id] = {\
460 AUX_COMMON_REG_LIST0(id), \
461 .AUXN_IMPCAL = 0, \
462 .AUXP_IMPCAL = 0, \
463 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
464 }
465
466 static const struct dce110_aux_registers aux_engine_regs[] = {
467 aux_engine_regs(0),
468 aux_engine_regs(1),
469 aux_engine_regs(2),
470 aux_engine_regs(3),
471 aux_engine_regs(4),
472 aux_engine_regs(5)
473 };
474
475 #define dwbc_regs_dcn3(id)\
476 [id] = {\
477 DWBC_COMMON_REG_LIST_DCN30(id),\
478 }
479
480 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
481 dwbc_regs_dcn3(0),
482 };
483
484 static const struct dcn30_dwbc_shift dwbc30_shift = {
485 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
486 };
487
488 static const struct dcn30_dwbc_mask dwbc30_mask = {
489 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
490 };
491
492 #define mcif_wb_regs_dcn3(id)\
493 [id] = {\
494 MCIF_WB_COMMON_REG_LIST_DCN30(id),\
495 }
496
497 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
498 mcif_wb_regs_dcn3(0)
499 };
500
501 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
502 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
503 };
504
505 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
506 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
507 };
508
509 #define dsc_regsDCN20(id)\
510 [id] = {\
511 DSC_REG_LIST_DCN20(id)\
512 }
513
514 static const struct dcn20_dsc_registers dsc_regs[] = {
515 dsc_regsDCN20(0),
516 dsc_regsDCN20(1),
517 dsc_regsDCN20(2),
518 dsc_regsDCN20(3),
519 dsc_regsDCN20(4),
520 dsc_regsDCN20(5)
521 };
522
523 static const struct dcn20_dsc_shift dsc_shift = {
524 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
525 };
526
527 static const struct dcn20_dsc_mask dsc_mask = {
528 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
529 };
530
531 static const struct dcn30_mpc_registers mpc_regs = {
532 MPC_REG_LIST_DCN3_0(0),
533 MPC_REG_LIST_DCN3_0(1),
534 MPC_REG_LIST_DCN3_0(2),
535 MPC_REG_LIST_DCN3_0(3),
536 MPC_REG_LIST_DCN3_0(4),
537 MPC_REG_LIST_DCN3_0(5),
538 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
539 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
540 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
541 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
542 MPC_OUT_MUX_REG_LIST_DCN3_0(4),
543 MPC_OUT_MUX_REG_LIST_DCN3_0(5),
544 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
545 MPC_RMU_REG_LIST_DCN3AG(0),
546 MPC_RMU_REG_LIST_DCN3AG(1),
547 MPC_RMU_REG_LIST_DCN3AG(2),
548 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
549 };
550
551 static const struct dcn30_mpc_shift mpc_shift = {
552 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
553 };
554
555 static const struct dcn30_mpc_mask mpc_mask = {
556 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
557 };
558
559 #define optc_regs(id)\
560 [id] = {OPTC_COMMON_REG_LIST_DCN3_0(id)}
561
562
563 static const struct dcn_optc_registers optc_regs[] = {
564 optc_regs(0),
565 optc_regs(1),
566 optc_regs(2),
567 optc_regs(3),
568 optc_regs(4),
569 optc_regs(5)
570 };
571
572 static const struct dcn_optc_shift optc_shift = {
573 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
574 };
575
576 static const struct dcn_optc_mask optc_mask = {
577 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
578 };
579
580 #define hubp_regs(id)\
581 [id] = {\
582 HUBP_REG_LIST_DCN30(id)\
583 }
584
585 static const struct dcn_hubp2_registers hubp_regs[] = {
586 hubp_regs(0),
587 hubp_regs(1),
588 hubp_regs(2),
589 hubp_regs(3),
590 hubp_regs(4),
591 hubp_regs(5)
592 };
593
594 static const struct dcn_hubp2_shift hubp_shift = {
595 HUBP_MASK_SH_LIST_DCN30(__SHIFT)
596 };
597
598 static const struct dcn_hubp2_mask hubp_mask = {
599 HUBP_MASK_SH_LIST_DCN30(_MASK)
600 };
601
602 static const struct dcn_hubbub_registers hubbub_reg = {
603 HUBBUB_REG_LIST_DCN30(0)
604 };
605
606 static const struct dcn_hubbub_shift hubbub_shift = {
607 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT)
608 };
609
610 static const struct dcn_hubbub_mask hubbub_mask = {
611 HUBBUB_MASK_SH_LIST_DCN30(_MASK)
612 };
613
614 static const struct dccg_registers dccg_regs = {
615 DCCG_REG_LIST_DCN30()
616 };
617
618 static const struct dccg_shift dccg_shift = {
619 DCCG_MASK_SH_LIST_DCN3(__SHIFT)
620 };
621
622 static const struct dccg_mask dccg_mask = {
623 DCCG_MASK_SH_LIST_DCN3(_MASK)
624 };
625
626 static const struct dce_hwseq_registers hwseq_reg = {
627 HWSEQ_DCN30_REG_LIST()
628 };
629
630 static const struct dce_hwseq_shift hwseq_shift = {
631 HWSEQ_DCN30_MASK_SH_LIST(__SHIFT)
632 };
633
634 static const struct dce_hwseq_mask hwseq_mask = {
635 HWSEQ_DCN30_MASK_SH_LIST(_MASK)
636 };
637 #define vmid_regs(id)\
638 [id] = {\
639 DCN20_VMID_REG_LIST(id)\
640 }
641
642 static const struct dcn_vmid_registers vmid_regs[] = {
643 vmid_regs(0),
644 vmid_regs(1),
645 vmid_regs(2),
646 vmid_regs(3),
647 vmid_regs(4),
648 vmid_regs(5),
649 vmid_regs(6),
650 vmid_regs(7),
651 vmid_regs(8),
652 vmid_regs(9),
653 vmid_regs(10),
654 vmid_regs(11),
655 vmid_regs(12),
656 vmid_regs(13),
657 vmid_regs(14),
658 vmid_regs(15)
659 };
660
661 static const struct dcn20_vmid_shift vmid_shifts = {
662 DCN20_VMID_MASK_SH_LIST(__SHIFT)
663 };
664
665 static const struct dcn20_vmid_mask vmid_masks = {
666 DCN20_VMID_MASK_SH_LIST(_MASK)
667 };
668
669 static const struct resource_caps res_cap_dcn3 = {
670 .num_timing_generator = 6,
671 .num_opp = 6,
672 .num_video_plane = 6,
673 .num_audio = 6,
674 .num_stream_encoder = 6,
675 .num_pll = 6,
676 .num_dwb = 1,
677 .num_ddc = 6,
678 .num_vmid = 16,
679 .num_mpc_3dlut = 3,
680 .num_dsc = 6,
681 };
682
683 static const struct dc_plane_cap plane_cap = {
684 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
685 .per_pixel_alpha = true,
686
687 .pixel_format_support = {
688 .argb8888 = true,
689 .nv12 = true,
690 .fp16 = true,
691 .p010 = true,
692 .ayuv = false,
693 },
694
695 .max_upscale_factor = {
696 .argb8888 = 16000,
697 .nv12 = 16000,
698 .fp16 = 16000
699 },
700
701 /* 6:1 downscaling ratio: 1000/6 = 166.666 */
702 .max_downscale_factor = {
703 .argb8888 = 167,
704 .nv12 = 167,
705 .fp16 = 167
706 },
707 16,
708 16
709 };
710
711 static const struct dc_debug_options debug_defaults_drv = {
712 .disable_dmcu = true, //No DMCU on DCN30
713 .force_abm_enable = false,
714 .clock_trace = true,
715 .disable_pplib_clock_request = true,
716 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
717 .force_single_disp_pipe_split = false,
718 .disable_dcc = DCC_ENABLE,
719 .vsr_support = true,
720 .performance_trace = false,
721 .max_downscale_src_width = 7680,/*upto 8K*/
722 .disable_pplib_wm_range = false,
723 .scl_reset_length10 = true,
724 .sanity_checks = false,
725 .underflow_assert_delay_us = 0xFFFFFFFF,
726 .dwb_fi_phase = -1, // -1 = disable,
727 .dmub_command_table = true,
728 .use_max_lb = true,
729 .exit_idle_opt_for_cursor_updates = true,
730 .enable_legacy_fast_update = false,
731 .using_dml2 = false,
732 };
733
734 static const struct dc_panel_config panel_config_defaults = {
735 .psr = {
736 .disable_psr = false,
737 .disallow_psrsu = false,
738 .disallow_replay = false,
739 },
740 };
741
dcn30_dpp_destroy(struct dpp ** dpp)742 static void dcn30_dpp_destroy(struct dpp **dpp)
743 {
744 kfree(TO_DCN20_DPP(*dpp));
745 *dpp = NULL;
746 }
747
dcn30_dpp_create(struct dc_context * ctx,uint32_t inst)748 static struct dpp *dcn30_dpp_create(
749 struct dc_context *ctx,
750 uint32_t inst)
751 {
752 struct dcn3_dpp *dpp =
753 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
754
755 if (!dpp)
756 return NULL;
757
758 if (dpp3_construct(dpp, ctx, inst,
759 &dpp_regs[inst], &tf_shift, &tf_mask))
760 return &dpp->base;
761
762 BREAK_TO_DEBUGGER();
763 kfree(dpp);
764 return NULL;
765 }
766
dcn30_opp_create(struct dc_context * ctx,uint32_t inst)767 static struct output_pixel_processor *dcn30_opp_create(
768 struct dc_context *ctx, uint32_t inst)
769 {
770 struct dcn20_opp *opp =
771 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
772
773 if (!opp) {
774 BREAK_TO_DEBUGGER();
775 return NULL;
776 }
777
778 dcn20_opp_construct(opp, ctx, inst,
779 &opp_regs[inst], &opp_shift, &opp_mask);
780 return &opp->base;
781 }
782
dcn30_aux_engine_create(struct dc_context * ctx,uint32_t inst)783 static struct dce_aux *dcn30_aux_engine_create(
784 struct dc_context *ctx,
785 uint32_t inst)
786 {
787 struct aux_engine_dce110 *aux_engine =
788 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
789
790 if (!aux_engine)
791 return NULL;
792
793 dce110_aux_engine_construct(aux_engine, ctx, inst,
794 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
795 &aux_engine_regs[inst],
796 &aux_mask,
797 &aux_shift,
798 ctx->dc->caps.extended_aux_timeout_support);
799
800 return &aux_engine->base;
801 }
802
803 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
804
805 static const struct dce_i2c_registers i2c_hw_regs[] = {
806 i2c_inst_regs(1),
807 i2c_inst_regs(2),
808 i2c_inst_regs(3),
809 i2c_inst_regs(4),
810 i2c_inst_regs(5),
811 i2c_inst_regs(6),
812 };
813
814 static const struct dce_i2c_shift i2c_shifts = {
815 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
816 };
817
818 static const struct dce_i2c_mask i2c_masks = {
819 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
820 };
821
dcn30_i2c_hw_create(struct dc_context * ctx,uint32_t inst)822 static struct dce_i2c_hw *dcn30_i2c_hw_create(
823 struct dc_context *ctx,
824 uint32_t inst)
825 {
826 struct dce_i2c_hw *dce_i2c_hw =
827 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
828
829 if (!dce_i2c_hw)
830 return NULL;
831
832 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
833 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
834
835 return dce_i2c_hw;
836 }
837
dcn30_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)838 static struct mpc *dcn30_mpc_create(
839 struct dc_context *ctx,
840 int num_mpcc,
841 int num_rmu)
842 {
843 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
844 GFP_KERNEL);
845
846 if (!mpc30)
847 return NULL;
848
849 dcn30_mpc_construct(mpc30, ctx,
850 &mpc_regs,
851 &mpc_shift,
852 &mpc_mask,
853 num_mpcc,
854 num_rmu);
855
856 return &mpc30->base;
857 }
858
dcn30_hubbub_create(struct dc_context * ctx)859 static struct hubbub *dcn30_hubbub_create(struct dc_context *ctx)
860 {
861 int i;
862
863 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
864 GFP_KERNEL);
865
866 if (!hubbub3)
867 return NULL;
868
869 hubbub3_construct(hubbub3, ctx,
870 &hubbub_reg,
871 &hubbub_shift,
872 &hubbub_mask);
873
874
875 for (i = 0; i < res_cap_dcn3.num_vmid; i++) {
876 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
877
878 vmid->ctx = ctx;
879
880 vmid->regs = &vmid_regs[i];
881 vmid->shifts = &vmid_shifts;
882 vmid->masks = &vmid_masks;
883 }
884
885 return &hubbub3->base;
886 }
887
dcn30_timing_generator_create(struct dc_context * ctx,uint32_t instance)888 static struct timing_generator *dcn30_timing_generator_create(
889 struct dc_context *ctx,
890 uint32_t instance)
891 {
892 struct optc *tgn10 =
893 kzalloc(sizeof(struct optc), GFP_KERNEL);
894
895 if (!tgn10)
896 return NULL;
897
898 tgn10->base.inst = instance;
899 tgn10->base.ctx = ctx;
900
901 tgn10->tg_regs = &optc_regs[instance];
902 tgn10->tg_shift = &optc_shift;
903 tgn10->tg_mask = &optc_mask;
904
905 dcn30_timing_generator_init(tgn10);
906
907 return &tgn10->base;
908 }
909
910 static const struct encoder_feature_support link_enc_feature = {
911 .max_hdmi_deep_color = COLOR_DEPTH_121212,
912 .max_hdmi_pixel_clock = 600000,
913 .hdmi_ycbcr420_supported = true,
914 .dp_ycbcr420_supported = true,
915 .fec_supported = true,
916 .flags.bits.IS_HBR2_CAPABLE = true,
917 .flags.bits.IS_HBR3_CAPABLE = true,
918 .flags.bits.IS_TPS3_CAPABLE = true,
919 .flags.bits.IS_TPS4_CAPABLE = true
920 };
921
dcn30_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)922 static struct link_encoder *dcn30_link_encoder_create(
923 struct dc_context *ctx,
924 const struct encoder_init_data *enc_init_data)
925 {
926 struct dcn20_link_encoder *enc20 =
927 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
928
929 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
930 return NULL;
931
932 dcn30_link_encoder_construct(enc20,
933 enc_init_data,
934 &link_enc_feature,
935 &link_enc_regs[enc_init_data->transmitter],
936 &link_enc_aux_regs[enc_init_data->channel - 1],
937 &link_enc_hpd_regs[enc_init_data->hpd_source],
938 &le_shift,
939 &le_mask);
940
941 return &enc20->enc10.base;
942 }
943
dcn30_panel_cntl_create(const struct panel_cntl_init_data * init_data)944 static struct panel_cntl *dcn30_panel_cntl_create(const struct panel_cntl_init_data *init_data)
945 {
946 struct dce_panel_cntl *panel_cntl =
947 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
948
949 if (!panel_cntl)
950 return NULL;
951
952 dce_panel_cntl_construct(panel_cntl,
953 init_data,
954 &panel_cntl_regs[init_data->inst],
955 &panel_cntl_shift,
956 &panel_cntl_mask);
957
958 return &panel_cntl->base;
959 }
960
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)961 static void read_dce_straps(
962 struct dc_context *ctx,
963 struct resource_straps *straps)
964 {
965 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
966 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
967
968 }
969
dcn30_create_audio(struct dc_context * ctx,unsigned int inst)970 static struct audio *dcn30_create_audio(
971 struct dc_context *ctx, unsigned int inst)
972 {
973 return dce_audio_create(ctx, inst,
974 &audio_regs[inst], &audio_shift, &audio_mask);
975 }
976
dcn30_vpg_create(struct dc_context * ctx,uint32_t inst)977 static struct vpg *dcn30_vpg_create(
978 struct dc_context *ctx,
979 uint32_t inst)
980 {
981 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
982
983 if (!vpg3)
984 return NULL;
985
986 vpg3_construct(vpg3, ctx, inst,
987 &vpg_regs[inst],
988 &vpg_shift,
989 &vpg_mask);
990
991 return &vpg3->base;
992 }
993
dcn30_afmt_create(struct dc_context * ctx,uint32_t inst)994 static struct afmt *dcn30_afmt_create(
995 struct dc_context *ctx,
996 uint32_t inst)
997 {
998 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
999
1000 if (!afmt3)
1001 return NULL;
1002
1003 afmt3_construct(afmt3, ctx, inst,
1004 &afmt_regs[inst],
1005 &afmt_shift,
1006 &afmt_mask);
1007
1008 return &afmt3->base;
1009 }
1010
dcn30_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1011 static struct stream_encoder *dcn30_stream_encoder_create(enum engine_id eng_id,
1012 struct dc_context *ctx)
1013 {
1014 struct dcn10_stream_encoder *enc1;
1015 struct vpg *vpg;
1016 struct afmt *afmt;
1017 int vpg_inst;
1018 int afmt_inst;
1019
1020 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1021 if (eng_id <= ENGINE_ID_DIGF) {
1022 vpg_inst = eng_id;
1023 afmt_inst = eng_id;
1024 } else
1025 return NULL;
1026
1027 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1028 vpg = dcn30_vpg_create(ctx, vpg_inst);
1029 afmt = dcn30_afmt_create(ctx, afmt_inst);
1030
1031 if (!enc1 || !vpg || !afmt) {
1032 kfree(enc1);
1033 kfree(vpg);
1034 kfree(afmt);
1035 return NULL;
1036 }
1037
1038 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1039 eng_id, vpg, afmt,
1040 &stream_enc_regs[eng_id],
1041 &se_shift, &se_mask);
1042
1043 return &enc1->base;
1044 }
1045
dcn30_hwseq_create(struct dc_context * ctx)1046 static struct dce_hwseq *dcn30_hwseq_create(struct dc_context *ctx)
1047 {
1048 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1049
1050 if (hws) {
1051 hws->ctx = ctx;
1052 hws->regs = &hwseq_reg;
1053 hws->shifts = &hwseq_shift;
1054 hws->masks = &hwseq_mask;
1055 }
1056 return hws;
1057 }
1058 static const struct resource_create_funcs res_create_funcs = {
1059 .read_dce_straps = read_dce_straps,
1060 .create_audio = dcn30_create_audio,
1061 .create_stream_encoder = dcn30_stream_encoder_create,
1062 .create_hwseq = dcn30_hwseq_create,
1063 };
1064
dcn30_resource_destruct(struct dcn30_resource_pool * pool)1065 static void dcn30_resource_destruct(struct dcn30_resource_pool *pool)
1066 {
1067 unsigned int i;
1068
1069 for (i = 0; i < pool->base.stream_enc_count; i++) {
1070 if (pool->base.stream_enc[i] != NULL) {
1071 if (pool->base.stream_enc[i]->vpg != NULL) {
1072 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1073 pool->base.stream_enc[i]->vpg = NULL;
1074 }
1075 if (pool->base.stream_enc[i]->afmt != NULL) {
1076 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1077 pool->base.stream_enc[i]->afmt = NULL;
1078 }
1079 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1080 pool->base.stream_enc[i] = NULL;
1081 }
1082 }
1083
1084 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1085 if (pool->base.dscs[i] != NULL)
1086 dcn20_dsc_destroy(&pool->base.dscs[i]);
1087 }
1088
1089 if (pool->base.mpc != NULL) {
1090 kfree(TO_DCN20_MPC(pool->base.mpc));
1091 pool->base.mpc = NULL;
1092 }
1093 if (pool->base.hubbub != NULL) {
1094 kfree(pool->base.hubbub);
1095 pool->base.hubbub = NULL;
1096 }
1097 for (i = 0; i < pool->base.pipe_count; i++) {
1098 if (pool->base.dpps[i] != NULL)
1099 dcn30_dpp_destroy(&pool->base.dpps[i]);
1100
1101 if (pool->base.ipps[i] != NULL)
1102 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1103
1104 if (pool->base.hubps[i] != NULL) {
1105 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1106 pool->base.hubps[i] = NULL;
1107 }
1108
1109 if (pool->base.irqs != NULL) {
1110 dal_irq_service_destroy(&pool->base.irqs);
1111 }
1112 }
1113
1114 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1115 if (pool->base.engines[i] != NULL)
1116 dce110_engine_destroy(&pool->base.engines[i]);
1117 if (pool->base.hw_i2cs[i] != NULL) {
1118 kfree(pool->base.hw_i2cs[i]);
1119 pool->base.hw_i2cs[i] = NULL;
1120 }
1121 if (pool->base.sw_i2cs[i] != NULL) {
1122 kfree(pool->base.sw_i2cs[i]);
1123 pool->base.sw_i2cs[i] = NULL;
1124 }
1125 }
1126
1127 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1128 if (pool->base.opps[i] != NULL)
1129 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1130 }
1131
1132 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1133 if (pool->base.timing_generators[i] != NULL) {
1134 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1135 pool->base.timing_generators[i] = NULL;
1136 }
1137 }
1138
1139 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1140 if (pool->base.dwbc[i] != NULL) {
1141 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1142 pool->base.dwbc[i] = NULL;
1143 }
1144 if (pool->base.mcif_wb[i] != NULL) {
1145 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1146 pool->base.mcif_wb[i] = NULL;
1147 }
1148 }
1149
1150 for (i = 0; i < pool->base.audio_count; i++) {
1151 if (pool->base.audios[i])
1152 dce_aud_destroy(&pool->base.audios[i]);
1153 }
1154
1155 for (i = 0; i < pool->base.clk_src_count; i++) {
1156 if (pool->base.clock_sources[i] != NULL) {
1157 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1158 pool->base.clock_sources[i] = NULL;
1159 }
1160 }
1161
1162 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1163 if (pool->base.mpc_lut[i] != NULL) {
1164 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1165 pool->base.mpc_lut[i] = NULL;
1166 }
1167 if (pool->base.mpc_shaper[i] != NULL) {
1168 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1169 pool->base.mpc_shaper[i] = NULL;
1170 }
1171 }
1172
1173 if (pool->base.dp_clock_source != NULL) {
1174 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1175 pool->base.dp_clock_source = NULL;
1176 }
1177
1178 for (i = 0; i < pool->base.pipe_count; i++) {
1179 if (pool->base.multiple_abms[i] != NULL)
1180 dce_abm_destroy(&pool->base.multiple_abms[i]);
1181 }
1182
1183 if (pool->base.psr != NULL)
1184 dmub_psr_destroy(&pool->base.psr);
1185
1186 if (pool->base.dccg != NULL)
1187 dcn_dccg_destroy(&pool->base.dccg);
1188
1189 if (pool->base.oem_device != NULL) {
1190 struct dc *dc = pool->base.oem_device->ctx->dc;
1191
1192 dc->link_srv->destroy_ddc_service(&pool->base.oem_device);
1193 }
1194 }
1195
dcn30_hubp_create(struct dc_context * ctx,uint32_t inst)1196 static struct hubp *dcn30_hubp_create(
1197 struct dc_context *ctx,
1198 uint32_t inst)
1199 {
1200 struct dcn20_hubp *hubp2 =
1201 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1202
1203 if (!hubp2)
1204 return NULL;
1205
1206 if (hubp3_construct(hubp2, ctx, inst,
1207 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1208 return &hubp2->base;
1209
1210 BREAK_TO_DEBUGGER();
1211 kfree(hubp2);
1212 return NULL;
1213 }
1214
dcn30_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)1215 static bool dcn30_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1216 {
1217 int i;
1218 uint32_t pipe_count = pool->res_cap->num_dwb;
1219
1220 for (i = 0; i < pipe_count; i++) {
1221 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1222 GFP_KERNEL);
1223
1224 if (!dwbc30) {
1225 dm_error("DC: failed to create dwbc30!\n");
1226 return false;
1227 }
1228
1229 dcn30_dwbc_construct(dwbc30, ctx,
1230 &dwbc30_regs[i],
1231 &dwbc30_shift,
1232 &dwbc30_mask,
1233 i);
1234
1235 pool->dwbc[i] = &dwbc30->base;
1236 }
1237 return true;
1238 }
1239
dcn30_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)1240 static bool dcn30_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1241 {
1242 int i;
1243 uint32_t pipe_count = pool->res_cap->num_dwb;
1244
1245 for (i = 0; i < pipe_count; i++) {
1246 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1247 GFP_KERNEL);
1248
1249 if (!mcif_wb30) {
1250 dm_error("DC: failed to create mcif_wb30!\n");
1251 return false;
1252 }
1253
1254 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1255 &mcif_wb30_regs[i],
1256 &mcif_wb30_shift,
1257 &mcif_wb30_mask,
1258 i);
1259
1260 pool->mcif_wb[i] = &mcif_wb30->base;
1261 }
1262 return true;
1263 }
1264
dcn30_dsc_create(struct dc_context * ctx,uint32_t inst)1265 static struct display_stream_compressor *dcn30_dsc_create(
1266 struct dc_context *ctx, uint32_t inst)
1267 {
1268 struct dcn20_dsc *dsc =
1269 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1270
1271 if (!dsc) {
1272 BREAK_TO_DEBUGGER();
1273 return NULL;
1274 }
1275
1276 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1277 return &dsc->base;
1278 }
1279
dcn30_add_stream_to_ctx(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * dc_stream)1280 enum dc_status dcn30_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1281 {
1282
1283 return dcn20_add_stream_to_ctx(dc, new_ctx, dc_stream);
1284 }
1285
dcn30_destroy_resource_pool(struct resource_pool ** pool)1286 static void dcn30_destroy_resource_pool(struct resource_pool **pool)
1287 {
1288 struct dcn30_resource_pool *dcn30_pool = TO_DCN30_RES_POOL(*pool);
1289
1290 dcn30_resource_destruct(dcn30_pool);
1291 kfree(dcn30_pool);
1292 *pool = NULL;
1293 }
1294
dcn30_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)1295 static struct clock_source *dcn30_clock_source_create(
1296 struct dc_context *ctx,
1297 struct dc_bios *bios,
1298 enum clock_source_id id,
1299 const struct dce110_clk_src_regs *regs,
1300 bool dp_clk_src)
1301 {
1302 struct dce110_clk_src *clk_src =
1303 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1304
1305 if (!clk_src)
1306 return NULL;
1307
1308 if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
1309 regs, &cs_shift, &cs_mask)) {
1310 clk_src->base.dp_clk_src = dp_clk_src;
1311 return &clk_src->base;
1312 }
1313
1314 kfree(clk_src);
1315 BREAK_TO_DEBUGGER();
1316 return NULL;
1317 }
1318
dcn30_populate_dml_pipes_from_context(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,bool fast_validate)1319 int dcn30_populate_dml_pipes_from_context(
1320 struct dc *dc, struct dc_state *context,
1321 display_e2e_pipe_params_st *pipes,
1322 bool fast_validate)
1323 {
1324 int i, pipe_cnt;
1325 struct resource_context *res_ctx = &context->res_ctx;
1326
1327 DC_FP_START();
1328 dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1329 DC_FP_END();
1330
1331 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1332 if (!res_ctx->pipe_ctx[i].stream)
1333 continue;
1334
1335 pipes[pipe_cnt++].pipe.scale_ratio_depth.lb_depth =
1336 dm_lb_16;
1337 }
1338
1339 return pipe_cnt;
1340 }
1341
dcn30_populate_dml_writeback_from_context(struct dc * dc,struct resource_context * res_ctx,display_e2e_pipe_params_st * pipes)1342 void dcn30_populate_dml_writeback_from_context(
1343 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1344 {
1345 DC_FP_START();
1346 dcn30_fpu_populate_dml_writeback_from_context(dc, res_ctx, pipes);
1347 DC_FP_END();
1348 }
1349
dcn30_calc_max_scaled_time(unsigned int time_per_pixel,enum mmhubbub_wbif_mode mode,unsigned int urgent_watermark)1350 unsigned int dcn30_calc_max_scaled_time(
1351 unsigned int time_per_pixel,
1352 enum mmhubbub_wbif_mode mode,
1353 unsigned int urgent_watermark)
1354 {
1355 unsigned int time_per_byte = 0;
1356 unsigned int total_free_entry = 0xb40;
1357 unsigned int buf_lh_capability;
1358 unsigned int max_scaled_time;
1359
1360 if (mode == PACKED_444) /* packed mode 32 bpp */
1361 time_per_byte = time_per_pixel/4;
1362 else if (mode == PACKED_444_FP16) /* packed mode 64 bpp */
1363 time_per_byte = time_per_pixel/8;
1364
1365 if (time_per_byte == 0)
1366 time_per_byte = 1;
1367
1368 buf_lh_capability = (total_free_entry*time_per_byte*32) >> 6; /* time_per_byte is in u6.6*/
1369 max_scaled_time = buf_lh_capability - urgent_watermark;
1370 return max_scaled_time;
1371 }
1372
dcn30_set_mcif_arb_params(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt)1373 void dcn30_set_mcif_arb_params(
1374 struct dc *dc,
1375 struct dc_state *context,
1376 display_e2e_pipe_params_st *pipes,
1377 int pipe_cnt)
1378 {
1379 enum mmhubbub_wbif_mode wbif_mode;
1380 struct display_mode_lib *dml = &context->bw_ctx.dml;
1381 struct mcif_arb_params *wb_arb_params;
1382 int i, j, dwb_pipe;
1383
1384 /* Writeback MCIF_WB arbitration parameters */
1385 dwb_pipe = 0;
1386 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1387
1388 if (!context->res_ctx.pipe_ctx[i].stream)
1389 continue;
1390
1391 for (j = 0; j < MAX_DWB_PIPES; j++) {
1392 struct dc_writeback_info *writeback_info = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j];
1393
1394 if (writeback_info->wb_enabled == false)
1395 continue;
1396
1397 //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params;
1398 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
1399
1400 if (writeback_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_ARGB ||
1401 writeback_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_RGBA)
1402 wbif_mode = PACKED_444_FP16;
1403 else
1404 wbif_mode = PACKED_444;
1405
1406 DC_FP_START();
1407 dcn30_fpu_set_mcif_arb_params(wb_arb_params, dml, pipes, pipe_cnt, j);
1408 DC_FP_END();
1409 wb_arb_params->time_per_pixel = (1000000 << 6) / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* time_per_pixel should be in u6.6 format */
1410 wb_arb_params->slice_lines = 32;
1411 wb_arb_params->arbitration_slice = 2; /* irrelevant since there is no YUV output */
1412 wb_arb_params->max_scaled_time = dcn30_calc_max_scaled_time(wb_arb_params->time_per_pixel,
1413 wbif_mode,
1414 wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */
1415
1416 dwb_pipe++;
1417
1418 if (dwb_pipe >= MAX_DWB_PIPES)
1419 return;
1420 }
1421 }
1422 }
1423
1424 static struct dc_cap_funcs cap_funcs = {
1425 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1426 };
1427
dcn30_acquire_post_bldn_3dlut(struct resource_context * res_ctx,const struct resource_pool * pool,int mpcc_id,struct dc_3dlut ** lut,struct dc_transfer_func ** shaper)1428 bool dcn30_acquire_post_bldn_3dlut(
1429 struct resource_context *res_ctx,
1430 const struct resource_pool *pool,
1431 int mpcc_id,
1432 struct dc_3dlut **lut,
1433 struct dc_transfer_func **shaper)
1434 {
1435 int i;
1436 bool ret = false;
1437 union dc_3dlut_state *state;
1438
1439 ASSERT(*lut == NULL && *shaper == NULL);
1440 *lut = NULL;
1441 *shaper = NULL;
1442
1443 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1444 if (!res_ctx->is_mpc_3dlut_acquired[i]) {
1445 *lut = pool->mpc_lut[i];
1446 *shaper = pool->mpc_shaper[i];
1447 state = &pool->mpc_lut[i]->state;
1448 res_ctx->is_mpc_3dlut_acquired[i] = true;
1449 state->bits.rmu_idx_valid = 1;
1450 state->bits.rmu_mux_num = i;
1451 if (state->bits.rmu_mux_num == 0)
1452 state->bits.mpc_rmu0_mux = mpcc_id;
1453 else if (state->bits.rmu_mux_num == 1)
1454 state->bits.mpc_rmu1_mux = mpcc_id;
1455 else if (state->bits.rmu_mux_num == 2)
1456 state->bits.mpc_rmu2_mux = mpcc_id;
1457 ret = true;
1458 break;
1459 }
1460 }
1461 return ret;
1462 }
1463
dcn30_release_post_bldn_3dlut(struct resource_context * res_ctx,const struct resource_pool * pool,struct dc_3dlut ** lut,struct dc_transfer_func ** shaper)1464 bool dcn30_release_post_bldn_3dlut(
1465 struct resource_context *res_ctx,
1466 const struct resource_pool *pool,
1467 struct dc_3dlut **lut,
1468 struct dc_transfer_func **shaper)
1469 {
1470 int i;
1471 bool ret = false;
1472
1473 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1474 if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) {
1475 res_ctx->is_mpc_3dlut_acquired[i] = false;
1476 pool->mpc_lut[i]->state.raw = 0;
1477 *lut = NULL;
1478 *shaper = NULL;
1479 ret = true;
1480 break;
1481 }
1482 }
1483 return ret;
1484 }
1485
is_soc_bounding_box_valid(struct dc * dc)1486 static bool is_soc_bounding_box_valid(struct dc *dc)
1487 {
1488 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
1489
1490 if (ASICREV_IS_SIENNA_CICHLID_P(hw_internal_rev))
1491 return true;
1492
1493 return false;
1494 }
1495
init_soc_bounding_box(struct dc * dc,struct dcn30_resource_pool * pool)1496 static bool init_soc_bounding_box(struct dc *dc,
1497 struct dcn30_resource_pool *pool)
1498 {
1499 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_0_soc;
1500 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_0_ip;
1501
1502 DC_LOGGER_INIT(dc->ctx->logger);
1503
1504 if (!is_soc_bounding_box_valid(dc)) {
1505 DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__);
1506 return false;
1507 }
1508
1509 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
1510 loaded_ip->max_num_dpp = pool->base.pipe_count;
1511 loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
1512 dcn20_patch_bounding_box(dc, loaded_bb);
1513 DC_FP_START();
1514 patch_dcn30_soc_bounding_box(dc, &dcn3_0_soc);
1515 DC_FP_END();
1516
1517 return true;
1518 }
1519
dcn30_split_stream_for_mpc_or_odm(const struct dc * dc,struct resource_context * res_ctx,struct pipe_ctx * pri_pipe,struct pipe_ctx * sec_pipe,bool odm)1520 static bool dcn30_split_stream_for_mpc_or_odm(
1521 const struct dc *dc,
1522 struct resource_context *res_ctx,
1523 struct pipe_ctx *pri_pipe,
1524 struct pipe_ctx *sec_pipe,
1525 bool odm)
1526 {
1527 int pipe_idx = sec_pipe->pipe_idx;
1528 const struct resource_pool *pool = dc->res_pool;
1529
1530 *sec_pipe = *pri_pipe;
1531
1532 sec_pipe->pipe_idx = pipe_idx;
1533 sec_pipe->plane_res.mi = pool->mis[pipe_idx];
1534 sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];
1535 sec_pipe->plane_res.ipp = pool->ipps[pipe_idx];
1536 sec_pipe->plane_res.xfm = pool->transforms[pipe_idx];
1537 sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];
1538 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
1539 sec_pipe->stream_res.dsc = NULL;
1540 if (odm) {
1541 if (pri_pipe->next_odm_pipe) {
1542 ASSERT(pri_pipe->next_odm_pipe != sec_pipe);
1543 sec_pipe->next_odm_pipe = pri_pipe->next_odm_pipe;
1544 sec_pipe->next_odm_pipe->prev_odm_pipe = sec_pipe;
1545 }
1546 if (pri_pipe->top_pipe && pri_pipe->top_pipe->next_odm_pipe) {
1547 pri_pipe->top_pipe->next_odm_pipe->bottom_pipe = sec_pipe;
1548 sec_pipe->top_pipe = pri_pipe->top_pipe->next_odm_pipe;
1549 }
1550 if (pri_pipe->bottom_pipe && pri_pipe->bottom_pipe->next_odm_pipe) {
1551 pri_pipe->bottom_pipe->next_odm_pipe->top_pipe = sec_pipe;
1552 sec_pipe->bottom_pipe = pri_pipe->bottom_pipe->next_odm_pipe;
1553 }
1554 pri_pipe->next_odm_pipe = sec_pipe;
1555 sec_pipe->prev_odm_pipe = pri_pipe;
1556
1557 if (!sec_pipe->top_pipe)
1558 sec_pipe->stream_res.opp = pool->opps[pipe_idx];
1559 else
1560 sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp;
1561 if (sec_pipe->stream->timing.flags.DSC == 1) {
1562 dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx);
1563 ASSERT(sec_pipe->stream_res.dsc);
1564 if (sec_pipe->stream_res.dsc == NULL)
1565 return false;
1566 }
1567 } else {
1568 if (pri_pipe->bottom_pipe) {
1569 ASSERT(pri_pipe->bottom_pipe != sec_pipe);
1570 sec_pipe->bottom_pipe = pri_pipe->bottom_pipe;
1571 sec_pipe->bottom_pipe->top_pipe = sec_pipe;
1572 }
1573 pri_pipe->bottom_pipe = sec_pipe;
1574 sec_pipe->top_pipe = pri_pipe;
1575
1576 ASSERT(pri_pipe->plane_state);
1577 }
1578
1579 return true;
1580 }
1581
dcn30_find_split_pipe(struct dc * dc,struct dc_state * context,int old_index)1582 static struct pipe_ctx *dcn30_find_split_pipe(
1583 struct dc *dc,
1584 struct dc_state *context,
1585 int old_index)
1586 {
1587 struct pipe_ctx *pipe = NULL;
1588 int i;
1589
1590 if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) {
1591 pipe = &context->res_ctx.pipe_ctx[old_index];
1592 pipe->pipe_idx = old_index;
1593 }
1594
1595 if (!pipe)
1596 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1597 if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL
1598 && dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {
1599 if (context->res_ctx.pipe_ctx[i].stream == NULL) {
1600 pipe = &context->res_ctx.pipe_ctx[i];
1601 pipe->pipe_idx = i;
1602 break;
1603 }
1604 }
1605 }
1606
1607 /*
1608 * May need to fix pipes getting tossed from 1 opp to another on flip
1609 * Add for debugging transient underflow during topology updates:
1610 * ASSERT(pipe);
1611 */
1612 if (!pipe)
1613 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1614 if (context->res_ctx.pipe_ctx[i].stream == NULL) {
1615 pipe = &context->res_ctx.pipe_ctx[i];
1616 pipe->pipe_idx = i;
1617 break;
1618 }
1619 }
1620
1621 return pipe;
1622 }
1623
dcn30_internal_validate_bw(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int * pipe_cnt_out,int * vlevel_out,bool fast_validate,bool allow_self_refresh_only)1624 noinline bool dcn30_internal_validate_bw(
1625 struct dc *dc,
1626 struct dc_state *context,
1627 display_e2e_pipe_params_st *pipes,
1628 int *pipe_cnt_out,
1629 int *vlevel_out,
1630 bool fast_validate,
1631 bool allow_self_refresh_only)
1632 {
1633 bool out = false;
1634 bool repopulate_pipes = false;
1635 int split[MAX_PIPES] = { 0 };
1636 bool merge[MAX_PIPES] = { false };
1637 bool newly_split[MAX_PIPES] = { false };
1638 int pipe_cnt, i, pipe_idx, vlevel = 0;
1639 struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
1640
1641 ASSERT(pipes);
1642 if (!pipes)
1643 return false;
1644
1645 context->bw_ctx.dml.vba.maxMpcComb = 0;
1646 context->bw_ctx.dml.vba.VoltageLevel = 0;
1647 context->bw_ctx.dml.vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive;
1648 dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
1649 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
1650
1651 if (!pipe_cnt) {
1652 out = true;
1653 goto validate_out;
1654 }
1655
1656 dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt);
1657
1658 if (!fast_validate || !allow_self_refresh_only) {
1659 /*
1660 * DML favors voltage over p-state, but we're more interested in
1661 * supporting p-state over voltage. We can't support p-state in
1662 * prefetch mode > 0 so try capping the prefetch mode to start.
1663 */
1664 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
1665 dm_allow_self_refresh_and_mclk_switch;
1666 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1667 /* This may adjust vlevel and maxMpcComb */
1668 if (vlevel < context->bw_ctx.dml.soc.num_states)
1669 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
1670 }
1671 if (allow_self_refresh_only &&
1672 (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states ||
1673 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported)) {
1674 /*
1675 * If mode is unsupported or there's still no p-state support
1676 * then fall back to favoring voltage.
1677 *
1678 * We don't actually support prefetch mode 2, so require that we
1679 * at least support prefetch mode 1.
1680 */
1681 context->bw_ctx.dml.validate_max_state = fast_validate;
1682 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
1683 dm_allow_self_refresh;
1684
1685 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1686 if (vlevel < context->bw_ctx.dml.soc.num_states) {
1687 memset(split, 0, sizeof(split));
1688 memset(merge, 0, sizeof(merge));
1689 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
1690 }
1691 context->bw_ctx.dml.validate_max_state = false;
1692 }
1693
1694 dml_log_mode_support_params(&context->bw_ctx.dml);
1695
1696 if (vlevel == context->bw_ctx.dml.soc.num_states)
1697 goto validate_fail;
1698
1699 if (!dc->config.enable_windowed_mpo_odm) {
1700 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1701 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1702 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
1703
1704 if (!pipe->stream)
1705 continue;
1706
1707 /* We only support full screen mpo with ODM */
1708 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
1709 && pipe->plane_state && mpo_pipe
1710 && memcmp(&mpo_pipe->plane_state->clip_rect,
1711 &pipe->stream->src,
1712 sizeof(struct rect)) != 0) {
1713 ASSERT(mpo_pipe->plane_state != pipe->plane_state);
1714 goto validate_fail;
1715 }
1716 pipe_idx++;
1717 }
1718 }
1719
1720 /* merge pipes if necessary */
1721 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1722 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1723
1724 /*skip pipes that don't need merging*/
1725 if (!merge[i])
1726 continue;
1727
1728 /* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */
1729 if (pipe->prev_odm_pipe) {
1730 /*split off odm pipe*/
1731 pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe;
1732 if (pipe->next_odm_pipe)
1733 pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe;
1734
1735 pipe->bottom_pipe = NULL;
1736 pipe->next_odm_pipe = NULL;
1737 pipe->plane_state = NULL;
1738 pipe->stream = NULL;
1739 pipe->top_pipe = NULL;
1740 pipe->prev_odm_pipe = NULL;
1741 if (pipe->stream_res.dsc)
1742 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);
1743 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
1744 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
1745 repopulate_pipes = true;
1746 } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
1747 struct pipe_ctx *top_pipe = pipe->top_pipe;
1748 struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;
1749
1750 top_pipe->bottom_pipe = bottom_pipe;
1751 if (bottom_pipe)
1752 bottom_pipe->top_pipe = top_pipe;
1753
1754 pipe->top_pipe = NULL;
1755 pipe->bottom_pipe = NULL;
1756 pipe->plane_state = NULL;
1757 pipe->stream = NULL;
1758 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
1759 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
1760 repopulate_pipes = true;
1761 } else
1762 ASSERT(0); /* Should never try to merge master pipe */
1763
1764 }
1765
1766 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
1767 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1768 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1769 struct pipe_ctx *hsplit_pipe = NULL;
1770 bool odm;
1771 int old_index = -1;
1772
1773 if (!pipe->stream || newly_split[i])
1774 continue;
1775
1776 pipe_idx++;
1777 odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled;
1778
1779 if (!pipe->plane_state && !odm)
1780 continue;
1781
1782 if (split[i]) {
1783 if (odm) {
1784 if (split[i] == 4 && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe)
1785 old_index = old_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
1786 else if (old_pipe->next_odm_pipe)
1787 old_index = old_pipe->next_odm_pipe->pipe_idx;
1788 } else {
1789 if (split[i] == 4 && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
1790 old_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1791 old_index = old_pipe->bottom_pipe->bottom_pipe->pipe_idx;
1792 else if (old_pipe->bottom_pipe &&
1793 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1794 old_index = old_pipe->bottom_pipe->pipe_idx;
1795 }
1796 hsplit_pipe = dcn30_find_split_pipe(dc, context, old_index);
1797 ASSERT(hsplit_pipe);
1798 if (!hsplit_pipe)
1799 goto validate_fail;
1800
1801 if (!dcn30_split_stream_for_mpc_or_odm(
1802 dc, &context->res_ctx,
1803 pipe, hsplit_pipe, odm))
1804 goto validate_fail;
1805
1806 newly_split[hsplit_pipe->pipe_idx] = true;
1807 repopulate_pipes = true;
1808 }
1809 if (split[i] == 4) {
1810 struct pipe_ctx *pipe_4to1;
1811
1812 if (odm && old_pipe->next_odm_pipe)
1813 old_index = old_pipe->next_odm_pipe->pipe_idx;
1814 else if (!odm && old_pipe->bottom_pipe &&
1815 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1816 old_index = old_pipe->bottom_pipe->pipe_idx;
1817 else
1818 old_index = -1;
1819 pipe_4to1 = dcn30_find_split_pipe(dc, context, old_index);
1820 ASSERT(pipe_4to1);
1821 if (!pipe_4to1)
1822 goto validate_fail;
1823 if (!dcn30_split_stream_for_mpc_or_odm(
1824 dc, &context->res_ctx,
1825 pipe, pipe_4to1, odm))
1826 goto validate_fail;
1827 newly_split[pipe_4to1->pipe_idx] = true;
1828
1829 if (odm && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe
1830 && old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe)
1831 old_index = old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
1832 else if (!odm && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
1833 old_pipe->bottom_pipe->bottom_pipe->bottom_pipe &&
1834 old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1835 old_index = old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->pipe_idx;
1836 else
1837 old_index = -1;
1838 pipe_4to1 = dcn30_find_split_pipe(dc, context, old_index);
1839 ASSERT(pipe_4to1);
1840 if (!pipe_4to1)
1841 goto validate_fail;
1842 if (!dcn30_split_stream_for_mpc_or_odm(
1843 dc, &context->res_ctx,
1844 hsplit_pipe, pipe_4to1, odm))
1845 goto validate_fail;
1846 newly_split[pipe_4to1->pipe_idx] = true;
1847 }
1848 if (odm)
1849 dcn20_build_mapped_resource(dc, context, pipe->stream);
1850 }
1851
1852 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1853 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1854
1855 if (pipe->plane_state) {
1856 if (!resource_build_scaling_params(pipe))
1857 goto validate_fail;
1858 }
1859 }
1860
1861 /* Actual dsc count per stream dsc validation*/
1862 if (!dcn20_validate_dsc(dc, context)) {
1863 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE;
1864 goto validate_fail;
1865 }
1866
1867 if (repopulate_pipes)
1868 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
1869 context->bw_ctx.dml.vba.VoltageLevel = vlevel;
1870 *vlevel_out = vlevel;
1871 *pipe_cnt_out = pipe_cnt;
1872
1873 out = true;
1874 goto validate_out;
1875
1876 validate_fail:
1877 out = false;
1878
1879 validate_out:
1880 return out;
1881 }
1882
get_refresh_rate(struct dc_state * context)1883 static int get_refresh_rate(struct dc_state *context)
1884 {
1885 int refresh_rate = 0;
1886 int h_v_total = 0;
1887 struct dc_crtc_timing *timing = NULL;
1888
1889 if (context == NULL || context->streams[0] == NULL)
1890 return 0;
1891
1892 /* check if refresh rate at least 120hz */
1893 timing = &context->streams[0]->timing;
1894 if (timing == NULL)
1895 return 0;
1896
1897 h_v_total = timing->h_total * timing->v_total;
1898 if (h_v_total == 0)
1899 return 0;
1900
1901 refresh_rate = ((timing->pix_clk_100hz * 100) / (h_v_total)) + 1;
1902 return refresh_rate;
1903 }
1904
1905 #define MAX_STRETCHED_V_BLANK 500 // in micro-seconds
1906 /*
1907 * Scaling factor for v_blank stretch calculations considering timing in
1908 * micro-seconds and pixel clock in 100hz.
1909 * Note: the parenthesis are necessary to ensure the correct order of
1910 * operation where V_SCALE is used.
1911 */
1912 #define V_SCALE (10000 / MAX_STRETCHED_V_BLANK)
1913
get_frame_rate_at_max_stretch_100hz(struct dc_state * context)1914 static int get_frame_rate_at_max_stretch_100hz(struct dc_state *context)
1915 {
1916 struct dc_crtc_timing *timing = NULL;
1917 uint32_t sec_per_100_lines;
1918 uint32_t max_v_blank;
1919 uint32_t curr_v_blank;
1920 uint32_t v_stretch_max;
1921 uint32_t stretched_frame_pix_cnt;
1922 uint32_t scaled_stretched_frame_pix_cnt;
1923 uint32_t scaled_refresh_rate;
1924
1925 if (context == NULL || context->streams[0] == NULL)
1926 return 0;
1927
1928 /* check if refresh rate at least 120hz */
1929 timing = &context->streams[0]->timing;
1930 if (timing == NULL)
1931 return 0;
1932
1933 sec_per_100_lines = timing->pix_clk_100hz / timing->h_total + 1;
1934 max_v_blank = sec_per_100_lines / V_SCALE + 1;
1935 curr_v_blank = timing->v_total - timing->v_addressable;
1936 v_stretch_max = (max_v_blank > curr_v_blank) ? (max_v_blank - curr_v_blank) : (0);
1937 stretched_frame_pix_cnt = (v_stretch_max + timing->v_total) * timing->h_total;
1938 scaled_stretched_frame_pix_cnt = stretched_frame_pix_cnt / 10000;
1939 scaled_refresh_rate = (timing->pix_clk_100hz) / scaled_stretched_frame_pix_cnt + 1;
1940
1941 return scaled_refresh_rate;
1942 }
1943
is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch(struct dc_state * context)1944 static bool is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch(struct dc_state *context)
1945 {
1946 int refresh_rate_max_stretch_100hz;
1947 int min_refresh_100hz;
1948
1949 if (context == NULL || context->streams[0] == NULL)
1950 return false;
1951
1952 refresh_rate_max_stretch_100hz = get_frame_rate_at_max_stretch_100hz(context);
1953 min_refresh_100hz = context->streams[0]->timing.min_refresh_in_uhz / 10000;
1954
1955 if (refresh_rate_max_stretch_100hz < min_refresh_100hz)
1956 return false;
1957
1958 return true;
1959 }
1960
dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc * dc,struct dc_state * context)1961 bool dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context)
1962 {
1963 int refresh_rate = 0;
1964 const int minimum_refreshrate_supported = 120;
1965 struct dc_stream_status *stream_status = NULL;
1966
1967 if (context == NULL || context->streams[0] == NULL)
1968 return false;
1969
1970 if (context->streams[0]->sink->edid_caps.panel_patch.disable_fams)
1971 return false;
1972
1973 if (dc->debug.disable_fams)
1974 return false;
1975
1976 if (!dc->caps.dmub_caps.mclk_sw)
1977 return false;
1978
1979 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching_shut_down)
1980 return false;
1981
1982 /* more then 1 monitor connected */
1983 if (context->stream_count != 1)
1984 return false;
1985
1986 refresh_rate = get_refresh_rate(context);
1987 if (refresh_rate < minimum_refreshrate_supported)
1988 return false;
1989
1990 if (!is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch(context))
1991 return false;
1992
1993 if (!context->streams[0]->allow_freesync)
1994 return false;
1995
1996 if (context->streams[0]->vrr_active_variable && (dc->debug.disable_fams_gaming == INGAME_FAMS_DISABLE))
1997 return false;
1998
1999 stream_status = dc_state_get_stream_status(context, context->streams[0]);
2000
2001 if (!stream_status)
2002 return false;
2003
2004 stream_status->fpo_in_use = true;
2005
2006 return true;
2007 }
2008
2009 /*
2010 * set up FPO watermarks, pstate, dram latency
2011 */
dcn30_setup_mclk_switch_using_fw_based_vblank_stretch(struct dc * dc,struct dc_state * context)2012 void dcn30_setup_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context)
2013 {
2014 ASSERT(dc != NULL && context != NULL);
2015 if (dc == NULL || context == NULL)
2016 return;
2017
2018 /* Set wm_a.pstate so high natural MCLK switches are impossible: 4 seconds */
2019 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U;
2020 }
2021
dcn30_update_soc_for_wm_a(struct dc * dc,struct dc_state * context)2022 void dcn30_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
2023 {
2024 DC_FP_START();
2025 dcn30_fpu_update_soc_for_wm_a(dc, context);
2026 DC_FP_END();
2027 }
2028
dcn30_calculate_wm_and_dlg(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt,int vlevel)2029 void dcn30_calculate_wm_and_dlg(
2030 struct dc *dc, struct dc_state *context,
2031 display_e2e_pipe_params_st *pipes,
2032 int pipe_cnt,
2033 int vlevel)
2034 {
2035 DC_FP_START();
2036 dcn30_fpu_calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
2037 DC_FP_END();
2038 }
2039
dcn30_validate_bandwidth(struct dc * dc,struct dc_state * context,bool fast_validate)2040 bool dcn30_validate_bandwidth(struct dc *dc,
2041 struct dc_state *context,
2042 bool fast_validate)
2043 {
2044 bool out = false;
2045
2046 BW_VAL_TRACE_SETUP();
2047
2048 int vlevel = 0;
2049 int pipe_cnt = 0;
2050 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
2051 DC_LOGGER_INIT(dc->ctx->logger);
2052
2053 BW_VAL_TRACE_COUNT();
2054
2055 if (!pipes)
2056 goto validate_fail;
2057
2058 DC_FP_START();
2059 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, true);
2060 DC_FP_END();
2061
2062 if (pipe_cnt == 0)
2063 goto validate_out;
2064
2065 if (!out)
2066 goto validate_fail;
2067
2068 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
2069
2070 if (fast_validate) {
2071 BW_VAL_TRACE_SKIP(fast);
2072 goto validate_out;
2073 }
2074
2075 DC_FP_START();
2076 if (dc->res_pool->funcs->calculate_wm_and_dlg)
2077 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
2078 DC_FP_END();
2079
2080 BW_VAL_TRACE_END_WATERMARKS();
2081
2082 goto validate_out;
2083
2084 validate_fail:
2085 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
2086 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
2087
2088 BW_VAL_TRACE_SKIP(fail);
2089 out = false;
2090
2091 validate_out:
2092 kfree(pipes);
2093
2094 BW_VAL_TRACE_FINISH();
2095
2096 return out;
2097 }
2098
dcn30_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)2099 void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
2100 {
2101 unsigned int i, j;
2102 unsigned int num_states = 0;
2103
2104 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};
2105 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};
2106 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};
2107 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};
2108
2109 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200};
2110 unsigned int num_dcfclk_sta_targets = 4;
2111 unsigned int num_uclk_states;
2112
2113 struct dc_bounding_box_max_clk dcn30_bb_max_clk;
2114
2115 memset(&dcn30_bb_max_clk, 0, sizeof(dcn30_bb_max_clk));
2116
2117 if (dc->ctx->dc_bios->vram_info.num_chans)
2118 dcn3_0_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;
2119
2120 DC_FP_START();
2121 dcn30_fpu_update_dram_channel_width_bytes(dc);
2122 DC_FP_END();
2123
2124 if (bw_params->clk_table.entries[0].memclk_mhz) {
2125
2126 for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
2127 if (bw_params->clk_table.entries[i].dcfclk_mhz > dcn30_bb_max_clk.max_dcfclk_mhz)
2128 dcn30_bb_max_clk.max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
2129 if (bw_params->clk_table.entries[i].dispclk_mhz > dcn30_bb_max_clk.max_dispclk_mhz)
2130 dcn30_bb_max_clk.max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
2131 if (bw_params->clk_table.entries[i].dppclk_mhz > dcn30_bb_max_clk.max_dppclk_mhz)
2132 dcn30_bb_max_clk.max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
2133 if (bw_params->clk_table.entries[i].phyclk_mhz > dcn30_bb_max_clk.max_phyclk_mhz)
2134 dcn30_bb_max_clk.max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
2135 }
2136
2137 DC_FP_START();
2138 dcn30_fpu_update_max_clk(&dcn30_bb_max_clk);
2139 DC_FP_END();
2140
2141 if (dcn30_bb_max_clk.max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2142 // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array
2143 dcfclk_sta_targets[num_dcfclk_sta_targets] = dcn30_bb_max_clk.max_dcfclk_mhz;
2144 num_dcfclk_sta_targets++;
2145 } else if (dcn30_bb_max_clk.max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2146 // If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates
2147 for (i = 0; i < num_dcfclk_sta_targets; i++) {
2148 if (dcfclk_sta_targets[i] > dcn30_bb_max_clk.max_dcfclk_mhz) {
2149 dcfclk_sta_targets[i] = dcn30_bb_max_clk.max_dcfclk_mhz;
2150 break;
2151 }
2152 }
2153 // Update size of array since we "removed" duplicates
2154 num_dcfclk_sta_targets = i + 1;
2155 }
2156
2157 num_uclk_states = bw_params->clk_table.num_entries;
2158
2159 // Calculate optimal dcfclk for each uclk
2160 for (i = 0; i < num_uclk_states; i++) {
2161 DC_FP_START();
2162 dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
2163 &optimal_dcfclk_for_uclk[i], NULL);
2164 DC_FP_END();
2165 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
2166 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
2167 }
2168 }
2169
2170 // Calculate optimal uclk for each dcfclk sta target
2171 for (i = 0; i < num_dcfclk_sta_targets; i++) {
2172 for (j = 0; j < num_uclk_states; j++) {
2173 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
2174 optimal_uclk_for_dcfclk_sta_targets[i] =
2175 bw_params->clk_table.entries[j].memclk_mhz * 16;
2176 break;
2177 } else {
2178 /* condition where (dcfclk_sta_targets[i] >= optimal_dcfclk_for_uclk[j]):
2179 * If it just so happens that the memory bandwidth is low enough such that
2180 * all the optimal DCFCLK for each UCLK is lower than the smallest DCFCLK STA
2181 * target, we need to populate the optimal UCLK for each DCFCLK STA target to
2182 * be the max UCLK.
2183 */
2184 if (j == num_uclk_states - 1) {
2185 optimal_uclk_for_dcfclk_sta_targets[i] =
2186 bw_params->clk_table.entries[j].memclk_mhz * 16;
2187 }
2188 }
2189 }
2190 }
2191
2192 i = 0;
2193 j = 0;
2194 // create the final dcfclk and uclk table
2195 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
2196 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
2197 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2198 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2199 } else {
2200 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= dcn30_bb_max_clk.max_dcfclk_mhz) {
2201 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2202 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2203 } else {
2204 j = num_uclk_states;
2205 }
2206 }
2207 }
2208
2209 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
2210 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2211 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2212 }
2213
2214 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
2215 optimal_dcfclk_for_uclk[j] <= dcn30_bb_max_clk.max_dcfclk_mhz) {
2216 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2217 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2218 }
2219
2220 dcn3_0_soc.num_states = num_states;
2221 DC_FP_START();
2222 dcn30_fpu_update_bw_bounding_box(dc, bw_params, &dcn30_bb_max_clk, dcfclk_mhz, dram_speed_mts);
2223 DC_FP_END();
2224 }
2225 }
2226
dcn30_get_panel_config_defaults(struct dc_panel_config * panel_config)2227 static void dcn30_get_panel_config_defaults(struct dc_panel_config *panel_config)
2228 {
2229 *panel_config = panel_config_defaults;
2230 }
2231
2232 static const struct resource_funcs dcn30_res_pool_funcs = {
2233 .destroy = dcn30_destroy_resource_pool,
2234 .link_enc_create = dcn30_link_encoder_create,
2235 .panel_cntl_create = dcn30_panel_cntl_create,
2236 .validate_bandwidth = dcn30_validate_bandwidth,
2237 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
2238 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
2239 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
2240 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
2241 .release_pipe = dcn20_release_pipe,
2242 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
2243 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
2244 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
2245 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
2246 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
2247 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
2248 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
2249 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
2250 .update_bw_bounding_box = dcn30_update_bw_bounding_box,
2251 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
2252 .get_panel_config_defaults = dcn30_get_panel_config_defaults,
2253 .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe
2254 };
2255
2256 #define CTX ctx
2257
2258 #define REG(reg_name) \
2259 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
2260
read_pipe_fuses(struct dc_context * ctx)2261 static uint32_t read_pipe_fuses(struct dc_context *ctx)
2262 {
2263 uint32_t value = REG_READ(CC_DC_PIPE_DIS);
2264 /* Support for max 6 pipes */
2265 value = value & 0x3f;
2266 return value;
2267 }
2268
dcn30_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn30_resource_pool * pool)2269 static bool dcn30_resource_construct(
2270 uint8_t num_virtual_links,
2271 struct dc *dc,
2272 struct dcn30_resource_pool *pool)
2273 {
2274 int i;
2275 struct dc_context *ctx = dc->ctx;
2276 struct irq_service_init_data init_data;
2277 struct ddc_service_init_data ddc_init_data = {0};
2278 uint32_t pipe_fuses = read_pipe_fuses(ctx);
2279 uint32_t num_pipes = 0;
2280
2281 if (!(pipe_fuses == 0 || pipe_fuses == 0x3e)) {
2282 BREAK_TO_DEBUGGER();
2283 dm_error("DC: Unexpected fuse recipe for navi2x !\n");
2284 /* fault to single pipe */
2285 pipe_fuses = 0x3e;
2286 }
2287
2288 DC_FP_START();
2289
2290 ctx->dc_bios->regs = &bios_regs;
2291
2292 pool->base.res_cap = &res_cap_dcn3;
2293
2294 pool->base.funcs = &dcn30_res_pool_funcs;
2295
2296 /*************************************************
2297 * Resource + asic cap harcoding *
2298 *************************************************/
2299 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
2300 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
2301 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
2302 dc->caps.max_downscale_ratio = 600;
2303 dc->caps.i2c_speed_in_khz = 100;
2304 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
2305 dc->caps.max_cursor_size = 256;
2306 dc->caps.min_horizontal_blanking_period = 80;
2307 dc->caps.dmdata_alloc_size = 2048;
2308 dc->caps.mall_size_per_mem_channel = 8;
2309 /* total size = mall per channel * num channels * 1024 * 1024 */
2310 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;
2311 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
2312
2313 dc->caps.max_slave_planes = 2;
2314 dc->caps.max_slave_yuv_planes = 2;
2315 dc->caps.max_slave_rgb_planes = 2;
2316 dc->caps.post_blend_color_processing = true;
2317 dc->caps.force_dp_tps4_for_cp2520 = true;
2318 dc->caps.extended_aux_timeout_support = true;
2319 dc->caps.dmcub_support = true;
2320
2321 /* Color pipeline capabilities */
2322 dc->caps.color.dpp.dcn_arch = 1;
2323 dc->caps.color.dpp.input_lut_shared = 0;
2324 dc->caps.color.dpp.icsc = 1;
2325 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
2326 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2327 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2328 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
2329 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
2330 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
2331 dc->caps.color.dpp.post_csc = 1;
2332 dc->caps.color.dpp.gamma_corr = 1;
2333 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
2334
2335 dc->caps.color.dpp.hw_3d_lut = 1;
2336 dc->caps.color.dpp.ogam_ram = 1;
2337 // no OGAM ROM on DCN3
2338 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2339 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2340 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2341 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2342 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2343 dc->caps.color.dpp.ocsc = 0;
2344
2345 dc->caps.color.mpc.gamut_remap = 1;
2346 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //3
2347 dc->caps.color.mpc.ogam_ram = 1;
2348 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2349 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2350 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2351 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2352 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2353 dc->caps.color.mpc.ocsc = 1;
2354
2355 dc->caps.dp_hdmi21_pcon_support = true;
2356 dc->caps.max_v_total = (1 << 15) - 1;
2357 dc->caps.vtotal_limited_by_fp2 = true;
2358
2359 /* read VBIOS LTTPR caps */
2360 {
2361 if (ctx->dc_bios->funcs->get_lttpr_caps) {
2362 enum bp_result bp_query_result;
2363 uint8_t is_vbios_lttpr_enable = 0;
2364
2365 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
2366 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
2367 }
2368
2369 if (ctx->dc_bios->funcs->get_lttpr_interop) {
2370 enum bp_result bp_query_result;
2371 uint8_t is_vbios_interop_enabled = 0;
2372
2373 bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios,
2374 &is_vbios_interop_enabled);
2375 dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
2376 }
2377 }
2378
2379 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2380 dc->debug = debug_defaults_drv;
2381
2382 // Init the vm_helper
2383 if (dc->vm_helper)
2384 vm_helper_init(dc->vm_helper, 16);
2385
2386 /*************************************************
2387 * Create resources *
2388 *************************************************/
2389
2390 /* Clock Sources for Pixel Clock*/
2391 pool->base.clock_sources[DCN30_CLK_SRC_PLL0] =
2392 dcn30_clock_source_create(ctx, ctx->dc_bios,
2393 CLOCK_SOURCE_COMBO_PHY_PLL0,
2394 &clk_src_regs[0], false);
2395 pool->base.clock_sources[DCN30_CLK_SRC_PLL1] =
2396 dcn30_clock_source_create(ctx, ctx->dc_bios,
2397 CLOCK_SOURCE_COMBO_PHY_PLL1,
2398 &clk_src_regs[1], false);
2399 pool->base.clock_sources[DCN30_CLK_SRC_PLL2] =
2400 dcn30_clock_source_create(ctx, ctx->dc_bios,
2401 CLOCK_SOURCE_COMBO_PHY_PLL2,
2402 &clk_src_regs[2], false);
2403 pool->base.clock_sources[DCN30_CLK_SRC_PLL3] =
2404 dcn30_clock_source_create(ctx, ctx->dc_bios,
2405 CLOCK_SOURCE_COMBO_PHY_PLL3,
2406 &clk_src_regs[3], false);
2407 pool->base.clock_sources[DCN30_CLK_SRC_PLL4] =
2408 dcn30_clock_source_create(ctx, ctx->dc_bios,
2409 CLOCK_SOURCE_COMBO_PHY_PLL4,
2410 &clk_src_regs[4], false);
2411 pool->base.clock_sources[DCN30_CLK_SRC_PLL5] =
2412 dcn30_clock_source_create(ctx, ctx->dc_bios,
2413 CLOCK_SOURCE_COMBO_PHY_PLL5,
2414 &clk_src_regs[5], false);
2415
2416 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
2417
2418 /* todo: not reuse phy_pll registers */
2419 pool->base.dp_clock_source =
2420 dcn30_clock_source_create(ctx, ctx->dc_bios,
2421 CLOCK_SOURCE_ID_DP_DTO,
2422 &clk_src_regs[0], true);
2423
2424 for (i = 0; i < pool->base.clk_src_count; i++) {
2425 if (pool->base.clock_sources[i] == NULL) {
2426 dm_error("DC: failed to create clock sources!\n");
2427 BREAK_TO_DEBUGGER();
2428 goto create_fail;
2429 }
2430 }
2431
2432 /* DCCG */
2433 pool->base.dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2434 if (pool->base.dccg == NULL) {
2435 dm_error("DC: failed to create dccg!\n");
2436 BREAK_TO_DEBUGGER();
2437 goto create_fail;
2438 }
2439
2440 /* PP Lib and SMU interfaces */
2441 init_soc_bounding_box(dc, pool);
2442
2443 num_pipes = dcn3_0_ip.max_num_dpp;
2444
2445 for (i = 0; i < dcn3_0_ip.max_num_dpp; i++)
2446 if (pipe_fuses & 1 << i)
2447 num_pipes--;
2448
2449 dcn3_0_ip.max_num_dpp = num_pipes;
2450 dcn3_0_ip.max_num_otg = num_pipes;
2451
2452 dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
2453
2454 /* IRQ */
2455 init_data.ctx = dc->ctx;
2456 pool->base.irqs = dal_irq_service_dcn30_create(&init_data);
2457 if (!pool->base.irqs)
2458 goto create_fail;
2459
2460 /* HUBBUB */
2461 pool->base.hubbub = dcn30_hubbub_create(ctx);
2462 if (pool->base.hubbub == NULL) {
2463 BREAK_TO_DEBUGGER();
2464 dm_error("DC: failed to create hubbub!\n");
2465 goto create_fail;
2466 }
2467
2468 /* HUBPs, DPPs, OPPs and TGs */
2469 for (i = 0; i < pool->base.pipe_count; i++) {
2470 pool->base.hubps[i] = dcn30_hubp_create(ctx, i);
2471 if (pool->base.hubps[i] == NULL) {
2472 BREAK_TO_DEBUGGER();
2473 dm_error(
2474 "DC: failed to create hubps!\n");
2475 goto create_fail;
2476 }
2477
2478 pool->base.dpps[i] = dcn30_dpp_create(ctx, i);
2479 if (pool->base.dpps[i] == NULL) {
2480 BREAK_TO_DEBUGGER();
2481 dm_error(
2482 "DC: failed to create dpps!\n");
2483 goto create_fail;
2484 }
2485 }
2486
2487 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2488 pool->base.opps[i] = dcn30_opp_create(ctx, i);
2489 if (pool->base.opps[i] == NULL) {
2490 BREAK_TO_DEBUGGER();
2491 dm_error(
2492 "DC: failed to create output pixel processor!\n");
2493 goto create_fail;
2494 }
2495 }
2496
2497 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2498 pool->base.timing_generators[i] = dcn30_timing_generator_create(
2499 ctx, i);
2500 if (pool->base.timing_generators[i] == NULL) {
2501 BREAK_TO_DEBUGGER();
2502 dm_error("DC: failed to create tg!\n");
2503 goto create_fail;
2504 }
2505 }
2506 pool->base.timing_generator_count = i;
2507 /* PSR */
2508 pool->base.psr = dmub_psr_create(ctx);
2509
2510 if (pool->base.psr == NULL) {
2511 dm_error("DC: failed to create PSR obj!\n");
2512 BREAK_TO_DEBUGGER();
2513 goto create_fail;
2514 }
2515
2516 /* ABM */
2517 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2518 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2519 &abm_regs[i],
2520 &abm_shift,
2521 &abm_mask);
2522 if (pool->base.multiple_abms[i] == NULL) {
2523 dm_error("DC: failed to create abm for pipe %d!\n", i);
2524 BREAK_TO_DEBUGGER();
2525 goto create_fail;
2526 }
2527 }
2528 /* MPC and DSC */
2529 pool->base.mpc = dcn30_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2530 if (pool->base.mpc == NULL) {
2531 BREAK_TO_DEBUGGER();
2532 dm_error("DC: failed to create mpc!\n");
2533 goto create_fail;
2534 }
2535
2536 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2537 pool->base.dscs[i] = dcn30_dsc_create(ctx, i);
2538 if (pool->base.dscs[i] == NULL) {
2539 BREAK_TO_DEBUGGER();
2540 dm_error("DC: failed to create display stream compressor %d!\n", i);
2541 goto create_fail;
2542 }
2543 }
2544
2545 /* DWB and MMHUBBUB */
2546 if (!dcn30_dwbc_create(ctx, &pool->base)) {
2547 BREAK_TO_DEBUGGER();
2548 dm_error("DC: failed to create dwbc!\n");
2549 goto create_fail;
2550 }
2551
2552 if (!dcn30_mmhubbub_create(ctx, &pool->base)) {
2553 BREAK_TO_DEBUGGER();
2554 dm_error("DC: failed to create mcif_wb!\n");
2555 goto create_fail;
2556 }
2557
2558 /* AUX and I2C */
2559 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2560 pool->base.engines[i] = dcn30_aux_engine_create(ctx, i);
2561 if (pool->base.engines[i] == NULL) {
2562 BREAK_TO_DEBUGGER();
2563 dm_error(
2564 "DC:failed to create aux engine!!\n");
2565 goto create_fail;
2566 }
2567 pool->base.hw_i2cs[i] = dcn30_i2c_hw_create(ctx, i);
2568 if (pool->base.hw_i2cs[i] == NULL) {
2569 BREAK_TO_DEBUGGER();
2570 dm_error(
2571 "DC:failed to create hw i2c!!\n");
2572 goto create_fail;
2573 }
2574 pool->base.sw_i2cs[i] = NULL;
2575 }
2576
2577 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2578 if (!resource_construct(num_virtual_links, dc, &pool->base,
2579 &res_create_funcs))
2580 goto create_fail;
2581
2582 /* HW Sequencer and Plane caps */
2583 dcn30_hw_sequencer_construct(dc);
2584
2585 dc->caps.max_planes = pool->base.pipe_count;
2586
2587 for (i = 0; i < dc->caps.max_planes; ++i)
2588 dc->caps.planes[i] = plane_cap;
2589
2590 dc->cap_funcs = cap_funcs;
2591
2592 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
2593 ddc_init_data.ctx = dc->ctx;
2594 ddc_init_data.link = NULL;
2595 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
2596 ddc_init_data.id.enum_id = 0;
2597 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
2598 pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);
2599 } else {
2600 pool->base.oem_device = NULL;
2601 }
2602
2603 DC_FP_END();
2604
2605 return true;
2606
2607 create_fail:
2608
2609 DC_FP_END();
2610 dcn30_resource_destruct(pool);
2611
2612 return false;
2613 }
2614
dcn30_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2615 struct resource_pool *dcn30_create_resource_pool(
2616 const struct dc_init_data *init_data,
2617 struct dc *dc)
2618 {
2619 struct dcn30_resource_pool *pool =
2620 kzalloc(sizeof(struct dcn30_resource_pool), GFP_KERNEL);
2621
2622 if (!pool)
2623 return NULL;
2624
2625 if (dcn30_resource_construct(init_data->num_virtual_links, dc, pool))
2626 return &pool->base;
2627
2628 BREAK_TO_DEBUGGER();
2629 kfree(pool);
2630 return NULL;
2631 }
2632