1 /*
2 * Copyright 2020 Mauro Rossi <issor.oruam@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <linux/slab.h>
27
28 #include "dce/dce_6_0_d.h"
29 #include "dce/dce_6_0_sh_mask.h"
30
31 #include "dm_services.h"
32
33 #include "link_encoder.h"
34 #include "stream_encoder.h"
35
36 #include "resource.h"
37 #include "clk_mgr.h"
38 #include "include/irq_service_interface.h"
39 #include "irq/dce60/irq_service_dce60.h"
40 #include "dce110/dce110_timing_generator.h"
41 #include "dce110/dce110_resource.h"
42 #include "dce60/dce60_timing_generator.h"
43 #include "dce/dce_mem_input.h"
44 #include "dce/dce_link_encoder.h"
45 #include "dce/dce_stream_encoder.h"
46 #include "dce/dce_ipp.h"
47 #include "dce/dce_transform.h"
48 #include "dce/dce_opp.h"
49 #include "dce/dce_clock_source.h"
50 #include "dce/dce_audio.h"
51 #include "dce/dce_hwseq.h"
52 #include "dce60/dce60_hwseq.h"
53 #include "dce100/dce100_resource.h"
54 #include "dce/dce_panel_cntl.h"
55
56 #include "reg_helper.h"
57
58 #include "dce/dce_dmcu.h"
59 #include "dce/dce_aux.h"
60 #include "dce/dce_abm.h"
61 #include "dce/dce_i2c.h"
62 /* TODO remove this include */
63
64 #include "dce60_resource.h"
65
66 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
67 #include "gmc/gmc_6_0_d.h"
68 #include "gmc/gmc_6_0_sh_mask.h"
69 #endif
70
71 #ifndef mmDP_DPHY_INTERNAL_CTRL
72 #define mmDP_DPHY_INTERNAL_CTRL 0x1CDE
73 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x1CDE
74 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x1FDE
75 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x42DE
76 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x45DE
77 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x48DE
78 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4BDE
79 #endif
80
81
82 #ifndef mmBIOS_SCRATCH_2
83 #define mmBIOS_SCRATCH_0 0x05C9
84 #define mmBIOS_SCRATCH_2 0x05CB
85 #define mmBIOS_SCRATCH_3 0x05CC
86 #define mmBIOS_SCRATCH_6 0x05CF
87 #endif
88
89 #ifndef mmDP_DPHY_FAST_TRAINING
90 #define mmDP_DPHY_FAST_TRAINING 0x1CCE
91 #define mmDP0_DP_DPHY_FAST_TRAINING 0x1CCE
92 #define mmDP1_DP_DPHY_FAST_TRAINING 0x1FCE
93 #define mmDP2_DP_DPHY_FAST_TRAINING 0x42CE
94 #define mmDP3_DP_DPHY_FAST_TRAINING 0x45CE
95 #define mmDP4_DP_DPHY_FAST_TRAINING 0x48CE
96 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4BCE
97 #endif
98
99
100 #ifndef mmHPD_DC_HPD_CONTROL
101 #define mmHPD_DC_HPD_CONTROL 0x189A
102 #define mmHPD0_DC_HPD_CONTROL 0x189A
103 #define mmHPD1_DC_HPD_CONTROL 0x18A2
104 #define mmHPD2_DC_HPD_CONTROL 0x18AA
105 #define mmHPD3_DC_HPD_CONTROL 0x18B2
106 #define mmHPD4_DC_HPD_CONTROL 0x18BA
107 #define mmHPD5_DC_HPD_CONTROL 0x18C2
108 #endif
109
110 #define DCE11_DIG_FE_CNTL 0x4a00
111 #define DCE11_DIG_BE_CNTL 0x4a47
112 #define DCE11_DP_SEC 0x4ac3
113
114 static const struct dce110_timing_generator_offsets dce60_tg_offsets[] = {
115 {
116 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
117 .dcp = (mmGRPH_CONTROL - mmGRPH_CONTROL),
118 .dmif = (mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL3
119 - mmDPG_PIPE_ARBITRATION_CONTROL3),
120 },
121 {
122 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
123 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
124 .dmif = (mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL3
125 - mmDPG_PIPE_ARBITRATION_CONTROL3),
126 },
127 {
128 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
129 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
130 .dmif = (mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL3
131 - mmDPG_PIPE_ARBITRATION_CONTROL3),
132 },
133 {
134 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
135 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
136 .dmif = (mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL3
137 - mmDPG_PIPE_ARBITRATION_CONTROL3),
138 },
139 {
140 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
141 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
142 .dmif = (mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL3
143 - mmDPG_PIPE_ARBITRATION_CONTROL3),
144 },
145 {
146 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
147 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
148 .dmif = (mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL3
149 - mmDPG_PIPE_ARBITRATION_CONTROL3),
150 }
151 };
152
153 /* set register offset */
154 #define SR(reg_name)\
155 .reg_name = mm ## reg_name
156
157 /* set register offset with instance */
158 #define SRI(reg_name, block, id)\
159 .reg_name = mm ## block ## id ## _ ## reg_name
160
161 #define ipp_regs(id)\
162 [id] = {\
163 IPP_COMMON_REG_LIST_DCE_BASE(id)\
164 }
165
166 static const struct dce_ipp_registers ipp_regs[] = {
167 ipp_regs(0),
168 ipp_regs(1),
169 ipp_regs(2),
170 ipp_regs(3),
171 ipp_regs(4),
172 ipp_regs(5)
173 };
174
175 static const struct dce_ipp_shift ipp_shift = {
176 IPP_DCE60_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
177 };
178
179 static const struct dce_ipp_mask ipp_mask = {
180 IPP_DCE60_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
181 };
182
183 #define transform_regs(id)\
184 [id] = {\
185 XFM_COMMON_REG_LIST_DCE60(id)\
186 }
187
188 static const struct dce_transform_registers xfm_regs[] = {
189 transform_regs(0),
190 transform_regs(1),
191 transform_regs(2),
192 transform_regs(3),
193 transform_regs(4),
194 transform_regs(5)
195 };
196
197 static const struct dce_transform_shift xfm_shift = {
198 XFM_COMMON_MASK_SH_LIST_DCE60(__SHIFT)
199 };
200
201 static const struct dce_transform_mask xfm_mask = {
202 XFM_COMMON_MASK_SH_LIST_DCE60(_MASK)
203 };
204
205 #define aux_regs(id)\
206 [id] = {\
207 AUX_REG_LIST(id)\
208 }
209
210 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
211 aux_regs(0),
212 aux_regs(1),
213 aux_regs(2),
214 aux_regs(3),
215 aux_regs(4),
216 aux_regs(5)
217 };
218
219 #define hpd_regs(id)\
220 [id] = {\
221 HPD_REG_LIST(id)\
222 }
223
224 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
225 hpd_regs(0),
226 hpd_regs(1),
227 hpd_regs(2),
228 hpd_regs(3),
229 hpd_regs(4),
230 hpd_regs(5)
231 };
232
233 #define link_regs(id)\
234 [id] = {\
235 LE_DCE60_REG_LIST(id)\
236 }
237
238 static const struct dce110_link_enc_registers link_enc_regs[] = {
239 link_regs(0),
240 link_regs(1),
241 link_regs(2),
242 link_regs(3),
243 link_regs(4),
244 link_regs(5),
245 {0},
246 {0}
247 };
248
249 #define stream_enc_regs(id)\
250 [id] = {\
251 SE_COMMON_REG_LIST_DCE_BASE(id),\
252 .AFMT_CNTL = 0,\
253 }
254
255 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
256 stream_enc_regs(0),
257 stream_enc_regs(1),
258 stream_enc_regs(2),
259 stream_enc_regs(3),
260 stream_enc_regs(4),
261 stream_enc_regs(5),
262 {0},
263 {SR(DAC_SOURCE_SELECT),} /* DACA */
264 };
265
266 static const struct dce_stream_encoder_shift se_shift = {
267 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT)
268 };
269
270 static const struct dce_stream_encoder_mask se_mask = {
271 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
272 };
273
274 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
275 { DCE_PANEL_CNTL_REG_LIST() }
276 };
277
278 static const struct dce_panel_cntl_shift panel_cntl_shift = {
279 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
280 };
281
282 static const struct dce_panel_cntl_mask panel_cntl_mask = {
283 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
284 };
285
286 #define opp_regs(id)\
287 [id] = {\
288 OPP_DCE_60_REG_LIST(id),\
289 }
290
291 static const struct dce_opp_registers opp_regs[] = {
292 opp_regs(0),
293 opp_regs(1),
294 opp_regs(2),
295 opp_regs(3),
296 opp_regs(4),
297 opp_regs(5)
298 };
299
300 static const struct dce_opp_shift opp_shift = {
301 OPP_COMMON_MASK_SH_LIST_DCE_60(__SHIFT)
302 };
303
304 static const struct dce_opp_mask opp_mask = {
305 OPP_COMMON_MASK_SH_LIST_DCE_60(_MASK)
306 };
307
308 static const struct dce110_aux_registers_shift aux_shift = {
309 DCE10_AUX_MASK_SH_LIST(__SHIFT)
310 };
311
312 static const struct dce110_aux_registers_mask aux_mask = {
313 DCE10_AUX_MASK_SH_LIST(_MASK)
314 };
315
316 #define aux_engine_regs(id)\
317 [id] = {\
318 AUX_COMMON_REG_LIST(id), \
319 .AUX_RESET_MASK = 0 \
320 }
321
322 static const struct dce110_aux_registers aux_engine_regs[] = {
323 aux_engine_regs(0),
324 aux_engine_regs(1),
325 aux_engine_regs(2),
326 aux_engine_regs(3),
327 aux_engine_regs(4),
328 aux_engine_regs(5)
329 };
330
331 #define audio_regs(id)\
332 [id] = {\
333 AUD_COMMON_REG_LIST(id)\
334 }
335
336 static const struct dce_audio_registers audio_regs[] = {
337 audio_regs(0),
338 audio_regs(1),
339 audio_regs(2),
340 audio_regs(3),
341 audio_regs(4),
342 audio_regs(5),
343 };
344
345 static const struct dce_audio_shift audio_shift = {
346 AUD_DCE60_MASK_SH_LIST(__SHIFT)
347 };
348
349 static const struct dce_audio_mask audio_mask = {
350 AUD_DCE60_MASK_SH_LIST(_MASK)
351 };
352
353 #define clk_src_regs(id)\
354 [id] = {\
355 CS_COMMON_REG_LIST_DCE_80(id),\
356 }
357
358
359 static const struct dce110_clk_src_regs clk_src_regs[] = {
360 clk_src_regs(0),
361 clk_src_regs(1),
362 clk_src_regs(2)
363 };
364
365 static const struct dce110_clk_src_shift cs_shift = {
366 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
367 };
368
369 static const struct dce110_clk_src_mask cs_mask = {
370 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
371 };
372
373 static const struct bios_registers bios_regs = {
374 .BIOS_SCRATCH_0 = mmBIOS_SCRATCH_0,
375 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
376 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
377 };
378
379 static const struct resource_caps res_cap = {
380 .num_timing_generator = 6,
381 .num_audio = 6,
382 .num_analog_stream_encoder = 1,
383 .num_stream_encoder = 6,
384 .num_pll = 3,
385 .num_ddc = 6,
386 };
387
388 static const struct resource_caps res_cap_61 = {
389 .num_timing_generator = 4,
390 .num_audio = 6,
391 .num_stream_encoder = 6,
392 .num_analog_stream_encoder = 1,
393 .num_pll = 3,
394 .num_ddc = 6,
395 };
396
397 static const struct resource_caps res_cap_64 = {
398 .num_timing_generator = 2,
399 .num_audio = 2,
400 .num_analog_stream_encoder = 1,
401 .num_stream_encoder = 2,
402 .num_pll = 3,
403 .num_ddc = 2,
404 };
405
406 static const struct dc_plane_cap plane_cap = {
407 .type = DC_PLANE_TYPE_DCE_RGB,
408
409 .pixel_format_support = {
410 .argb8888 = true,
411 .nv12 = false,
412 .fp16 = false
413 },
414
415 .max_upscale_factor = {
416 .argb8888 = 1,
417 .nv12 = 1,
418 .fp16 = 1
419 },
420
421 .max_downscale_factor = {
422 .argb8888 = 1,
423 .nv12 = 1,
424 .fp16 = 1
425 }
426 };
427
428 static const struct dce_dmcu_registers dmcu_regs = {
429 DMCU_DCE60_REG_LIST()
430 };
431
432 static const struct dce_dmcu_shift dmcu_shift = {
433 DMCU_MASK_SH_LIST_DCE60(__SHIFT)
434 };
435
436 static const struct dce_dmcu_mask dmcu_mask = {
437 DMCU_MASK_SH_LIST_DCE60(_MASK)
438 };
439 static const struct dce_abm_registers abm_regs = {
440 ABM_DCE110_COMMON_REG_LIST()
441 };
442
443 static const struct dce_abm_shift abm_shift = {
444 ABM_MASK_SH_LIST_DCE110(__SHIFT)
445 };
446
447 static const struct dce_abm_mask abm_mask = {
448 ABM_MASK_SH_LIST_DCE110(_MASK)
449 };
450
451 static const struct dc_debug_options debug_defaults = { 0 };
452
453 static const struct dc_check_config config_defaults = {
454 .enable_legacy_fast_update = true,
455 };
456
457 #define CTX ctx
458 #define REG(reg) mm ## reg
459
460 #ifndef mmCC_DC_HDMI_STRAPS
461 #define mmCC_DC_HDMI_STRAPS 0x1918
462 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
463 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
464 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
465 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
466 #endif
467
map_transmitter_id_to_phy_instance(enum transmitter transmitter)468 static int map_transmitter_id_to_phy_instance(
469 enum transmitter transmitter)
470 {
471 switch (transmitter) {
472 case TRANSMITTER_UNIPHY_A:
473 return 0;
474 case TRANSMITTER_UNIPHY_B:
475 return 1;
476 case TRANSMITTER_UNIPHY_C:
477 return 2;
478 case TRANSMITTER_UNIPHY_D:
479 return 3;
480 case TRANSMITTER_UNIPHY_E:
481 return 4;
482 case TRANSMITTER_UNIPHY_F:
483 return 5;
484 case TRANSMITTER_UNIPHY_G:
485 return 6;
486 default:
487 ASSERT(0);
488 return 0;
489 }
490 }
491
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)492 static void read_dce_straps(
493 struct dc_context *ctx,
494 struct resource_straps *straps)
495 {
496 REG_GET_2(CC_DC_HDMI_STRAPS,
497 HDMI_DISABLE, &straps->hdmi_disable,
498 AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
499
500 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
501 }
502
create_audio(struct dc_context * ctx,unsigned int inst)503 static struct audio *create_audio(
504 struct dc_context *ctx, unsigned int inst)
505 {
506 return dce_audio_create(ctx, inst,
507 &audio_regs[inst], &audio_shift, &audio_mask);
508 }
509
dce60_timing_generator_create(struct dc_context * ctx,uint32_t instance,const struct dce110_timing_generator_offsets * offsets)510 static struct timing_generator *dce60_timing_generator_create(
511 struct dc_context *ctx,
512 uint32_t instance,
513 const struct dce110_timing_generator_offsets *offsets)
514 {
515 struct dce110_timing_generator *tg110 =
516 kzalloc_obj(struct dce110_timing_generator);
517
518 if (!tg110)
519 return NULL;
520
521 dce60_timing_generator_construct(tg110, ctx, instance, offsets);
522 return &tg110->base;
523 }
524
dce60_opp_create(struct dc_context * ctx,uint32_t inst)525 static struct output_pixel_processor *dce60_opp_create(
526 struct dc_context *ctx,
527 uint32_t inst)
528 {
529 struct dce110_opp *opp =
530 kzalloc_obj(struct dce110_opp);
531
532 if (!opp)
533 return NULL;
534
535 dce60_opp_construct(opp,
536 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
537 return &opp->base;
538 }
539
dce60_aux_engine_create(struct dc_context * ctx,uint32_t inst)540 static struct dce_aux *dce60_aux_engine_create(
541 struct dc_context *ctx,
542 uint32_t inst)
543 {
544 struct aux_engine_dce110 *aux_engine =
545 kzalloc_obj(struct aux_engine_dce110);
546
547 if (!aux_engine)
548 return NULL;
549
550 dce110_aux_engine_construct(aux_engine, ctx, inst,
551 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
552 &aux_engine_regs[inst],
553 &aux_mask,
554 &aux_shift,
555 ctx->dc->caps.extended_aux_timeout_support);
556
557 return &aux_engine->base;
558 }
559 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
560
561 static const struct dce_i2c_registers i2c_hw_regs[] = {
562 i2c_inst_regs(1),
563 i2c_inst_regs(2),
564 i2c_inst_regs(3),
565 i2c_inst_regs(4),
566 i2c_inst_regs(5),
567 i2c_inst_regs(6),
568 };
569
570 static const struct dce_i2c_shift i2c_shifts = {
571 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
572 };
573
574 static const struct dce_i2c_mask i2c_masks = {
575 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
576 };
577
dce60_i2c_hw_create(struct dc_context * ctx,uint32_t inst)578 static struct dce_i2c_hw *dce60_i2c_hw_create(
579 struct dc_context *ctx,
580 uint32_t inst)
581 {
582 struct dce_i2c_hw *dce_i2c_hw =
583 kzalloc_obj(struct dce_i2c_hw);
584
585 if (!dce_i2c_hw)
586 return NULL;
587
588 dce_i2c_hw_construct(dce_i2c_hw, ctx, inst,
589 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
590
591 return dce_i2c_hw;
592 }
593
dce60_i2c_sw_create(struct dc_context * ctx)594 static struct dce_i2c_sw *dce60_i2c_sw_create(
595 struct dc_context *ctx)
596 {
597 struct dce_i2c_sw *dce_i2c_sw =
598 kzalloc_obj(struct dce_i2c_sw);
599
600 if (!dce_i2c_sw)
601 return NULL;
602
603 dce_i2c_sw_construct(dce_i2c_sw, ctx);
604
605 return dce_i2c_sw;
606 }
dce60_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)607 static struct stream_encoder *dce60_stream_encoder_create(
608 enum engine_id eng_id,
609 struct dc_context *ctx)
610 {
611 struct dce110_stream_encoder *enc110 =
612 kzalloc_obj(struct dce110_stream_encoder);
613
614 if (!enc110)
615 return NULL;
616
617 if (eng_id == ENGINE_ID_DACA || eng_id == ENGINE_ID_DACB) {
618 dce110_analog_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
619 &stream_enc_regs[eng_id], &se_shift, &se_mask);
620 return &enc110->base;
621 }
622
623 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
624 &stream_enc_regs[eng_id],
625 &se_shift, &se_mask);
626 return &enc110->base;
627 }
628
629 #define SRII(reg_name, block, id)\
630 .reg_name[id] = mm ## block ## id ## _ ## reg_name
631
632 static const struct dce_hwseq_registers hwseq_reg = {
633 HWSEQ_DCE6_REG_LIST()
634 };
635
636 static const struct dce_hwseq_shift hwseq_shift = {
637 HWSEQ_DCE6_MASK_SH_LIST(__SHIFT)
638 };
639
640 static const struct dce_hwseq_mask hwseq_mask = {
641 HWSEQ_DCE6_MASK_SH_LIST(_MASK)
642 };
643
dce60_hwseq_create(struct dc_context * ctx)644 static struct dce_hwseq *dce60_hwseq_create(
645 struct dc_context *ctx)
646 {
647 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);
648
649 if (hws) {
650 hws->ctx = ctx;
651 hws->regs = &hwseq_reg;
652 hws->shifts = &hwseq_shift;
653 hws->masks = &hwseq_mask;
654 }
655 return hws;
656 }
657
658 static const struct resource_create_funcs res_create_funcs = {
659 .read_dce_straps = read_dce_straps,
660 .create_audio = create_audio,
661 .create_stream_encoder = dce60_stream_encoder_create,
662 .create_hwseq = dce60_hwseq_create,
663 };
664
665 #define mi_inst_regs(id) { \
666 MI_DCE6_REG_LIST(id), \
667 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
668 }
669 static const struct dce_mem_input_registers mi_regs[] = {
670 mi_inst_regs(0),
671 mi_inst_regs(1),
672 mi_inst_regs(2),
673 mi_inst_regs(3),
674 mi_inst_regs(4),
675 mi_inst_regs(5),
676 };
677
678 static const struct dce_mem_input_shift mi_shifts = {
679 MI_DCE6_MASK_SH_LIST(__SHIFT),
680 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
681 };
682
683 static const struct dce_mem_input_mask mi_masks = {
684 MI_DCE6_MASK_SH_LIST(_MASK),
685 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
686 };
687
dce60_mem_input_create(struct dc_context * ctx,uint32_t inst)688 static struct mem_input *dce60_mem_input_create(
689 struct dc_context *ctx,
690 uint32_t inst)
691 {
692 struct dce_mem_input *dce_mi = kzalloc_obj(struct dce_mem_input);
693
694 if (!dce_mi) {
695 BREAK_TO_DEBUGGER();
696 return NULL;
697 }
698
699 dce60_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
700 dce_mi->wa.single_head_rdreq_dmif_limit = 2;
701 return &dce_mi->base;
702 }
703
dce60_transform_destroy(struct transform ** xfm)704 static void dce60_transform_destroy(struct transform **xfm)
705 {
706 kfree(TO_DCE_TRANSFORM(*xfm));
707 *xfm = NULL;
708 }
709
dce60_transform_create(struct dc_context * ctx,uint32_t inst)710 static struct transform *dce60_transform_create(
711 struct dc_context *ctx,
712 uint32_t inst)
713 {
714 struct dce_transform *transform =
715 kzalloc_obj(struct dce_transform);
716
717 if (!transform)
718 return NULL;
719
720 dce60_transform_construct(transform, ctx, inst,
721 &xfm_regs[inst], &xfm_shift, &xfm_mask);
722 transform->prescaler_on = false;
723 return &transform->base;
724 }
725
726 static const struct encoder_feature_support link_enc_feature = {
727 .max_hdmi_deep_color = COLOR_DEPTH_121212,
728 .max_hdmi_pixel_clock = 297000,
729 .flags.bits.IS_HBR2_CAPABLE = true,
730 .flags.bits.IS_TPS3_CAPABLE = true
731 };
732
dce60_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)733 static struct link_encoder *dce60_link_encoder_create(
734 struct dc_context *ctx,
735 const struct encoder_init_data *enc_init_data)
736 {
737 struct dce110_link_encoder *enc110 =
738 kzalloc_obj(struct dce110_link_encoder);
739 int link_regs_id;
740
741 if (!enc110)
742 return NULL;
743
744 if (enc_init_data->connector.id == CONNECTOR_ID_VGA &&
745 enc_init_data->analog_engine != ENGINE_ID_UNKNOWN) {
746 dce60_link_encoder_construct(enc110,
747 enc_init_data,
748 &link_enc_feature,
749 &link_enc_regs[ENGINE_ID_DACA],
750 NULL,
751 NULL);
752 return &enc110->base;
753 }
754
755 link_regs_id =
756 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
757
758 dce60_link_encoder_construct(enc110,
759 enc_init_data,
760 &link_enc_feature,
761 &link_enc_regs[link_regs_id],
762 enc_init_data->channel == CHANNEL_ID_UNKNOWN ?
763 NULL : &link_enc_aux_regs[enc_init_data->channel - 1],
764 enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs) ?
765 NULL : &link_enc_hpd_regs[enc_init_data->hpd_source]);
766 return &enc110->base;
767 }
768
dce60_panel_cntl_create(const struct panel_cntl_init_data * init_data)769 static struct panel_cntl *dce60_panel_cntl_create(const struct panel_cntl_init_data *init_data)
770 {
771 struct dce_panel_cntl *panel_cntl =
772 kzalloc_obj(struct dce_panel_cntl);
773
774 if (!panel_cntl)
775 return NULL;
776
777 dce_panel_cntl_construct(panel_cntl,
778 init_data,
779 &panel_cntl_regs[init_data->inst],
780 &panel_cntl_shift,
781 &panel_cntl_mask);
782
783 return &panel_cntl->base;
784 }
785
dce60_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)786 static struct clock_source *dce60_clock_source_create(
787 struct dc_context *ctx,
788 struct dc_bios *bios,
789 enum clock_source_id id,
790 const struct dce110_clk_src_regs *regs,
791 bool dp_clk_src)
792 {
793 struct dce110_clk_src *clk_src =
794 kzalloc_obj(struct dce110_clk_src);
795
796 if (!clk_src)
797 return NULL;
798
799 if (dce110_clk_src_construct(clk_src, ctx, bios, id,
800 regs, &cs_shift, &cs_mask)) {
801 clk_src->base.dp_clk_src = dp_clk_src;
802 return &clk_src->base;
803 }
804
805 kfree(clk_src);
806 BREAK_TO_DEBUGGER();
807 return NULL;
808 }
809
dce60_clock_source_destroy(struct clock_source ** clk_src)810 static void dce60_clock_source_destroy(struct clock_source **clk_src)
811 {
812 kfree(TO_DCE110_CLK_SRC(*clk_src));
813 *clk_src = NULL;
814 }
815
dce60_ipp_create(struct dc_context * ctx,uint32_t inst)816 static struct input_pixel_processor *dce60_ipp_create(
817 struct dc_context *ctx, uint32_t inst)
818 {
819 struct dce_ipp *ipp = kzalloc_obj(struct dce_ipp);
820
821 if (!ipp) {
822 BREAK_TO_DEBUGGER();
823 return NULL;
824 }
825
826 dce60_ipp_construct(ipp, ctx, inst,
827 &ipp_regs[inst], &ipp_shift, &ipp_mask);
828 return &ipp->base;
829 }
830
dce60_resource_destruct(struct dce110_resource_pool * pool)831 static void dce60_resource_destruct(struct dce110_resource_pool *pool)
832 {
833 unsigned int i;
834
835 for (i = 0; i < pool->base.pipe_count; i++) {
836 if (pool->base.opps[i] != NULL)
837 dce110_opp_destroy(&pool->base.opps[i]);
838
839 if (pool->base.transforms[i] != NULL)
840 dce60_transform_destroy(&pool->base.transforms[i]);
841
842 if (pool->base.ipps[i] != NULL)
843 dce_ipp_destroy(&pool->base.ipps[i]);
844
845 if (pool->base.mis[i] != NULL) {
846 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
847 pool->base.mis[i] = NULL;
848 }
849
850 if (pool->base.timing_generators[i] != NULL) {
851 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
852 pool->base.timing_generators[i] = NULL;
853 }
854 }
855
856 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
857 if (pool->base.engines[i] != NULL)
858 dce110_engine_destroy(&pool->base.engines[i]);
859 if (pool->base.hw_i2cs[i] != NULL) {
860 kfree(pool->base.hw_i2cs[i]);
861 pool->base.hw_i2cs[i] = NULL;
862 }
863 if (pool->base.sw_i2cs[i] != NULL) {
864 kfree(pool->base.sw_i2cs[i]);
865 pool->base.sw_i2cs[i] = NULL;
866 }
867 }
868
869 for (i = 0; i < pool->base.stream_enc_count; i++) {
870 if (pool->base.stream_enc[i] != NULL)
871 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
872 }
873
874 for (i = 0; i < pool->base.clk_src_count; i++) {
875 if (pool->base.clock_sources[i] != NULL) {
876 dce60_clock_source_destroy(&pool->base.clock_sources[i]);
877 }
878 }
879
880 if (pool->base.abm != NULL)
881 dce_abm_destroy(&pool->base.abm);
882
883 if (pool->base.dmcu != NULL)
884 dce_dmcu_destroy(&pool->base.dmcu);
885
886 if (pool->base.dp_clock_source != NULL)
887 dce60_clock_source_destroy(&pool->base.dp_clock_source);
888
889 for (i = 0; i < pool->base.audio_count; i++) {
890 if (pool->base.audios[i] != NULL) {
891 dce_aud_destroy(&pool->base.audios[i]);
892 }
893 }
894
895 if (pool->base.irqs != NULL) {
896 dal_irq_service_destroy(&pool->base.irqs);
897 }
898 }
899
dce60_destroy_resource_pool(struct resource_pool ** pool)900 static void dce60_destroy_resource_pool(struct resource_pool **pool)
901 {
902 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
903
904 dce60_resource_destruct(dce110_pool);
905 kfree(dce110_pool);
906 *pool = NULL;
907 }
908
909 static const struct resource_funcs dce60_res_pool_funcs = {
910 .destroy = dce60_destroy_resource_pool,
911 .link_enc_create = dce60_link_encoder_create,
912 .panel_cntl_create = dce60_panel_cntl_create,
913 .validate_bandwidth = dce100_validate_bandwidth,
914 .validate_plane = dce100_validate_plane,
915 .add_stream_to_ctx = dce100_add_stream_to_ctx,
916 .validate_global = dce100_validate_global,
917 .find_first_free_match_stream_enc_for_link = dce100_find_first_free_match_stream_enc_for_link
918 };
919
dce60_construct(uint8_t num_virtual_links,struct dc * dc,struct dce110_resource_pool * pool)920 static bool dce60_construct(
921 uint8_t num_virtual_links,
922 struct dc *dc,
923 struct dce110_resource_pool *pool)
924 {
925 unsigned int i;
926 struct dc_context *ctx = dc->ctx;
927 struct dc_bios *bp;
928
929 ctx->dc_bios->regs = &bios_regs;
930
931 pool->base.res_cap = &res_cap;
932 pool->base.funcs = &dce60_res_pool_funcs;
933
934
935 /*************************************************
936 * Resource + asic cap harcoding *
937 *************************************************/
938 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
939 pool->base.pipe_count = res_cap.num_timing_generator;
940 pool->base.timing_generator_count = res_cap.num_timing_generator;
941 dc->caps.max_downscale_ratio = 200;
942 dc->caps.i2c_speed_in_khz = 40;
943 dc->caps.max_cursor_size = 64;
944 dc->caps.dual_link_dvi = true;
945 dc->caps.extended_aux_timeout_support = false;
946 dc->debug = debug_defaults;
947 dc->check_config = config_defaults;
948
949 /*************************************************
950 * Create resources *
951 *************************************************/
952
953 bp = ctx->dc_bios;
954
955 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
956 pool->base.dp_clock_source =
957 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
958
959 /* DCE 6.0 and 6.4: PLL0 can only be used with DP. Don't initialize it here. */
960 pool->base.clock_sources[0] =
961 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
962 pool->base.clock_sources[1] =
963 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
964 pool->base.clk_src_count = 2;
965
966 } else {
967 pool->base.dp_clock_source =
968 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
969
970 pool->base.clock_sources[0] =
971 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
972 pool->base.clock_sources[1] =
973 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
974 pool->base.clk_src_count = 2;
975 }
976
977 if (pool->base.dp_clock_source == NULL) {
978 dm_error("DC: failed to create dp clock source!\n");
979 BREAK_TO_DEBUGGER();
980 goto res_create_fail;
981 }
982
983 for (i = 0; i < pool->base.clk_src_count; i++) {
984 if (pool->base.clock_sources[i] == NULL) {
985 dm_error("DC: failed to create clock sources!\n");
986 BREAK_TO_DEBUGGER();
987 goto res_create_fail;
988 }
989 }
990
991 pool->base.dmcu = dce_dmcu_create(ctx,
992 &dmcu_regs,
993 &dmcu_shift,
994 &dmcu_mask);
995 if (pool->base.dmcu == NULL) {
996 dm_error("DC: failed to create dmcu!\n");
997 BREAK_TO_DEBUGGER();
998 goto res_create_fail;
999 }
1000
1001 pool->base.abm = dce_abm_create(ctx,
1002 &abm_regs,
1003 &abm_shift,
1004 &abm_mask);
1005 if (pool->base.abm == NULL) {
1006 dm_error("DC: failed to create abm!\n");
1007 BREAK_TO_DEBUGGER();
1008 goto res_create_fail;
1009 }
1010
1011 {
1012 struct irq_service_init_data init_data;
1013 init_data.ctx = dc->ctx;
1014 pool->base.irqs = dal_irq_service_dce60_create(&init_data);
1015 if (!pool->base.irqs)
1016 goto res_create_fail;
1017 }
1018
1019 for (i = 0; i < pool->base.pipe_count; i++) {
1020 pool->base.timing_generators[i] = dce60_timing_generator_create(
1021 ctx, i, &dce60_tg_offsets[i]);
1022 if (pool->base.timing_generators[i] == NULL) {
1023 BREAK_TO_DEBUGGER();
1024 dm_error("DC: failed to create tg!\n");
1025 goto res_create_fail;
1026 }
1027
1028 pool->base.mis[i] = dce60_mem_input_create(ctx, i);
1029 if (pool->base.mis[i] == NULL) {
1030 BREAK_TO_DEBUGGER();
1031 dm_error("DC: failed to create memory input!\n");
1032 goto res_create_fail;
1033 }
1034
1035 pool->base.ipps[i] = dce60_ipp_create(ctx, i);
1036 if (pool->base.ipps[i] == NULL) {
1037 BREAK_TO_DEBUGGER();
1038 dm_error("DC: failed to create input pixel processor!\n");
1039 goto res_create_fail;
1040 }
1041
1042 pool->base.transforms[i] = dce60_transform_create(ctx, i);
1043 if (pool->base.transforms[i] == NULL) {
1044 BREAK_TO_DEBUGGER();
1045 dm_error("DC: failed to create transform!\n");
1046 goto res_create_fail;
1047 }
1048
1049 pool->base.opps[i] = dce60_opp_create(ctx, i);
1050 if (pool->base.opps[i] == NULL) {
1051 BREAK_TO_DEBUGGER();
1052 dm_error("DC: failed to create output pixel processor!\n");
1053 goto res_create_fail;
1054 }
1055 }
1056
1057 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1058 pool->base.engines[i] = dce60_aux_engine_create(ctx, i);
1059 if (pool->base.engines[i] == NULL) {
1060 BREAK_TO_DEBUGGER();
1061 dm_error(
1062 "DC:failed to create aux engine!!\n");
1063 goto res_create_fail;
1064 }
1065 pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i);
1066 if (pool->base.hw_i2cs[i] == NULL) {
1067 BREAK_TO_DEBUGGER();
1068 dm_error(
1069 "DC:failed to create i2c engine!!\n");
1070 goto res_create_fail;
1071 }
1072 pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx);
1073 if (pool->base.sw_i2cs[i] == NULL) {
1074 BREAK_TO_DEBUGGER();
1075 dm_error(
1076 "DC:failed to create sw i2c!!\n");
1077 goto res_create_fail;
1078 }
1079 }
1080
1081 dc->caps.max_planes = pool->base.pipe_count;
1082
1083 for (i = 0; i < dc->caps.max_planes; ++i)
1084 dc->caps.planes[i] = plane_cap;
1085
1086 dc->caps.disable_dp_clk_share = true;
1087
1088 if (!resource_construct(num_virtual_links, dc, &pool->base,
1089 &res_create_funcs))
1090 goto res_create_fail;
1091
1092 /* Create hardware sequencer */
1093 dce60_hw_sequencer_construct(dc);
1094
1095 return true;
1096
1097 res_create_fail:
1098 dce60_resource_destruct(pool);
1099 return false;
1100 }
1101
dce60_create_resource_pool(uint8_t num_virtual_links,struct dc * dc)1102 struct resource_pool *dce60_create_resource_pool(
1103 uint8_t num_virtual_links,
1104 struct dc *dc)
1105 {
1106 struct dce110_resource_pool *pool =
1107 kzalloc_obj(struct dce110_resource_pool);
1108
1109 if (!pool)
1110 return NULL;
1111
1112 if (dce60_construct(num_virtual_links, dc, pool))
1113 return &pool->base;
1114
1115 kfree(pool);
1116 BREAK_TO_DEBUGGER();
1117 return NULL;
1118 }
1119
dce61_construct(uint8_t num_virtual_links,struct dc * dc,struct dce110_resource_pool * pool)1120 static bool dce61_construct(
1121 uint8_t num_virtual_links,
1122 struct dc *dc,
1123 struct dce110_resource_pool *pool)
1124 {
1125 unsigned int i;
1126 struct dc_context *ctx = dc->ctx;
1127 struct dc_bios *bp;
1128
1129 ctx->dc_bios->regs = &bios_regs;
1130
1131 pool->base.res_cap = &res_cap_61;
1132 pool->base.funcs = &dce60_res_pool_funcs;
1133
1134
1135 /*************************************************
1136 * Resource + asic cap harcoding *
1137 *************************************************/
1138 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1139 pool->base.pipe_count = res_cap_61.num_timing_generator;
1140 pool->base.timing_generator_count = res_cap_61.num_timing_generator;
1141 dc->caps.max_downscale_ratio = 200;
1142 dc->caps.i2c_speed_in_khz = 40;
1143 dc->caps.max_cursor_size = 64;
1144 dc->caps.is_apu = true;
1145 dc->debug = debug_defaults;
1146 dc->check_config = config_defaults;
1147
1148 /*************************************************
1149 * Create resources *
1150 *************************************************/
1151
1152 bp = ctx->dc_bios;
1153
1154 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
1155 pool->base.dp_clock_source =
1156 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1157
1158 pool->base.clock_sources[0] =
1159 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
1160 pool->base.clock_sources[1] =
1161 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1162 pool->base.clock_sources[2] =
1163 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1164 pool->base.clk_src_count = 3;
1165
1166 } else {
1167 pool->base.dp_clock_source =
1168 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
1169
1170 pool->base.clock_sources[0] =
1171 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1172 pool->base.clock_sources[1] =
1173 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1174 pool->base.clk_src_count = 2;
1175 }
1176
1177 if (pool->base.dp_clock_source == NULL) {
1178 dm_error("DC: failed to create dp clock source!\n");
1179 BREAK_TO_DEBUGGER();
1180 goto res_create_fail;
1181 }
1182
1183 for (i = 0; i < pool->base.clk_src_count; i++) {
1184 if (pool->base.clock_sources[i] == NULL) {
1185 dm_error("DC: failed to create clock sources!\n");
1186 BREAK_TO_DEBUGGER();
1187 goto res_create_fail;
1188 }
1189 }
1190
1191 pool->base.dmcu = dce_dmcu_create(ctx,
1192 &dmcu_regs,
1193 &dmcu_shift,
1194 &dmcu_mask);
1195 if (pool->base.dmcu == NULL) {
1196 dm_error("DC: failed to create dmcu!\n");
1197 BREAK_TO_DEBUGGER();
1198 goto res_create_fail;
1199 }
1200
1201 pool->base.abm = dce_abm_create(ctx,
1202 &abm_regs,
1203 &abm_shift,
1204 &abm_mask);
1205 if (pool->base.abm == NULL) {
1206 dm_error("DC: failed to create abm!\n");
1207 BREAK_TO_DEBUGGER();
1208 goto res_create_fail;
1209 }
1210
1211 {
1212 struct irq_service_init_data init_data;
1213 init_data.ctx = dc->ctx;
1214 pool->base.irqs = dal_irq_service_dce60_create(&init_data);
1215 if (!pool->base.irqs)
1216 goto res_create_fail;
1217 }
1218
1219 for (i = 0; i < pool->base.pipe_count; i++) {
1220 pool->base.timing_generators[i] = dce60_timing_generator_create(
1221 ctx, i, &dce60_tg_offsets[i]);
1222 if (pool->base.timing_generators[i] == NULL) {
1223 BREAK_TO_DEBUGGER();
1224 dm_error("DC: failed to create tg!\n");
1225 goto res_create_fail;
1226 }
1227
1228 pool->base.mis[i] = dce60_mem_input_create(ctx, i);
1229 if (pool->base.mis[i] == NULL) {
1230 BREAK_TO_DEBUGGER();
1231 dm_error("DC: failed to create memory input!\n");
1232 goto res_create_fail;
1233 }
1234
1235 pool->base.ipps[i] = dce60_ipp_create(ctx, i);
1236 if (pool->base.ipps[i] == NULL) {
1237 BREAK_TO_DEBUGGER();
1238 dm_error("DC: failed to create input pixel processor!\n");
1239 goto res_create_fail;
1240 }
1241
1242 pool->base.transforms[i] = dce60_transform_create(ctx, i);
1243 if (pool->base.transforms[i] == NULL) {
1244 BREAK_TO_DEBUGGER();
1245 dm_error("DC: failed to create transform!\n");
1246 goto res_create_fail;
1247 }
1248
1249 pool->base.opps[i] = dce60_opp_create(ctx, i);
1250 if (pool->base.opps[i] == NULL) {
1251 BREAK_TO_DEBUGGER();
1252 dm_error("DC: failed to create output pixel processor!\n");
1253 goto res_create_fail;
1254 }
1255 }
1256
1257 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1258 pool->base.engines[i] = dce60_aux_engine_create(ctx, i);
1259 if (pool->base.engines[i] == NULL) {
1260 BREAK_TO_DEBUGGER();
1261 dm_error(
1262 "DC:failed to create aux engine!!\n");
1263 goto res_create_fail;
1264 }
1265 pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i);
1266 if (pool->base.hw_i2cs[i] == NULL) {
1267 BREAK_TO_DEBUGGER();
1268 dm_error(
1269 "DC:failed to create i2c engine!!\n");
1270 goto res_create_fail;
1271 }
1272 pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx);
1273 if (pool->base.sw_i2cs[i] == NULL) {
1274 BREAK_TO_DEBUGGER();
1275 dm_error(
1276 "DC:failed to create sw i2c!!\n");
1277 goto res_create_fail;
1278 }
1279 }
1280
1281 dc->caps.max_planes = pool->base.pipe_count;
1282
1283 for (i = 0; i < dc->caps.max_planes; ++i)
1284 dc->caps.planes[i] = plane_cap;
1285
1286 dc->caps.disable_dp_clk_share = true;
1287
1288 if (!resource_construct(num_virtual_links, dc, &pool->base,
1289 &res_create_funcs))
1290 goto res_create_fail;
1291
1292 /* Create hardware sequencer */
1293 dce60_hw_sequencer_construct(dc);
1294
1295 return true;
1296
1297 res_create_fail:
1298 dce60_resource_destruct(pool);
1299 return false;
1300 }
1301
dce61_create_resource_pool(uint8_t num_virtual_links,struct dc * dc)1302 struct resource_pool *dce61_create_resource_pool(
1303 uint8_t num_virtual_links,
1304 struct dc *dc)
1305 {
1306 struct dce110_resource_pool *pool =
1307 kzalloc_obj(struct dce110_resource_pool);
1308
1309 if (!pool)
1310 return NULL;
1311
1312 if (dce61_construct(num_virtual_links, dc, pool))
1313 return &pool->base;
1314
1315 kfree(pool);
1316 BREAK_TO_DEBUGGER();
1317 return NULL;
1318 }
1319
dce64_construct(uint8_t num_virtual_links,struct dc * dc,struct dce110_resource_pool * pool)1320 static bool dce64_construct(
1321 uint8_t num_virtual_links,
1322 struct dc *dc,
1323 struct dce110_resource_pool *pool)
1324 {
1325 unsigned int i;
1326 struct dc_context *ctx = dc->ctx;
1327 struct dc_bios *bp;
1328
1329 ctx->dc_bios->regs = &bios_regs;
1330
1331 pool->base.res_cap = &res_cap_64;
1332 pool->base.funcs = &dce60_res_pool_funcs;
1333
1334
1335 /*************************************************
1336 * Resource + asic cap harcoding *
1337 *************************************************/
1338 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1339 pool->base.pipe_count = res_cap_64.num_timing_generator;
1340 pool->base.timing_generator_count = res_cap_64.num_timing_generator;
1341 dc->caps.max_downscale_ratio = 200;
1342 dc->caps.i2c_speed_in_khz = 40;
1343 dc->caps.max_cursor_size = 64;
1344 dc->debug = debug_defaults;
1345 dc->check_config = config_defaults;
1346
1347 /*************************************************
1348 * Create resources *
1349 *************************************************/
1350
1351 bp = ctx->dc_bios;
1352
1353 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
1354 pool->base.dp_clock_source =
1355 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1356
1357 /* DCE 6.0 and 6.4: PLL0 can only be used with DP. Don't initialize it here. */
1358 pool->base.clock_sources[0] =
1359 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1360 pool->base.clock_sources[1] =
1361 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1362 pool->base.clk_src_count = 2;
1363
1364 } else {
1365 pool->base.dp_clock_source =
1366 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
1367
1368 pool->base.clock_sources[0] =
1369 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1370 pool->base.clock_sources[1] =
1371 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1372 pool->base.clk_src_count = 2;
1373 }
1374
1375 if (pool->base.dp_clock_source == NULL) {
1376 dm_error("DC: failed to create dp clock source!\n");
1377 BREAK_TO_DEBUGGER();
1378 goto res_create_fail;
1379 }
1380
1381 for (i = 0; i < pool->base.clk_src_count; i++) {
1382 if (pool->base.clock_sources[i] == NULL) {
1383 dm_error("DC: failed to create clock sources!\n");
1384 BREAK_TO_DEBUGGER();
1385 goto res_create_fail;
1386 }
1387 }
1388
1389 pool->base.dmcu = dce_dmcu_create(ctx,
1390 &dmcu_regs,
1391 &dmcu_shift,
1392 &dmcu_mask);
1393 if (pool->base.dmcu == NULL) {
1394 dm_error("DC: failed to create dmcu!\n");
1395 BREAK_TO_DEBUGGER();
1396 goto res_create_fail;
1397 }
1398
1399 pool->base.abm = dce_abm_create(ctx,
1400 &abm_regs,
1401 &abm_shift,
1402 &abm_mask);
1403 if (pool->base.abm == NULL) {
1404 dm_error("DC: failed to create abm!\n");
1405 BREAK_TO_DEBUGGER();
1406 goto res_create_fail;
1407 }
1408
1409 {
1410 struct irq_service_init_data init_data;
1411 init_data.ctx = dc->ctx;
1412 pool->base.irqs = dal_irq_service_dce60_create(&init_data);
1413 if (!pool->base.irqs)
1414 goto res_create_fail;
1415 }
1416
1417 for (i = 0; i < pool->base.pipe_count; i++) {
1418 pool->base.timing_generators[i] = dce60_timing_generator_create(
1419 ctx, i, &dce60_tg_offsets[i]);
1420 if (pool->base.timing_generators[i] == NULL) {
1421 BREAK_TO_DEBUGGER();
1422 dm_error("DC: failed to create tg!\n");
1423 goto res_create_fail;
1424 }
1425
1426 pool->base.mis[i] = dce60_mem_input_create(ctx, i);
1427 if (pool->base.mis[i] == NULL) {
1428 BREAK_TO_DEBUGGER();
1429 dm_error("DC: failed to create memory input!\n");
1430 goto res_create_fail;
1431 }
1432
1433 pool->base.ipps[i] = dce60_ipp_create(ctx, i);
1434 if (pool->base.ipps[i] == NULL) {
1435 BREAK_TO_DEBUGGER();
1436 dm_error("DC: failed to create input pixel processor!\n");
1437 goto res_create_fail;
1438 }
1439
1440 pool->base.transforms[i] = dce60_transform_create(ctx, i);
1441 if (pool->base.transforms[i] == NULL) {
1442 BREAK_TO_DEBUGGER();
1443 dm_error("DC: failed to create transform!\n");
1444 goto res_create_fail;
1445 }
1446
1447 pool->base.opps[i] = dce60_opp_create(ctx, i);
1448 if (pool->base.opps[i] == NULL) {
1449 BREAK_TO_DEBUGGER();
1450 dm_error("DC: failed to create output pixel processor!\n");
1451 goto res_create_fail;
1452 }
1453 }
1454
1455 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1456 pool->base.engines[i] = dce60_aux_engine_create(ctx, i);
1457 if (pool->base.engines[i] == NULL) {
1458 BREAK_TO_DEBUGGER();
1459 dm_error(
1460 "DC:failed to create aux engine!!\n");
1461 goto res_create_fail;
1462 }
1463 pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i);
1464 if (pool->base.hw_i2cs[i] == NULL) {
1465 BREAK_TO_DEBUGGER();
1466 dm_error(
1467 "DC:failed to create i2c engine!!\n");
1468 goto res_create_fail;
1469 }
1470 pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx);
1471 if (pool->base.sw_i2cs[i] == NULL) {
1472 BREAK_TO_DEBUGGER();
1473 dm_error(
1474 "DC:failed to create sw i2c!!\n");
1475 goto res_create_fail;
1476 }
1477 }
1478
1479 dc->caps.max_planes = pool->base.pipe_count;
1480
1481 for (i = 0; i < dc->caps.max_planes; ++i)
1482 dc->caps.planes[i] = plane_cap;
1483
1484 dc->caps.disable_dp_clk_share = true;
1485
1486 if (!resource_construct(num_virtual_links, dc, &pool->base,
1487 &res_create_funcs))
1488 goto res_create_fail;
1489
1490 /* Create hardware sequencer */
1491 dce60_hw_sequencer_construct(dc);
1492
1493 return true;
1494
1495 res_create_fail:
1496 dce60_resource_destruct(pool);
1497 return false;
1498 }
1499
dce64_create_resource_pool(uint8_t num_virtual_links,struct dc * dc)1500 struct resource_pool *dce64_create_resource_pool(
1501 uint8_t num_virtual_links,
1502 struct dc *dc)
1503 {
1504 struct dce110_resource_pool *pool =
1505 kzalloc_obj(struct dce110_resource_pool);
1506
1507 if (!pool)
1508 return NULL;
1509
1510 if (dce64_construct(num_virtual_links, dc, pool))
1511 return &pool->base;
1512
1513 kfree(pool);
1514 BREAK_TO_DEBUGGER();
1515 return NULL;
1516 }
1517