1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.cls
3 *
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #include "dm_services.h"
28
29
30 #include "stream_encoder.h"
31 #include "resource.h"
32 #include "include/irq_service_interface.h"
33 #include "dce120_resource.h"
34
35 #include "dce112/dce112_resource.h"
36
37 #include "dce110/dce110_resource.h"
38 #include "dio/virtual/virtual_stream_encoder.h"
39 #include "dce120/dce120_timing_generator.h"
40 #include "irq/dce120/irq_service_dce120.h"
41 #include "dce/dce_opp.h"
42 #include "dce/dce_clock_source.h"
43 #include "dce/dce_ipp.h"
44 #include "dce/dce_mem_input.h"
45 #include "dce/dce_panel_cntl.h"
46
47 #include "dce110/dce110_hwseq.h"
48 #include "dce120/dce120_hwseq.h"
49 #include "dce/dce_transform.h"
50 #include "clk_mgr.h"
51 #include "dce/dce_audio.h"
52 #include "dce/dce_link_encoder.h"
53 #include "dce/dce_stream_encoder.h"
54 #include "dce/dce_hwseq.h"
55 #include "dce/dce_abm.h"
56 #include "dce/dce_dmcu.h"
57 #include "dce/dce_aux.h"
58 #include "dce/dce_i2c.h"
59
60 #include "dce/dce_12_0_offset.h"
61 #include "dce/dce_12_0_sh_mask.h"
62 #include "soc15_hw_ip.h"
63 #include "vega10_ip_offset.h"
64 #include "nbio/nbio_6_1_offset.h"
65 #include "mmhub/mmhub_1_0_offset.h"
66 #include "mmhub/mmhub_1_0_sh_mask.h"
67 #include "reg_helper.h"
68
69 #include "dce100/dce100_resource.h"
70 #include "link_service.h"
71
72 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
73 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f
74 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
75 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f
76 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
77 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f
78 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
79 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f
80 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
81 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f
82 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
83 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f
84 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
85 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f
86 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
87 #endif
88
89 enum dce120_clk_src_array_id {
90 DCE120_CLK_SRC_PLL0,
91 DCE120_CLK_SRC_PLL1,
92 DCE120_CLK_SRC_PLL2,
93 DCE120_CLK_SRC_PLL3,
94 DCE120_CLK_SRC_PLL4,
95 DCE120_CLK_SRC_PLL5,
96
97 DCE120_CLK_SRC_TOTAL
98 };
99
100 static const struct dce110_timing_generator_offsets dce120_tg_offsets[] = {
101 {
102 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
103 },
104 {
105 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
106 },
107 {
108 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
109 },
110 {
111 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
112 },
113 {
114 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
115 },
116 {
117 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
118 }
119 };
120
121 /* begin *********************
122 * macros to expend register list macro defined in HW object header file */
123
124 #define BASE_INNER(seg) \
125 DCE_BASE__INST0_SEG ## seg
126
127 #define NBIO_BASE_INNER(seg) \
128 NBIF_BASE__INST0_SEG ## seg
129
130 #define NBIO_BASE(seg) \
131 NBIO_BASE_INNER(seg)
132
133 /* compile time expand base address. */
134 #define BASE(seg) \
135 BASE_INNER(seg)
136
137 #define SR(reg_name)\
138 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
139 mm ## reg_name
140
141 #define SRI(reg_name, block, id)\
142 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
143 mm ## block ## id ## _ ## reg_name
144
145 /* MMHUB */
146 #define MMHUB_BASE_INNER(seg) \
147 MMHUB_BASE__INST0_SEG ## seg
148
149 #define MMHUB_BASE(seg) \
150 MMHUB_BASE_INNER(seg)
151
152 #define MMHUB_SR(reg_name)\
153 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \
154 mm ## reg_name
155
156 /* macros to expend register list macro defined in HW object header file
157 * end *********************/
158
159
160 static const struct dce_dmcu_registers dmcu_regs = {
161 DMCU_DCE110_COMMON_REG_LIST()
162 };
163
164 static const struct dce_dmcu_shift dmcu_shift = {
165 DMCU_MASK_SH_LIST_DCE110(__SHIFT)
166 };
167
168 static const struct dce_dmcu_mask dmcu_mask = {
169 DMCU_MASK_SH_LIST_DCE110(_MASK)
170 };
171
172 static const struct dce_abm_registers abm_regs = {
173 ABM_DCE110_COMMON_REG_LIST()
174 };
175
176 static const struct dce_abm_shift abm_shift = {
177 ABM_MASK_SH_LIST_DCE110(__SHIFT)
178 };
179
180 static const struct dce_abm_mask abm_mask = {
181 ABM_MASK_SH_LIST_DCE110(_MASK)
182 };
183
184 #define ipp_regs(id)\
185 [id] = {\
186 IPP_DCE110_REG_LIST_DCE_BASE(id)\
187 }
188
189 static const struct dce_ipp_registers ipp_regs[] = {
190 ipp_regs(0),
191 ipp_regs(1),
192 ipp_regs(2),
193 ipp_regs(3),
194 ipp_regs(4),
195 ipp_regs(5)
196 };
197
198 static const struct dce_ipp_shift ipp_shift = {
199 IPP_DCE120_MASK_SH_LIST_SOC_BASE(__SHIFT)
200 };
201
202 static const struct dce_ipp_mask ipp_mask = {
203 IPP_DCE120_MASK_SH_LIST_SOC_BASE(_MASK)
204 };
205
206 #define transform_regs(id)\
207 [id] = {\
208 XFM_COMMON_REG_LIST_DCE110(id)\
209 }
210
211 static const struct dce_transform_registers xfm_regs[] = {
212 transform_regs(0),
213 transform_regs(1),
214 transform_regs(2),
215 transform_regs(3),
216 transform_regs(4),
217 transform_regs(5)
218 };
219
220 static const struct dce_transform_shift xfm_shift = {
221 XFM_COMMON_MASK_SH_LIST_SOC_BASE(__SHIFT)
222 };
223
224 static const struct dce_transform_mask xfm_mask = {
225 XFM_COMMON_MASK_SH_LIST_SOC_BASE(_MASK)
226 };
227
228 #define aux_regs(id)\
229 [id] = {\
230 AUX_REG_LIST(id)\
231 }
232
233 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
234 aux_regs(0),
235 aux_regs(1),
236 aux_regs(2),
237 aux_regs(3),
238 aux_regs(4),
239 aux_regs(5)
240 };
241
242 #define hpd_regs(id)\
243 [id] = {\
244 HPD_REG_LIST(id)\
245 }
246
247 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
248 hpd_regs(0),
249 hpd_regs(1),
250 hpd_regs(2),
251 hpd_regs(3),
252 hpd_regs(4),
253 hpd_regs(5)
254 };
255
256 #define link_regs(id)\
257 [id] = {\
258 LE_DCE120_REG_LIST(id), \
259 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
260 }
261
262 static const struct dce110_link_enc_registers link_enc_regs[] = {
263 link_regs(0),
264 link_regs(1),
265 link_regs(2),
266 link_regs(3),
267 link_regs(4),
268 link_regs(5),
269 link_regs(6),
270 };
271
272
273 #define stream_enc_regs(id)\
274 [id] = {\
275 SE_COMMON_REG_LIST(id),\
276 .TMDS_CNTL = 0,\
277 }
278
279 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
280 stream_enc_regs(0),
281 stream_enc_regs(1),
282 stream_enc_regs(2),
283 stream_enc_regs(3),
284 stream_enc_regs(4),
285 stream_enc_regs(5)
286 };
287
288 static const struct dce_stream_encoder_shift se_shift = {
289 SE_COMMON_MASK_SH_LIST_DCE120(__SHIFT)
290 };
291
292 static const struct dce_stream_encoder_mask se_mask = {
293 SE_COMMON_MASK_SH_LIST_DCE120(_MASK)
294 };
295
296 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
297 { DCE_PANEL_CNTL_REG_LIST() }
298 };
299
300 static const struct dce_panel_cntl_shift panel_cntl_shift = {
301 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
302 };
303
304 static const struct dce_panel_cntl_mask panel_cntl_mask = {
305 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
306 };
307
308 static const struct dce110_aux_registers_shift aux_shift = {
309 DCE12_AUX_MASK_SH_LIST(__SHIFT)
310 };
311
312 static const struct dce110_aux_registers_mask aux_mask = {
313 DCE12_AUX_MASK_SH_LIST(_MASK)
314 };
315
316 #define opp_regs(id)\
317 [id] = {\
318 OPP_DCE_120_REG_LIST(id),\
319 }
320
321 static const struct dce_opp_registers opp_regs[] = {
322 opp_regs(0),
323 opp_regs(1),
324 opp_regs(2),
325 opp_regs(3),
326 opp_regs(4),
327 opp_regs(5)
328 };
329
330 static const struct dce_opp_shift opp_shift = {
331 OPP_COMMON_MASK_SH_LIST_DCE_120(__SHIFT)
332 };
333
334 static const struct dce_opp_mask opp_mask = {
335 OPP_COMMON_MASK_SH_LIST_DCE_120(_MASK)
336 };
337 #define aux_engine_regs(id)\
338 [id] = {\
339 AUX_COMMON_REG_LIST(id), \
340 .AUX_RESET_MASK = 0 \
341 }
342
343 static const struct dce110_aux_registers aux_engine_regs[] = {
344 aux_engine_regs(0),
345 aux_engine_regs(1),
346 aux_engine_regs(2),
347 aux_engine_regs(3),
348 aux_engine_regs(4),
349 aux_engine_regs(5)
350 };
351
352 #define audio_regs(id)\
353 [id] = {\
354 AUD_COMMON_REG_LIST(id)\
355 }
356
357 static const struct dce_audio_registers audio_regs[] = {
358 audio_regs(0),
359 audio_regs(1),
360 audio_regs(2),
361 audio_regs(3),
362 audio_regs(4),
363 audio_regs(5),
364 audio_regs(6),
365 };
366
367 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
368 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
369 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
370 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
371
372 static const struct dce_audio_shift audio_shift = {
373 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
374 };
375
376 static const struct dce_audio_mask audio_mask = {
377 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
378 };
379
map_transmitter_id_to_phy_instance(enum transmitter transmitter)380 static int map_transmitter_id_to_phy_instance(
381 enum transmitter transmitter)
382 {
383 switch (transmitter) {
384 case TRANSMITTER_UNIPHY_A:
385 return 0;
386 case TRANSMITTER_UNIPHY_B:
387 return 1;
388 case TRANSMITTER_UNIPHY_C:
389 return 2;
390 case TRANSMITTER_UNIPHY_D:
391 return 3;
392 case TRANSMITTER_UNIPHY_E:
393 return 4;
394 case TRANSMITTER_UNIPHY_F:
395 return 5;
396 case TRANSMITTER_UNIPHY_G:
397 return 6;
398 default:
399 ASSERT(0);
400 return 0;
401 }
402 }
403
404 #define clk_src_regs(index, id)\
405 [index] = {\
406 CS_COMMON_REG_LIST_DCE_112(id),\
407 }
408
409 static const struct dce110_clk_src_regs clk_src_regs[] = {
410 clk_src_regs(0, A),
411 clk_src_regs(1, B),
412 clk_src_regs(2, C),
413 clk_src_regs(3, D),
414 clk_src_regs(4, E),
415 clk_src_regs(5, F)
416 };
417
418 static const struct dce110_clk_src_shift cs_shift = {
419 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT)
420 };
421
422 static const struct dce110_clk_src_mask cs_mask = {
423 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK)
424 };
425
dce120_opp_create(struct dc_context * ctx,uint32_t inst)426 static struct output_pixel_processor *dce120_opp_create(
427 struct dc_context *ctx,
428 uint32_t inst)
429 {
430 struct dce110_opp *opp =
431 kzalloc_obj(struct dce110_opp);
432
433 if (!opp)
434 return NULL;
435
436 dce110_opp_construct(opp,
437 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
438 return &opp->base;
439 }
dce120_aux_engine_create(struct dc_context * ctx,uint32_t inst)440 static struct dce_aux *dce120_aux_engine_create(
441 struct dc_context *ctx,
442 uint32_t inst)
443 {
444 struct aux_engine_dce110 *aux_engine =
445 kzalloc_obj(struct aux_engine_dce110);
446
447 if (!aux_engine)
448 return NULL;
449
450 dce110_aux_engine_construct(aux_engine, ctx, inst,
451 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
452 &aux_engine_regs[inst],
453 &aux_mask,
454 &aux_shift,
455 ctx->dc->caps.extended_aux_timeout_support);
456
457 return &aux_engine->base;
458 }
459 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
460
461 static const struct dce_i2c_registers i2c_hw_regs[] = {
462 i2c_inst_regs(1),
463 i2c_inst_regs(2),
464 i2c_inst_regs(3),
465 i2c_inst_regs(4),
466 i2c_inst_regs(5),
467 i2c_inst_regs(6),
468 };
469
470 static const struct dce_i2c_shift i2c_shifts = {
471 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
472 };
473
474 static const struct dce_i2c_mask i2c_masks = {
475 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
476 };
477
dce120_i2c_hw_create(struct dc_context * ctx,uint32_t inst)478 static struct dce_i2c_hw *dce120_i2c_hw_create(
479 struct dc_context *ctx,
480 uint32_t inst)
481 {
482 struct dce_i2c_hw *dce_i2c_hw =
483 kzalloc_obj(struct dce_i2c_hw);
484
485 if (!dce_i2c_hw)
486 return NULL;
487
488 dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst,
489 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
490
491 return dce_i2c_hw;
492 }
493 static const struct bios_registers bios_regs = {
494 .BIOS_SCRATCH_0 = mmBIOS_SCRATCH_0 + NBIO_BASE(mmBIOS_SCRATCH_0_BASE_IDX),
495 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3 + NBIO_BASE(mmBIOS_SCRATCH_3_BASE_IDX),
496 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX)
497 };
498
499 static const struct resource_caps res_cap = {
500 .num_timing_generator = 6,
501 .num_audio = 7,
502 .num_stream_encoder = 6,
503 .num_pll = 6,
504 .num_ddc = 6,
505 };
506
507 static const struct dc_plane_cap plane_cap = {
508 .type = DC_PLANE_TYPE_DCE_RGB,
509
510 .pixel_format_support = {
511 .argb8888 = true,
512 .nv12 = false,
513 .fp16 = true
514 },
515
516 .max_upscale_factor = {
517 .argb8888 = 16000,
518 .nv12 = 1,
519 .fp16 = 1
520 },
521
522 .max_downscale_factor = {
523 .argb8888 = 250,
524 .nv12 = 1,
525 .fp16 = 1
526 }
527 };
528
529 static const struct dc_debug_options debug_defaults = {
530 .disable_clock_gate = true,
531 };
532
533 static const struct dc_check_config config_defaults = {
534 .enable_legacy_fast_update = true,
535 };
536
dce120_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)537 static struct clock_source *dce120_clock_source_create(
538 struct dc_context *ctx,
539 struct dc_bios *bios,
540 enum clock_source_id id,
541 const struct dce110_clk_src_regs *regs,
542 bool dp_clk_src)
543 {
544 struct dce110_clk_src *clk_src = kzalloc_obj(*clk_src);
545
546 if (!clk_src)
547 return NULL;
548
549 if (dce112_clk_src_construct(clk_src, ctx, bios, id,
550 regs, &cs_shift, &cs_mask)) {
551 clk_src->base.dp_clk_src = dp_clk_src;
552 return &clk_src->base;
553 }
554
555 kfree(clk_src);
556 BREAK_TO_DEBUGGER();
557 return NULL;
558 }
559
dce120_clock_source_destroy(struct clock_source ** clk_src)560 static void dce120_clock_source_destroy(struct clock_source **clk_src)
561 {
562 kfree(TO_DCE110_CLK_SRC(*clk_src));
563 *clk_src = NULL;
564 }
565
566
dce120_hw_sequencer_create(struct dc * dc)567 static bool dce120_hw_sequencer_create(struct dc *dc)
568 {
569 /* All registers used by dce11.2 match those in dce11 in offset and
570 * structure
571 */
572 dce120_hw_sequencer_construct(dc);
573
574 /*TODO Move to separate file and Override what is needed */
575
576 return true;
577 }
578
dce120_timing_generator_create(struct dc_context * ctx,uint32_t instance,const struct dce110_timing_generator_offsets * offsets)579 static struct timing_generator *dce120_timing_generator_create(
580 struct dc_context *ctx,
581 uint32_t instance,
582 const struct dce110_timing_generator_offsets *offsets)
583 {
584 struct dce110_timing_generator *tg110 =
585 kzalloc_obj(struct dce110_timing_generator);
586
587 if (!tg110)
588 return NULL;
589
590 dce120_timing_generator_construct(tg110, ctx, instance, offsets);
591 return &tg110->base;
592 }
593
dce120_transform_destroy(struct transform ** xfm)594 static void dce120_transform_destroy(struct transform **xfm)
595 {
596 kfree(TO_DCE_TRANSFORM(*xfm));
597 *xfm = NULL;
598 }
599
dce120_resource_destruct(struct dce110_resource_pool * pool)600 static void dce120_resource_destruct(struct dce110_resource_pool *pool)
601 {
602 unsigned int i;
603
604 for (i = 0; i < pool->base.pipe_count; i++) {
605 if (pool->base.opps[i] != NULL)
606 dce110_opp_destroy(&pool->base.opps[i]);
607
608 if (pool->base.transforms[i] != NULL)
609 dce120_transform_destroy(&pool->base.transforms[i]);
610
611 if (pool->base.ipps[i] != NULL)
612 dce_ipp_destroy(&pool->base.ipps[i]);
613
614 if (pool->base.mis[i] != NULL) {
615 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
616 pool->base.mis[i] = NULL;
617 }
618
619 if (pool->base.irqs != NULL) {
620 dal_irq_service_destroy(&pool->base.irqs);
621 }
622
623 if (pool->base.timing_generators[i] != NULL) {
624 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
625 pool->base.timing_generators[i] = NULL;
626 }
627 }
628
629 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
630 if (pool->base.engines[i] != NULL)
631 dce110_engine_destroy(&pool->base.engines[i]);
632 if (pool->base.hw_i2cs[i] != NULL) {
633 kfree(pool->base.hw_i2cs[i]);
634 pool->base.hw_i2cs[i] = NULL;
635 }
636 if (pool->base.sw_i2cs[i] != NULL) {
637 kfree(pool->base.sw_i2cs[i]);
638 pool->base.sw_i2cs[i] = NULL;
639 }
640 }
641
642 for (i = 0; i < pool->base.audio_count; i++) {
643 if (pool->base.audios[i])
644 dce_aud_destroy(&pool->base.audios[i]);
645 }
646
647 for (i = 0; i < pool->base.stream_enc_count; i++) {
648 if (pool->base.stream_enc[i] != NULL)
649 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
650 }
651
652 for (i = 0; i < pool->base.clk_src_count; i++) {
653 if (pool->base.clock_sources[i] != NULL)
654 dce120_clock_source_destroy(
655 &pool->base.clock_sources[i]);
656 }
657
658 if (pool->base.dp_clock_source != NULL)
659 dce120_clock_source_destroy(&pool->base.dp_clock_source);
660
661 if (pool->base.abm != NULL)
662 dce_abm_destroy(&pool->base.abm);
663
664 if (pool->base.dmcu != NULL)
665 dce_dmcu_destroy(&pool->base.dmcu);
666
667 if (pool->base.oem_device != NULL) {
668 struct dc *dc = pool->base.oem_device->ctx->dc;
669
670 dc->link_srv->destroy_ddc_service(&pool->base.oem_device);
671 }
672 }
673
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)674 static void read_dce_straps(
675 struct dc_context *ctx,
676 struct resource_straps *straps)
677 {
678 uint32_t reg_val = dm_read_reg_soc15(ctx, mmCC_DC_MISC_STRAPS, 0);
679
680 straps->audio_stream_number = get_reg_field_value(reg_val,
681 CC_DC_MISC_STRAPS,
682 AUDIO_STREAM_NUMBER);
683 straps->hdmi_disable = get_reg_field_value(reg_val,
684 CC_DC_MISC_STRAPS,
685 HDMI_DISABLE);
686
687 reg_val = dm_read_reg_soc15(ctx, mmDC_PINSTRAPS, 0);
688 straps->dc_pinstraps_audio = get_reg_field_value(reg_val,
689 DC_PINSTRAPS,
690 DC_PINSTRAPS_AUDIO);
691 }
692
create_audio(struct dc_context * ctx,unsigned int inst)693 static struct audio *create_audio(
694 struct dc_context *ctx, unsigned int inst)
695 {
696 return dce_audio_create(ctx, inst,
697 &audio_regs[inst], &audio_shift, &audio_mask);
698 }
699
700 static const struct encoder_feature_support link_enc_feature = {
701 .max_hdmi_deep_color = COLOR_DEPTH_121212,
702 .max_hdmi_pixel_clock = 600000,
703 .hdmi_ycbcr420_supported = true,
704 .dp_ycbcr420_supported = false,
705 .flags.bits.IS_HBR2_CAPABLE = true,
706 .flags.bits.IS_HBR3_CAPABLE = true,
707 .flags.bits.IS_TPS3_CAPABLE = true,
708 .flags.bits.IS_TPS4_CAPABLE = true,
709 };
710
dce120_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)711 static struct link_encoder *dce120_link_encoder_create(
712 struct dc_context *ctx,
713 const struct encoder_init_data *enc_init_data)
714 {
715 struct dce110_link_encoder *enc110 =
716 kzalloc_obj(struct dce110_link_encoder);
717 int link_regs_id;
718
719 if (!enc110)
720 return NULL;
721
722 link_regs_id =
723 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
724
725 dce110_link_encoder_construct(enc110,
726 enc_init_data,
727 &link_enc_feature,
728 &link_enc_regs[link_regs_id],
729 &link_enc_aux_regs[enc_init_data->channel - 1],
730 enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs) ?
731 NULL : &link_enc_hpd_regs[enc_init_data->hpd_source]);
732
733 return &enc110->base;
734 }
735
dce120_panel_cntl_create(const struct panel_cntl_init_data * init_data)736 static struct panel_cntl *dce120_panel_cntl_create(const struct panel_cntl_init_data *init_data)
737 {
738 struct dce_panel_cntl *panel_cntl =
739 kzalloc_obj(struct dce_panel_cntl);
740
741 if (!panel_cntl)
742 return NULL;
743
744 dce_panel_cntl_construct(panel_cntl,
745 init_data,
746 &panel_cntl_regs[init_data->inst],
747 &panel_cntl_shift,
748 &panel_cntl_mask);
749
750 return &panel_cntl->base;
751 }
752
dce120_ipp_create(struct dc_context * ctx,uint32_t inst)753 static struct input_pixel_processor *dce120_ipp_create(
754 struct dc_context *ctx, uint32_t inst)
755 {
756 struct dce_ipp *ipp = kzalloc_obj(struct dce_ipp);
757
758 if (!ipp) {
759 BREAK_TO_DEBUGGER();
760 return NULL;
761 }
762
763 dce_ipp_construct(ipp, ctx, inst,
764 &ipp_regs[inst], &ipp_shift, &ipp_mask);
765 return &ipp->base;
766 }
767
dce120_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)768 static struct stream_encoder *dce120_stream_encoder_create(
769 enum engine_id eng_id,
770 struct dc_context *ctx)
771 {
772 struct dce110_stream_encoder *enc110 =
773 kzalloc_obj(struct dce110_stream_encoder);
774
775 if (!enc110)
776 return NULL;
777
778 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
779 &stream_enc_regs[eng_id],
780 &se_shift, &se_mask);
781 return &enc110->base;
782 }
783
784 #define SRII(reg_name, block, id)\
785 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
786 mm ## block ## id ## _ ## reg_name
787
788 static const struct dce_hwseq_registers hwseq_reg = {
789 HWSEQ_DCE120_REG_LIST()
790 };
791
792 static const struct dce_hwseq_shift hwseq_shift = {
793 HWSEQ_DCE12_MASK_SH_LIST(__SHIFT)
794 };
795
796 static const struct dce_hwseq_mask hwseq_mask = {
797 HWSEQ_DCE12_MASK_SH_LIST(_MASK)
798 };
799
800 /* HWSEQ regs for VG20 */
801 static const struct dce_hwseq_registers dce121_hwseq_reg = {
802 HWSEQ_VG20_REG_LIST()
803 };
804
805 static const struct dce_hwseq_shift dce121_hwseq_shift = {
806 HWSEQ_VG20_MASK_SH_LIST(__SHIFT)
807 };
808
809 static const struct dce_hwseq_mask dce121_hwseq_mask = {
810 HWSEQ_VG20_MASK_SH_LIST(_MASK)
811 };
812
dce120_hwseq_create(struct dc_context * ctx)813 static struct dce_hwseq *dce120_hwseq_create(
814 struct dc_context *ctx)
815 {
816 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);
817
818 if (hws) {
819 hws->ctx = ctx;
820 hws->regs = &hwseq_reg;
821 hws->shifts = &hwseq_shift;
822 hws->masks = &hwseq_mask;
823 }
824 return hws;
825 }
826
dce121_hwseq_create(struct dc_context * ctx)827 static struct dce_hwseq *dce121_hwseq_create(
828 struct dc_context *ctx)
829 {
830 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);
831
832 if (hws) {
833 hws->ctx = ctx;
834 hws->regs = &dce121_hwseq_reg;
835 hws->shifts = &dce121_hwseq_shift;
836 hws->masks = &dce121_hwseq_mask;
837 }
838 return hws;
839 }
840
841 static const struct resource_create_funcs res_create_funcs = {
842 .read_dce_straps = read_dce_straps,
843 .create_audio = create_audio,
844 .create_stream_encoder = dce120_stream_encoder_create,
845 .create_hwseq = dce120_hwseq_create,
846 };
847
848 static const struct resource_create_funcs dce121_res_create_funcs = {
849 .read_dce_straps = read_dce_straps,
850 .create_audio = create_audio,
851 .create_stream_encoder = dce120_stream_encoder_create,
852 .create_hwseq = dce121_hwseq_create,
853 };
854
855
856 #define mi_inst_regs(id) { MI_DCE12_REG_LIST(id) }
857 static const struct dce_mem_input_registers mi_regs[] = {
858 mi_inst_regs(0),
859 mi_inst_regs(1),
860 mi_inst_regs(2),
861 mi_inst_regs(3),
862 mi_inst_regs(4),
863 mi_inst_regs(5),
864 };
865
866 static const struct dce_mem_input_shift mi_shifts = {
867 MI_DCE12_MASK_SH_LIST(__SHIFT)
868 };
869
870 static const struct dce_mem_input_mask mi_masks = {
871 MI_DCE12_MASK_SH_LIST(_MASK)
872 };
873
dce120_mem_input_create(struct dc_context * ctx,uint32_t inst)874 static struct mem_input *dce120_mem_input_create(
875 struct dc_context *ctx,
876 uint32_t inst)
877 {
878 struct dce_mem_input *dce_mi = kzalloc_obj(struct dce_mem_input);
879
880 if (!dce_mi) {
881 BREAK_TO_DEBUGGER();
882 return NULL;
883 }
884
885 dce120_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
886 return &dce_mi->base;
887 }
888
dce120_transform_create(struct dc_context * ctx,uint32_t inst)889 static struct transform *dce120_transform_create(
890 struct dc_context *ctx,
891 uint32_t inst)
892 {
893 struct dce_transform *transform =
894 kzalloc_obj(struct dce_transform);
895
896 if (!transform)
897 return NULL;
898
899 dce_transform_construct(transform, ctx, inst,
900 &xfm_regs[inst], &xfm_shift, &xfm_mask);
901 transform->lb_memory_size = 0x1404; /*5124*/
902 return &transform->base;
903 }
904
dce120_destroy_resource_pool(struct resource_pool ** pool)905 static void dce120_destroy_resource_pool(struct resource_pool **pool)
906 {
907 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
908
909 dce120_resource_destruct(dce110_pool);
910 kfree(dce110_pool);
911 *pool = NULL;
912 }
913
914 static const struct resource_funcs dce120_res_pool_funcs = {
915 .destroy = dce120_destroy_resource_pool,
916 .link_enc_create = dce120_link_encoder_create,
917 .panel_cntl_create = dce120_panel_cntl_create,
918 .validate_bandwidth = dce112_validate_bandwidth,
919 .validate_plane = dce100_validate_plane,
920 .add_stream_to_ctx = dce112_add_stream_to_ctx,
921 .find_first_free_match_stream_enc_for_link = dce110_find_first_free_match_stream_enc_for_link
922 };
923
bw_calcs_data_update_from_pplib(struct dc * dc)924 static void bw_calcs_data_update_from_pplib(struct dc *dc)
925 {
926 struct dm_pp_clock_levels_with_latency eng_clks = {0};
927 struct dm_pp_clock_levels_with_latency mem_clks = {0};
928 struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0};
929 int i;
930 unsigned int clk;
931 unsigned int latency;
932 /*original logic in dal3*/
933 int memory_type_multiplier = MEMORY_TYPE_MULTIPLIER_CZ;
934
935 /*do system clock*/
936 if (!dm_pp_get_clock_levels_by_type_with_latency(
937 dc->ctx,
938 DM_PP_CLOCK_TYPE_ENGINE_CLK,
939 &eng_clks) || eng_clks.num_levels == 0) {
940
941 eng_clks.num_levels = 8;
942 clk = 300000;
943
944 for (i = 0; i < eng_clks.num_levels; i++) {
945 eng_clks.data[i].clocks_in_khz = clk;
946 clk += 100000;
947 }
948 }
949
950 /* convert all the clock fro kHz to fix point mHz TODO: wloop data */
951 dc->bw_vbios->high_sclk = bw_frc_to_fixed(
952 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000);
953 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed(
954 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000);
955 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed(
956 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000);
957 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed(
958 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000);
959 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed(
960 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000);
961 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed(
962 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000);
963 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed(
964 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000);
965 dc->bw_vbios->low_sclk = bw_frc_to_fixed(
966 eng_clks.data[0].clocks_in_khz, 1000);
967
968 /*do memory clock*/
969 if (!dm_pp_get_clock_levels_by_type_with_latency(
970 dc->ctx,
971 DM_PP_CLOCK_TYPE_MEMORY_CLK,
972 &mem_clks) || mem_clks.num_levels == 0) {
973
974 mem_clks.num_levels = 3;
975 clk = 250000;
976 latency = 45;
977
978 for (i = 0; i < eng_clks.num_levels; i++) {
979 mem_clks.data[i].clocks_in_khz = clk;
980 mem_clks.data[i].latency_in_us = latency;
981 clk += 500000;
982 latency -= 5;
983 }
984
985 }
986
987 /* we don't need to call PPLIB for validation clock since they
988 * also give us the highest sclk and highest mclk (UMA clock).
989 * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula):
990 * YCLK = UMACLK*m_memoryTypeMultiplier
991 */
992 if (dc->bw_vbios->memory_type == bw_def_hbm)
993 memory_type_multiplier = MEMORY_TYPE_HBM;
994
995 dc->bw_vbios->low_yclk = bw_frc_to_fixed(
996 (int64_t)mem_clks.data[0].clocks_in_khz * memory_type_multiplier, 1000);
997 dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
998 (int64_t)mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * memory_type_multiplier,
999 1000);
1000 dc->bw_vbios->high_yclk = bw_frc_to_fixed(
1001 (int64_t)mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * memory_type_multiplier,
1002 1000);
1003
1004 /* Now notify PPLib/SMU about which Watermarks sets they should select
1005 * depending on DPM state they are in. And update BW MGR GFX Engine and
1006 * Memory clock member variables for Watermarks calculations for each
1007 * Watermark Set
1008 */
1009 clk_ranges.num_wm_sets = 4;
1010 clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A;
1011 clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz =
1012 eng_clks.data[0].clocks_in_khz;
1013 clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz =
1014 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
1015 clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz =
1016 mem_clks.data[0].clocks_in_khz;
1017 clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz =
1018 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
1019
1020 clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B;
1021 clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz =
1022 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
1023 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
1024 clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000;
1025 clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz =
1026 mem_clks.data[0].clocks_in_khz;
1027 clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz =
1028 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
1029
1030 clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C;
1031 clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz =
1032 eng_clks.data[0].clocks_in_khz;
1033 clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz =
1034 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
1035 clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz =
1036 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
1037 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
1038 clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000;
1039
1040 clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D;
1041 clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz =
1042 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
1043 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
1044 clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000;
1045 clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz =
1046 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
1047 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
1048 clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000;
1049
1050 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
1051 dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges);
1052 }
1053
read_pipe_fuses(struct dc_context * ctx)1054 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1055 {
1056 uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0);
1057 /* VG20 support max 6 pipes */
1058 value = value & 0x3f;
1059 return value;
1060 }
1061
dce120_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dce110_resource_pool * pool)1062 static bool dce120_resource_construct(
1063 uint8_t num_virtual_links,
1064 struct dc *dc,
1065 struct dce110_resource_pool *pool)
1066 {
1067 struct ddc_service_init_data ddc_init_data = {0};
1068 unsigned int i;
1069 int j;
1070 struct dc_context *ctx = dc->ctx;
1071 struct irq_service_init_data irq_init_data;
1072 static const struct resource_create_funcs *res_funcs;
1073 bool is_vg20 = ASICREV_IS_VEGA20_P(ctx->asic_id.hw_internal_rev);
1074 uint32_t pipe_fuses = 0;
1075
1076 ctx->dc_bios->regs = &bios_regs;
1077
1078 pool->base.res_cap = &res_cap;
1079 pool->base.funcs = &dce120_res_pool_funcs;
1080
1081 /* TODO: Fill more data from GreenlandAsicCapability.cpp */
1082 pool->base.pipe_count = res_cap.num_timing_generator;
1083 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
1084 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1085
1086 dc->caps.max_downscale_ratio = 200;
1087 dc->caps.i2c_speed_in_khz = 100;
1088 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
1089 dc->caps.max_cursor_size = 128;
1090 dc->caps.min_horizontal_blanking_period = 80;
1091 dc->caps.dual_link_dvi = true;
1092 dc->caps.psp_setup_panel_mode = true;
1093 dc->caps.extended_aux_timeout_support = false;
1094 dc->debug = debug_defaults;
1095 dc->check_config = config_defaults;
1096
1097 /*************************************************
1098 * Create resources *
1099 *************************************************/
1100
1101 pool->base.clock_sources[DCE120_CLK_SRC_PLL0] =
1102 dce120_clock_source_create(ctx, ctx->dc_bios,
1103 CLOCK_SOURCE_COMBO_PHY_PLL0,
1104 &clk_src_regs[0], false);
1105 pool->base.clock_sources[DCE120_CLK_SRC_PLL1] =
1106 dce120_clock_source_create(ctx, ctx->dc_bios,
1107 CLOCK_SOURCE_COMBO_PHY_PLL1,
1108 &clk_src_regs[1], false);
1109 pool->base.clock_sources[DCE120_CLK_SRC_PLL2] =
1110 dce120_clock_source_create(ctx, ctx->dc_bios,
1111 CLOCK_SOURCE_COMBO_PHY_PLL2,
1112 &clk_src_regs[2], false);
1113 pool->base.clock_sources[DCE120_CLK_SRC_PLL3] =
1114 dce120_clock_source_create(ctx, ctx->dc_bios,
1115 CLOCK_SOURCE_COMBO_PHY_PLL3,
1116 &clk_src_regs[3], false);
1117 pool->base.clock_sources[DCE120_CLK_SRC_PLL4] =
1118 dce120_clock_source_create(ctx, ctx->dc_bios,
1119 CLOCK_SOURCE_COMBO_PHY_PLL4,
1120 &clk_src_regs[4], false);
1121 pool->base.clock_sources[DCE120_CLK_SRC_PLL5] =
1122 dce120_clock_source_create(ctx, ctx->dc_bios,
1123 CLOCK_SOURCE_COMBO_PHY_PLL5,
1124 &clk_src_regs[5], false);
1125 pool->base.clk_src_count = DCE120_CLK_SRC_TOTAL;
1126
1127 pool->base.dp_clock_source =
1128 dce120_clock_source_create(ctx, ctx->dc_bios,
1129 CLOCK_SOURCE_ID_DP_DTO,
1130 &clk_src_regs[0], true);
1131
1132 for (i = 0; i < pool->base.clk_src_count; i++) {
1133 if (pool->base.clock_sources[i] == NULL) {
1134 dm_error("DC: failed to create clock sources!\n");
1135 BREAK_TO_DEBUGGER();
1136 goto clk_src_create_fail;
1137 }
1138 }
1139
1140 pool->base.dmcu = dce_dmcu_create(ctx,
1141 &dmcu_regs,
1142 &dmcu_shift,
1143 &dmcu_mask);
1144 if (pool->base.dmcu == NULL) {
1145 dm_error("DC: failed to create dmcu!\n");
1146 BREAK_TO_DEBUGGER();
1147 goto res_create_fail;
1148 }
1149
1150 pool->base.abm = dce_abm_create(ctx,
1151 &abm_regs,
1152 &abm_shift,
1153 &abm_mask);
1154 if (pool->base.abm == NULL) {
1155 dm_error("DC: failed to create abm!\n");
1156 BREAK_TO_DEBUGGER();
1157 goto res_create_fail;
1158 }
1159
1160
1161 irq_init_data.ctx = dc->ctx;
1162 pool->base.irqs = dal_irq_service_dce120_create(&irq_init_data);
1163 if (!pool->base.irqs)
1164 goto irqs_create_fail;
1165
1166 /* VG20: Pipe harvesting enabled, retrieve valid pipe fuses */
1167 if (is_vg20)
1168 pipe_fuses = read_pipe_fuses(ctx);
1169
1170 /* index to valid pipe resource */
1171 j = 0;
1172 for (i = 0; i < pool->base.pipe_count; i++) {
1173 if (is_vg20) {
1174 if ((pipe_fuses & (1 << i)) != 0) {
1175 dm_error("DC: skip invalid pipe %d!\n", i);
1176 continue;
1177 }
1178 }
1179
1180 pool->base.timing_generators[j] =
1181 dce120_timing_generator_create(
1182 ctx,
1183 i,
1184 &dce120_tg_offsets[i]);
1185 if (pool->base.timing_generators[j] == NULL) {
1186 BREAK_TO_DEBUGGER();
1187 dm_error("DC: failed to create tg!\n");
1188 goto controller_create_fail;
1189 }
1190
1191 pool->base.mis[j] = dce120_mem_input_create(ctx, i);
1192
1193 if (pool->base.mis[j] == NULL) {
1194 BREAK_TO_DEBUGGER();
1195 dm_error(
1196 "DC: failed to create memory input!\n");
1197 goto controller_create_fail;
1198 }
1199
1200 pool->base.ipps[j] = dce120_ipp_create(ctx, i);
1201 if (pool->base.ipps[i] == NULL) {
1202 BREAK_TO_DEBUGGER();
1203 dm_error(
1204 "DC: failed to create input pixel processor!\n");
1205 goto controller_create_fail;
1206 }
1207
1208 pool->base.transforms[j] = dce120_transform_create(ctx, i);
1209 if (pool->base.transforms[i] == NULL) {
1210 BREAK_TO_DEBUGGER();
1211 dm_error(
1212 "DC: failed to create transform!\n");
1213 goto res_create_fail;
1214 }
1215
1216 pool->base.opps[j] = dce120_opp_create(
1217 ctx,
1218 i);
1219 if (pool->base.opps[j] == NULL) {
1220 BREAK_TO_DEBUGGER();
1221 dm_error(
1222 "DC: failed to create output pixel processor!\n");
1223 }
1224
1225 /* check next valid pipe */
1226 j++;
1227 }
1228
1229 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1230 pool->base.engines[i] = dce120_aux_engine_create(ctx, i);
1231 if (pool->base.engines[i] == NULL) {
1232 BREAK_TO_DEBUGGER();
1233 dm_error(
1234 "DC:failed to create aux engine!!\n");
1235 goto res_create_fail;
1236 }
1237 pool->base.hw_i2cs[i] = dce120_i2c_hw_create(ctx, i);
1238 if (pool->base.hw_i2cs[i] == NULL) {
1239 BREAK_TO_DEBUGGER();
1240 dm_error(
1241 "DC:failed to create i2c engine!!\n");
1242 goto res_create_fail;
1243 }
1244 pool->base.sw_i2cs[i] = NULL;
1245 }
1246
1247 /* valid pipe num */
1248 pool->base.pipe_count = j;
1249 pool->base.timing_generator_count = j;
1250
1251 if (is_vg20)
1252 res_funcs = &dce121_res_create_funcs;
1253 else
1254 res_funcs = &res_create_funcs;
1255
1256 if (!resource_construct(num_virtual_links, dc, &pool->base, res_funcs))
1257 goto res_create_fail;
1258
1259 /* Create hardware sequencer */
1260 if (!dce120_hw_sequencer_create(dc))
1261 goto controller_create_fail;
1262
1263 dc->caps.max_planes = pool->base.pipe_count;
1264
1265 for (i = 0; i < dc->caps.max_planes; ++i)
1266 dc->caps.planes[i] = plane_cap;
1267
1268 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
1269
1270 bw_calcs_data_update_from_pplib(dc);
1271
1272 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
1273 ddc_init_data.ctx = dc->ctx;
1274 ddc_init_data.link = NULL;
1275 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
1276 ddc_init_data.id.enum_id = 0;
1277 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
1278 pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);
1279 }
1280
1281 return true;
1282
1283 irqs_create_fail:
1284 controller_create_fail:
1285 clk_src_create_fail:
1286 res_create_fail:
1287
1288 dce120_resource_destruct(pool);
1289
1290 return false;
1291 }
1292
dce120_create_resource_pool(uint8_t num_virtual_links,struct dc * dc)1293 struct resource_pool *dce120_create_resource_pool(
1294 uint8_t num_virtual_links,
1295 struct dc *dc)
1296 {
1297 struct dce110_resource_pool *pool =
1298 kzalloc_obj(struct dce110_resource_pool);
1299
1300 if (!pool)
1301 return NULL;
1302
1303 if (dce120_resource_construct(num_virtual_links, dc, pool))
1304 return &pool->base;
1305
1306 kfree(pool);
1307 BREAK_TO_DEBUGGER();
1308 return NULL;
1309 }
1310