1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "link_encoder.h" 29 #include "stream_encoder.h" 30 31 #include "resource.h" 32 #include "dce110/dce110_resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dce/dce_audio.h" 35 #include "dce110/dce110_timing_generator.h" 36 #include "irq/dce110/irq_service_dce110.h" 37 #include "dce110/dce110_timing_generator_v.h" 38 #include "dce/dce_link_encoder.h" 39 #include "dce/dce_stream_encoder.h" 40 #include "dce/dce_mem_input.h" 41 #include "dce110/dce110_mem_input_v.h" 42 #include "dce/dce_ipp.h" 43 #include "dce/dce_transform.h" 44 #include "dce110/dce110_transform_v.h" 45 #include "dce/dce_opp.h" 46 #include "dce110/dce110_opp_v.h" 47 #include "dce/dce_clock_source.h" 48 #include "dce/dce_hwseq.h" 49 #include "dce110/dce110_hwseq.h" 50 #include "dce/dce_aux.h" 51 #include "dce/dce_abm.h" 52 #include "dce/dce_dmcu.h" 53 #include "dce/dce_i2c.h" 54 #include "dce/dce_panel_cntl.h" 55 56 #define DC_LOGGER \ 57 dc->ctx->logger 58 59 #include "dce110/dce110_compressor.h" 60 61 #include "reg_helper.h" 62 63 #include "dce/dce_11_0_d.h" 64 #include "dce/dce_11_0_sh_mask.h" 65 66 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT 67 #include "gmc/gmc_8_2_d.h" 68 #include "gmc/gmc_8_2_sh_mask.h" 69 #endif 70 71 #ifndef mmDP_DPHY_INTERNAL_CTRL 72 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 73 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 74 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 75 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 76 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 77 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 78 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 79 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 80 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 81 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 82 #endif 83 84 #ifndef mmBIOS_SCRATCH_2 85 #define mmBIOS_SCRATCH_0 0x05C9 86 #define mmBIOS_SCRATCH_2 0x05CB 87 #define mmBIOS_SCRATCH_3 0x05CC 88 #define mmBIOS_SCRATCH_6 0x05CF 89 #endif 90 91 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL 92 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 93 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 94 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC 95 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC 96 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC 97 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC 98 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC 99 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC 100 #endif 101 102 #ifndef mmDP_DPHY_FAST_TRAINING 103 #define mmDP_DPHY_FAST_TRAINING 0x4ABC 104 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC 105 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC 106 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC 107 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC 108 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC 109 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC 110 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC 111 #endif 112 113 #ifndef DPHY_RX_FAST_TRAINING_CAPABLE 114 #define DPHY_RX_FAST_TRAINING_CAPABLE 0x1 115 #endif 116 117 static const struct dce110_timing_generator_offsets dce110_tg_offsets[] = { 118 { 119 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 120 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL), 121 }, 122 { 123 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 124 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 125 }, 126 { 127 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 128 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 129 }, 130 { 131 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 132 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 133 }, 134 { 135 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 136 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 137 }, 138 { 139 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 140 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 141 } 142 }; 143 144 /* set register offset */ 145 #define SR(reg_name)\ 146 .reg_name = mm ## reg_name 147 148 /* set register offset with instance */ 149 #define SRI(reg_name, block, id)\ 150 .reg_name = mm ## block ## id ## _ ## reg_name 151 152 static const struct dce_dmcu_registers dmcu_regs = { 153 DMCU_DCE110_COMMON_REG_LIST() 154 }; 155 156 static const struct dce_dmcu_shift dmcu_shift = { 157 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 158 }; 159 160 static const struct dce_dmcu_mask dmcu_mask = { 161 DMCU_MASK_SH_LIST_DCE110(_MASK) 162 }; 163 164 static const struct dce_abm_registers abm_regs = { 165 ABM_DCE110_COMMON_REG_LIST() 166 }; 167 168 static const struct dce_abm_shift abm_shift = { 169 ABM_MASK_SH_LIST_DCE110(__SHIFT) 170 }; 171 172 static const struct dce_abm_mask abm_mask = { 173 ABM_MASK_SH_LIST_DCE110(_MASK) 174 }; 175 176 #define ipp_regs(id)\ 177 [id] = {\ 178 IPP_DCE110_REG_LIST_DCE_BASE(id)\ 179 } 180 181 static const struct dce_ipp_registers ipp_regs[] = { 182 ipp_regs(0), 183 ipp_regs(1), 184 ipp_regs(2) 185 }; 186 187 static const struct dce_ipp_shift ipp_shift = { 188 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 189 }; 190 191 static const struct dce_ipp_mask ipp_mask = { 192 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 193 }; 194 195 #define transform_regs(id)\ 196 [id] = {\ 197 XFM_COMMON_REG_LIST_DCE110(id)\ 198 } 199 200 static const struct dce_transform_registers xfm_regs[] = { 201 transform_regs(0), 202 transform_regs(1), 203 transform_regs(2) 204 }; 205 206 static const struct dce_transform_shift xfm_shift = { 207 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 208 }; 209 210 static const struct dce_transform_mask xfm_mask = { 211 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK) 212 }; 213 214 #define aux_regs(id)\ 215 [id] = {\ 216 AUX_REG_LIST(id)\ 217 } 218 219 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 220 aux_regs(0), 221 aux_regs(1), 222 aux_regs(2), 223 aux_regs(3), 224 aux_regs(4), 225 aux_regs(5) 226 }; 227 228 #define hpd_regs(id)\ 229 [id] = {\ 230 HPD_REG_LIST(id)\ 231 } 232 233 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 234 hpd_regs(0), 235 hpd_regs(1), 236 hpd_regs(2), 237 hpd_regs(3), 238 hpd_regs(4), 239 hpd_regs(5) 240 }; 241 242 243 #define link_regs(id)\ 244 [id] = {\ 245 LE_DCE110_REG_LIST(id)\ 246 } 247 248 static const struct dce110_link_enc_registers link_enc_regs[] = { 249 link_regs(0), 250 link_regs(1), 251 link_regs(2), 252 link_regs(3), 253 link_regs(4), 254 link_regs(5), 255 link_regs(6), 256 }; 257 258 #define stream_enc_regs(id)\ 259 [id] = {\ 260 SE_COMMON_REG_LIST(id),\ 261 .TMDS_CNTL = 0,\ 262 } 263 264 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 265 stream_enc_regs(0), 266 stream_enc_regs(1), 267 stream_enc_regs(2) 268 }; 269 270 static const struct dce_stream_encoder_shift se_shift = { 271 SE_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 272 }; 273 274 static const struct dce_stream_encoder_mask se_mask = { 275 SE_COMMON_MASK_SH_LIST_DCE110(_MASK) 276 }; 277 278 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 279 { DCE_PANEL_CNTL_REG_LIST() } 280 }; 281 282 static const struct dce_panel_cntl_shift panel_cntl_shift = { 283 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 284 }; 285 286 static const struct dce_panel_cntl_mask panel_cntl_mask = { 287 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 288 }; 289 290 static const struct dce110_aux_registers_shift aux_shift = { 291 DCE_AUX_MASK_SH_LIST(__SHIFT) 292 }; 293 294 static const struct dce110_aux_registers_mask aux_mask = { 295 DCE_AUX_MASK_SH_LIST(_MASK) 296 }; 297 298 #define opp_regs(id)\ 299 [id] = {\ 300 OPP_DCE_110_REG_LIST(id),\ 301 } 302 303 static const struct dce_opp_registers opp_regs[] = { 304 opp_regs(0), 305 opp_regs(1), 306 opp_regs(2), 307 opp_regs(3), 308 opp_regs(4), 309 opp_regs(5) 310 }; 311 312 static const struct dce_opp_shift opp_shift = { 313 OPP_COMMON_MASK_SH_LIST_DCE_110(__SHIFT) 314 }; 315 316 static const struct dce_opp_mask opp_mask = { 317 OPP_COMMON_MASK_SH_LIST_DCE_110(_MASK) 318 }; 319 320 #define aux_engine_regs(id)\ 321 [id] = {\ 322 AUX_COMMON_REG_LIST(id), \ 323 .AUX_RESET_MASK = 0 \ 324 } 325 326 static const struct dce110_aux_registers aux_engine_regs[] = { 327 aux_engine_regs(0), 328 aux_engine_regs(1), 329 aux_engine_regs(2), 330 aux_engine_regs(3), 331 aux_engine_regs(4), 332 aux_engine_regs(5) 333 }; 334 335 #define audio_regs(id)\ 336 [id] = {\ 337 AUD_COMMON_REG_LIST(id)\ 338 } 339 340 static const struct dce_audio_registers audio_regs[] = { 341 audio_regs(0), 342 audio_regs(1), 343 audio_regs(2), 344 audio_regs(3), 345 audio_regs(4), 346 audio_regs(5), 347 audio_regs(6), 348 }; 349 350 static const struct dce_audio_shift audio_shift = { 351 AUD_COMMON_MASK_SH_LIST(__SHIFT) 352 }; 353 354 static const struct dce_audio_mask audio_mask = { 355 AUD_COMMON_MASK_SH_LIST(_MASK) 356 }; 357 358 /* AG TBD Needs to be reduced back to 3 pipes once dce10 hw sequencer implemented. */ 359 360 361 #define clk_src_regs(id)\ 362 [id] = {\ 363 CS_COMMON_REG_LIST_DCE_100_110(id),\ 364 } 365 366 static const struct dce110_clk_src_regs clk_src_regs[] = { 367 clk_src_regs(0), 368 clk_src_regs(1), 369 clk_src_regs(2) 370 }; 371 372 static const struct dce110_clk_src_shift cs_shift = { 373 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 374 }; 375 376 static const struct dce110_clk_src_mask cs_mask = { 377 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 378 }; 379 380 static const struct bios_registers bios_regs = { 381 .BIOS_SCRATCH_0 = mmBIOS_SCRATCH_0, 382 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3, 383 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 384 }; 385 386 static const struct resource_caps carrizo_resource_cap = { 387 .num_timing_generator = 3, 388 .num_video_plane = 1, 389 .num_audio = 3, 390 .num_stream_encoder = 3, 391 .num_pll = 2, 392 .num_ddc = 3, 393 }; 394 395 static const struct resource_caps stoney_resource_cap = { 396 .num_timing_generator = 2, 397 .num_video_plane = 1, 398 .num_audio = 3, 399 .num_stream_encoder = 3, 400 .num_pll = 2, 401 .num_ddc = 3, 402 }; 403 404 static const struct dc_plane_cap plane_cap = { 405 .type = DC_PLANE_TYPE_DCE_RGB, 406 .per_pixel_alpha = 1, 407 408 .pixel_format_support = { 409 .argb8888 = true, 410 .nv12 = false, 411 .fp16 = true 412 }, 413 414 .max_upscale_factor = { 415 .argb8888 = 16000, 416 .nv12 = 1, 417 .fp16 = 1 418 }, 419 420 .max_downscale_factor = { 421 .argb8888 = 250, 422 .nv12 = 1, 423 .fp16 = 1 424 }, 425 64, 426 64 427 }; 428 429 static const struct dc_debug_options debug_defaults = { 0 }; 430 431 static const struct dc_check_config config_defaults = { 432 .enable_legacy_fast_update = true, 433 }; 434 435 static const struct dc_plane_cap underlay_plane_cap = { 436 .type = DC_PLANE_TYPE_DCE_UNDERLAY, 437 .per_pixel_alpha = 1, 438 439 .pixel_format_support = { 440 .argb8888 = false, 441 .nv12 = true, 442 .fp16 = false 443 }, 444 445 .max_upscale_factor = { 446 .argb8888 = 1, 447 .nv12 = 16000, 448 .fp16 = 1 449 }, 450 451 .max_downscale_factor = { 452 .argb8888 = 1, 453 .nv12 = 250, 454 .fp16 = 1 455 }, 456 64, 457 64 458 }; 459 460 #define CTX ctx 461 #define REG(reg) mm ## reg 462 463 #ifndef mmCC_DC_HDMI_STRAPS 464 #define mmCC_DC_HDMI_STRAPS 0x4819 465 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 466 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 467 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 468 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 469 #endif 470 471 static int map_transmitter_id_to_phy_instance( 472 enum transmitter transmitter) 473 { 474 switch (transmitter) { 475 case TRANSMITTER_UNIPHY_A: 476 return 0; 477 case TRANSMITTER_UNIPHY_B: 478 return 1; 479 case TRANSMITTER_UNIPHY_C: 480 return 2; 481 case TRANSMITTER_UNIPHY_D: 482 return 3; 483 case TRANSMITTER_UNIPHY_E: 484 return 4; 485 case TRANSMITTER_UNIPHY_F: 486 return 5; 487 case TRANSMITTER_UNIPHY_G: 488 return 6; 489 default: 490 ASSERT(0); 491 return 0; 492 } 493 } 494 495 static void read_dce_straps( 496 struct dc_context *ctx, 497 struct resource_straps *straps) 498 { 499 REG_GET_2(CC_DC_HDMI_STRAPS, 500 HDMI_DISABLE, &straps->hdmi_disable, 501 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 502 503 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 504 } 505 506 static struct audio *create_audio( 507 struct dc_context *ctx, unsigned int inst) 508 { 509 return dce_audio_create(ctx, inst, 510 &audio_regs[inst], &audio_shift, &audio_mask); 511 } 512 513 static struct timing_generator *dce110_timing_generator_create( 514 struct dc_context *ctx, 515 uint32_t instance, 516 const struct dce110_timing_generator_offsets *offsets) 517 { 518 struct dce110_timing_generator *tg110 = 519 kzalloc_obj(struct dce110_timing_generator); 520 521 if (!tg110) 522 return NULL; 523 524 dce110_timing_generator_construct(tg110, ctx, instance, offsets); 525 return &tg110->base; 526 } 527 528 static struct stream_encoder *dce110_stream_encoder_create( 529 enum engine_id eng_id, 530 struct dc_context *ctx) 531 { 532 struct dce110_stream_encoder *enc110 = 533 kzalloc_obj(struct dce110_stream_encoder); 534 535 if (!enc110) 536 return NULL; 537 538 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 539 &stream_enc_regs[eng_id], 540 &se_shift, &se_mask); 541 return &enc110->base; 542 } 543 544 #define SRII(reg_name, block, id)\ 545 .reg_name[id] = mm ## block ## id ## _ ## reg_name 546 547 static const struct dce_hwseq_registers hwseq_stoney_reg = { 548 HWSEQ_ST_REG_LIST() 549 }; 550 551 static const struct dce_hwseq_registers hwseq_cz_reg = { 552 HWSEQ_CZ_REG_LIST() 553 }; 554 555 static const struct dce_hwseq_shift hwseq_shift = { 556 HWSEQ_DCE11_MASK_SH_LIST(__SHIFT), 557 }; 558 559 static const struct dce_hwseq_mask hwseq_mask = { 560 HWSEQ_DCE11_MASK_SH_LIST(_MASK), 561 }; 562 563 static struct dce_hwseq *dce110_hwseq_create( 564 struct dc_context *ctx) 565 { 566 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq); 567 568 if (hws) { 569 hws->ctx = ctx; 570 hws->regs = ASIC_REV_IS_STONEY(ctx->asic_id.hw_internal_rev) ? 571 &hwseq_stoney_reg : &hwseq_cz_reg; 572 hws->shifts = &hwseq_shift; 573 hws->masks = &hwseq_mask; 574 hws->wa.blnd_crtc_trigger = true; 575 } 576 return hws; 577 } 578 579 static const struct resource_create_funcs res_create_funcs = { 580 .read_dce_straps = read_dce_straps, 581 .create_audio = create_audio, 582 .create_stream_encoder = dce110_stream_encoder_create, 583 .create_hwseq = dce110_hwseq_create, 584 }; 585 586 #define mi_inst_regs(id) { \ 587 MI_DCE11_REG_LIST(id), \ 588 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ 589 } 590 static const struct dce_mem_input_registers mi_regs[] = { 591 mi_inst_regs(0), 592 mi_inst_regs(1), 593 mi_inst_regs(2), 594 }; 595 596 static const struct dce_mem_input_shift mi_shifts = { 597 MI_DCE11_MASK_SH_LIST(__SHIFT), 598 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 599 }; 600 601 static const struct dce_mem_input_mask mi_masks = { 602 MI_DCE11_MASK_SH_LIST(_MASK), 603 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 604 }; 605 606 607 static struct mem_input *dce110_mem_input_create( 608 struct dc_context *ctx, 609 uint32_t inst) 610 { 611 struct dce_mem_input *dce_mi = kzalloc_obj(struct dce_mem_input); 612 613 if (!dce_mi) { 614 BREAK_TO_DEBUGGER(); 615 return NULL; 616 } 617 618 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 619 dce_mi->wa.single_head_rdreq_dmif_limit = 3; 620 return &dce_mi->base; 621 } 622 623 static void dce110_transform_destroy(struct transform **xfm) 624 { 625 kfree(TO_DCE_TRANSFORM(*xfm)); 626 *xfm = NULL; 627 } 628 629 static struct transform *dce110_transform_create( 630 struct dc_context *ctx, 631 uint32_t inst) 632 { 633 struct dce_transform *transform = 634 kzalloc_obj(struct dce_transform); 635 636 if (!transform) 637 return NULL; 638 639 dce_transform_construct(transform, ctx, inst, 640 &xfm_regs[inst], &xfm_shift, &xfm_mask); 641 return &transform->base; 642 } 643 644 static struct input_pixel_processor *dce110_ipp_create( 645 struct dc_context *ctx, uint32_t inst) 646 { 647 struct dce_ipp *ipp = kzalloc_obj(struct dce_ipp); 648 649 if (!ipp) { 650 BREAK_TO_DEBUGGER(); 651 return NULL; 652 } 653 654 dce_ipp_construct(ipp, ctx, inst, 655 &ipp_regs[inst], &ipp_shift, &ipp_mask); 656 return &ipp->base; 657 } 658 659 static const struct encoder_feature_support link_enc_feature = { 660 .max_hdmi_deep_color = COLOR_DEPTH_121212, 661 .max_hdmi_pixel_clock = 300000, 662 .flags.bits.IS_HBR2_CAPABLE = true, 663 .flags.bits.IS_TPS3_CAPABLE = true 664 }; 665 666 static struct link_encoder *dce110_link_encoder_create( 667 struct dc_context *ctx, 668 const struct encoder_init_data *enc_init_data) 669 { 670 (void)ctx; 671 struct dce110_link_encoder *enc110 = 672 kzalloc_obj(struct dce110_link_encoder); 673 int link_regs_id; 674 675 if (!enc110) 676 return NULL; 677 678 link_regs_id = 679 map_transmitter_id_to_phy_instance(enc_init_data->transmitter); 680 681 dce110_link_encoder_construct(enc110, 682 enc_init_data, 683 &link_enc_feature, 684 &link_enc_regs[link_regs_id], 685 &link_enc_aux_regs[enc_init_data->channel - 1], 686 enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs) ? 687 NULL : &link_enc_hpd_regs[enc_init_data->hpd_source]); 688 return &enc110->base; 689 } 690 691 static struct panel_cntl *dce110_panel_cntl_create(const struct panel_cntl_init_data *init_data) 692 { 693 struct dce_panel_cntl *panel_cntl = 694 kzalloc_obj(struct dce_panel_cntl); 695 696 if (!panel_cntl) 697 return NULL; 698 699 dce_panel_cntl_construct(panel_cntl, 700 init_data, 701 &panel_cntl_regs[init_data->inst], 702 &panel_cntl_shift, 703 &panel_cntl_mask); 704 705 return &panel_cntl->base; 706 } 707 708 static struct output_pixel_processor *dce110_opp_create( 709 struct dc_context *ctx, 710 uint32_t inst) 711 { 712 struct dce110_opp *opp = 713 kzalloc_obj(struct dce110_opp); 714 715 if (!opp) 716 return NULL; 717 718 dce110_opp_construct(opp, 719 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 720 return &opp->base; 721 } 722 723 static struct dce_aux *dce110_aux_engine_create( 724 struct dc_context *ctx, 725 uint32_t inst) 726 { 727 struct aux_engine_dce110 *aux_engine = 728 kzalloc_obj(struct aux_engine_dce110); 729 730 if (!aux_engine) 731 return NULL; 732 733 dce110_aux_engine_construct(aux_engine, ctx, inst, 734 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 735 &aux_engine_regs[inst], 736 &aux_mask, 737 &aux_shift, 738 ctx->dc->caps.extended_aux_timeout_support); 739 740 return &aux_engine->base; 741 } 742 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 743 744 static const struct dce_i2c_registers i2c_hw_regs[] = { 745 i2c_inst_regs(1), 746 i2c_inst_regs(2), 747 i2c_inst_regs(3), 748 i2c_inst_regs(4), 749 i2c_inst_regs(5), 750 i2c_inst_regs(6), 751 }; 752 753 static const struct dce_i2c_shift i2c_shifts = { 754 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 755 }; 756 757 static const struct dce_i2c_mask i2c_masks = { 758 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) 759 }; 760 761 static struct dce_i2c_hw *dce110_i2c_hw_create( 762 struct dc_context *ctx, 763 uint32_t inst) 764 { 765 struct dce_i2c_hw *dce_i2c_hw = 766 kzalloc_obj(struct dce_i2c_hw); 767 768 if (!dce_i2c_hw) 769 return NULL; 770 771 dce100_i2c_hw_construct(dce_i2c_hw, ctx, inst, 772 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 773 774 return dce_i2c_hw; 775 } 776 static struct clock_source *dce110_clock_source_create( 777 struct dc_context *ctx, 778 struct dc_bios *bios, 779 enum clock_source_id id, 780 const struct dce110_clk_src_regs *regs, 781 bool dp_clk_src) 782 { 783 struct dce110_clk_src *clk_src = 784 kzalloc_obj(struct dce110_clk_src); 785 786 if (!clk_src) 787 return NULL; 788 789 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 790 regs, &cs_shift, &cs_mask)) { 791 clk_src->base.dp_clk_src = dp_clk_src; 792 return &clk_src->base; 793 } 794 795 kfree(clk_src); 796 BREAK_TO_DEBUGGER(); 797 return NULL; 798 } 799 800 static void dce110_clock_source_destroy(struct clock_source **clk_src) 801 { 802 struct dce110_clk_src *dce110_clk_src; 803 804 if (!clk_src) 805 return; 806 807 dce110_clk_src = TO_DCE110_CLK_SRC(*clk_src); 808 809 kfree(dce110_clk_src->dp_ss_params); 810 kfree(dce110_clk_src->hdmi_ss_params); 811 kfree(dce110_clk_src->dvi_ss_params); 812 813 kfree(dce110_clk_src); 814 *clk_src = NULL; 815 } 816 817 static void dce110_resource_destruct(struct dce110_resource_pool *pool) 818 { 819 unsigned int i; 820 821 for (i = 0; i < pool->base.pipe_count; i++) { 822 if (pool->base.opps[i] != NULL) 823 dce110_opp_destroy(&pool->base.opps[i]); 824 825 if (pool->base.transforms[i] != NULL) 826 dce110_transform_destroy(&pool->base.transforms[i]); 827 828 if (pool->base.ipps[i] != NULL) 829 dce_ipp_destroy(&pool->base.ipps[i]); 830 831 if (pool->base.mis[i] != NULL) { 832 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 833 pool->base.mis[i] = NULL; 834 } 835 836 if (pool->base.timing_generators[i] != NULL) { 837 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 838 pool->base.timing_generators[i] = NULL; 839 } 840 } 841 842 for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { 843 if (pool->base.engines[i] != NULL) 844 dce110_engine_destroy(&pool->base.engines[i]); 845 if (pool->base.hw_i2cs[i] != NULL) { 846 kfree(pool->base.hw_i2cs[i]); 847 pool->base.hw_i2cs[i] = NULL; 848 } 849 if (pool->base.sw_i2cs[i] != NULL) { 850 kfree(pool->base.sw_i2cs[i]); 851 pool->base.sw_i2cs[i] = NULL; 852 } 853 } 854 855 for (i = 0; i < pool->base.stream_enc_count; i++) { 856 if (pool->base.stream_enc[i] != NULL) 857 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 858 } 859 860 for (i = 0; i < pool->base.clk_src_count; i++) { 861 if (pool->base.clock_sources[i] != NULL) { 862 dce110_clock_source_destroy(&pool->base.clock_sources[i]); 863 } 864 } 865 866 if (pool->base.dp_clock_source != NULL) 867 dce110_clock_source_destroy(&pool->base.dp_clock_source); 868 869 for (i = 0; i < pool->base.audio_count; i++) { 870 if (pool->base.audios[i] != NULL) { 871 dce_aud_destroy(&pool->base.audios[i]); 872 } 873 } 874 875 if (pool->base.abm != NULL) 876 dce_abm_destroy(&pool->base.abm); 877 878 if (pool->base.dmcu != NULL) 879 dce_dmcu_destroy(&pool->base.dmcu); 880 881 if (pool->base.irqs != NULL) { 882 dal_irq_service_destroy(&pool->base.irqs); 883 } 884 } 885 886 887 static void get_pixel_clock_parameters( 888 const struct pipe_ctx *pipe_ctx, 889 struct pixel_clk_params *pixel_clk_params) 890 { 891 const struct dc_stream_state *stream = pipe_ctx->stream; 892 893 /*TODO: is this halved for YCbCr 420? in that case we might want to move 894 * the pixel clock normalization for hdmi up to here instead of doing it 895 * in pll_adjust_pix_clk 896 */ 897 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; 898 pixel_clk_params->encoder_object_id = stream->link->link_enc->id; 899 if (dc_is_rgb_signal(pipe_ctx->stream->signal)) 900 pixel_clk_params->encoder_object_id = stream->link->link_enc->analog_id; 901 pixel_clk_params->signal_type = pipe_ctx->stream->signal; 902 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; 903 /* TODO: un-hardcode*/ 904 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * 905 LINK_RATE_REF_FREQ_IN_KHZ; 906 pixel_clk_params->flags.ENABLE_SS = 0; 907 pixel_clk_params->color_depth = 908 stream->timing.display_color_depth; 909 pixel_clk_params->flags.DISPLAY_BLANKED = 1; 910 pixel_clk_params->flags.SUPPORT_YCBCR420 = (stream->timing.pixel_encoding == 911 PIXEL_ENCODING_YCBCR420); 912 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; 913 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) { 914 pixel_clk_params->color_depth = COLOR_DEPTH_888; 915 } 916 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 917 pixel_clk_params->requested_pix_clk_100hz = pixel_clk_params->requested_pix_clk_100hz / 2; 918 } 919 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 920 pixel_clk_params->requested_pix_clk_100hz *= 2; 921 922 } 923 924 void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx) 925 { 926 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); 927 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( 928 pipe_ctx->clock_source, 929 &pipe_ctx->stream_res.pix_clk_params, 930 &pipe_ctx->pll_settings); 931 resource_build_bit_depth_reduction_params(pipe_ctx->stream, 932 &pipe_ctx->stream->bit_depth_params); 933 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; 934 } 935 936 static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigned int underlay_idx) 937 { 938 if (pipe_ctx->pipe_idx != underlay_idx) 939 return true; 940 if (!pipe_ctx->plane_state) 941 return false; 942 if (pipe_ctx->plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 943 return false; 944 return true; 945 } 946 947 static enum dc_status build_mapped_resource( 948 const struct dc *dc, 949 struct dc_state *context, 950 struct dc_stream_state *stream) 951 { 952 struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream); 953 954 if (!pipe_ctx) 955 return DC_ERROR_UNEXPECTED; 956 957 if (!is_surface_pixel_format_supported(pipe_ctx, 958 dc->res_pool->underlay_pipe_index)) 959 return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED; 960 961 dce110_resource_build_pipe_hw_param(pipe_ctx); 962 963 /* TODO: validate audio ASIC caps, encoder */ 964 965 resource_build_info_frame(pipe_ctx); 966 967 return DC_OK; 968 } 969 970 static enum dc_status dce110_validate_bandwidth( 971 struct dc *dc, 972 struct dc_state *context, 973 enum dc_validate_mode validate_mode) 974 { 975 (void)validate_mode; 976 bool result = false; 977 978 DC_LOG_BANDWIDTH_CALCS( 979 "%s: start", 980 __func__); 981 982 if (bw_calcs( 983 dc->ctx, 984 dc->bw_dceip, 985 dc->bw_vbios, 986 context->res_ctx.pipe_ctx, 987 dc->res_pool->pipe_count, 988 &context->bw_ctx.bw.dce)) 989 result = true; 990 991 if (!result) 992 DC_LOG_BANDWIDTH_VALIDATION("%s: %dx%d@%d Bandwidth validation failed!\n", 993 __func__, 994 context->streams[0]->timing.h_addressable, 995 context->streams[0]->timing.v_addressable, 996 context->streams[0]->timing.pix_clk_100hz / 10); 997 998 if (memcmp(&dc->current_state->bw_ctx.bw.dce, 999 &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) { 1000 1001 DC_LOG_BANDWIDTH_CALCS( 1002 "%s: finish,\n" 1003 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 1004 "stutMark_b: %d stutMark_a: %d\n" 1005 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 1006 "stutMark_b: %d stutMark_a: %d\n" 1007 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 1008 "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n" 1009 "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n" 1010 "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n" 1011 , 1012 __func__, 1013 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].b_mark, 1014 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].a_mark, 1015 context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark, 1016 context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark, 1017 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].b_mark, 1018 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].a_mark, 1019 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].b_mark, 1020 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].a_mark, 1021 context->bw_ctx.bw.dce.urgent_wm_ns[1].b_mark, 1022 context->bw_ctx.bw.dce.urgent_wm_ns[1].a_mark, 1023 context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].b_mark, 1024 context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].a_mark, 1025 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].b_mark, 1026 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].a_mark, 1027 context->bw_ctx.bw.dce.urgent_wm_ns[2].b_mark, 1028 context->bw_ctx.bw.dce.urgent_wm_ns[2].a_mark, 1029 context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].b_mark, 1030 context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].a_mark, 1031 context->bw_ctx.bw.dce.stutter_mode_enable, 1032 context->bw_ctx.bw.dce.cpuc_state_change_enable, 1033 context->bw_ctx.bw.dce.cpup_state_change_enable, 1034 context->bw_ctx.bw.dce.nbp_state_change_enable, 1035 context->bw_ctx.bw.dce.all_displays_in_sync, 1036 context->bw_ctx.bw.dce.dispclk_khz, 1037 context->bw_ctx.bw.dce.sclk_khz, 1038 context->bw_ctx.bw.dce.sclk_deep_sleep_khz, 1039 context->bw_ctx.bw.dce.yclk_khz, 1040 context->bw_ctx.bw.dce.blackout_recovery_time_us); 1041 } 1042 return result ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE; 1043 } 1044 1045 static enum dc_status dce110_validate_plane(const struct dc_plane_state *plane_state, 1046 struct dc_caps *caps) 1047 { 1048 (void)caps; 1049 if (((plane_state->dst_rect.width * 2) < plane_state->src_rect.width) || 1050 ((plane_state->dst_rect.height * 2) < plane_state->src_rect.height)) 1051 return DC_FAIL_SURFACE_VALIDATE; 1052 1053 return DC_OK; 1054 } 1055 1056 static bool dce110_validate_surface_sets( 1057 struct dc_state *context) 1058 { 1059 int i, j; 1060 1061 for (i = 0; i < context->stream_count; i++) { 1062 if (context->stream_status[i].plane_count == 0) 1063 continue; 1064 1065 if (context->stream_status[i].plane_count > 2) 1066 return false; 1067 1068 for (j = 0; j < context->stream_status[i].plane_count; j++) { 1069 struct dc_plane_state *plane = 1070 context->stream_status[i].plane_states[j]; 1071 1072 /* underlay validation */ 1073 if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 1074 1075 if ((plane->src_rect.width > 1920 || 1076 plane->src_rect.height > 1080)) 1077 return false; 1078 1079 /* we don't have the logic to support underlay 1080 * only yet so block the use case where we get 1081 * NV12 plane as top layer 1082 */ 1083 if (j == 0) 1084 return false; 1085 1086 /* irrespective of plane format, 1087 * stream should be RGB encoded 1088 */ 1089 if (context->streams[i]->timing.pixel_encoding 1090 != PIXEL_ENCODING_RGB) 1091 return false; 1092 1093 } 1094 1095 } 1096 } 1097 1098 return true; 1099 } 1100 1101 static enum dc_status dce110_validate_global( 1102 struct dc *dc, 1103 struct dc_state *context) 1104 { 1105 (void)dc; 1106 if (!dce110_validate_surface_sets(context)) 1107 return DC_FAIL_SURFACE_VALIDATE; 1108 1109 return DC_OK; 1110 } 1111 1112 static enum dc_status dce110_add_stream_to_ctx( 1113 struct dc *dc, 1114 struct dc_state *new_ctx, 1115 struct dc_stream_state *dc_stream) 1116 { 1117 enum dc_status result = DC_ERROR_UNEXPECTED; 1118 1119 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 1120 1121 if (result == DC_OK) 1122 result = resource_map_clock_resources(dc, new_ctx, dc_stream); 1123 1124 1125 if (result == DC_OK) 1126 result = build_mapped_resource(dc, new_ctx, dc_stream); 1127 1128 return result; 1129 } 1130 1131 static struct pipe_ctx *dce110_acquire_underlay( 1132 const struct dc_state *cur_ctx, 1133 struct dc_state *new_ctx, 1134 const struct resource_pool *pool, 1135 const struct pipe_ctx *opp_head_pipe) 1136 { 1137 (void)cur_ctx; 1138 struct dc_stream_state *stream = opp_head_pipe->stream; 1139 struct dc *dc = stream->ctx->dc; 1140 struct dce_hwseq *hws = dc->hwseq; 1141 struct resource_context *res_ctx = &new_ctx->res_ctx; 1142 unsigned int underlay_idx = pool->underlay_pipe_index; 1143 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx]; 1144 1145 if (res_ctx->pipe_ctx[underlay_idx].stream) 1146 return NULL; 1147 1148 pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx]; 1149 pipe_ctx->plane_res.mi = pool->mis[underlay_idx]; 1150 /*pipe_ctx->plane_res.ipp = res_ctx->pool->ipps[underlay_idx];*/ 1151 pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx]; 1152 pipe_ctx->stream_res.opp = pool->opps[underlay_idx]; 1153 pipe_ctx->pipe_idx = (uint8_t)underlay_idx; 1154 1155 pipe_ctx->stream = stream; 1156 1157 if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) { 1158 struct tg_color black_color = {0}; 1159 struct dc_bios *dcb = dc->ctx->dc_bios; 1160 1161 hws->funcs.enable_display_power_gating( 1162 dc, 1163 (uint8_t)pipe_ctx->stream_res.tg->inst, 1164 dcb, PIPE_GATING_CONTROL_DISABLE); 1165 1166 /* 1167 * This is for powering on underlay, so crtc does not 1168 * need to be enabled 1169 */ 1170 1171 pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg, 1172 &stream->timing, 1173 0, 1174 0, 1175 0, 1176 0, 1177 0, 1178 pipe_ctx->stream->signal, 1179 false); 1180 1181 pipe_ctx->stream_res.tg->funcs->enable_advanced_request( 1182 pipe_ctx->stream_res.tg, 1183 true, 1184 &stream->timing); 1185 1186 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi, 1187 stream->timing.h_total, 1188 stream->timing.v_total, 1189 stream->timing.pix_clk_100hz / 10, 1190 new_ctx->stream_count); 1191 1192 color_space_to_black_color(dc, 1193 COLOR_SPACE_YCBCR601, &black_color); 1194 pipe_ctx->stream_res.tg->funcs->set_blank_color( 1195 pipe_ctx->stream_res.tg, 1196 &black_color); 1197 } 1198 1199 return pipe_ctx; 1200 } 1201 1202 static void dce110_destroy_resource_pool(struct resource_pool **pool) 1203 { 1204 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 1205 1206 dce110_resource_destruct(dce110_pool); 1207 kfree(dce110_pool); 1208 *pool = NULL; 1209 } 1210 1211 struct stream_encoder *dce110_find_first_free_match_stream_enc_for_link( 1212 struct resource_context *res_ctx, 1213 const struct resource_pool *pool, 1214 struct dc_stream_state *stream) 1215 { 1216 unsigned int i; 1217 int j = -1; 1218 struct dc_link *link = stream->link; 1219 1220 for (i = 0; i < pool->stream_enc_count; i++) { 1221 if (!res_ctx->is_stream_enc_acquired[i] && 1222 pool->stream_enc[i]) { 1223 /* Store first available for MST second display 1224 * in daisy chain use case 1225 */ 1226 j = (int)i; 1227 if (pool->stream_enc[i]->id == 1228 link->link_enc->preferred_engine) 1229 return pool->stream_enc[i]; 1230 } 1231 } 1232 1233 /* 1234 * For CZ and later, we can allow DIG FE and BE to differ for all display types 1235 */ 1236 1237 if (j >= 0) 1238 return pool->stream_enc[j]; 1239 1240 return NULL; 1241 } 1242 1243 1244 static const struct resource_funcs dce110_res_pool_funcs = { 1245 .destroy = dce110_destroy_resource_pool, 1246 .link_enc_create = dce110_link_encoder_create, 1247 .panel_cntl_create = dce110_panel_cntl_create, 1248 .validate_bandwidth = dce110_validate_bandwidth, 1249 .validate_plane = dce110_validate_plane, 1250 .acquire_free_pipe_as_secondary_dpp_pipe = dce110_acquire_underlay, 1251 .add_stream_to_ctx = dce110_add_stream_to_ctx, 1252 .validate_global = dce110_validate_global, 1253 .find_first_free_match_stream_enc_for_link = dce110_find_first_free_match_stream_enc_for_link 1254 }; 1255 1256 static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool) 1257 { 1258 struct dce110_timing_generator *dce110_tgv = kzalloc_obj(*dce110_tgv); 1259 struct dce_transform *dce110_xfmv = kzalloc_obj(*dce110_xfmv); 1260 struct dce_mem_input *dce110_miv = kzalloc_obj(*dce110_miv); 1261 struct dce110_opp *dce110_oppv = kzalloc_obj(*dce110_oppv); 1262 1263 if (!dce110_tgv || !dce110_xfmv || !dce110_miv || !dce110_oppv) { 1264 kfree(dce110_tgv); 1265 kfree(dce110_xfmv); 1266 kfree(dce110_miv); 1267 kfree(dce110_oppv); 1268 return false; 1269 } 1270 1271 dce110_opp_v_construct(dce110_oppv, ctx); 1272 1273 dce110_timing_generator_v_construct(dce110_tgv, ctx); 1274 dce110_mem_input_v_construct(dce110_miv, ctx); 1275 dce110_transform_v_construct(dce110_xfmv, ctx); 1276 1277 pool->opps[pool->pipe_count] = &dce110_oppv->base; 1278 pool->timing_generators[pool->pipe_count] = &dce110_tgv->base; 1279 pool->mis[pool->pipe_count] = &dce110_miv->base; 1280 pool->transforms[pool->pipe_count] = &dce110_xfmv->base; 1281 pool->pipe_count++; 1282 1283 /* update the public caps to indicate an underlay is available */ 1284 ctx->dc->caps.max_slave_planes = 1; 1285 ctx->dc->caps.max_slave_yuv_planes = 1; 1286 ctx->dc->caps.max_slave_rgb_planes = 0; 1287 1288 return true; 1289 } 1290 1291 static void bw_calcs_data_update_from_pplib(struct dc *dc) 1292 { 1293 struct dm_pp_clock_levels clks = {0}; 1294 1295 /*do system clock*/ 1296 dm_pp_get_clock_levels_by_type( 1297 dc->ctx, 1298 DM_PP_CLOCK_TYPE_ENGINE_CLK, 1299 &clks); 1300 /* convert all the clock fro kHz to fix point mHz */ 1301 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 1302 clks.clocks_in_khz[clks.num_levels-1], 1000); 1303 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 1304 clks.clocks_in_khz[clks.num_levels/8], 1000); 1305 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 1306 clks.clocks_in_khz[clks.num_levels*2/8], 1000); 1307 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 1308 clks.clocks_in_khz[clks.num_levels*3/8], 1000); 1309 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 1310 clks.clocks_in_khz[clks.num_levels*4/8], 1000); 1311 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 1312 clks.clocks_in_khz[clks.num_levels*5/8], 1000); 1313 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 1314 clks.clocks_in_khz[clks.num_levels*6/8], 1000); 1315 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 1316 clks.clocks_in_khz[0], 1000); 1317 dc->sclk_lvls = clks; 1318 1319 /*do display clock*/ 1320 dm_pp_get_clock_levels_by_type( 1321 dc->ctx, 1322 DM_PP_CLOCK_TYPE_DISPLAY_CLK, 1323 &clks); 1324 dc->bw_vbios->high_voltage_max_dispclk = bw_frc_to_fixed( 1325 clks.clocks_in_khz[clks.num_levels-1], 1000); 1326 dc->bw_vbios->mid_voltage_max_dispclk = bw_frc_to_fixed( 1327 clks.clocks_in_khz[clks.num_levels>>1], 1000); 1328 dc->bw_vbios->low_voltage_max_dispclk = bw_frc_to_fixed( 1329 clks.clocks_in_khz[0], 1000); 1330 1331 /*do memory clock*/ 1332 dm_pp_get_clock_levels_by_type( 1333 dc->ctx, 1334 DM_PP_CLOCK_TYPE_MEMORY_CLK, 1335 &clks); 1336 1337 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 1338 clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER_CZ, 1000); 1339 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 1340 clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER_CZ, 1341 1000); 1342 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 1343 clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER_CZ, 1344 1000); 1345 } 1346 1347 static const struct resource_caps *dce110_resource_cap( 1348 struct hw_asic_id *asic_id) 1349 { 1350 if (ASIC_REV_IS_STONEY(asic_id->hw_internal_rev)) 1351 return &stoney_resource_cap; 1352 else 1353 return &carrizo_resource_cap; 1354 } 1355 1356 static bool dce110_resource_construct( 1357 uint8_t num_virtual_links, 1358 struct dc *dc, 1359 struct dce110_resource_pool *pool, 1360 struct hw_asic_id asic_id) 1361 { 1362 (void)asic_id; 1363 unsigned int i; 1364 struct dc_context *ctx = dc->ctx; 1365 struct dc_bios *bp; 1366 1367 ctx->dc_bios->regs = &bios_regs; 1368 1369 pool->base.res_cap = dce110_resource_cap(&ctx->asic_id); 1370 pool->base.funcs = &dce110_res_pool_funcs; 1371 1372 /************************************************* 1373 * Resource + asic cap harcoding * 1374 *************************************************/ 1375 1376 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1377 pool->base.underlay_pipe_index = pool->base.pipe_count; 1378 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; 1379 dc->caps.max_downscale_ratio = 150; 1380 dc->caps.i2c_speed_in_khz = 40; 1381 dc->caps.i2c_speed_in_khz_hdcp = 40; 1382 dc->caps.max_cursor_size = 128; 1383 dc->caps.min_horizontal_blanking_period = 80; 1384 dc->caps.is_apu = true; 1385 dc->caps.extended_aux_timeout_support = false; 1386 dc->debug = debug_defaults; 1387 dc->check_config = config_defaults; 1388 1389 /************************************************* 1390 * Create resources * 1391 *************************************************/ 1392 1393 bp = ctx->dc_bios; 1394 1395 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) { 1396 pool->base.dp_clock_source = 1397 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1398 1399 pool->base.clock_sources[0] = 1400 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, 1401 &clk_src_regs[0], false); 1402 pool->base.clock_sources[1] = 1403 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, 1404 &clk_src_regs[1], false); 1405 1406 pool->base.clk_src_count = 2; 1407 1408 /* TODO: find out if CZ support 3 PLLs */ 1409 } 1410 1411 if (pool->base.dp_clock_source == NULL) { 1412 dm_error("DC: failed to create dp clock source!\n"); 1413 BREAK_TO_DEBUGGER(); 1414 goto res_create_fail; 1415 } 1416 1417 for (i = 0; i < pool->base.clk_src_count; i++) { 1418 if (pool->base.clock_sources[i] == NULL) { 1419 dm_error("DC: failed to create clock sources!\n"); 1420 BREAK_TO_DEBUGGER(); 1421 goto res_create_fail; 1422 } 1423 } 1424 1425 pool->base.dmcu = dce_dmcu_create(ctx, 1426 &dmcu_regs, 1427 &dmcu_shift, 1428 &dmcu_mask); 1429 if (pool->base.dmcu == NULL) { 1430 dm_error("DC: failed to create dmcu!\n"); 1431 BREAK_TO_DEBUGGER(); 1432 goto res_create_fail; 1433 } 1434 1435 pool->base.abm = dce_abm_create(ctx, 1436 &abm_regs, 1437 &abm_shift, 1438 &abm_mask); 1439 if (pool->base.abm == NULL) { 1440 dm_error("DC: failed to create abm!\n"); 1441 BREAK_TO_DEBUGGER(); 1442 goto res_create_fail; 1443 } 1444 1445 { 1446 struct irq_service_init_data init_data; 1447 init_data.ctx = dc->ctx; 1448 pool->base.irqs = dal_irq_service_dce110_create(&init_data); 1449 if (!pool->base.irqs) 1450 goto res_create_fail; 1451 } 1452 1453 for (i = 0; i < pool->base.pipe_count; i++) { 1454 pool->base.timing_generators[i] = dce110_timing_generator_create( 1455 ctx, i, &dce110_tg_offsets[i]); 1456 if (pool->base.timing_generators[i] == NULL) { 1457 BREAK_TO_DEBUGGER(); 1458 dm_error("DC: failed to create tg!\n"); 1459 goto res_create_fail; 1460 } 1461 1462 pool->base.mis[i] = dce110_mem_input_create(ctx, i); 1463 if (pool->base.mis[i] == NULL) { 1464 BREAK_TO_DEBUGGER(); 1465 dm_error( 1466 "DC: failed to create memory input!\n"); 1467 goto res_create_fail; 1468 } 1469 1470 pool->base.ipps[i] = dce110_ipp_create(ctx, i); 1471 if (pool->base.ipps[i] == NULL) { 1472 BREAK_TO_DEBUGGER(); 1473 dm_error( 1474 "DC: failed to create input pixel processor!\n"); 1475 goto res_create_fail; 1476 } 1477 1478 pool->base.transforms[i] = dce110_transform_create(ctx, i); 1479 if (pool->base.transforms[i] == NULL) { 1480 BREAK_TO_DEBUGGER(); 1481 dm_error( 1482 "DC: failed to create transform!\n"); 1483 goto res_create_fail; 1484 } 1485 1486 pool->base.opps[i] = dce110_opp_create(ctx, i); 1487 if (pool->base.opps[i] == NULL) { 1488 BREAK_TO_DEBUGGER(); 1489 dm_error( 1490 "DC: failed to create output pixel processor!\n"); 1491 goto res_create_fail; 1492 } 1493 } 1494 1495 for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { 1496 pool->base.engines[i] = dce110_aux_engine_create(ctx, i); 1497 if (pool->base.engines[i] == NULL) { 1498 BREAK_TO_DEBUGGER(); 1499 dm_error( 1500 "DC:failed to create aux engine!!\n"); 1501 goto res_create_fail; 1502 } 1503 pool->base.hw_i2cs[i] = dce110_i2c_hw_create(ctx, i); 1504 if (pool->base.hw_i2cs[i] == NULL) { 1505 BREAK_TO_DEBUGGER(); 1506 dm_error( 1507 "DC:failed to create i2c engine!!\n"); 1508 goto res_create_fail; 1509 } 1510 pool->base.sw_i2cs[i] = NULL; 1511 } 1512 1513 if (dc->config.fbc_support) 1514 dc->fbc_compressor = dce110_compressor_create(ctx); 1515 1516 if (!underlay_create(ctx, &pool->base)) 1517 goto res_create_fail; 1518 1519 if (!resource_construct(num_virtual_links, dc, &pool->base, 1520 &res_create_funcs)) 1521 goto res_create_fail; 1522 1523 /* Create hardware sequencer */ 1524 dce110_hw_sequencer_construct(dc); 1525 1526 dc->caps.max_planes = pool->base.pipe_count; 1527 1528 for (i = 0; i < pool->base.underlay_pipe_index; ++i) 1529 dc->caps.planes[i] = plane_cap; 1530 1531 dc->caps.planes[pool->base.underlay_pipe_index] = underlay_plane_cap; 1532 1533 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); 1534 1535 bw_calcs_data_update_from_pplib(dc); 1536 1537 return true; 1538 1539 res_create_fail: 1540 dce110_resource_destruct(pool); 1541 return false; 1542 } 1543 1544 struct resource_pool *dce110_create_resource_pool( 1545 uint8_t num_virtual_links, 1546 struct dc *dc, 1547 struct hw_asic_id asic_id) 1548 { 1549 struct dce110_resource_pool *pool = 1550 kzalloc_obj(struct dce110_resource_pool); 1551 1552 if (!pool) 1553 return NULL; 1554 1555 if (dce110_resource_construct(num_virtual_links, dc, pool, asic_id)) 1556 return &pool->base; 1557 1558 kfree(pool); 1559 BREAK_TO_DEBUGGER(); 1560 return NULL; 1561 } 1562