1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27
28 #include "link_encoder.h"
29 #include "stream_encoder.h"
30
31 #include "resource.h"
32 #include "clk_mgr.h"
33 #include "include/irq_service_interface.h"
34 #include "dio/virtual/virtual_stream_encoder.h"
35 #include "dce110/dce110_resource.h"
36 #include "dce110/dce110_timing_generator.h"
37 #include "irq/dce110/irq_service_dce110.h"
38 #include "dce/dce_link_encoder.h"
39 #include "dce/dce_stream_encoder.h"
40 #include "dce/dce_mem_input.h"
41 #include "dce/dce_ipp.h"
42 #include "dce/dce_transform.h"
43 #include "dce/dce_opp.h"
44 #include "dce/dce_clock_source.h"
45 #include "dce/dce_audio.h"
46 #include "dce/dce_hwseq.h"
47 #include "dce100/dce100_hwseq.h"
48 #include "dce/dce_panel_cntl.h"
49
50 #include "reg_helper.h"
51
52 #include "dce/dce_10_0_d.h"
53 #include "dce/dce_10_0_sh_mask.h"
54
55 #include "dce/dce_dmcu.h"
56 #include "dce/dce_aux.h"
57 #include "dce/dce_abm.h"
58 #include "dce/dce_i2c.h"
59
60 #include "dce100_resource.h"
61
62 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
63 #include "gmc/gmc_8_2_d.h"
64 #include "gmc/gmc_8_2_sh_mask.h"
65 #endif
66
67 #ifndef mmDP_DPHY_INTERNAL_CTRL
68 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
69 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
70 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
71 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
72 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
73 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
74 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
75 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
76 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
77 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
78 #endif
79
80 #ifndef mmBIOS_SCRATCH_2
81 #define mmBIOS_SCRATCH_0 0x05C9
82 #define mmBIOS_SCRATCH_2 0x05CB
83 #define mmBIOS_SCRATCH_3 0x05CC
84 #define mmBIOS_SCRATCH_6 0x05CF
85 #endif
86
87 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
88 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
89 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
90 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC
91 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC
92 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC
93 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC
94 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC
95 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC
96 #endif
97
98 #ifndef mmDP_DPHY_FAST_TRAINING
99 #define mmDP_DPHY_FAST_TRAINING 0x4ABC
100 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC
101 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC
102 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC
103 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC
104 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC
105 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC
106 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC
107 #endif
108
109 static const struct dce110_timing_generator_offsets dce100_tg_offsets[] = {
110 {
111 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
112 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
113 },
114 {
115 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
116 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
117 },
118 {
119 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
120 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
121 },
122 {
123 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
124 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
125 },
126 {
127 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
128 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
129 },
130 {
131 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
132 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
133 }
134 };
135
136 /* set register offset */
137 #define SR(reg_name)\
138 .reg_name = mm ## reg_name
139
140 /* set register offset with instance */
141 #define SRI(reg_name, block, id)\
142 .reg_name = mm ## block ## id ## _ ## reg_name
143
144 #define ipp_regs(id)\
145 [id] = {\
146 IPP_DCE100_REG_LIST_DCE_BASE(id)\
147 }
148
149 static const struct dce_ipp_registers ipp_regs[] = {
150 ipp_regs(0),
151 ipp_regs(1),
152 ipp_regs(2),
153 ipp_regs(3),
154 ipp_regs(4),
155 ipp_regs(5)
156 };
157
158 static const struct dce_ipp_shift ipp_shift = {
159 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
160 };
161
162 static const struct dce_ipp_mask ipp_mask = {
163 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
164 };
165
166 #define transform_regs(id)\
167 [id] = {\
168 XFM_COMMON_REG_LIST_DCE100(id)\
169 }
170
171 static const struct dce_transform_registers xfm_regs[] = {
172 transform_regs(0),
173 transform_regs(1),
174 transform_regs(2),
175 transform_regs(3),
176 transform_regs(4),
177 transform_regs(5)
178 };
179
180 static const struct dce_transform_shift xfm_shift = {
181 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
182 };
183
184 static const struct dce_transform_mask xfm_mask = {
185 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK)
186 };
187
188 #define aux_regs(id)\
189 [id] = {\
190 AUX_REG_LIST(id)\
191 }
192
193 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
194 aux_regs(0),
195 aux_regs(1),
196 aux_regs(2),
197 aux_regs(3),
198 aux_regs(4),
199 aux_regs(5)
200 };
201
202 #define hpd_regs(id)\
203 [id] = {\
204 HPD_REG_LIST(id)\
205 }
206
207 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
208 hpd_regs(0),
209 hpd_regs(1),
210 hpd_regs(2),
211 hpd_regs(3),
212 hpd_regs(4),
213 hpd_regs(5)
214 };
215
216 #define link_regs(id)\
217 [id] = {\
218 LE_DCE100_REG_LIST(id)\
219 }
220
221 static const struct dce110_link_enc_registers link_enc_regs[] = {
222 link_regs(0),
223 link_regs(1),
224 link_regs(2),
225 link_regs(3),
226 link_regs(4),
227 link_regs(5),
228 link_regs(6),
229 {0}
230 };
231
232 #define stream_enc_regs(id)\
233 [id] = {\
234 SE_COMMON_REG_LIST_DCE_BASE(id),\
235 .AFMT_CNTL = 0,\
236 }
237
238 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
239 stream_enc_regs(0),
240 stream_enc_regs(1),
241 stream_enc_regs(2),
242 stream_enc_regs(3),
243 stream_enc_regs(4),
244 stream_enc_regs(5),
245 stream_enc_regs(6),
246 {SR(DAC_SOURCE_SELECT),} /* DACA */
247 };
248
249 static const struct dce_stream_encoder_shift se_shift = {
250 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT)
251 };
252
253 static const struct dce_stream_encoder_mask se_mask = {
254 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
255 };
256
257 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
258 { DCE_PANEL_CNTL_REG_LIST() }
259 };
260
261 static const struct dce_panel_cntl_shift panel_cntl_shift = {
262 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
263 };
264
265 static const struct dce_panel_cntl_mask panel_cntl_mask = {
266 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
267 };
268
269 #define opp_regs(id)\
270 [id] = {\
271 OPP_DCE_100_REG_LIST(id),\
272 }
273
274 static const struct dce_opp_registers opp_regs[] = {
275 opp_regs(0),
276 opp_regs(1),
277 opp_regs(2),
278 opp_regs(3),
279 opp_regs(4),
280 opp_regs(5)
281 };
282
283 static const struct dce_opp_shift opp_shift = {
284 OPP_COMMON_MASK_SH_LIST_DCE_100(__SHIFT)
285 };
286
287 static const struct dce_opp_mask opp_mask = {
288 OPP_COMMON_MASK_SH_LIST_DCE_100(_MASK)
289 };
290 #define aux_engine_regs(id)\
291 [id] = {\
292 AUX_COMMON_REG_LIST(id), \
293 .AUX_RESET_MASK = 0 \
294 }
295
296 static const struct dce110_aux_registers aux_engine_regs[] = {
297 aux_engine_regs(0),
298 aux_engine_regs(1),
299 aux_engine_regs(2),
300 aux_engine_regs(3),
301 aux_engine_regs(4),
302 aux_engine_regs(5)
303 };
304
305 #define audio_regs(id)\
306 [id] = {\
307 AUD_COMMON_REG_LIST(id)\
308 }
309
310 static const struct dce_audio_registers audio_regs[] = {
311 audio_regs(0),
312 audio_regs(1),
313 audio_regs(2),
314 audio_regs(3),
315 audio_regs(4),
316 audio_regs(5),
317 audio_regs(6),
318 };
319
320 static const struct dce_audio_shift audio_shift = {
321 AUD_COMMON_MASK_SH_LIST(__SHIFT)
322 };
323
324 static const struct dce_audio_mask audio_mask = {
325 AUD_COMMON_MASK_SH_LIST(_MASK)
326 };
327
328 #define clk_src_regs(id)\
329 [id] = {\
330 CS_COMMON_REG_LIST_DCE_100_110(id),\
331 }
332
333 static const struct dce110_clk_src_regs clk_src_regs[] = {
334 clk_src_regs(0),
335 clk_src_regs(1),
336 clk_src_regs(2)
337 };
338
339 static const struct dce110_clk_src_shift cs_shift = {
340 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
341 };
342
343 static const struct dce110_clk_src_mask cs_mask = {
344 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
345 };
346
347 static const struct dce_dmcu_registers dmcu_regs = {
348 DMCU_DCE110_COMMON_REG_LIST()
349 };
350
351 static const struct dce_dmcu_shift dmcu_shift = {
352 DMCU_MASK_SH_LIST_DCE110(__SHIFT)
353 };
354
355 static const struct dce_dmcu_mask dmcu_mask = {
356 DMCU_MASK_SH_LIST_DCE110(_MASK)
357 };
358
359 static const struct dce_abm_registers abm_regs = {
360 ABM_DCE110_COMMON_REG_LIST()
361 };
362
363 static const struct dce_abm_shift abm_shift = {
364 ABM_MASK_SH_LIST_DCE110(__SHIFT)
365 };
366
367 static const struct dce_abm_mask abm_mask = {
368 ABM_MASK_SH_LIST_DCE110(_MASK)
369 };
370
371 #define DCFE_MEM_PWR_CTRL_REG_BASE 0x1b03
372
373 static const struct bios_registers bios_regs = {
374 .BIOS_SCRATCH_0 = mmBIOS_SCRATCH_0,
375 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
376 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
377 };
378
379 static const struct resource_caps res_cap = {
380 .num_timing_generator = 6,
381 .num_audio = 6,
382 .num_analog_stream_encoder = 1,
383 .num_stream_encoder = 6,
384 .num_pll = 3,
385 .num_ddc = 6,
386 };
387
388 static const struct dc_plane_cap plane_cap = {
389 .type = DC_PLANE_TYPE_DCE_RGB,
390
391 .pixel_format_support = {
392 .argb8888 = true,
393 .nv12 = false,
394 .fp16 = true
395 },
396
397 .max_upscale_factor = {
398 .argb8888 = 16000,
399 .nv12 = 1,
400 .fp16 = 1
401 },
402
403 .max_downscale_factor = {
404 .argb8888 = 250,
405 .nv12 = 1,
406 .fp16 = 1
407 }
408 };
409
410 static const struct dc_debug_options debug_defaults = { 0 };
411
412 static const struct dc_check_config config_defaults = {
413 .enable_legacy_fast_update = true,
414 };
415
416 #define CTX ctx
417 #define REG(reg) mm ## reg
418
419 #ifndef mmCC_DC_HDMI_STRAPS
420 #define mmCC_DC_HDMI_STRAPS 0x1918
421 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
422 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
423 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
424 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
425 #endif
426
map_transmitter_id_to_phy_instance(enum transmitter transmitter)427 static int map_transmitter_id_to_phy_instance(
428 enum transmitter transmitter)
429 {
430 switch (transmitter) {
431 case TRANSMITTER_UNIPHY_A:
432 return 0;
433 case TRANSMITTER_UNIPHY_B:
434 return 1;
435 case TRANSMITTER_UNIPHY_C:
436 return 2;
437 case TRANSMITTER_UNIPHY_D:
438 return 3;
439 case TRANSMITTER_UNIPHY_E:
440 return 4;
441 case TRANSMITTER_UNIPHY_F:
442 return 5;
443 case TRANSMITTER_UNIPHY_G:
444 return 6;
445 default:
446 ASSERT(0);
447 return 0;
448 }
449 }
450
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)451 static void read_dce_straps(
452 struct dc_context *ctx,
453 struct resource_straps *straps)
454 {
455 REG_GET_2(CC_DC_HDMI_STRAPS,
456 HDMI_DISABLE, &straps->hdmi_disable,
457 AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
458
459 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
460 }
461
create_audio(struct dc_context * ctx,unsigned int inst)462 static struct audio *create_audio(
463 struct dc_context *ctx, unsigned int inst)
464 {
465 return dce_audio_create(ctx, inst,
466 &audio_regs[inst], &audio_shift, &audio_mask);
467 }
468
dce100_timing_generator_create(struct dc_context * ctx,uint32_t instance,const struct dce110_timing_generator_offsets * offsets)469 static struct timing_generator *dce100_timing_generator_create(
470 struct dc_context *ctx,
471 uint32_t instance,
472 const struct dce110_timing_generator_offsets *offsets)
473 {
474 struct dce110_timing_generator *tg110 =
475 kzalloc_obj(struct dce110_timing_generator);
476
477 if (!tg110)
478 return NULL;
479
480 dce110_timing_generator_construct(tg110, ctx, instance, offsets);
481 return &tg110->base;
482 }
483
dce100_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)484 static struct stream_encoder *dce100_stream_encoder_create(
485 enum engine_id eng_id,
486 struct dc_context *ctx)
487 {
488 struct dce110_stream_encoder *enc110 =
489 kzalloc_obj(struct dce110_stream_encoder);
490
491 if (!enc110)
492 return NULL;
493
494 if (eng_id == ENGINE_ID_DACA || eng_id == ENGINE_ID_DACB) {
495 dce110_analog_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
496 &stream_enc_regs[eng_id], &se_shift, &se_mask);
497 return &enc110->base;
498 }
499
500 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
501 &stream_enc_regs[eng_id], &se_shift, &se_mask);
502 return &enc110->base;
503 }
504
505 #define SRII(reg_name, block, id)\
506 .reg_name[id] = mm ## block ## id ## _ ## reg_name
507
508 static const struct dce_hwseq_registers hwseq_reg = {
509 HWSEQ_DCE10_REG_LIST()
510 };
511
512 static const struct dce_hwseq_shift hwseq_shift = {
513 HWSEQ_DCE10_MASK_SH_LIST(__SHIFT)
514 };
515
516 static const struct dce_hwseq_mask hwseq_mask = {
517 HWSEQ_DCE10_MASK_SH_LIST(_MASK)
518 };
519
dce100_hwseq_create(struct dc_context * ctx)520 static struct dce_hwseq *dce100_hwseq_create(
521 struct dc_context *ctx)
522 {
523 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);
524
525 if (hws) {
526 hws->ctx = ctx;
527 hws->regs = &hwseq_reg;
528 hws->shifts = &hwseq_shift;
529 hws->masks = &hwseq_mask;
530 }
531 return hws;
532 }
533
534 static const struct resource_create_funcs res_create_funcs = {
535 .read_dce_straps = read_dce_straps,
536 .create_audio = create_audio,
537 .create_stream_encoder = dce100_stream_encoder_create,
538 .create_hwseq = dce100_hwseq_create,
539 };
540
541 #define mi_inst_regs(id) { \
542 MI_DCE8_REG_LIST(id), \
543 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
544 }
545 static const struct dce_mem_input_registers mi_regs[] = {
546 mi_inst_regs(0),
547 mi_inst_regs(1),
548 mi_inst_regs(2),
549 mi_inst_regs(3),
550 mi_inst_regs(4),
551 mi_inst_regs(5),
552 };
553
554 static const struct dce_mem_input_shift mi_shifts = {
555 MI_DCE8_MASK_SH_LIST(__SHIFT),
556 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
557 };
558
559 static const struct dce_mem_input_mask mi_masks = {
560 MI_DCE8_MASK_SH_LIST(_MASK),
561 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
562 };
563
564 static const struct dce110_aux_registers_shift aux_shift = {
565 DCE10_AUX_MASK_SH_LIST(__SHIFT)
566 };
567
568 static const struct dce110_aux_registers_mask aux_mask = {
569 DCE10_AUX_MASK_SH_LIST(_MASK)
570 };
571
dce100_mem_input_create(struct dc_context * ctx,uint32_t inst)572 static struct mem_input *dce100_mem_input_create(
573 struct dc_context *ctx,
574 uint32_t inst)
575 {
576 struct dce_mem_input *dce_mi = kzalloc_obj(struct dce_mem_input);
577
578 if (!dce_mi) {
579 BREAK_TO_DEBUGGER();
580 return NULL;
581 }
582
583 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
584 dce_mi->wa.single_head_rdreq_dmif_limit = 2;
585 return &dce_mi->base;
586 }
587
dce100_transform_destroy(struct transform ** xfm)588 static void dce100_transform_destroy(struct transform **xfm)
589 {
590 kfree(TO_DCE_TRANSFORM(*xfm));
591 *xfm = NULL;
592 }
593
dce100_transform_create(struct dc_context * ctx,uint32_t inst)594 static struct transform *dce100_transform_create(
595 struct dc_context *ctx,
596 uint32_t inst)
597 {
598 struct dce_transform *transform =
599 kzalloc_obj(struct dce_transform);
600
601 if (!transform)
602 return NULL;
603
604 dce_transform_construct(transform, ctx, inst,
605 &xfm_regs[inst], &xfm_shift, &xfm_mask);
606 return &transform->base;
607 }
608
dce100_ipp_create(struct dc_context * ctx,uint32_t inst)609 static struct input_pixel_processor *dce100_ipp_create(
610 struct dc_context *ctx, uint32_t inst)
611 {
612 struct dce_ipp *ipp = kzalloc_obj(struct dce_ipp);
613
614 if (!ipp) {
615 BREAK_TO_DEBUGGER();
616 return NULL;
617 }
618
619 dce_ipp_construct(ipp, ctx, inst,
620 &ipp_regs[inst], &ipp_shift, &ipp_mask);
621 return &ipp->base;
622 }
623
624 static const struct encoder_feature_support link_enc_feature = {
625 .max_hdmi_deep_color = COLOR_DEPTH_121212,
626 .max_hdmi_pixel_clock = 300000,
627 .flags.bits.IS_HBR2_CAPABLE = true,
628 .flags.bits.IS_TPS3_CAPABLE = true
629 };
630
dce100_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)631 static struct link_encoder *dce100_link_encoder_create(
632 struct dc_context *ctx,
633 const struct encoder_init_data *enc_init_data)
634 {
635 struct dce110_link_encoder *enc110 =
636 kzalloc_obj(struct dce110_link_encoder);
637 int link_regs_id;
638
639 if (!enc110)
640 return NULL;
641
642 if (enc_init_data->connector.id == CONNECTOR_ID_VGA &&
643 enc_init_data->analog_engine != ENGINE_ID_UNKNOWN) {
644 dce110_link_encoder_construct(enc110,
645 enc_init_data,
646 &link_enc_feature,
647 &link_enc_regs[ENGINE_ID_DACA],
648 NULL,
649 NULL);
650 return &enc110->base;
651 }
652
653 link_regs_id =
654 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
655
656 dce110_link_encoder_construct(enc110,
657 enc_init_data,
658 &link_enc_feature,
659 &link_enc_regs[link_regs_id],
660 &link_enc_aux_regs[enc_init_data->channel - 1],
661 enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs) ?
662 NULL : &link_enc_hpd_regs[enc_init_data->hpd_source]);
663 return &enc110->base;
664 }
665
dce100_panel_cntl_create(const struct panel_cntl_init_data * init_data)666 static struct panel_cntl *dce100_panel_cntl_create(const struct panel_cntl_init_data *init_data)
667 {
668 struct dce_panel_cntl *panel_cntl =
669 kzalloc_obj(struct dce_panel_cntl);
670
671 if (!panel_cntl)
672 return NULL;
673
674 dce_panel_cntl_construct(panel_cntl,
675 init_data,
676 &panel_cntl_regs[init_data->inst],
677 &panel_cntl_shift,
678 &panel_cntl_mask);
679
680 return &panel_cntl->base;
681 }
682
dce100_opp_create(struct dc_context * ctx,uint32_t inst)683 static struct output_pixel_processor *dce100_opp_create(
684 struct dc_context *ctx,
685 uint32_t inst)
686 {
687 struct dce110_opp *opp =
688 kzalloc_obj(struct dce110_opp);
689
690 if (!opp)
691 return NULL;
692
693 dce110_opp_construct(opp,
694 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
695 return &opp->base;
696 }
697
dce100_aux_engine_create(struct dc_context * ctx,uint32_t inst)698 static struct dce_aux *dce100_aux_engine_create(
699 struct dc_context *ctx,
700 uint32_t inst)
701 {
702 struct aux_engine_dce110 *aux_engine =
703 kzalloc_obj(struct aux_engine_dce110);
704
705 if (!aux_engine)
706 return NULL;
707
708 dce110_aux_engine_construct(aux_engine, ctx, inst,
709 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
710 &aux_engine_regs[inst],
711 &aux_mask,
712 &aux_shift,
713 ctx->dc->caps.extended_aux_timeout_support);
714
715 return &aux_engine->base;
716 }
717 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
718
719 static const struct dce_i2c_registers i2c_hw_regs[] = {
720 i2c_inst_regs(1),
721 i2c_inst_regs(2),
722 i2c_inst_regs(3),
723 i2c_inst_regs(4),
724 i2c_inst_regs(5),
725 i2c_inst_regs(6),
726 };
727
728 static const struct dce_i2c_shift i2c_shifts = {
729 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
730 };
731
732 static const struct dce_i2c_mask i2c_masks = {
733 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
734 };
735
dce100_i2c_hw_create(struct dc_context * ctx,uint32_t inst)736 static struct dce_i2c_hw *dce100_i2c_hw_create(
737 struct dc_context *ctx,
738 uint32_t inst)
739 {
740 struct dce_i2c_hw *dce_i2c_hw =
741 kzalloc_obj(struct dce_i2c_hw);
742
743 if (!dce_i2c_hw)
744 return NULL;
745
746 dce100_i2c_hw_construct(dce_i2c_hw, ctx, inst,
747 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
748
749 return dce_i2c_hw;
750 }
dce100_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)751 static struct clock_source *dce100_clock_source_create(
752 struct dc_context *ctx,
753 struct dc_bios *bios,
754 enum clock_source_id id,
755 const struct dce110_clk_src_regs *regs,
756 bool dp_clk_src)
757 {
758 struct dce110_clk_src *clk_src =
759 kzalloc_obj(struct dce110_clk_src);
760
761 if (!clk_src)
762 return NULL;
763
764 if (dce110_clk_src_construct(clk_src, ctx, bios, id,
765 regs, &cs_shift, &cs_mask)) {
766 clk_src->base.dp_clk_src = dp_clk_src;
767 return &clk_src->base;
768 }
769
770 kfree(clk_src);
771 BREAK_TO_DEBUGGER();
772 return NULL;
773 }
774
dce100_clock_source_destroy(struct clock_source ** clk_src)775 static void dce100_clock_source_destroy(struct clock_source **clk_src)
776 {
777 kfree(TO_DCE110_CLK_SRC(*clk_src));
778 *clk_src = NULL;
779 }
780
dce100_resource_destruct(struct dce110_resource_pool * pool)781 static void dce100_resource_destruct(struct dce110_resource_pool *pool)
782 {
783 unsigned int i;
784
785 for (i = 0; i < pool->base.pipe_count; i++) {
786 if (pool->base.opps[i] != NULL)
787 dce110_opp_destroy(&pool->base.opps[i]);
788
789 if (pool->base.transforms[i] != NULL)
790 dce100_transform_destroy(&pool->base.transforms[i]);
791
792 if (pool->base.ipps[i] != NULL)
793 dce_ipp_destroy(&pool->base.ipps[i]);
794
795 if (pool->base.mis[i] != NULL) {
796 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
797 pool->base.mis[i] = NULL;
798 }
799
800 if (pool->base.timing_generators[i] != NULL) {
801 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
802 pool->base.timing_generators[i] = NULL;
803 }
804 }
805
806 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
807 if (pool->base.engines[i] != NULL)
808 dce110_engine_destroy(&pool->base.engines[i]);
809 if (pool->base.hw_i2cs[i] != NULL) {
810 kfree(pool->base.hw_i2cs[i]);
811 pool->base.hw_i2cs[i] = NULL;
812 }
813 if (pool->base.sw_i2cs[i] != NULL) {
814 kfree(pool->base.sw_i2cs[i]);
815 pool->base.sw_i2cs[i] = NULL;
816 }
817 }
818
819 for (i = 0; i < pool->base.stream_enc_count; i++) {
820 if (pool->base.stream_enc[i] != NULL)
821 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
822 }
823
824 for (i = 0; i < pool->base.clk_src_count; i++) {
825 if (pool->base.clock_sources[i] != NULL)
826 dce100_clock_source_destroy(&pool->base.clock_sources[i]);
827 }
828
829 if (pool->base.dp_clock_source != NULL)
830 dce100_clock_source_destroy(&pool->base.dp_clock_source);
831
832 for (i = 0; i < pool->base.audio_count; i++) {
833 if (pool->base.audios[i] != NULL)
834 dce_aud_destroy(&pool->base.audios[i]);
835 }
836
837 if (pool->base.abm != NULL)
838 dce_abm_destroy(&pool->base.abm);
839
840 if (pool->base.dmcu != NULL)
841 dce_dmcu_destroy(&pool->base.dmcu);
842
843 if (pool->base.irqs != NULL)
844 dal_irq_service_destroy(&pool->base.irqs);
845 }
846
build_mapped_resource(const struct dc * dc,struct dc_state * context,struct dc_stream_state * stream)847 static enum dc_status build_mapped_resource(
848 const struct dc *dc,
849 struct dc_state *context,
850 struct dc_stream_state *stream)
851 {
852 struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);
853
854 if (!pipe_ctx)
855 return DC_ERROR_UNEXPECTED;
856
857 dce110_resource_build_pipe_hw_param(pipe_ctx);
858
859 resource_build_info_frame(pipe_ctx);
860
861 return DC_OK;
862 }
863
dce100_validate_bandwidth(struct dc * dc,struct dc_state * context,enum dc_validate_mode validate_mode)864 enum dc_status dce100_validate_bandwidth(
865 struct dc *dc,
866 struct dc_state *context,
867 enum dc_validate_mode validate_mode)
868 {
869 int i;
870 bool at_least_one_pipe = false;
871 struct dc_stream_state *stream = NULL;
872 const uint32_t max_pix_clk_khz = max(dc->clk_mgr->clks.max_supported_dispclk_khz, 400000);
873
874 for (i = 0; i < dc->res_pool->pipe_count; i++) {
875 stream = context->res_ctx.pipe_ctx[i].stream;
876 if (stream) {
877 at_least_one_pipe = true;
878
879 if (stream->timing.pix_clk_100hz >= max_pix_clk_khz * 10)
880 return DC_FAIL_BANDWIDTH_VALIDATE;
881 }
882 }
883
884 if (at_least_one_pipe) {
885 /* TODO implement when needed but for now hardcode max value*/
886 context->bw_ctx.bw.dce.dispclk_khz = 681000;
887 context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;
888 } else {
889 /* On DCE 6.0 and 6.4 the PLL0 is both the display engine clock and
890 * the DP clock, and shouldn't be turned off. Just select the display
891 * clock value from its low power mode.
892 */
893 if (dc->ctx->dce_version == DCE_VERSION_6_0 ||
894 dc->ctx->dce_version == DCE_VERSION_6_4)
895 context->bw_ctx.bw.dce.dispclk_khz = 352000;
896 else
897 context->bw_ctx.bw.dce.dispclk_khz = 0;
898
899 context->bw_ctx.bw.dce.yclk_khz = 0;
900 }
901
902 return DC_OK;
903 }
904
dce100_validate_surface_sets(struct dc_state * context)905 static bool dce100_validate_surface_sets(
906 struct dc_state *context)
907 {
908 int i;
909
910 for (i = 0; i < context->stream_count; i++) {
911 if (context->stream_status[i].plane_count == 0)
912 continue;
913
914 if (context->stream_status[i].plane_count > 1)
915 return false;
916
917 if (context->stream_status[i].plane_states[0]->format
918 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
919 return false;
920 }
921
922 return true;
923 }
924
dce100_validate_global(struct dc * dc,struct dc_state * context)925 enum dc_status dce100_validate_global(
926 struct dc *dc,
927 struct dc_state *context)
928 {
929 if (!dce100_validate_surface_sets(context))
930 return DC_FAIL_SURFACE_VALIDATE;
931
932 return DC_OK;
933 }
934
dce100_add_stream_to_ctx(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * dc_stream)935 enum dc_status dce100_add_stream_to_ctx(
936 struct dc *dc,
937 struct dc_state *new_ctx,
938 struct dc_stream_state *dc_stream)
939 {
940 enum dc_status result = DC_ERROR_UNEXPECTED;
941
942 result = resource_map_pool_resources(dc, new_ctx, dc_stream);
943
944 if (result == DC_OK)
945 result = resource_map_clock_resources(dc, new_ctx, dc_stream);
946
947 if (result == DC_OK)
948 result = build_mapped_resource(dc, new_ctx, dc_stream);
949
950 return result;
951 }
952
dce100_destroy_resource_pool(struct resource_pool ** pool)953 static void dce100_destroy_resource_pool(struct resource_pool **pool)
954 {
955 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
956
957 dce100_resource_destruct(dce110_pool);
958 kfree(dce110_pool);
959 *pool = NULL;
960 }
961
dce100_validate_plane(const struct dc_plane_state * plane_state,struct dc_caps * caps)962 enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps)
963 {
964
965 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
966 return DC_OK;
967
968 return DC_FAIL_SURFACE_VALIDATE;
969 }
970
dce100_find_first_free_match_stream_enc_for_link(struct resource_context * res_ctx,const struct resource_pool * pool,struct dc_stream_state * stream)971 struct stream_encoder *dce100_find_first_free_match_stream_enc_for_link(
972 struct resource_context *res_ctx,
973 const struct resource_pool *pool,
974 struct dc_stream_state *stream)
975 {
976 int i;
977 int j = -1;
978 struct dc_link *link = stream->link;
979 enum engine_id preferred_engine = link->link_enc->preferred_engine;
980
981 /* Prefer analog engine if the link encoder has one.
982 * Otherwise, it's an external encoder.
983 */
984 if (dc_is_rgb_signal(stream->signal) && link->link_enc->analog_engine != ENGINE_ID_UNKNOWN)
985 preferred_engine = link->link_enc->analog_engine;
986
987 for (i = 0; i < pool->stream_enc_count; i++) {
988 if (!res_ctx->is_stream_enc_acquired[i] &&
989 pool->stream_enc[i]) {
990 /* Store first available for MST second display
991 * in daisy chain use case
992 */
993 j = i;
994 if (pool->stream_enc[i]->id == preferred_engine)
995 return pool->stream_enc[i];
996 }
997 }
998
999 /*
1000 * below can happen in cases when stream encoder is acquired:
1001 * 1) for second MST display in chain, so preferred engine already
1002 * acquired;
1003 * 2) for another link, which preferred engine already acquired by any
1004 * MST configuration.
1005 *
1006 * If signal is of DP type and preferred engine not found, return last available
1007 *
1008 * TODO - This is just a patch up and a generic solution is
1009 * required for non DP connectors.
1010 */
1011
1012 if (j >= 0 && link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT)
1013 return pool->stream_enc[j];
1014
1015 return NULL;
1016 }
1017
1018 static const struct resource_funcs dce100_res_pool_funcs = {
1019 .destroy = dce100_destroy_resource_pool,
1020 .link_enc_create = dce100_link_encoder_create,
1021 .panel_cntl_create = dce100_panel_cntl_create,
1022 .validate_bandwidth = dce100_validate_bandwidth,
1023 .validate_plane = dce100_validate_plane,
1024 .add_stream_to_ctx = dce100_add_stream_to_ctx,
1025 .validate_global = dce100_validate_global,
1026 .find_first_free_match_stream_enc_for_link = dce100_find_first_free_match_stream_enc_for_link
1027 };
1028
dce100_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dce110_resource_pool * pool)1029 static bool dce100_resource_construct(
1030 uint8_t num_virtual_links,
1031 struct dc *dc,
1032 struct dce110_resource_pool *pool)
1033 {
1034 unsigned int i;
1035 struct dc_context *ctx = dc->ctx;
1036 struct dc_bios *bp;
1037
1038 ctx->dc_bios->regs = &bios_regs;
1039
1040 pool->base.res_cap = &res_cap;
1041 pool->base.funcs = &dce100_res_pool_funcs;
1042 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1043
1044 bp = ctx->dc_bios;
1045
1046 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
1047 pool->base.dp_clock_source =
1048 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1049
1050 pool->base.clock_sources[0] =
1051 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
1052 pool->base.clock_sources[1] =
1053 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1054 pool->base.clock_sources[2] =
1055 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1056 pool->base.clk_src_count = 3;
1057
1058 } else {
1059 pool->base.dp_clock_source =
1060 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
1061
1062 pool->base.clock_sources[0] =
1063 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1064 pool->base.clock_sources[1] =
1065 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1066 pool->base.clk_src_count = 2;
1067 }
1068
1069 if (pool->base.dp_clock_source == NULL) {
1070 dm_error("DC: failed to create dp clock source!\n");
1071 BREAK_TO_DEBUGGER();
1072 goto res_create_fail;
1073 }
1074
1075 for (i = 0; i < pool->base.clk_src_count; i++) {
1076 if (pool->base.clock_sources[i] == NULL) {
1077 dm_error("DC: failed to create clock sources!\n");
1078 BREAK_TO_DEBUGGER();
1079 goto res_create_fail;
1080 }
1081 }
1082
1083 pool->base.dmcu = dce_dmcu_create(ctx,
1084 &dmcu_regs,
1085 &dmcu_shift,
1086 &dmcu_mask);
1087 if (pool->base.dmcu == NULL) {
1088 dm_error("DC: failed to create dmcu!\n");
1089 BREAK_TO_DEBUGGER();
1090 goto res_create_fail;
1091 }
1092
1093 pool->base.abm = dce_abm_create(ctx,
1094 &abm_regs,
1095 &abm_shift,
1096 &abm_mask);
1097 if (pool->base.abm == NULL) {
1098 dm_error("DC: failed to create abm!\n");
1099 BREAK_TO_DEBUGGER();
1100 goto res_create_fail;
1101 }
1102
1103 {
1104 struct irq_service_init_data init_data;
1105 init_data.ctx = dc->ctx;
1106 pool->base.irqs = dal_irq_service_dce110_create(&init_data);
1107 if (!pool->base.irqs)
1108 goto res_create_fail;
1109 }
1110
1111 /*************************************************
1112 * Resource + asic cap harcoding *
1113 *************************************************/
1114 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1115 pool->base.pipe_count = res_cap.num_timing_generator;
1116 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
1117 dc->caps.max_downscale_ratio = 200;
1118 dc->caps.i2c_speed_in_khz = 40;
1119 dc->caps.i2c_speed_in_khz_hdcp = 40;
1120 dc->caps.max_cursor_size = 128;
1121 dc->caps.min_horizontal_blanking_period = 80;
1122 dc->caps.dual_link_dvi = true;
1123 dc->caps.disable_dp_clk_share = true;
1124 dc->caps.extended_aux_timeout_support = false;
1125 dc->debug = debug_defaults;
1126 dc->check_config = config_defaults;
1127
1128 for (i = 0; i < pool->base.pipe_count; i++) {
1129 pool->base.timing_generators[i] =
1130 dce100_timing_generator_create(
1131 ctx,
1132 i,
1133 &dce100_tg_offsets[i]);
1134 if (pool->base.timing_generators[i] == NULL) {
1135 BREAK_TO_DEBUGGER();
1136 dm_error("DC: failed to create tg!\n");
1137 goto res_create_fail;
1138 }
1139
1140 pool->base.mis[i] = dce100_mem_input_create(ctx, i);
1141 if (pool->base.mis[i] == NULL) {
1142 BREAK_TO_DEBUGGER();
1143 dm_error(
1144 "DC: failed to create memory input!\n");
1145 goto res_create_fail;
1146 }
1147
1148 pool->base.ipps[i] = dce100_ipp_create(ctx, i);
1149 if (pool->base.ipps[i] == NULL) {
1150 BREAK_TO_DEBUGGER();
1151 dm_error(
1152 "DC: failed to create input pixel processor!\n");
1153 goto res_create_fail;
1154 }
1155
1156 pool->base.transforms[i] = dce100_transform_create(ctx, i);
1157 if (pool->base.transforms[i] == NULL) {
1158 BREAK_TO_DEBUGGER();
1159 dm_error(
1160 "DC: failed to create transform!\n");
1161 goto res_create_fail;
1162 }
1163
1164 pool->base.opps[i] = dce100_opp_create(ctx, i);
1165 if (pool->base.opps[i] == NULL) {
1166 BREAK_TO_DEBUGGER();
1167 dm_error(
1168 "DC: failed to create output pixel processor!\n");
1169 goto res_create_fail;
1170 }
1171 }
1172
1173 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1174 pool->base.engines[i] = dce100_aux_engine_create(ctx, i);
1175 if (pool->base.engines[i] == NULL) {
1176 BREAK_TO_DEBUGGER();
1177 dm_error(
1178 "DC:failed to create aux engine!!\n");
1179 goto res_create_fail;
1180 }
1181 pool->base.hw_i2cs[i] = dce100_i2c_hw_create(ctx, i);
1182 if (pool->base.hw_i2cs[i] == NULL) {
1183 BREAK_TO_DEBUGGER();
1184 dm_error(
1185 "DC:failed to create i2c engine!!\n");
1186 goto res_create_fail;
1187 }
1188 pool->base.sw_i2cs[i] = NULL;
1189 }
1190
1191 dc->caps.max_planes = pool->base.pipe_count;
1192
1193 for (i = 0; i < dc->caps.max_planes; ++i)
1194 dc->caps.planes[i] = plane_cap;
1195
1196 if (!resource_construct(num_virtual_links, dc, &pool->base,
1197 &res_create_funcs))
1198 goto res_create_fail;
1199
1200 /* Create hardware sequencer */
1201 dce100_hw_sequencer_construct(dc);
1202 return true;
1203
1204 res_create_fail:
1205 dce100_resource_destruct(pool);
1206
1207 return false;
1208 }
1209
dce100_create_resource_pool(uint8_t num_virtual_links,struct dc * dc)1210 struct resource_pool *dce100_create_resource_pool(
1211 uint8_t num_virtual_links,
1212 struct dc *dc)
1213 {
1214 struct dce110_resource_pool *pool =
1215 kzalloc_obj(struct dce110_resource_pool);
1216
1217 if (!pool)
1218 return NULL;
1219
1220 if (dce100_resource_construct(num_virtual_links, dc, pool))
1221 return &pool->base;
1222
1223 kfree(pool);
1224 BREAK_TO_DEBUGGER();
1225 return NULL;
1226 }
1227
1228