1 /*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27 #include "dcn35_clk_mgr.h"
28
29 #include "dccg.h"
30 #include "clk_mgr_internal.h"
31
32 // For dce12_get_dp_ref_freq_khz
33 #include "dce100/dce_clk_mgr.h"
34
35 // For dcn20_update_clocks_update_dpp_dto
36 #include "dcn20/dcn20_clk_mgr.h"
37
38
39 #include "reg_helper.h"
40 #include "core_types.h"
41 #include "dcn35_smu.h"
42 #include "dm_helpers.h"
43
44 #include "dcn31/dcn31_clk_mgr.h"
45
46 #include "dc_dmub_srv.h"
47 #include "link_service.h"
48 #include "logger_types.h"
49
50 #undef DC_LOGGER
51 #define DC_LOGGER \
52 clk_mgr->base.base.ctx->logger
53
54 #define DCN_BASE__INST0_SEG1 0x000000C0
55 #define mmCLK1_CLK_PLL_REQ 0x16E37
56
57 #define mmCLK1_CLK0_DFS_CNTL 0x16E69
58 #define mmCLK1_CLK1_DFS_CNTL 0x16E6C
59 #define mmCLK1_CLK2_DFS_CNTL 0x16E6F
60 #define mmCLK1_CLK3_DFS_CNTL 0x16E72
61 #define mmCLK1_CLK4_DFS_CNTL 0x16E75
62 #define mmCLK1_CLK5_DFS_CNTL 0x16E78
63
64 #define mmCLK1_CLK0_CURRENT_CNT 0x16EFB
65 #define mmCLK1_CLK1_CURRENT_CNT 0x16EFC
66 #define mmCLK1_CLK2_CURRENT_CNT 0x16EFD
67 #define mmCLK1_CLK3_CURRENT_CNT 0x16EFE
68 #define mmCLK1_CLK4_CURRENT_CNT 0x16EFF
69 #define mmCLK1_CLK5_CURRENT_CNT 0x16F00
70
71 #define mmCLK1_CLK0_BYPASS_CNTL 0x16E8A
72 #define mmCLK1_CLK1_BYPASS_CNTL 0x16E93
73 #define mmCLK1_CLK2_BYPASS_CNTL 0x16E9C
74 #define mmCLK1_CLK3_BYPASS_CNTL 0x16EA5
75 #define mmCLK1_CLK4_BYPASS_CNTL 0x16EAE
76 #define mmCLK1_CLK5_BYPASS_CNTL 0x16EB7
77
78 #define mmCLK1_CLK0_DS_CNTL 0x16E83
79 #define mmCLK1_CLK1_DS_CNTL 0x16E8C
80 #define mmCLK1_CLK2_DS_CNTL 0x16E95
81 #define mmCLK1_CLK3_DS_CNTL 0x16E9E
82 #define mmCLK1_CLK4_DS_CNTL 0x16EA7
83 #define mmCLK1_CLK5_DS_CNTL 0x16EB0
84
85 #define mmCLK1_CLK0_ALLOW_DS 0x16E84
86 #define mmCLK1_CLK1_ALLOW_DS 0x16E8D
87 #define mmCLK1_CLK2_ALLOW_DS 0x16E96
88 #define mmCLK1_CLK3_ALLOW_DS 0x16E9F
89 #define mmCLK1_CLK4_ALLOW_DS 0x16EA8
90 #define mmCLK1_CLK5_ALLOW_DS 0x16EB1
91
92 #define mmCLK5_spll_field_8 0x1B24B
93 #define mmCLK6_spll_field_8 0x1B24B
94 #define mmDENTIST_DISPCLK_CNTL 0x0124
95 #define regDENTIST_DISPCLK_CNTL 0x0064
96 #define regDENTIST_DISPCLK_CNTL_BASE_IDX 1
97
98 #define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
99 #define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc
100 #define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
101 #define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
102 #define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L
103 #define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
104
105 #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK 0x00000007L
106 #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV_MASK 0x000F0000L
107 // DENTIST_DISPCLK_CNTL
108 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0
109 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8
110 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13
111 #define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE__SHIFT 0x14
112 #define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER__SHIFT 0x18
113 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x0000007FL
114 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x00007F00L
115 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x00080000L
116 #define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE_MASK 0x00100000L
117 #define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER_MASK 0x7F000000L
118
119 #define CLK5_spll_field_8__spll_ssc_en_MASK 0x00002000L
120 #define CLK6_spll_field_8__spll_ssc_en_MASK 0x00002000L
121
122 #define SMU_VER_THRESHOLD 0x5D4A00 //93.74.0
123 #undef FN
124 #define FN(reg_name, field_name) \
125 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
126
127 #define REG(reg) \
128 (clk_mgr->regs->reg)
129
130 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
131
132 #define BASE(seg) BASE_INNER(seg)
133
134 #define SR(reg_name)\
135 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
136 reg ## reg_name
137
138 #define CLK_SR_DCN35(reg_name)\
139 .reg_name = mm ## reg_name
140
141 static const struct clk_mgr_registers clk_mgr_regs_dcn35 = {
142 CLK_REG_LIST_DCN35()
143 };
144
145 static const struct clk_mgr_shift clk_mgr_shift_dcn35 = {
146 CLK_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
147 };
148
149 static const struct clk_mgr_mask clk_mgr_mask_dcn35 = {
150 CLK_COMMON_MASK_SH_LIST_DCN32(_MASK)
151 };
152
153 #define TO_CLK_MGR_DCN35(clk_mgr)\
154 container_of(clk_mgr, struct clk_mgr_dcn35, base)
155
dcn35_get_active_display_cnt_wa(struct dc * dc,struct dc_state * context,int * all_active_disps)156 static int dcn35_get_active_display_cnt_wa(
157 struct dc *dc,
158 struct dc_state *context,
159 int *all_active_disps)
160 {
161 int i, display_count = 0;
162 bool tmds_present = false;
163
164 for (i = 0; i < context->stream_count; i++) {
165 const struct dc_stream_state *stream = context->streams[i];
166
167 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
168 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
169 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
170 tmds_present = true;
171 }
172
173 for (i = 0; i < dc->link_count; i++) {
174 const struct dc_link *link = dc->links[i];
175
176 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
177 if (link->link_enc && link->link_enc->funcs->is_dig_enabled &&
178 link->link_enc->funcs->is_dig_enabled(link->link_enc))
179 display_count++;
180 }
181 if (all_active_disps != NULL)
182 *all_active_disps = display_count;
183 /* WA for hang on HDMI after display off back on*/
184 if (display_count == 0 && tmds_present)
185 display_count = 1;
186
187 return display_count;
188 }
dcn35_disable_otg_wa(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower,bool disable)189 void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context,
190 bool safe_to_lower, bool disable)
191 {
192 struct dc *dc = clk_mgr_base->ctx->dc;
193 int i;
194
195 if (dc->ctx->dce_environment == DCE_ENV_DIAG)
196 return;
197
198 for (i = 0; i < dc->res_pool->pipe_count; ++i) {
199 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
200 struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];
201 struct clk_mgr_internal *clk_mgr_internal = TO_CLK_MGR_INTERNAL(clk_mgr_base);
202 struct dccg *dccg = clk_mgr_internal->dccg;
203 struct pipe_ctx *pipe = safe_to_lower
204 ? &context->res_ctx.pipe_ctx[i]
205 : &dc->current_state->res_ctx.pipe_ctx[i];
206 struct link_encoder *new_pipe_link_enc = new_pipe->link_res.dio_link_enc;
207 struct link_encoder *pipe_link_enc = pipe->link_res.dio_link_enc;
208 bool stream_changed_otg_dig_on = false;
209 bool has_active_hpo = false;
210
211 if (pipe->top_pipe || pipe->prev_odm_pipe)
212 continue;
213
214 if (!dc->config.unify_link_enc_assignment) {
215 if (new_pipe->stream)
216 new_pipe_link_enc = new_pipe->stream->link_enc;
217 if (pipe->stream)
218 pipe_link_enc = pipe->stream->link_enc;
219 }
220
221 stream_changed_otg_dig_on = old_pipe->stream && new_pipe->stream &&
222 old_pipe->stream != new_pipe->stream &&
223 old_pipe->stream_res.tg == new_pipe->stream_res.tg &&
224 new_pipe_link_enc && !new_pipe->stream->dpms_off &&
225 new_pipe_link_enc->funcs->is_dig_enabled &&
226 new_pipe_link_enc->funcs->is_dig_enabled(
227 new_pipe_link_enc) &&
228 new_pipe->stream_res.stream_enc &&
229 new_pipe->stream_res.stream_enc->funcs->is_fifo_enabled &&
230 new_pipe->stream_res.stream_enc->funcs->is_fifo_enabled(new_pipe->stream_res.stream_enc);
231
232 if (old_pipe->stream && new_pipe->stream && old_pipe->stream == new_pipe->stream) {
233 has_active_hpo = dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(old_pipe) &&
234 dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(new_pipe);
235
236 }
237
238 if (!has_active_hpo && !stream_changed_otg_dig_on && pipe->stream &&
239 (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal) || !pipe_link_enc) &&
240 !dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe)) {
241 /* This w/a should not trigger when we have a dig active */
242 if (disable) {
243 if (pipe->stream_res.tg && pipe->stream_res.tg->funcs->immediate_disable_crtc)
244 pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
245
246 reset_sync_context_for_pipe(dc, context, i);
247 } else {
248 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
249 }
250 }
251 }
252 }
253
dcn35_update_clocks_update_dtb_dto(struct clk_mgr_internal * clk_mgr,struct dc_state * context,int ref_dtbclk_khz)254 static void dcn35_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr,
255 struct dc_state *context,
256 int ref_dtbclk_khz)
257 {
258 struct dccg *dccg = clk_mgr->dccg;
259 uint32_t tg_mask = 0;
260 int i;
261
262 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
263 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
264 struct dtbclk_dto_params dto_params = {0};
265
266 /* use mask to program DTO once per tg */
267 if (pipe_ctx->stream_res.tg &&
268 !(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) {
269 tg_mask |= (1 << pipe_ctx->stream_res.tg->inst);
270
271 dto_params.otg_inst = pipe_ctx->stream_res.tg->inst;
272 dto_params.ref_dtbclk_khz = ref_dtbclk_khz;
273
274 dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params);
275 //dccg->funcs->set_audio_dtbclk_dto(clk_mgr->dccg, &dto_params);
276 }
277 }
278 }
279
dcn35_update_clocks_update_dpp_dto(struct clk_mgr_internal * clk_mgr,struct dc_state * context,bool safe_to_lower)280 static void dcn35_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
281 struct dc_state *context, bool safe_to_lower)
282 {
283 int i;
284 bool dppclk_active[MAX_PIPES] = {0};
285
286
287 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;
288 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
289 int dpp_inst = 0, dppclk_khz, prev_dppclk_khz;
290
291 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
292
293 if (context->res_ctx.pipe_ctx[i].plane_res.dpp)
294 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
295 else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {
296 /* dpp == NULL && dppclk_khz == 0 is valid because of pipe harvesting.
297 * In this case just continue in loop
298 */
299 continue;
300 } else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {
301 /* The software state is not valid if dpp resource is NULL and
302 * dppclk_khz > 0.
303 */
304 ASSERT(false);
305 continue;
306 }
307
308 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];
309
310 if (safe_to_lower || prev_dppclk_khz < dppclk_khz)
311 clk_mgr->dccg->funcs->update_dpp_dto(
312 clk_mgr->dccg, dpp_inst, dppclk_khz);
313 dppclk_active[dpp_inst] = true;
314 }
315 if (safe_to_lower)
316 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
317 struct dpp *old_dpp = clk_mgr->base.ctx->dc->current_state->res_ctx.pipe_ctx[i].plane_res.dpp;
318
319 if (old_dpp && !dppclk_active[old_dpp->inst])
320 clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, old_dpp->inst, 0);
321 }
322 }
323
get_lowest_dpia_index(const struct dc_link * link)324 static uint8_t get_lowest_dpia_index(const struct dc_link *link)
325 {
326 const struct dc *dc_struct = link->dc;
327 uint8_t idx = 0xFF;
328 int i;
329
330 for (i = 0; i < MAX_PIPES * 2; ++i) {
331 if (!dc_struct->links[i] || dc_struct->links[i]->ep_type != DISPLAY_ENDPOINT_USB4_DPIA)
332 continue;
333
334 if (idx > dc_struct->links[i]->link_index)
335 idx = dc_struct->links[i]->link_index;
336 }
337
338 return idx;
339 }
340
dcn35_notify_host_router_bw(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)341 static void dcn35_notify_host_router_bw(struct clk_mgr *clk_mgr_base, struct dc_state *context,
342 bool safe_to_lower)
343 {
344 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
345 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
346 uint32_t host_router_bw_kbps[MAX_HOST_ROUTERS_NUM] = { 0 };
347 int i;
348 for (i = 0; i < context->stream_count; ++i) {
349 const struct dc_stream_state *stream = context->streams[i];
350 const struct dc_link *link = stream->link;
351 uint8_t lowest_dpia_index = 0;
352 unsigned int hr_index = 0;
353
354 if (!link)
355 continue;
356
357 lowest_dpia_index = get_lowest_dpia_index(link);
358 if (link->link_index < lowest_dpia_index)
359 continue;
360
361 hr_index = (link->link_index - lowest_dpia_index) / 2;
362 if (hr_index >= MAX_HOST_ROUTERS_NUM)
363 continue;
364 host_router_bw_kbps[hr_index] += dc_bandwidth_in_kbps_from_timing(
365 &stream->timing, dc_link_get_highest_encoding_format(link));
366 }
367
368 for (i = 0; i < MAX_HOST_ROUTERS_NUM; ++i) {
369 new_clocks->host_router_bw_kbps[i] = host_router_bw_kbps[i];
370 if (should_set_clock(safe_to_lower, new_clocks->host_router_bw_kbps[i], clk_mgr_base->clks.host_router_bw_kbps[i])) {
371 clk_mgr_base->clks.host_router_bw_kbps[i] = new_clocks->host_router_bw_kbps[i];
372 dcn35_smu_notify_host_router_bw(clk_mgr, i, new_clocks->host_router_bw_kbps[i]);
373 }
374 }
375 }
376
dcn35_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)377 void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,
378 struct dc_state *context,
379 bool safe_to_lower)
380 {
381 union dmub_rb_cmd cmd;
382 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
383 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
384 struct dc *dc = clk_mgr_base->ctx->dc;
385 int display_count = 0;
386 bool update_dppclk = false;
387 bool update_dispclk = false;
388 bool dpp_clock_lowered = false;
389 int all_active_disps = 0;
390
391 if (dc->work_arounds.skip_clock_update)
392 return;
393
394 display_count = dcn35_get_active_display_cnt_wa(dc, context, &all_active_disps);
395 if (new_clocks->dtbclk_en && !new_clocks->ref_dtbclk_khz)
396 new_clocks->ref_dtbclk_khz = 600000;
397 else if (!new_clocks->dtbclk_en && new_clocks->ref_dtbclk_khz > 590000)
398 new_clocks->ref_dtbclk_khz = 0;
399
400 /*
401 * if it is safe to lower, but we are already in the lower state, we don't have to do anything
402 * also if safe to lower is false, we just go in the higher state
403 */
404 if (safe_to_lower) {
405 if (new_clocks->zstate_support != DCN_ZSTATE_SUPPORT_DISALLOW &&
406 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) {
407 dcn35_smu_set_zstate_support(clk_mgr, new_clocks->zstate_support);
408 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
409 }
410
411 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) {
412 if (clk_mgr->base.ctx->dc->config.allow_0_dtb_clk)
413 dcn35_smu_set_dtbclk(clk_mgr, false);
414
415 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
416 }
417 /* check that we're not already in lower */
418 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
419 /* if we can go lower, go lower */
420 if (display_count == 0)
421 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
422 }
423 } else {
424 if (new_clocks->zstate_support == DCN_ZSTATE_SUPPORT_DISALLOW &&
425 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) {
426 dcn35_smu_set_zstate_support(clk_mgr, DCN_ZSTATE_SUPPORT_DISALLOW);
427 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
428 }
429
430 if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) {
431 int actual_dtbclk = 0;
432
433 dcn35_update_clocks_update_dtb_dto(clk_mgr, context, new_clocks->ref_dtbclk_khz);
434 dcn35_smu_set_dtbclk(clk_mgr, true);
435
436 actual_dtbclk = REG_READ(CLK1_CLK4_CURRENT_CNT);
437
438 if (actual_dtbclk > 590000) {
439 clk_mgr_base->clks.ref_dtbclk_khz = new_clocks->ref_dtbclk_khz;
440 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
441 }
442 }
443
444 /* check that we're not already in D0 */
445 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
446 union display_idle_optimization_u idle_info = { 0 };
447
448 dcn35_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
449 /* update power state */
450 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
451 }
452 }
453 if (dc->debug.force_min_dcfclk_mhz > 0)
454 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
455 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
456
457 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
458 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
459 dcn35_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
460 }
461
462 if (should_set_clock(safe_to_lower,
463 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
464 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
465 dcn35_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
466 }
467
468 // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
469 if (new_clocks->dppclk_khz < 100000)
470 new_clocks->dppclk_khz = 100000;
471
472 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
473 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
474 dpp_clock_lowered = true;
475 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
476 update_dppclk = true;
477 }
478
479 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) &&
480 (new_clocks->dispclk_khz > 0 || (safe_to_lower && display_count == 0))) {
481 int requested_dispclk_khz = new_clocks->dispclk_khz;
482
483 dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true);
484
485 /* Clamp the requested clock to PMFW based on their limit. */
486 if (dc->debug.min_disp_clk_khz > 0 && requested_dispclk_khz < dc->debug.min_disp_clk_khz)
487 requested_dispclk_khz = dc->debug.min_disp_clk_khz;
488
489 dcn35_smu_set_dispclk(clk_mgr, requested_dispclk_khz);
490 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
491
492 dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false);
493
494 update_dispclk = true;
495 }
496
497 /* clock limits are received with MHz precision, divide by 1000 to prevent setting clocks at every call */
498 if (!dc->debug.disable_dtb_ref_clk_switch &&
499 should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000,
500 clk_mgr_base->clks.ref_dtbclk_khz / 1000)) {
501 dcn35_update_clocks_update_dtb_dto(clk_mgr, context, new_clocks->ref_dtbclk_khz);
502 clk_mgr_base->clks.ref_dtbclk_khz = new_clocks->ref_dtbclk_khz;
503 }
504
505 if (dpp_clock_lowered) {
506 // increase per DPP DTO before lowering global dppclk
507 dcn35_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
508 dcn35_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
509 } else {
510 // increase global DPPCLK before lowering per DPP DTO
511 if (update_dppclk || update_dispclk)
512 dcn35_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
513 dcn35_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
514 }
515
516 // notify PMFW of bandwidth per DPIA tunnel
517 if (dc->debug.notify_dpia_hr_bw)
518 dcn35_notify_host_router_bw(clk_mgr_base, context, safe_to_lower);
519
520 // notify DMCUB of latest clocks
521 memset(&cmd, 0, sizeof(cmd));
522 cmd.notify_clocks.header.type = DMUB_CMD__CLK_MGR;
523 cmd.notify_clocks.header.sub_type = DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS;
524 cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz;
525 cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz =
526 clk_mgr_base->clks.dcfclk_deep_sleep_khz;
527 cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz;
528 cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz;
529
530 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
531 }
532
get_vco_frequency_from_reg(struct clk_mgr_internal * clk_mgr)533 static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
534 {
535 /* get FbMult value */
536 struct fixed31_32 pll_req;
537 unsigned int fbmult_frac_val = 0;
538 unsigned int fbmult_int_val = 0;
539
540 /*
541 * Register value of fbmult is in 8.16 format, we are converting to 314.32
542 * to leverage the fix point operations available in driver
543 */
544
545 REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
546 REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
547
548 pll_req = dc_fixpt_from_int(fbmult_int_val);
549
550 /*
551 * since fractional part is only 16 bit in register definition but is 32 bit
552 * in our fix point definiton, need to shift left by 16 to obtain correct value
553 */
554 pll_req.value |= fbmult_frac_val << 16;
555
556 /* multiply by REFCLK period */
557 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
558
559 /* integer part is now VCO frequency in kHz */
560 return dc_fixpt_floor(pll_req);
561 }
562
dcn35_enable_pme_wa(struct clk_mgr * clk_mgr_base)563 static void dcn35_enable_pme_wa(struct clk_mgr *clk_mgr_base)
564 {
565 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
566
567 dcn35_smu_enable_pme_wa(clk_mgr);
568 }
569
570
dcn35_are_clock_states_equal(struct dc_clocks * a,struct dc_clocks * b)571 bool dcn35_are_clock_states_equal(struct dc_clocks *a,
572 struct dc_clocks *b)
573 {
574 if (a->dispclk_khz != b->dispclk_khz)
575 return false;
576 else if (a->dppclk_khz != b->dppclk_khz)
577 return false;
578 else if (a->dcfclk_khz != b->dcfclk_khz)
579 return false;
580 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
581 return false;
582 else if (a->zstate_support != b->zstate_support)
583 return false;
584 else if (a->dtbclk_en != b->dtbclk_en)
585 return false;
586
587 return true;
588 }
589
dcn35_save_clk_registers_internal(struct dcn35_clk_internal * internal,struct clk_mgr * clk_mgr_base)590 static void dcn35_save_clk_registers_internal(struct dcn35_clk_internal *internal, struct clk_mgr *clk_mgr_base)
591 {
592 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
593
594 // read dtbclk
595 internal->CLK1_CLK4_CURRENT_CNT = REG_READ(CLK1_CLK4_CURRENT_CNT);
596 internal->CLK1_CLK4_BYPASS_CNTL = REG_READ(CLK1_CLK4_BYPASS_CNTL);
597
598 // read dcfclk
599 internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_CLK3_CURRENT_CNT);
600 internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_CLK3_BYPASS_CNTL);
601
602 // read dcf deep sleep divider
603 internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_CLK3_DS_CNTL);
604 internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_CLK3_ALLOW_DS);
605
606 // read dppclk
607 internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_CLK1_CURRENT_CNT);
608 internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_CLK1_BYPASS_CNTL);
609
610 // read dprefclk
611 internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_CLK2_CURRENT_CNT);
612 internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_CLK2_BYPASS_CNTL);
613
614 // read dispclk
615 internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_CLK0_CURRENT_CNT);
616 internal->CLK1_CLK0_BYPASS_CNTL = REG_READ(CLK1_CLK0_BYPASS_CNTL);
617 }
618
dcn35_save_clk_registers(struct clk_state_registers_and_bypass * regs_and_bypass,struct clk_mgr_dcn35 * clk_mgr)619 static void dcn35_save_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
620 struct clk_mgr_dcn35 *clk_mgr)
621 {
622 struct dcn35_clk_internal internal = {0};
623 char *bypass_clks[5] = {"0x0 DFS", "0x1 REFCLK", "0x2 ERROR", "0x3 400 FCH", "0x4 600 FCH"};
624
625 dcn35_save_clk_registers_internal(&internal, &clk_mgr->base.base);
626
627 regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10;
628 regs_and_bypass->dcf_deep_sleep_divider = internal.CLK1_CLK3_DS_CNTL / 10;
629 regs_and_bypass->dcf_deep_sleep_allow = internal.CLK1_CLK3_ALLOW_DS;
630 regs_and_bypass->dprefclk = internal.CLK1_CLK2_CURRENT_CNT / 10;
631 regs_and_bypass->dispclk = internal.CLK1_CLK0_CURRENT_CNT / 10;
632 regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10;
633 regs_and_bypass->dtbclk = internal.CLK1_CLK4_CURRENT_CNT / 10;
634
635 regs_and_bypass->dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL & 0x0007;
636 if (regs_and_bypass->dppclk_bypass > 4)
637 regs_and_bypass->dppclk_bypass = 0;
638 regs_and_bypass->dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL & 0x0007;
639 if (regs_and_bypass->dcfclk_bypass > 4)
640 regs_and_bypass->dcfclk_bypass = 0;
641 regs_and_bypass->dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL & 0x0007;
642 if (regs_and_bypass->dispclk_bypass > 4)
643 regs_and_bypass->dispclk_bypass = 0;
644 regs_and_bypass->dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL & 0x0007;
645 if (regs_and_bypass->dprefclk_bypass > 4)
646 regs_and_bypass->dprefclk_bypass = 0;
647
648 if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {
649 DC_LOG_SMU("clk_type,clk_value,deepsleep_cntl,deepsleep_allow,bypass\n");
650
651 DC_LOG_SMU("dcfclk,%d,%d,%d,%s\n",
652 regs_and_bypass->dcfclk,
653 regs_and_bypass->dcf_deep_sleep_divider,
654 regs_and_bypass->dcf_deep_sleep_allow,
655 bypass_clks[(int) regs_and_bypass->dcfclk_bypass]);
656
657 DC_LOG_SMU("dprefclk,%d,N/A,N/A,%s\n",
658 regs_and_bypass->dprefclk,
659 bypass_clks[(int) regs_and_bypass->dprefclk_bypass]);
660
661 DC_LOG_SMU("dispclk,%d,N/A,N/A,%s\n",
662 regs_and_bypass->dispclk,
663 bypass_clks[(int) regs_and_bypass->dispclk_bypass]);
664
665 // REGISTER VALUES
666 DC_LOG_SMU("reg_name,value,clk_type");
667
668 DC_LOG_SMU("CLK1_CLK3_CURRENT_CNT,%d,dcfclk",
669 internal.CLK1_CLK3_CURRENT_CNT);
670
671 DC_LOG_SMU("CLK1_CLK4_CURRENT_CNT,%d,dtbclk",
672 internal.CLK1_CLK4_CURRENT_CNT);
673
674 DC_LOG_SMU("CLK1_CLK3_DS_CNTL,%d,dcf_deep_sleep_divider",
675 internal.CLK1_CLK3_DS_CNTL);
676
677 DC_LOG_SMU("CLK1_CLK3_ALLOW_DS,%d,dcf_deep_sleep_allow",
678 internal.CLK1_CLK3_ALLOW_DS);
679
680 DC_LOG_SMU("CLK1_CLK2_CURRENT_CNT,%d,dprefclk",
681 internal.CLK1_CLK2_CURRENT_CNT);
682
683 DC_LOG_SMU("CLK1_CLK0_CURRENT_CNT,%d,dispclk",
684 internal.CLK1_CLK0_CURRENT_CNT);
685
686 DC_LOG_SMU("CLK1_CLK1_CURRENT_CNT,%d,dppclk",
687 internal.CLK1_CLK1_CURRENT_CNT);
688
689 DC_LOG_SMU("CLK1_CLK3_BYPASS_CNTL,%d,dcfclk_bypass",
690 internal.CLK1_CLK3_BYPASS_CNTL);
691
692 DC_LOG_SMU("CLK1_CLK2_BYPASS_CNTL,%d,dprefclk_bypass",
693 internal.CLK1_CLK2_BYPASS_CNTL);
694
695 DC_LOG_SMU("CLK1_CLK0_BYPASS_CNTL,%d,dispclk_bypass",
696 internal.CLK1_CLK0_BYPASS_CNTL);
697
698 DC_LOG_SMU("CLK1_CLK1_BYPASS_CNTL,%d,dppclk_bypass",
699 internal.CLK1_CLK1_BYPASS_CNTL);
700
701 }
702 }
703
dcn35_is_spll_ssc_enabled(struct clk_mgr * clk_mgr_base)704 static bool dcn35_is_spll_ssc_enabled(struct clk_mgr *clk_mgr_base)
705 {
706 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
707
708 uint32_t ssc_enable;
709
710 if (clk_mgr_base->ctx->dce_version == DCN_VERSION_3_51) {
711 ssc_enable = REG_READ(CLK6_spll_field_8) & CLK6_spll_field_8__spll_ssc_en_MASK;
712 } else {
713 ssc_enable = REG_READ(CLK5_spll_field_8) & CLK5_spll_field_8__spll_ssc_en_MASK;
714 }
715
716 return ssc_enable != 0;
717 }
718
init_clk_states(struct clk_mgr * clk_mgr)719 static void init_clk_states(struct clk_mgr *clk_mgr)
720 {
721 uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz;
722
723 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
724
725 clk_mgr->clks.ref_dtbclk_khz = ref_dtbclk; // restore ref_dtbclk
726 clk_mgr->clks.p_state_change_support = true;
727 clk_mgr->clks.prev_p_state_change_support = true;
728 clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
729 clk_mgr->clks.zstate_support = DCN_ZSTATE_SUPPORT_UNKNOWN;
730 }
731
dcn35_init_clocks(struct clk_mgr * clk_mgr)732 void dcn35_init_clocks(struct clk_mgr *clk_mgr)
733 {
734 struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);
735 struct clk_mgr_dcn35 *clk_mgr_dcn35 = TO_CLK_MGR_DCN35(clk_mgr_int);
736
737 init_clk_states(clk_mgr);
738
739 // to adjust dp_dto reference clock if ssc is enable otherwise to apply dprefclk
740 if (dcn35_is_spll_ssc_enabled(clk_mgr))
741 clk_mgr->dp_dto_source_clock_in_khz =
742 dce_adjust_dp_ref_freq_for_ss(clk_mgr_int, clk_mgr->dprefclk_khz);
743 else
744 clk_mgr->dp_dto_source_clock_in_khz = clk_mgr->dprefclk_khz;
745
746 dcn35_save_clk_registers(&clk_mgr->boot_snapshot, clk_mgr_dcn35);
747
748 clk_mgr->clks.ref_dtbclk_khz = clk_mgr->boot_snapshot.dtbclk * 10;
749 if (clk_mgr->boot_snapshot.dtbclk > 59000) {
750 /*dtbclk enabled based on */
751 clk_mgr->clks.dtbclk_en = true;
752 }
753 }
754 static struct clk_bw_params dcn35_bw_params = {
755 .vram_type = Ddr4MemType,
756 .num_channels = 1,
757 .clk_table = {
758 .num_entries = 4,
759 },
760
761 };
762
763 static struct wm_table ddr5_wm_table = {
764 .entries = {
765 {
766 .wm_inst = WM_A,
767 .wm_type = WM_TYPE_PSTATE_CHG,
768 .pstate_latency_us = 11.72,
769 .sr_exit_time_us = 31.0,
770 .sr_enter_plus_exit_time_us = 33.0,
771 .valid = true,
772 },
773 {
774 .wm_inst = WM_B,
775 .wm_type = WM_TYPE_PSTATE_CHG,
776 .pstate_latency_us = 11.72,
777 .sr_exit_time_us = 31.0,
778 .sr_enter_plus_exit_time_us = 33.0,
779 .valid = true,
780 },
781 {
782 .wm_inst = WM_C,
783 .wm_type = WM_TYPE_PSTATE_CHG,
784 .pstate_latency_us = 11.72,
785 .sr_exit_time_us = 31.0,
786 .sr_enter_plus_exit_time_us = 33.0,
787 .valid = true,
788 },
789 {
790 .wm_inst = WM_D,
791 .wm_type = WM_TYPE_PSTATE_CHG,
792 .pstate_latency_us = 11.72,
793 .sr_exit_time_us = 31.0,
794 .sr_enter_plus_exit_time_us = 33.0,
795 .valid = true,
796 },
797 }
798 };
799
800 static struct wm_table lpddr5_wm_table = {
801 .entries = {
802 {
803 .wm_inst = WM_A,
804 .wm_type = WM_TYPE_PSTATE_CHG,
805 .pstate_latency_us = 11.65333,
806 .sr_exit_time_us = 28.0,
807 .sr_enter_plus_exit_time_us = 30.0,
808 .valid = true,
809 },
810 {
811 .wm_inst = WM_B,
812 .wm_type = WM_TYPE_PSTATE_CHG,
813 .pstate_latency_us = 11.65333,
814 .sr_exit_time_us = 28.0,
815 .sr_enter_plus_exit_time_us = 30.0,
816 .valid = true,
817 },
818 {
819 .wm_inst = WM_C,
820 .wm_type = WM_TYPE_PSTATE_CHG,
821 .pstate_latency_us = 11.65333,
822 .sr_exit_time_us = 28.0,
823 .sr_enter_plus_exit_time_us = 30.0,
824 .valid = true,
825 },
826 {
827 .wm_inst = WM_D,
828 .wm_type = WM_TYPE_PSTATE_CHG,
829 .pstate_latency_us = 11.65333,
830 .sr_exit_time_us = 28.0,
831 .sr_enter_plus_exit_time_us = 30.0,
832 .valid = true,
833 },
834 }
835 };
836
837 static DpmClocks_t_dcn35 dummy_clocks;
838 static DpmClocks_t_dcn351 dummy_clocks_dcn351;
839
840 static struct dcn35_watermarks dummy_wms = { 0 };
841
842 static struct dcn35_ss_info_table ss_info_table = {
843 .ss_divider = 1000,
844 .ss_percentage = {0, 0, 375, 375, 375}
845 };
846
dcn35_read_ss_info_from_lut(struct clk_mgr_internal * clk_mgr)847 static void dcn35_read_ss_info_from_lut(struct clk_mgr_internal *clk_mgr)
848 {
849 uint32_t clock_source = 0;
850
851 clock_source = REG_READ(CLK1_CLK2_BYPASS_CNTL) & CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK;
852
853 // If it's DFS mode, clock_source is 0.
854 if (dcn35_is_spll_ssc_enabled(&clk_mgr->base) && (clock_source < ARRAY_SIZE(ss_info_table.ss_percentage))) {
855 clk_mgr->dprefclk_ss_percentage = ss_info_table.ss_percentage[clock_source];
856
857 if (clk_mgr->dprefclk_ss_percentage != 0) {
858 clk_mgr->ss_on_dprefclk = true;
859 clk_mgr->dprefclk_ss_divider = ss_info_table.ss_divider;
860 }
861 }
862 }
863
dcn35_build_watermark_ranges(struct clk_bw_params * bw_params,struct dcn35_watermarks * table)864 static void dcn35_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn35_watermarks *table)
865 {
866 int i, num_valid_sets;
867
868 num_valid_sets = 0;
869
870 for (i = 0; i < WM_SET_COUNT; i++) {
871 /* skip empty entries, the smu array has no holes*/
872 if (!bw_params->wm_table.entries[i].valid)
873 continue;
874
875 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
876 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
877 /* We will not select WM based on fclk, so leave it as unconstrained */
878 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
879 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
880
881 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
882 if (i == 0)
883 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
884 else {
885 /* add 1 to make it non-overlapping with next lvl */
886 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
887 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
888 }
889 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
890 bw_params->clk_table.entries[i].dcfclk_mhz;
891
892 } else {
893 /* unconstrained for memory retraining */
894 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
895 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
896
897 /* Modify previous watermark range to cover up to max */
898 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
899 }
900 num_valid_sets++;
901 }
902
903 ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
904
905 /* modify the min and max to make sure we cover the whole range*/
906 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;
907 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;
908 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;
909 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
910
911 /* This is for writeback only, does not matter currently as no writeback support*/
912 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
913 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;
914 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;
915 table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;
916 table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;
917 }
918
dcn35_notify_wm_ranges(struct clk_mgr * clk_mgr_base)919 static void dcn35_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
920 {
921 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
922 struct clk_mgr_dcn35 *clk_mgr_dcn35 = TO_CLK_MGR_DCN35(clk_mgr);
923 struct dcn35_watermarks *table = clk_mgr_dcn35->smu_wm_set.wm_set;
924
925 if (!clk_mgr->smu_ver)
926 return;
927
928 if (!table || clk_mgr_dcn35->smu_wm_set.mc_address.quad_part == 0)
929 return;
930
931 memset(table, 0, sizeof(*table));
932
933 dcn35_build_watermark_ranges(clk_mgr_base->bw_params, table);
934
935 dcn35_smu_set_dram_addr_high(clk_mgr,
936 clk_mgr_dcn35->smu_wm_set.mc_address.high_part);
937 dcn35_smu_set_dram_addr_low(clk_mgr,
938 clk_mgr_dcn35->smu_wm_set.mc_address.low_part);
939 dcn35_smu_transfer_wm_table_dram_2_smu(clk_mgr);
940 }
941
dcn35_get_dpm_table_from_smu(struct clk_mgr_internal * clk_mgr,struct dcn35_smu_dpm_clks * smu_dpm_clks)942 static void dcn35_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
943 struct dcn35_smu_dpm_clks *smu_dpm_clks)
944 {
945 DpmClocks_t_dcn35 *table = smu_dpm_clks->dpm_clks;
946
947 if (!clk_mgr->smu_ver)
948 return;
949
950 if (!table || smu_dpm_clks->mc_address.quad_part == 0)
951 return;
952
953 memset(table, 0, sizeof(*table));
954
955 dcn35_smu_set_dram_addr_high(clk_mgr,
956 smu_dpm_clks->mc_address.high_part);
957 dcn35_smu_set_dram_addr_low(clk_mgr,
958 smu_dpm_clks->mc_address.low_part);
959 dcn35_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
960 }
961
dcn351_get_dpm_table_from_smu(struct clk_mgr_internal * clk_mgr,struct dcn351_smu_dpm_clks * smu_dpm_clks)962 static void dcn351_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
963 struct dcn351_smu_dpm_clks *smu_dpm_clks)
964 {
965 DpmClocks_t_dcn351 *table = smu_dpm_clks->dpm_clks;
966
967 if (!clk_mgr->smu_ver)
968 return;
969 if (!table || smu_dpm_clks->mc_address.quad_part == 0)
970 return;
971 memset(table, 0, sizeof(*table));
972 dcn35_smu_set_dram_addr_high(clk_mgr,
973 smu_dpm_clks->mc_address.high_part);
974 dcn35_smu_set_dram_addr_low(clk_mgr,
975 smu_dpm_clks->mc_address.low_part);
976 dcn35_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
977 }
find_max_clk_value(const uint32_t clocks[],uint32_t num_clocks)978 static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks)
979 {
980 uint32_t max = 0;
981 int i;
982
983 for (i = 0; i < num_clocks; ++i) {
984 if (clocks[i] > max)
985 max = clocks[i];
986 }
987
988 return max;
989 }
990
is_valid_clock_value(uint32_t clock_value)991 static inline bool is_valid_clock_value(uint32_t clock_value)
992 {
993 return clock_value > 1 && clock_value < 100000;
994 }
995
convert_wck_ratio(uint8_t wck_ratio)996 static unsigned int convert_wck_ratio(uint8_t wck_ratio)
997 {
998 switch (wck_ratio) {
999 case WCK_RATIO_1_2:
1000 return 2;
1001
1002 case WCK_RATIO_1_4:
1003 return 4;
1004 /* Find lowest DPM, FCLK is filled in reverse order*/
1005
1006 default:
1007 break;
1008 }
1009
1010 return 1;
1011 }
1012
calc_dram_speed_mts(const MemPstateTable_t * entry)1013 static inline uint32_t calc_dram_speed_mts(const MemPstateTable_t *entry)
1014 {
1015 return entry->UClk * convert_wck_ratio(entry->WckRatio) * 2;
1016 }
1017
dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal * clk_mgr,struct integrated_info * bios_info,DpmClocks_t_dcn35 * clock_table)1018 static void dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk_mgr,
1019 struct integrated_info *bios_info,
1020 DpmClocks_t_dcn35 *clock_table)
1021 {
1022 struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
1023 struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entries - 1];
1024 uint32_t max_fclk = 0, min_pstate = 0, max_dispclk = 0, max_dppclk = 0;
1025 uint32_t max_pstate = 0, max_dram_speed_mts = 0, min_dram_speed_mts = 0;
1026 uint32_t num_memps, num_fclk, num_dcfclk;
1027 int i;
1028
1029 /* Determine min/max p-state values. */
1030 num_memps = (clock_table->NumMemPstatesEnabled > NUM_MEM_PSTATE_LEVELS) ? NUM_MEM_PSTATE_LEVELS :
1031 clock_table->NumMemPstatesEnabled;
1032 for (i = 0; i < num_memps; i++) {
1033 uint32_t dram_speed_mts = calc_dram_speed_mts(&clock_table->MemPstateTable[i]);
1034
1035 if (is_valid_clock_value(dram_speed_mts) && dram_speed_mts > max_dram_speed_mts) {
1036 max_dram_speed_mts = dram_speed_mts;
1037 max_pstate = i;
1038 }
1039 }
1040
1041 min_dram_speed_mts = max_dram_speed_mts;
1042 min_pstate = max_pstate;
1043
1044 for (i = 0; i < num_memps; i++) {
1045 uint32_t dram_speed_mts = calc_dram_speed_mts(&clock_table->MemPstateTable[i]);
1046
1047 if (is_valid_clock_value(dram_speed_mts) && dram_speed_mts < min_dram_speed_mts) {
1048 min_dram_speed_mts = dram_speed_mts;
1049 min_pstate = i;
1050 }
1051 }
1052
1053 /* We expect the table to contain at least one valid P-state entry. */
1054 ASSERT(clock_table->NumMemPstatesEnabled &&
1055 is_valid_clock_value(max_dram_speed_mts) &&
1056 is_valid_clock_value(min_dram_speed_mts));
1057
1058 /* dispclk and dppclk can be max at any voltage, same number of levels for both */
1059 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS &&
1060 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) {
1061 max_dispclk = find_max_clk_value(clock_table->DispClocks,
1062 clock_table->NumDispClkLevelsEnabled);
1063 max_dppclk = find_max_clk_value(clock_table->DppClocks,
1064 clock_table->NumDispClkLevelsEnabled);
1065 } else {
1066 /* Invalid number of entries in the table from PMFW. */
1067 ASSERT(0);
1068 }
1069
1070 /* Base the clock table on dcfclk, need at least one entry regardless of pmfw table */
1071 ASSERT(clock_table->NumDcfClkLevelsEnabled > 0);
1072
1073 num_fclk = (clock_table->NumFclkLevelsEnabled > NUM_FCLK_DPM_LEVELS) ? NUM_FCLK_DPM_LEVELS :
1074 clock_table->NumFclkLevelsEnabled;
1075 max_fclk = find_max_clk_value(clock_table->FclkClocks_Freq, num_fclk);
1076
1077 num_dcfclk = (clock_table->NumDcfClkLevelsEnabled > NUM_DCFCLK_DPM_LEVELS) ? NUM_DCFCLK_DPM_LEVELS :
1078 clock_table->NumDcfClkLevelsEnabled;
1079 for (i = 0; i < num_dcfclk; i++) {
1080 int j;
1081
1082 /* First search defaults for the clocks we don't read using closest lower or equal default dcfclk */
1083 for (j = bw_params->clk_table.num_entries - 1; j > 0; j--)
1084 if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i])
1085 break;
1086
1087 bw_params->clk_table.entries[i].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz;
1088 bw_params->clk_table.entries[i].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz;
1089 bw_params->clk_table.entries[i].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz;
1090
1091 /* Now update clocks we do read */
1092 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemPstateTable[min_pstate].MemClk;
1093 bw_params->clk_table.entries[i].voltage = clock_table->MemPstateTable[min_pstate].Voltage;
1094 bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i];
1095 bw_params->clk_table.entries[i].socclk_mhz = clock_table->SocClocks[i];
1096 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
1097 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
1098 bw_params->clk_table.entries[i].wck_ratio =
1099 convert_wck_ratio(clock_table->MemPstateTable[min_pstate].WckRatio);
1100
1101 /* Dcfclk and Fclk are tied, but at a different ratio */
1102 bw_params->clk_table.entries[i].fclk_mhz = min(max_fclk, 2 * clock_table->DcfClocks[i]);
1103 }
1104
1105 /* Make sure to include at least one entry at highest pstate */
1106 if (max_pstate != min_pstate || i == 0) {
1107 if (i > MAX_NUM_DPM_LVL - 1)
1108 i = MAX_NUM_DPM_LVL - 1;
1109
1110 bw_params->clk_table.entries[i].fclk_mhz = max_fclk;
1111 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemPstateTable[max_pstate].MemClk;
1112 bw_params->clk_table.entries[i].voltage = clock_table->MemPstateTable[max_pstate].Voltage;
1113 bw_params->clk_table.entries[i].dcfclk_mhz =
1114 find_max_clk_value(clock_table->DcfClocks, NUM_DCFCLK_DPM_LEVELS);
1115 bw_params->clk_table.entries[i].socclk_mhz =
1116 find_max_clk_value(clock_table->SocClocks, NUM_SOCCLK_DPM_LEVELS);
1117 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
1118 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
1119 bw_params->clk_table.entries[i].wck_ratio = convert_wck_ratio(
1120 clock_table->MemPstateTable[max_pstate].WckRatio);
1121 i++;
1122 }
1123 bw_params->clk_table.num_entries = i--;
1124
1125 /* Make sure all highest clocks are included*/
1126 bw_params->clk_table.entries[i].socclk_mhz =
1127 find_max_clk_value(clock_table->SocClocks, NUM_SOCCLK_DPM_LEVELS);
1128 bw_params->clk_table.entries[i].dispclk_mhz =
1129 find_max_clk_value(clock_table->DispClocks, NUM_DISPCLK_DPM_LEVELS);
1130 bw_params->clk_table.entries[i].dppclk_mhz =
1131 find_max_clk_value(clock_table->DppClocks, NUM_DPPCLK_DPM_LEVELS);
1132 bw_params->clk_table.entries[i].fclk_mhz =
1133 find_max_clk_value(clock_table->FclkClocks_Freq, NUM_FCLK_DPM_LEVELS);
1134 ASSERT(clock_table->DcfClocks[i] == find_max_clk_value(clock_table->DcfClocks, NUM_DCFCLK_DPM_LEVELS));
1135 bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz;
1136 bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz;
1137 bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz;
1138 bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels = clock_table->NumDcfClkLevelsEnabled;
1139 bw_params->clk_table.num_entries_per_clk.num_dispclk_levels = clock_table->NumDispClkLevelsEnabled;
1140 bw_params->clk_table.num_entries_per_clk.num_dppclk_levels = clock_table->NumDispClkLevelsEnabled;
1141 bw_params->clk_table.num_entries_per_clk.num_fclk_levels = clock_table->NumFclkLevelsEnabled;
1142 bw_params->clk_table.num_entries_per_clk.num_memclk_levels = clock_table->NumMemPstatesEnabled;
1143 bw_params->clk_table.num_entries_per_clk.num_socclk_levels = clock_table->NumSocClkLevelsEnabled;
1144
1145 /*
1146 * Set any 0 clocks to max default setting. Not an issue for
1147 * power since we aren't doing switching in such case anyway
1148 */
1149 for (i = 0; i < bw_params->clk_table.num_entries; i++) {
1150 if (!bw_params->clk_table.entries[i].fclk_mhz) {
1151 bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz;
1152 bw_params->clk_table.entries[i].memclk_mhz = def_max.memclk_mhz;
1153 bw_params->clk_table.entries[i].voltage = def_max.voltage;
1154 }
1155 if (!bw_params->clk_table.entries[i].dcfclk_mhz)
1156 bw_params->clk_table.entries[i].dcfclk_mhz = def_max.dcfclk_mhz;
1157 if (!bw_params->clk_table.entries[i].socclk_mhz)
1158 bw_params->clk_table.entries[i].socclk_mhz = def_max.socclk_mhz;
1159 if (!bw_params->clk_table.entries[i].dispclk_mhz)
1160 bw_params->clk_table.entries[i].dispclk_mhz = def_max.dispclk_mhz;
1161 if (!bw_params->clk_table.entries[i].dppclk_mhz)
1162 bw_params->clk_table.entries[i].dppclk_mhz = def_max.dppclk_mhz;
1163 if (!bw_params->clk_table.entries[i].fclk_mhz)
1164 bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz;
1165 if (!bw_params->clk_table.entries[i].phyclk_mhz)
1166 bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz;
1167 if (!bw_params->clk_table.entries[i].phyclk_d18_mhz)
1168 bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz;
1169 if (!bw_params->clk_table.entries[i].dtbclk_mhz)
1170 bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz;
1171 }
1172 ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz);
1173 bw_params->vram_type = bios_info->memory_type;
1174 bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4;
1175 bw_params->num_channels = bios_info->ma_channel_number ? bios_info->ma_channel_number : 4;
1176
1177 for (i = 0; i < WM_SET_COUNT; i++) {
1178 bw_params->wm_table.entries[i].wm_inst = i;
1179
1180 if (i >= bw_params->clk_table.num_entries) {
1181 bw_params->wm_table.entries[i].valid = false;
1182 continue;
1183 }
1184
1185 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
1186 bw_params->wm_table.entries[i].valid = true;
1187 }
1188 }
1189
dcn35_set_low_power_state(struct clk_mgr * clk_mgr_base)1190 static void dcn35_set_low_power_state(struct clk_mgr *clk_mgr_base)
1191 {
1192 int display_count;
1193 struct dc *dc = clk_mgr_base->ctx->dc;
1194 struct dc_state *context = dc->current_state;
1195
1196 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
1197 display_count = dcn35_get_active_display_cnt_wa(dc, context, NULL);
1198 /* if we can go lower, go lower */
1199 if (display_count == 0)
1200 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
1201 }
1202 }
1203
dcn35_exit_low_power_state(struct clk_mgr * clk_mgr_base)1204 static void dcn35_exit_low_power_state(struct clk_mgr *clk_mgr_base)
1205 {
1206 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1207
1208 //SMU optimization is performed part of low power state exit.
1209 dcn35_smu_exit_low_power_state(clk_mgr);
1210
1211 }
1212
dcn35_is_ips_supported(struct clk_mgr * clk_mgr_base)1213 static bool dcn35_is_ips_supported(struct clk_mgr *clk_mgr_base)
1214 {
1215 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1216
1217 return dcn35_smu_get_ips_supported(clk_mgr) ? true : false;
1218 }
1219
dcn35_init_clocks_fpga(struct clk_mgr * clk_mgr)1220 static void dcn35_init_clocks_fpga(struct clk_mgr *clk_mgr)
1221 {
1222 init_clk_states(clk_mgr);
1223
1224 /* TODO: Implement the functions and remove the ifndef guard */
1225 }
1226
dcn35_update_clocks_fpga(struct clk_mgr * clk_mgr,struct dc_state * context,bool safe_to_lower)1227 static void dcn35_update_clocks_fpga(struct clk_mgr *clk_mgr,
1228 struct dc_state *context,
1229 bool safe_to_lower)
1230 {
1231 struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);
1232 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
1233 int fclk_adj = new_clocks->fclk_khz;
1234
1235 /* TODO: remove this after correctly set by DML */
1236 new_clocks->dcfclk_khz = 400000;
1237 new_clocks->socclk_khz = 400000;
1238
1239 /* Min fclk = 1.2GHz since all the extra scemi logic seems to run off of it */
1240 //int fclk_adj = new_clocks->fclk_khz > 1200000 ? new_clocks->fclk_khz : 1200000;
1241 new_clocks->fclk_khz = 4320000;
1242
1243 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr->clks.phyclk_khz)) {
1244 clk_mgr->clks.phyclk_khz = new_clocks->phyclk_khz;
1245 }
1246
1247 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr->clks.dcfclk_khz)) {
1248 clk_mgr->clks.dcfclk_khz = new_clocks->dcfclk_khz;
1249 }
1250
1251 if (should_set_clock(safe_to_lower,
1252 new_clocks->dcfclk_deep_sleep_khz, clk_mgr->clks.dcfclk_deep_sleep_khz)) {
1253 clk_mgr->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
1254 }
1255
1256 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr->clks.socclk_khz)) {
1257 clk_mgr->clks.socclk_khz = new_clocks->socclk_khz;
1258 }
1259
1260 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr->clks.dramclk_khz)) {
1261 clk_mgr->clks.dramclk_khz = new_clocks->dramclk_khz;
1262 }
1263
1264 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->clks.dppclk_khz)) {
1265 clk_mgr->clks.dppclk_khz = new_clocks->dppclk_khz;
1266 }
1267
1268 if (should_set_clock(safe_to_lower, fclk_adj, clk_mgr->clks.fclk_khz)) {
1269 clk_mgr->clks.fclk_khz = fclk_adj;
1270 }
1271
1272 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr->clks.dispclk_khz)) {
1273 clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz;
1274 }
1275
1276 /* Both fclk and ref_dppclk run on the same scemi clock.
1277 * So take the higher value since the DPP DTO is typically programmed
1278 * such that max dppclk is 1:1 with ref_dppclk.
1279 */
1280 if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz)
1281 clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz;
1282 if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz)
1283 clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz;
1284
1285 // Both fclk and ref_dppclk run on the same scemi clock.
1286 clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz;
1287
1288 /* TODO: set dtbclk in correct place */
1289 clk_mgr->clks.dtbclk_en = true;
1290 dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks);
1291 dcn35_update_clocks_update_dpp_dto(clk_mgr_int, context, safe_to_lower);
1292
1293 dcn35_update_clocks_update_dtb_dto(clk_mgr_int, context, clk_mgr->clks.ref_dtbclk_khz);
1294 }
1295
dcn35_get_max_clock_khz(struct clk_mgr * clk_mgr_base,enum clk_type clk_type)1296 static unsigned int dcn35_get_max_clock_khz(struct clk_mgr *clk_mgr_base, enum clk_type clk_type)
1297 {
1298 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1299
1300 unsigned int num_clk_levels;
1301
1302 switch (clk_type) {
1303 case CLK_TYPE_DISPCLK:
1304 num_clk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dispclk_levels;
1305 return num_clk_levels ?
1306 clk_mgr->base.bw_params->clk_table.entries[num_clk_levels - 1].dispclk_mhz * 1000 :
1307 clk_mgr->base.boot_snapshot.dispclk;
1308 case CLK_TYPE_DPPCLK:
1309 num_clk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dppclk_levels;
1310 return num_clk_levels ?
1311 clk_mgr->base.bw_params->clk_table.entries[num_clk_levels - 1].dppclk_mhz * 1000 :
1312 clk_mgr->base.boot_snapshot.dppclk;
1313 case CLK_TYPE_DSCCLK:
1314 num_clk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dispclk_levels;
1315 return num_clk_levels ?
1316 clk_mgr->base.bw_params->clk_table.entries[num_clk_levels - 1].dispclk_mhz * 1000 / 3 :
1317 clk_mgr->base.boot_snapshot.dispclk / 3;
1318 default:
1319 break;
1320 }
1321
1322 return 0;
1323 }
1324
1325 static struct clk_mgr_funcs dcn35_funcs = {
1326 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
1327 .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
1328 .update_clocks = dcn35_update_clocks,
1329 .init_clocks = dcn35_init_clocks,
1330 .enable_pme_wa = dcn35_enable_pme_wa,
1331 .are_clock_states_equal = dcn35_are_clock_states_equal,
1332 .notify_wm_ranges = dcn35_notify_wm_ranges,
1333 .set_low_power_state = dcn35_set_low_power_state,
1334 .exit_low_power_state = dcn35_exit_low_power_state,
1335 .is_ips_supported = dcn35_is_ips_supported,
1336 .get_max_clock_khz = dcn35_get_max_clock_khz,
1337 };
1338
1339 struct clk_mgr_funcs dcn35_fpga_funcs = {
1340 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
1341 .update_clocks = dcn35_update_clocks_fpga,
1342 .init_clocks = dcn35_init_clocks_fpga,
1343 .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
1344 };
1345
translate_to_DpmClocks_t_dcn35(struct dcn351_smu_dpm_clks * smu_dpm_clks_a,struct dcn35_smu_dpm_clks * smu_dpm_clks_b)1346 static void translate_to_DpmClocks_t_dcn35(struct dcn351_smu_dpm_clks *smu_dpm_clks_a,
1347 struct dcn35_smu_dpm_clks *smu_dpm_clks_b)
1348 {
1349 /*translate two structures and only take need clock tables*/
1350 uint8_t i;
1351
1352 if (smu_dpm_clks_a == NULL || smu_dpm_clks_b == NULL ||
1353 smu_dpm_clks_a->dpm_clks == NULL || smu_dpm_clks_b->dpm_clks == NULL)
1354 return;
1355
1356 for (i = 0; i < NUM_DCFCLK_DPM_LEVELS; i++)
1357 smu_dpm_clks_b->dpm_clks->DcfClocks[i] = smu_dpm_clks_a->dpm_clks->DcfClocks[i];
1358
1359 for (i = 0; i < NUM_DISPCLK_DPM_LEVELS; i++)
1360 smu_dpm_clks_b->dpm_clks->DispClocks[i] = smu_dpm_clks_a->dpm_clks->DispClocks[i];
1361
1362 for (i = 0; i < NUM_DPPCLK_DPM_LEVELS; i++)
1363 smu_dpm_clks_b->dpm_clks->DppClocks[i] = smu_dpm_clks_a->dpm_clks->DppClocks[i];
1364
1365 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
1366 smu_dpm_clks_b->dpm_clks->FclkClocks_Freq[i] = smu_dpm_clks_a->dpm_clks->FclkClocks_Freq[i];
1367 smu_dpm_clks_b->dpm_clks->FclkClocks_Voltage[i] = smu_dpm_clks_a->dpm_clks->FclkClocks_Voltage[i];
1368 }
1369 for (i = 0; i < NUM_MEM_PSTATE_LEVELS; i++) {
1370 smu_dpm_clks_b->dpm_clks->MemPstateTable[i].MemClk =
1371 smu_dpm_clks_a->dpm_clks->MemPstateTable[i].MemClk;
1372 smu_dpm_clks_b->dpm_clks->MemPstateTable[i].UClk =
1373 smu_dpm_clks_a->dpm_clks->MemPstateTable[i].UClk;
1374 smu_dpm_clks_b->dpm_clks->MemPstateTable[i].Voltage =
1375 smu_dpm_clks_a->dpm_clks->MemPstateTable[i].Voltage;
1376 smu_dpm_clks_b->dpm_clks->MemPstateTable[i].WckRatio =
1377 smu_dpm_clks_a->dpm_clks->MemPstateTable[i].WckRatio;
1378 }
1379 smu_dpm_clks_b->dpm_clks->MaxGfxClk = smu_dpm_clks_a->dpm_clks->MaxGfxClk;
1380 smu_dpm_clks_b->dpm_clks->MinGfxClk = smu_dpm_clks_a->dpm_clks->MinGfxClk;
1381 smu_dpm_clks_b->dpm_clks->NumDcfClkLevelsEnabled =
1382 smu_dpm_clks_a->dpm_clks->NumDcfClkLevelsEnabled;
1383 smu_dpm_clks_b->dpm_clks->NumDispClkLevelsEnabled =
1384 smu_dpm_clks_a->dpm_clks->NumDispClkLevelsEnabled;
1385 smu_dpm_clks_b->dpm_clks->NumFclkLevelsEnabled =
1386 smu_dpm_clks_a->dpm_clks->NumFclkLevelsEnabled;
1387 smu_dpm_clks_b->dpm_clks->NumMemPstatesEnabled =
1388 smu_dpm_clks_a->dpm_clks->NumMemPstatesEnabled;
1389 smu_dpm_clks_b->dpm_clks->NumSocClkLevelsEnabled =
1390 smu_dpm_clks_a->dpm_clks->NumSocClkLevelsEnabled;
1391
1392 for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++) {
1393 smu_dpm_clks_b->dpm_clks->SocClocks[i] = smu_dpm_clks_a->dpm_clks->SocClocks[i];
1394 smu_dpm_clks_b->dpm_clks->SocVoltage[i] = smu_dpm_clks_a->dpm_clks->SocVoltage[i];
1395 }
1396 }
dcn35_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_dcn35 * clk_mgr,struct pp_smu_funcs * pp_smu,struct dccg * dccg)1397 void dcn35_clk_mgr_construct(
1398 struct dc_context *ctx,
1399 struct clk_mgr_dcn35 *clk_mgr,
1400 struct pp_smu_funcs *pp_smu,
1401 struct dccg *dccg)
1402 {
1403 struct dcn35_smu_dpm_clks smu_dpm_clks = { 0 };
1404 struct dcn351_smu_dpm_clks smu_dpm_clks_dcn351 = { 0 };
1405 clk_mgr->base.base.ctx = ctx;
1406 clk_mgr->base.base.funcs = &dcn35_funcs;
1407
1408 clk_mgr->base.pp_smu = pp_smu;
1409
1410 clk_mgr->base.dccg = dccg;
1411 clk_mgr->base.dfs_bypass_disp_clk = 0;
1412
1413 clk_mgr->base.dprefclk_ss_percentage = 0;
1414 clk_mgr->base.dprefclk_ss_divider = 1000;
1415 clk_mgr->base.ss_on_dprefclk = false;
1416 clk_mgr->base.dfs_ref_freq_khz = 48000;
1417 if (ctx->dce_version != DCN_VERSION_3_51) {
1418 clk_mgr->base.regs = &clk_mgr_regs_dcn35;
1419 clk_mgr->base.clk_mgr_shift = &clk_mgr_shift_dcn35;
1420 clk_mgr->base.clk_mgr_mask = &clk_mgr_mask_dcn35;
1421 }
1422
1423
1424 clk_mgr->smu_wm_set.wm_set = (struct dcn35_watermarks *)dm_helpers_allocate_gpu_mem(
1425 clk_mgr->base.base.ctx,
1426 DC_MEM_ALLOC_TYPE_GART,
1427 sizeof(struct dcn35_watermarks),
1428 &clk_mgr->smu_wm_set.mc_address.quad_part);
1429
1430 if (!clk_mgr->smu_wm_set.wm_set) {
1431 clk_mgr->smu_wm_set.wm_set = &dummy_wms;
1432 clk_mgr->smu_wm_set.mc_address.quad_part = 0;
1433 }
1434 ASSERT(clk_mgr->smu_wm_set.wm_set);
1435
1436 smu_dpm_clks.dpm_clks = (DpmClocks_t_dcn35 *)dm_helpers_allocate_gpu_mem(
1437 clk_mgr->base.base.ctx,
1438 DC_MEM_ALLOC_TYPE_GART,
1439 sizeof(DpmClocks_t_dcn35),
1440 &smu_dpm_clks.mc_address.quad_part);
1441 if (smu_dpm_clks.dpm_clks == NULL) {
1442 smu_dpm_clks.dpm_clks = &dummy_clocks;
1443 smu_dpm_clks.mc_address.quad_part = 0;
1444 }
1445 ASSERT(smu_dpm_clks.dpm_clks);
1446
1447 if (ctx->dce_version == DCN_VERSION_3_51) {
1448 smu_dpm_clks_dcn351.dpm_clks = (DpmClocks_t_dcn351 *)dm_helpers_allocate_gpu_mem(
1449 clk_mgr->base.base.ctx,
1450 DC_MEM_ALLOC_TYPE_GART,
1451 sizeof(DpmClocks_t_dcn351),
1452 &smu_dpm_clks_dcn351.mc_address.quad_part);
1453 if (smu_dpm_clks_dcn351.dpm_clks == NULL) {
1454 smu_dpm_clks_dcn351.dpm_clks = &dummy_clocks_dcn351;
1455 smu_dpm_clks_dcn351.mc_address.quad_part = 0;
1456 }
1457 }
1458
1459 clk_mgr->base.smu_ver = dcn35_smu_get_smu_version(&clk_mgr->base);
1460
1461 if (clk_mgr->base.smu_ver)
1462 clk_mgr->base.smu_present = true;
1463
1464 /* TODO: Check we get what we expect during bringup */
1465 clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base);
1466
1467 if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
1468 dcn35_bw_params.wm_table = lpddr5_wm_table;
1469 } else {
1470 dcn35_bw_params.wm_table = ddr5_wm_table;
1471 }
1472 /* Saved clocks configured at boot for debug purposes */
1473 dcn35_save_clk_registers(&clk_mgr->base.base.boot_snapshot, clk_mgr);
1474
1475 clk_mgr->base.base.dprefclk_khz = dcn35_smu_get_dprefclk(&clk_mgr->base);
1476 clk_mgr->base.base.clks.ref_dtbclk_khz = 600000;
1477
1478 dce_clock_read_ss_info(&clk_mgr->base);
1479 /*when clk src is from FCH, it could have ss, same clock src as DPREF clk*/
1480
1481 dcn35_read_ss_info_from_lut(&clk_mgr->base);
1482
1483 clk_mgr->base.base.bw_params = &dcn35_bw_params;
1484
1485 if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {
1486 int i;
1487 if (ctx->dce_version == DCN_VERSION_3_51) {
1488 dcn351_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks_dcn351);
1489 translate_to_DpmClocks_t_dcn35(&smu_dpm_clks_dcn351, &smu_dpm_clks);
1490 } else
1491 dcn35_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
1492 DC_LOG_SMU("NumDcfClkLevelsEnabled: %d\n"
1493 "NumDispClkLevelsEnabled: %d\n"
1494 "NumSocClkLevelsEnabled: %d\n"
1495 "VcnClkLevelsEnabled: %d\n"
1496 "FClkLevelsEnabled: %d\n"
1497 "NumMemPstatesEnabled: %d\n"
1498 "MinGfxClk: %d\n"
1499 "MaxGfxClk: %d\n",
1500 smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled,
1501 smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled,
1502 smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled,
1503 smu_dpm_clks.dpm_clks->VcnClkLevelsEnabled,
1504 smu_dpm_clks.dpm_clks->NumFclkLevelsEnabled,
1505 smu_dpm_clks.dpm_clks->NumMemPstatesEnabled,
1506 smu_dpm_clks.dpm_clks->MinGfxClk,
1507 smu_dpm_clks.dpm_clks->MaxGfxClk);
1508 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled; i++) {
1509 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DcfClocks[%d] = %d\n",
1510 i,
1511 smu_dpm_clks.dpm_clks->DcfClocks[i]);
1512 }
1513 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) {
1514 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DispClocks[%d] = %d\n",
1515 i, smu_dpm_clks.dpm_clks->DispClocks[i]);
1516 }
1517 for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++) {
1518 DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocClocks[%d] = %d\n",
1519 i, smu_dpm_clks.dpm_clks->SocClocks[i]);
1520 }
1521 for (i = 0; i < smu_dpm_clks.dpm_clks->NumFclkLevelsEnabled; i++) {
1522 DC_LOG_SMU("smu_dpm_clks.dpm_clks->FclkClocks_Freq[%d] = %d\n",
1523 i, smu_dpm_clks.dpm_clks->FclkClocks_Freq[i]);
1524 DC_LOG_SMU("smu_dpm_clks.dpm_clks->FclkClocks_Voltage[%d] = %d\n",
1525 i, smu_dpm_clks.dpm_clks->FclkClocks_Voltage[i]);
1526 }
1527 for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++)
1528 DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocVoltage[%d] = %d\n",
1529 i, smu_dpm_clks.dpm_clks->SocVoltage[i]);
1530
1531 for (i = 0; i < smu_dpm_clks.dpm_clks->NumMemPstatesEnabled; i++) {
1532 DC_LOG_SMU("smu_dpm_clks.dpm_clks.MemPstateTable[%d].UClk = %d\n"
1533 "smu_dpm_clks.dpm_clks->MemPstateTable[%d].MemClk= %d\n"
1534 "smu_dpm_clks.dpm_clks->MemPstateTable[%d].Voltage = %d\n",
1535 i, smu_dpm_clks.dpm_clks->MemPstateTable[i].UClk,
1536 i, smu_dpm_clks.dpm_clks->MemPstateTable[i].MemClk,
1537 i, smu_dpm_clks.dpm_clks->MemPstateTable[i].Voltage);
1538 }
1539
1540 if (ctx->dc_bios->integrated_info && ctx->dc->config.use_default_clock_table == false) {
1541 dcn35_clk_mgr_helper_populate_bw_params(
1542 &clk_mgr->base,
1543 ctx->dc_bios->integrated_info,
1544 smu_dpm_clks.dpm_clks);
1545 }
1546 }
1547
1548 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
1549 dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_GART,
1550 smu_dpm_clks.dpm_clks);
1551
1552 if (smu_dpm_clks_dcn351.dpm_clks && smu_dpm_clks_dcn351.mc_address.quad_part != 0)
1553 dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_GART,
1554 smu_dpm_clks_dcn351.dpm_clks);
1555
1556 if (ctx->dc->config.disable_ips != DMUB_IPS_DISABLE_ALL) {
1557 bool ips_support = false;
1558
1559 /*avoid call pmfw at init*/
1560 ips_support = dcn35_smu_get_ips_supported(&clk_mgr->base);
1561 if (ips_support) {
1562 ctx->dc->debug.ignore_pg = false;
1563 ctx->dc->debug.disable_dpp_power_gate = false;
1564 ctx->dc->debug.disable_hubp_power_gate = false;
1565 ctx->dc->debug.disable_dsc_power_gate = false;
1566
1567 /* Disable dynamic IPS2 in older PMFW (93.12) for Z8 interop. */
1568 if (ctx->dc->config.disable_ips == DMUB_IPS_ENABLE &&
1569 ctx->dce_version != DCN_VERSION_3_51 &&
1570 ((clk_mgr->base.smu_ver & 0x00FFFFFF) <= 0x005d0c00))
1571 ctx->dc->config.disable_ips = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;
1572 } else {
1573 /*let's reset the config control flag*/
1574 ctx->dc->config.disable_ips = DMUB_IPS_DISABLE_ALL; /*pmfw not support it, disable it all*/
1575 }
1576 }
1577 }
1578
dcn35_clk_mgr_destroy(struct clk_mgr_internal * clk_mgr_int)1579 void dcn35_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)
1580 {
1581 struct clk_mgr_dcn35 *clk_mgr = TO_CLK_MGR_DCN35(clk_mgr_int);
1582
1583 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0)
1584 dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
1585 clk_mgr->smu_wm_set.wm_set);
1586 }
1587