1 // SPDX-License-Identifier: GPL-2.0-only
2 // cs42l42-sdw.c -- CS42L42 ALSA SoC audio driver SoundWire driver
3 //
4 // Copyright (C) 2022 Cirrus Logic, Inc. and
5 // Cirrus Logic International Semiconductor Ltd.
6
7 #include <linux/acpi.h>
8 #include <linux/device.h>
9 #include <linux/gpio/consumer.h>
10 #include <linux/iopoll.h>
11 #include <linux/module.h>
12 #include <linux/of_irq.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/soundwire/sdw.h>
15 #include <linux/soundwire/sdw_registers.h>
16 #include <linux/soundwire/sdw_type.h>
17 #include <sound/pcm.h>
18 #include <sound/pcm_params.h>
19 #include <sound/sdw.h>
20 #include <sound/soc.h>
21
22 #include "cs42l42.h"
23
24 #define CS42L42_SDW_CAPTURE_PORT 1
25 #define CS42L42_SDW_PLAYBACK_PORT 2
26
27 /* Register addresses are offset when sent over SoundWire */
28 #define CS42L42_SDW_ADDR_OFFSET 0x8000
29
30 #define CS42L42_SDW_MEM_ACCESS_STATUS 0xd0
31 #define CS42L42_SDW_MEM_READ_DATA 0xd8
32
33 #define CS42L42_SDW_LAST_LATE BIT(3)
34 #define CS42L42_SDW_CMD_IN_PROGRESS BIT(2)
35 #define CS42L42_SDW_RDATA_RDY BIT(0)
36
37 #define CS42L42_DELAYED_READ_POLL_US 1
38 #define CS42L42_DELAYED_READ_TIMEOUT_US 100
39
40 static const struct snd_soc_dapm_route cs42l42_sdw_audio_map[] = {
41 /* Playback Path */
42 { "HP", NULL, "MIXER" },
43 { "MIXER", NULL, "DACSRC" },
44 { "DACSRC", NULL, "Playback" },
45
46 /* Capture Path */
47 { "ADCSRC", NULL, "HS" },
48 { "Capture", NULL, "ADCSRC" },
49 };
50
cs42l42_sdw_dai_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)51 static int cs42l42_sdw_dai_startup(struct snd_pcm_substream *substream,
52 struct snd_soc_dai *dai)
53 {
54 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(dai->component);
55
56 if (!cs42l42->init_done)
57 return -ENODEV;
58
59 return 0;
60 }
61
cs42l42_sdw_dai_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)62 static int cs42l42_sdw_dai_hw_params(struct snd_pcm_substream *substream,
63 struct snd_pcm_hw_params *params,
64 struct snd_soc_dai *dai)
65 {
66 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(dai->component);
67 struct sdw_stream_runtime *sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
68 struct sdw_stream_config stream_config = {0};
69 struct sdw_port_config port_config = {0};
70 int ret;
71
72 if (!sdw_stream)
73 return -EINVAL;
74
75 /* Needed for PLL configuration when we are notified of new bus config */
76 cs42l42->sample_rate = params_rate(params);
77
78 snd_sdw_params_to_config(substream, params, &stream_config, &port_config);
79
80 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
81 port_config.num = CS42L42_SDW_PLAYBACK_PORT;
82 else
83 port_config.num = CS42L42_SDW_CAPTURE_PORT;
84
85 ret = sdw_stream_add_slave(cs42l42->sdw_peripheral, &stream_config, &port_config, 1,
86 sdw_stream);
87 if (ret) {
88 dev_err(dai->dev, "Failed to add sdw stream: %d\n", ret);
89 return ret;
90 }
91
92 cs42l42_src_config(dai->component, params_rate(params));
93
94 return 0;
95 }
96
cs42l42_sdw_dai_prepare(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)97 static int cs42l42_sdw_dai_prepare(struct snd_pcm_substream *substream,
98 struct snd_soc_dai *dai)
99 {
100 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(dai->component);
101
102 dev_dbg(dai->dev, "dai_prepare: sclk=%u rate=%u\n", cs42l42->sclk, cs42l42->sample_rate);
103
104 if (!cs42l42->sclk || !cs42l42->sample_rate)
105 return -EINVAL;
106
107 /*
108 * At this point we know the sample rate from hw_params, and the SWIRE_CLK from bus_config()
109 * callback. This could only fail if the ACPI or machine driver are misconfigured to allow
110 * an unsupported SWIRE_CLK and sample_rate combination.
111 */
112
113 return cs42l42_pll_config(dai->component, cs42l42->sclk, cs42l42->sample_rate);
114 }
115
cs42l42_sdw_dai_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)116 static int cs42l42_sdw_dai_hw_free(struct snd_pcm_substream *substream,
117 struct snd_soc_dai *dai)
118 {
119 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(dai->component);
120 struct sdw_stream_runtime *sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
121
122 sdw_stream_remove_slave(cs42l42->sdw_peripheral, sdw_stream);
123 cs42l42->sample_rate = 0;
124
125 return 0;
126 }
127
cs42l42_sdw_port_prep(struct sdw_slave * slave,struct sdw_prepare_ch * prepare_ch,enum sdw_port_prep_ops state)128 static int cs42l42_sdw_port_prep(struct sdw_slave *slave,
129 struct sdw_prepare_ch *prepare_ch,
130 enum sdw_port_prep_ops state)
131 {
132 struct cs42l42_private *cs42l42 = dev_get_drvdata(&slave->dev);
133 unsigned int pdn_mask;
134
135 if (prepare_ch->num == CS42L42_SDW_PLAYBACK_PORT)
136 pdn_mask = CS42L42_HP_PDN_MASK;
137 else
138 pdn_mask = CS42L42_ADC_PDN_MASK;
139
140 if (state == SDW_OPS_PORT_PRE_PREP) {
141 dev_dbg(cs42l42->dev, "Prep Port pdn_mask:%x\n", pdn_mask);
142 regmap_clear_bits(cs42l42->regmap, CS42L42_PWR_CTL1, pdn_mask);
143 usleep_range(CS42L42_HP_ADC_EN_TIME_US, CS42L42_HP_ADC_EN_TIME_US + 1000);
144 } else if (state == SDW_OPS_PORT_POST_DEPREP) {
145 dev_dbg(cs42l42->dev, "Deprep Port pdn_mask:%x\n", pdn_mask);
146 regmap_set_bits(cs42l42->regmap, CS42L42_PWR_CTL1, pdn_mask);
147 }
148
149 return 0;
150 }
151
cs42l42_sdw_dai_set_sdw_stream(struct snd_soc_dai * dai,void * sdw_stream,int direction)152 static int cs42l42_sdw_dai_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
153 int direction)
154 {
155 snd_soc_dai_dma_data_set(dai, direction, sdw_stream);
156
157 return 0;
158 }
159
cs42l42_sdw_dai_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)160 static void cs42l42_sdw_dai_shutdown(struct snd_pcm_substream *substream,
161 struct snd_soc_dai *dai)
162 {
163 snd_soc_dai_set_dma_data(dai, substream, NULL);
164 }
165
166 static const struct snd_soc_dai_ops cs42l42_sdw_dai_ops = {
167 .startup = cs42l42_sdw_dai_startup,
168 .shutdown = cs42l42_sdw_dai_shutdown,
169 .hw_params = cs42l42_sdw_dai_hw_params,
170 .prepare = cs42l42_sdw_dai_prepare,
171 .hw_free = cs42l42_sdw_dai_hw_free,
172 .mute_stream = cs42l42_mute_stream,
173 .set_stream = cs42l42_sdw_dai_set_sdw_stream,
174 };
175
176 static struct snd_soc_dai_driver cs42l42_sdw_dai = {
177 .name = "cs42l42-sdw",
178 .playback = {
179 .stream_name = "Playback",
180 .channels_min = 1,
181 .channels_max = 2,
182 /* Restrict which rates and formats are supported */
183 .rates = SNDRV_PCM_RATE_8000_96000,
184 .formats = SNDRV_PCM_FMTBIT_S16_LE |
185 SNDRV_PCM_FMTBIT_S24_LE |
186 SNDRV_PCM_FMTBIT_S32_LE,
187 },
188 .capture = {
189 .stream_name = "Capture",
190 .channels_min = 1,
191 .channels_max = 1,
192 /* Restrict which rates and formats are supported */
193 .rates = SNDRV_PCM_RATE_8000_96000,
194 .formats = SNDRV_PCM_FMTBIT_S16_LE |
195 SNDRV_PCM_FMTBIT_S24_LE |
196 SNDRV_PCM_FMTBIT_S32_LE,
197 },
198 .symmetric_rate = 1,
199 .ops = &cs42l42_sdw_dai_ops,
200 };
201
cs42l42_sdw_poll_status(struct sdw_slave * peripheral,u8 mask,u8 match)202 static int cs42l42_sdw_poll_status(struct sdw_slave *peripheral, u8 mask, u8 match)
203 {
204 int ret, sdwret;
205
206 ret = read_poll_timeout(sdw_read_no_pm, sdwret,
207 (sdwret < 0) || ((sdwret & mask) == match),
208 CS42L42_DELAYED_READ_POLL_US, CS42L42_DELAYED_READ_TIMEOUT_US,
209 false, peripheral, CS42L42_SDW_MEM_ACCESS_STATUS);
210 if (ret == 0)
211 ret = sdwret;
212
213 if (ret < 0)
214 dev_err(&peripheral->dev, "MEM_ACCESS_STATUS & %#x for %#x fail: %d\n",
215 mask, match, ret);
216
217 return ret;
218 }
219
cs42l42_sdw_read(void * context,unsigned int reg,unsigned int * val)220 static int cs42l42_sdw_read(void *context, unsigned int reg, unsigned int *val)
221 {
222 struct sdw_slave *peripheral = context;
223 u8 data;
224 int ret;
225
226 reg += CS42L42_SDW_ADDR_OFFSET;
227
228 ret = cs42l42_sdw_poll_status(peripheral, CS42L42_SDW_CMD_IN_PROGRESS, 0);
229 if (ret < 0)
230 return ret;
231
232 ret = sdw_read_no_pm(peripheral, reg);
233 if (ret < 0) {
234 dev_err(&peripheral->dev, "Failed to issue read @0x%x: %d\n", reg, ret);
235 return ret;
236 }
237
238 data = (u8)ret; /* possible non-delayed read value */
239 ret = sdw_read_no_pm(peripheral, CS42L42_SDW_MEM_ACCESS_STATUS);
240 if (ret < 0) {
241 dev_err(&peripheral->dev, "Failed to read MEM_ACCESS_STATUS: %d\n", ret);
242 return ret;
243 }
244
245 /* If read was not delayed we already have the result */
246 if ((ret & CS42L42_SDW_LAST_LATE) == 0) {
247 *val = data;
248 return 0;
249 }
250
251 /* Poll for delayed read completion */
252 if ((ret & CS42L42_SDW_RDATA_RDY) == 0) {
253 ret = cs42l42_sdw_poll_status(peripheral,
254 CS42L42_SDW_RDATA_RDY, CS42L42_SDW_RDATA_RDY);
255 if (ret < 0)
256 return ret;
257 }
258
259 ret = sdw_read_no_pm(peripheral, CS42L42_SDW_MEM_READ_DATA);
260 if (ret < 0) {
261 dev_err(&peripheral->dev, "Failed to read READ_DATA: %d\n", ret);
262 return ret;
263 }
264
265 *val = (u8)ret;
266
267 return 0;
268 }
269
cs42l42_sdw_write(void * context,unsigned int reg,unsigned int val)270 static int cs42l42_sdw_write(void *context, unsigned int reg, unsigned int val)
271 {
272 struct sdw_slave *peripheral = context;
273 int ret;
274
275 ret = cs42l42_sdw_poll_status(peripheral, CS42L42_SDW_CMD_IN_PROGRESS, 0);
276 if (ret < 0)
277 return ret;
278
279 return sdw_write_no_pm(peripheral, reg + CS42L42_SDW_ADDR_OFFSET, (u8)val);
280 }
281
282 /* Initialise cs42l42 using SoundWire - this is only called once, during initialisation */
cs42l42_sdw_init(struct sdw_slave * peripheral)283 static void cs42l42_sdw_init(struct sdw_slave *peripheral)
284 {
285 struct cs42l42_private *cs42l42 = dev_get_drvdata(&peripheral->dev);
286 int ret;
287
288 regcache_cache_only(cs42l42->regmap, false);
289
290 ret = cs42l42_init(cs42l42);
291 if (ret < 0) {
292 regcache_cache_only(cs42l42->regmap, true);
293 goto err;
294 }
295
296 /* Write out any cached changes that happened between probe and attach */
297 ret = regcache_sync(cs42l42->regmap);
298 if (ret < 0)
299 dev_warn(cs42l42->dev, "Failed to sync cache: %d\n", ret);
300
301 /* Disable internal logic that makes clock-stop conditional */
302 regmap_clear_bits(cs42l42->regmap, CS42L42_PWR_CTL3, CS42L42_SW_CLK_STP_STAT_SEL_MASK);
303
304 err:
305 /* This cancels the pm_runtime_get_noresume() call from cs42l42_sdw_probe(). */
306 pm_runtime_put_autosuspend(cs42l42->dev);
307 }
308
cs42l42_sdw_read_prop(struct sdw_slave * peripheral)309 static int cs42l42_sdw_read_prop(struct sdw_slave *peripheral)
310 {
311 struct cs42l42_private *cs42l42 = dev_get_drvdata(&peripheral->dev);
312 struct sdw_slave_prop *prop = &peripheral->prop;
313 struct sdw_dpn_prop *ports;
314
315 ports = devm_kcalloc(cs42l42->dev, 2, sizeof(*ports), GFP_KERNEL);
316 if (!ports)
317 return -ENOMEM;
318
319 prop->source_ports = BIT(CS42L42_SDW_CAPTURE_PORT);
320 prop->sink_ports = BIT(CS42L42_SDW_PLAYBACK_PORT);
321 prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
322 prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
323
324 /* DP1 - capture */
325 ports[0].num = CS42L42_SDW_CAPTURE_PORT;
326 ports[0].type = SDW_DPN_FULL;
327 ports[0].ch_prep_timeout = 10;
328 prop->src_dpn_prop = &ports[0];
329
330 /* DP2 - playback */
331 ports[1].num = CS42L42_SDW_PLAYBACK_PORT;
332 ports[1].type = SDW_DPN_FULL;
333 ports[1].ch_prep_timeout = 10;
334 prop->sink_dpn_prop = &ports[1];
335
336 return 0;
337 }
338
cs42l42_sdw_update_status(struct sdw_slave * peripheral,enum sdw_slave_status status)339 static int cs42l42_sdw_update_status(struct sdw_slave *peripheral,
340 enum sdw_slave_status status)
341 {
342 struct cs42l42_private *cs42l42 = dev_get_drvdata(&peripheral->dev);
343
344 switch (status) {
345 case SDW_SLAVE_ATTACHED:
346 dev_dbg(cs42l42->dev, "ATTACHED\n");
347
348 /*
349 * The SoundWire core can report stale ATTACH notifications
350 * if we hard-reset CS42L42 in probe() but it had already been
351 * enumerated. Reject the ATTACH if we haven't yet seen an
352 * UNATTACH report for the device being in reset.
353 */
354 if (cs42l42->sdw_waiting_first_unattach)
355 break;
356
357 /*
358 * Initialise codec, this only needs to be done once.
359 * When resuming from suspend, resume callback will handle re-init of codec,
360 * using regcache_sync().
361 */
362 if (!cs42l42->init_done)
363 cs42l42_sdw_init(peripheral);
364 break;
365 case SDW_SLAVE_UNATTACHED:
366 dev_dbg(cs42l42->dev, "UNATTACHED\n");
367
368 if (cs42l42->sdw_waiting_first_unattach) {
369 /*
370 * SoundWire core has seen that CS42L42 is not on
371 * the bus so release RESET and wait for ATTACH.
372 */
373 cs42l42->sdw_waiting_first_unattach = false;
374 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
375 }
376
377 break;
378 default:
379 break;
380 }
381
382 return 0;
383 }
384
cs42l42_sdw_bus_config(struct sdw_slave * peripheral,struct sdw_bus_params * params)385 static int cs42l42_sdw_bus_config(struct sdw_slave *peripheral,
386 struct sdw_bus_params *params)
387 {
388 struct cs42l42_private *cs42l42 = dev_get_drvdata(&peripheral->dev);
389 unsigned int new_sclk = params->curr_dr_freq / 2;
390
391 /* The cs42l42 cannot support a glitchless SWIRE_CLK change. */
392 if ((new_sclk != cs42l42->sclk) && cs42l42->stream_use) {
393 dev_warn(cs42l42->dev, "Rejected SCLK change while audio active\n");
394 return -EBUSY;
395 }
396
397 cs42l42->sclk = new_sclk;
398
399 dev_dbg(cs42l42->dev, "bus_config: sclk=%u c=%u r=%u\n",
400 cs42l42->sclk, params->col, params->row);
401
402 return 0;
403 }
404
405 static const struct sdw_slave_ops cs42l42_sdw_ops = {
406 /* No interrupt callback because only hardware INT is supported for Jack Detect in the CS42L42 */
407 .read_prop = cs42l42_sdw_read_prop,
408 .update_status = cs42l42_sdw_update_status,
409 .bus_config = cs42l42_sdw_bus_config,
410 .port_prep = cs42l42_sdw_port_prep,
411 };
412
cs42l42_sdw_runtime_suspend(struct device * dev)413 static int cs42l42_sdw_runtime_suspend(struct device *dev)
414 {
415 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
416
417 dev_dbg(dev, "Runtime suspend\n");
418
419 if (!cs42l42->init_done)
420 return 0;
421
422 /* The host controller could suspend, which would mean no register access */
423 regcache_cache_only(cs42l42->regmap, true);
424
425 return 0;
426 }
427
428 static const struct reg_sequence cs42l42_soft_reboot_seq[] = {
429 REG_SEQ0(CS42L42_SOFT_RESET_REBOOT, 0x1e),
430 };
431
cs42l42_sdw_handle_unattach(struct cs42l42_private * cs42l42)432 static int cs42l42_sdw_handle_unattach(struct cs42l42_private *cs42l42)
433 {
434 struct sdw_slave *peripheral = cs42l42->sdw_peripheral;
435 int ret;
436
437 if (!peripheral->unattach_request)
438 return 0;
439
440 /* Cannot access registers until master re-attaches. */
441 dev_dbg(&peripheral->dev, "Wait for initialization_complete\n");
442 ret = sdw_slave_wait_for_init(peripheral, 5000);
443 if (ret)
444 return ret;
445
446 /*
447 * After a bus reset there must be a reconfiguration reset to
448 * reinitialize the internal state of CS42L42.
449 */
450 regmap_multi_reg_write_bypassed(cs42l42->regmap,
451 cs42l42_soft_reboot_seq,
452 ARRAY_SIZE(cs42l42_soft_reboot_seq));
453 usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2);
454 regcache_mark_dirty(cs42l42->regmap);
455
456 return 0;
457 }
458
cs42l42_sdw_runtime_resume(struct device * dev)459 static int cs42l42_sdw_runtime_resume(struct device *dev)
460 {
461 static const unsigned int ts_dbnce_ms[] = { 0, 125, 250, 500, 750, 1000, 1250, 1500};
462 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
463 unsigned int dbnce;
464 int ret;
465
466 dev_dbg(dev, "Runtime resume\n");
467
468 if (!cs42l42->init_done)
469 return 0;
470
471 ret = cs42l42_sdw_handle_unattach(cs42l42);
472 if (ret < 0) {
473 return ret;
474 } else if (ret > 0) {
475 dbnce = max(cs42l42->ts_dbnc_rise, cs42l42->ts_dbnc_fall);
476
477 if (dbnce > 0)
478 msleep(ts_dbnce_ms[dbnce]);
479 }
480
481 regcache_cache_only(cs42l42->regmap, false);
482
483 /* Sync LATCH_TO_VP first so the VP domain registers sync correctly */
484 ret = regcache_sync_region(cs42l42->regmap, CS42L42_MIC_DET_CTL1, CS42L42_MIC_DET_CTL1);
485 if (ret)
486 goto err_sync;
487
488 ret = regcache_sync(cs42l42->regmap);
489 if (ret)
490 goto err_sync;
491
492 return 0;
493
494 err_sync:
495 regcache_cache_only(cs42l42->regmap, true);
496 regcache_mark_dirty(cs42l42->regmap);
497 return ret;
498 }
499
cs42l42_sdw_resume(struct device * dev)500 static int cs42l42_sdw_resume(struct device *dev)
501 {
502 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
503 int ret;
504
505 dev_dbg(dev, "System resume\n");
506
507 /* Power-up so it can re-enumerate */
508 ret = cs42l42_resume(dev);
509 if (ret)
510 return ret;
511
512 /* Wait for re-attach */
513 ret = cs42l42_sdw_handle_unattach(cs42l42);
514 if (ret < 0)
515 return ret;
516
517 cs42l42_resume_restore(dev);
518
519 return 0;
520 }
521
cs42l42_sdw_probe(struct sdw_slave * peripheral,const struct sdw_device_id * id)522 static int cs42l42_sdw_probe(struct sdw_slave *peripheral, const struct sdw_device_id *id)
523 {
524 struct snd_soc_component_driver *component_drv;
525 struct device *dev = &peripheral->dev;
526 struct cs42l42_private *cs42l42;
527 struct regmap_config *regmap_conf;
528 struct regmap *regmap;
529 int irq, ret;
530
531 cs42l42 = devm_kzalloc(dev, sizeof(*cs42l42), GFP_KERNEL);
532 if (!cs42l42)
533 return -ENOMEM;
534
535 if (has_acpi_companion(dev))
536 irq = acpi_dev_gpio_irq_get(ACPI_COMPANION(dev), 0);
537 else
538 irq = of_irq_get(dev->of_node, 0);
539
540 if (irq == -ENOENT)
541 irq = 0;
542 else if (irq < 0)
543 return dev_err_probe(dev, irq, "Failed to get IRQ\n");
544
545 regmap_conf = devm_kmemdup(dev, &cs42l42_regmap, sizeof(cs42l42_regmap), GFP_KERNEL);
546 if (!regmap_conf)
547 return -ENOMEM;
548 regmap_conf->reg_bits = 16;
549 regmap_conf->num_ranges = 0;
550 regmap_conf->reg_read = cs42l42_sdw_read;
551 regmap_conf->reg_write = cs42l42_sdw_write;
552
553 regmap = devm_regmap_init(dev, NULL, peripheral, regmap_conf);
554 if (IS_ERR(regmap))
555 return dev_err_probe(dev, PTR_ERR(regmap), "Failed to allocate register map\n");
556
557 /* Start in cache-only until device is enumerated */
558 regcache_cache_only(regmap, true);
559
560 component_drv = devm_kmemdup(dev,
561 &cs42l42_soc_component,
562 sizeof(cs42l42_soc_component),
563 GFP_KERNEL);
564 if (!component_drv)
565 return -ENOMEM;
566
567 component_drv->dapm_routes = cs42l42_sdw_audio_map;
568 component_drv->num_dapm_routes = ARRAY_SIZE(cs42l42_sdw_audio_map);
569
570 cs42l42->dev = dev;
571 cs42l42->regmap = regmap;
572 cs42l42->sdw_peripheral = peripheral;
573 cs42l42->irq = irq;
574 cs42l42->devid = CS42L42_CHIP_ID;
575
576 /*
577 * pm_runtime is needed to control bus manager suspend, and to
578 * recover from an unattach_request when the manager suspends.
579 */
580 pm_runtime_set_autosuspend_delay(cs42l42->dev, 3000);
581 pm_runtime_use_autosuspend(cs42l42->dev);
582 pm_runtime_mark_last_busy(cs42l42->dev);
583 pm_runtime_set_active(cs42l42->dev);
584 pm_runtime_get_noresume(cs42l42->dev);
585 pm_runtime_enable(cs42l42->dev);
586
587 ret = cs42l42_common_probe(cs42l42, component_drv, &cs42l42_sdw_dai);
588 if (ret < 0)
589 return ret;
590
591 return 0;
592 }
593
cs42l42_sdw_remove(struct sdw_slave * peripheral)594 static void cs42l42_sdw_remove(struct sdw_slave *peripheral)
595 {
596 struct cs42l42_private *cs42l42 = dev_get_drvdata(&peripheral->dev);
597
598 cs42l42_common_remove(cs42l42);
599 pm_runtime_disable(cs42l42->dev);
600 }
601
602 static const struct dev_pm_ops cs42l42_sdw_pm = {
603 SYSTEM_SLEEP_PM_OPS(cs42l42_suspend, cs42l42_sdw_resume)
604 RUNTIME_PM_OPS(cs42l42_sdw_runtime_suspend, cs42l42_sdw_runtime_resume, NULL)
605 };
606
607 static const struct sdw_device_id cs42l42_sdw_id[] = {
608 SDW_SLAVE_ENTRY(0x01FA, 0x4242, 0),
609 {},
610 };
611 MODULE_DEVICE_TABLE(sdw, cs42l42_sdw_id);
612
613 static struct sdw_driver cs42l42_sdw_driver = {
614 .driver = {
615 .name = "cs42l42-sdw",
616 .pm = pm_ptr(&cs42l42_sdw_pm),
617 },
618 .probe = cs42l42_sdw_probe,
619 .remove = cs42l42_sdw_remove,
620 .ops = &cs42l42_sdw_ops,
621 .id_table = cs42l42_sdw_id,
622 };
623
624 module_sdw_driver(cs42l42_sdw_driver);
625
626 MODULE_DESCRIPTION("ASoC CS42L42 SoundWire driver");
627 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>");
628 MODULE_LICENSE("GPL");
629 MODULE_IMPORT_NS("SND_SOC_CS42L42_CORE");
630