1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip KSZ8XXX series switch driver 4 * 5 * It supports the following switches: 6 * - KSZ8995XA (the oldest ancestor) 7 * - KSZ8463 8 * - KSZ8863, KSZ8873 aka KSZ88X3 9 * - KSZ8895, KSZ8864 aka KSZ8895 family 10 * - KSZ8794, KSZ8795, KSZ8765 aka KSZ87XX 11 * Note that it does NOT support: 12 * - KSZ8563, KSZ8567 - see KSZ9477 driver 13 * 14 * Copyright (C) 2017 Microchip Technology Inc. 15 * Tristram Ha <Tristram.Ha@microchip.com> 16 */ 17 18 #include <linux/bitfield.h> 19 #include <linux/delay.h> 20 #include <linux/dsa/ksz_common.h> 21 #include <linux/export.h> 22 #include <linux/gpio/consumer.h> 23 #include <linux/if_vlan.h> 24 #include <linux/iopoll.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/platform_data/microchip-ksz.h> 28 #include <linux/phy.h> 29 #include <linux/etherdevice.h> 30 #include <linux/if_bridge.h> 31 #include <linux/micrel_phy.h> 32 #include <net/dsa.h> 33 #include <net/switchdev.h> 34 #include <linux/phylink.h> 35 36 #include "ksz_common.h" 37 #include "ksz_dcb.h" 38 #include "ksz8_reg.h" 39 #include "ksz8.h" 40 41 /* 42 * We use only the high-byte (so odd addresses) of the 16-bits registers to fit 43 * in the common IRQ framework 44 */ 45 #define KSZ8463_REG_ISR 0x191 46 #define KSZ8463_REG_IER 0x193 47 48 /* ksz88x3_drive_strengths - Drive strength mapping for KSZ8863, KSZ8873, .. 49 * variants. 50 * This values are documented in KSZ8873 and KSZ8863 datasheets. 51 */ 52 static const struct ksz_drive_strength ksz88x3_drive_strengths[] = { 53 { 0, 8000 }, 54 { KSZ8873_DRIVE_STRENGTH_16MA, 16000 }, 55 }; 56 57 struct ksz88xx_stats_raw { 58 u64 rx; 59 u64 rx_hi; 60 u64 rx_undersize; 61 u64 rx_fragments; 62 u64 rx_oversize; 63 u64 rx_jabbers; 64 u64 rx_symbol_err; 65 u64 rx_crc_err; 66 u64 rx_align_err; 67 u64 rx_mac_ctrl; 68 u64 rx_pause; 69 u64 rx_bcast; 70 u64 rx_mcast; 71 u64 rx_ucast; 72 u64 rx_64_or_less; 73 u64 rx_65_127; 74 u64 rx_128_255; 75 u64 rx_256_511; 76 u64 rx_512_1023; 77 u64 rx_1024_1522; 78 u64 tx; 79 u64 tx_hi; 80 u64 tx_late_col; 81 u64 tx_pause; 82 u64 tx_bcast; 83 u64 tx_mcast; 84 u64 tx_ucast; 85 u64 tx_deferred; 86 u64 tx_total_col; 87 u64 tx_exc_col; 88 u64 tx_single_col; 89 u64 tx_mult_col; 90 u64 rx_discards; 91 u64 tx_discards; 92 }; 93 94 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set) 95 { 96 ksz_rmw8(dev, addr, bits, set ? bits : 0); 97 } 98 99 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits, 100 bool set) 101 { 102 ksz_rmw8(dev, dev->dev_ops->get_port_addr(port, offset), bits, 103 set ? bits : 0); 104 } 105 106 /** 107 * ksz8_ind_write8 - EEE/ACL/PME indirect register write 108 * @dev: The device structure. 109 * @table: Function & table select, register 110. 110 * @addr: Indirect access control, register 111. 111 * @data: The data to be written. 112 * 113 * This function performs an indirect register write for EEE, ACL or 114 * PME switch functionalities. Both 8-bit registers 110 and 111 are 115 * written at once with ksz_write16, using the serial multiple write 116 * functionality. 117 * 118 * Return: 0 on success, or an error code on failure. 119 */ 120 static int ksz8_ind_write8(struct ksz_device *dev, u8 table, u16 addr, u8 data) 121 { 122 const u16 *regs; 123 u16 ctrl_addr; 124 int ret = 0; 125 126 regs = dev->info->regs; 127 128 mutex_lock(&dev->alu_mutex); 129 130 ctrl_addr = IND_ACC_TABLE(table) | addr; 131 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 132 if (!ret) 133 ret = ksz_write8(dev, regs[REG_IND_BYTE], data); 134 135 mutex_unlock(&dev->alu_mutex); 136 137 return ret; 138 } 139 140 /** 141 * ksz8_ind_read8 - EEE/ACL/PME indirect register read 142 * @dev: The device structure. 143 * @table: Function & table select, register 110. 144 * @addr: Indirect access control, register 111. 145 * @val: The value read. 146 * 147 * This function performs an indirect register read for EEE, ACL or 148 * PME switch functionalities. Both 8-bit registers 110 and 111 are 149 * written at once with ksz_write16, using the serial multiple write 150 * functionality. 151 * 152 * Return: 0 on success, or an error code on failure. 153 */ 154 static int ksz8_ind_read8(struct ksz_device *dev, u8 table, u16 addr, u8 *val) 155 { 156 const u16 *regs; 157 u16 ctrl_addr; 158 int ret = 0; 159 160 regs = dev->info->regs; 161 162 mutex_lock(&dev->alu_mutex); 163 164 ctrl_addr = IND_ACC_TABLE(table | TABLE_READ) | addr; 165 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 166 if (!ret) 167 ret = ksz_read8(dev, regs[REG_IND_BYTE], val); 168 169 mutex_unlock(&dev->alu_mutex); 170 171 return ret; 172 } 173 174 static int ksz8_pme_write8(struct ksz_device *dev, u32 reg, u8 value) 175 { 176 return ksz8_ind_write8(dev, (u8)(reg >> 8), (u8)(reg), value); 177 } 178 179 static int ksz8_pme_pread8(struct ksz_device *dev, int port, int offset, u8 *data) 180 { 181 u8 table = (u8)(offset >> 8 | (port + 1)); 182 183 return ksz8_ind_read8(dev, table, (u8)(offset), data); 184 } 185 186 static int ksz8_pme_pwrite8(struct ksz_device *dev, int port, int offset, u8 data) 187 { 188 u8 table = (u8)(offset >> 8 | (port + 1)); 189 190 return ksz8_ind_write8(dev, table, (u8)(offset), data); 191 } 192 193 static void ksz8463_irq_mask(struct irq_data *d) 194 { 195 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 196 197 kirq->masked &= ~BIT(d->hwirq); 198 } 199 200 static void ksz8463_irq_unmask(struct irq_data *d) 201 { 202 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 203 204 kirq->masked |= BIT(d->hwirq); 205 } 206 207 static const struct irq_chip ksz8463_irq_chip = { 208 .name = "ksz8463-irq", 209 .irq_mask = ksz8463_irq_mask, 210 .irq_unmask = ksz8463_irq_unmask, 211 .irq_bus_lock = ksz_irq_bus_lock, 212 .irq_bus_sync_unlock = ksz_irq_bus_sync_unlock, 213 }; 214 215 static int ksz8463_irq_domain_map(struct irq_domain *d, 216 unsigned int irq, irq_hw_number_t hwirq) 217 { 218 irq_set_chip_data(irq, d->host_data); 219 irq_set_chip_and_handler(irq, &ksz8463_irq_chip, handle_level_irq); 220 irq_set_noprobe(irq); 221 222 return 0; 223 } 224 225 static const struct irq_domain_ops ksz8463_irq_domain_ops = { 226 .map = ksz8463_irq_domain_map, 227 .xlate = irq_domain_xlate_twocell, 228 }; 229 230 static int ksz8463_girq_setup(struct ksz_device *dev) 231 { 232 struct ksz_irq *girq = &dev->girq; 233 234 girq->nirqs = 8; 235 girq->reg_mask = KSZ8463_REG_IER; 236 girq->reg_status = KSZ8463_REG_ISR; 237 girq->masked = 0; 238 snprintf(girq->name, sizeof(girq->name), "ksz8463-girq"); 239 240 girq->irq_num = dev->irq; 241 242 return ksz_irq_common_setup(dev, girq, &ksz8463_irq_domain_ops); 243 } 244 245 static int ksz8463_reset_switch(struct ksz_device *dev) 246 { 247 ksz_cfg(dev, KSZ8463_REG_SW_RESET, 248 KSZ8463_GLOBAL_SOFTWARE_RESET | KSZ8463_PTP_SOFTWARE_RESET, 249 true); 250 ksz_cfg(dev, KSZ8463_REG_SW_RESET, 251 KSZ8463_GLOBAL_SOFTWARE_RESET | KSZ8463_PTP_SOFTWARE_RESET, 252 false); 253 return 0; 254 } 255 256 static int ksz8_reset_switch(struct ksz_device *dev) 257 { 258 if (ksz_is_ksz8995xa(dev)) { 259 unsigned int port, reg, val; 260 int ret; 261 262 /* The KSZ8995XA switch itself cannot be reset by software, but 263 * often boot loaders have fun with ports, so reset them. This 264 * reset bit is self-clearing. 265 */ 266 for (port = 0; port < dev->info->port_cnt; port++) { 267 ret = ksz_prmw8(dev, port, REG_PORT_STATUS_3, 268 PORT_PHY_SOFT_RESET, 269 PORT_PHY_SOFT_RESET); 270 if (ret) 271 return ret; 272 } 273 274 /* IEEE 802.3 allows up to 500 ms for a PHY reset. */ 275 for (port = 0; port < dev->info->port_cnt; port++) { 276 reg = dev->dev_ops->get_port_addr(port, REG_PORT_STATUS_3); 277 ret = regmap_read_poll_timeout(ksz_regmap_8(dev), reg, val, 278 !(val & PORT_PHY_SOFT_RESET), 279 1000, 600000); 280 if (ret) 281 return ret; 282 } 283 284 /* Some PHYs need additional settling time after reset. */ 285 usleep_range(1000, 2000); 286 } else if (ksz_is_ksz88x3(dev)) { 287 /* reset switch */ 288 ksz_cfg(dev, KSZ8863_REG_SW_RESET, 289 KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, true); 290 ksz_cfg(dev, KSZ8863_REG_SW_RESET, 291 KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, false); 292 } else { 293 /* reset switch */ 294 ksz_write8(dev, REG_POWER_MANAGEMENT_1, 295 SW_SOFTWARE_POWER_DOWN << SW_POWER_MANAGEMENT_MODE_S); 296 ksz_write8(dev, REG_POWER_MANAGEMENT_1, 0); 297 } 298 299 return 0; 300 } 301 302 static int ksz8995xa_change_mtu(struct dsa_switch *ds, int port, int mtu) 303 { 304 struct ksz_device *dev = ds->priv; 305 int frame_size; 306 u8 ctrl2 = 0; 307 308 if (!dsa_is_cpu_port(dev->ds, port)) 309 return 0; 310 311 frame_size = mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 312 313 /* The legal packet size bit polarity documented in the KSZ8995XA 314 * manual appears to be wrong. Practical tests show that the same 315 * semantics as the other switches are correct; using the documented 316 * polarity makes the switch hang on big packets. 317 */ 318 if (frame_size <= KSZ8995XA_LEGAL_PACKET_SIZE) 319 ctrl2 |= KSZ8863_LEGAL_PACKET_ENABLE; 320 else if (frame_size > KSZ8863_NORMAL_PACKET_SIZE) 321 ctrl2 |= KSZ8863_HUGE_PACKET_ENABLE; 322 323 return ksz_rmw8(dev, REG_SW_CTRL_2, KSZ8863_LEGAL_PACKET_ENABLE | 324 KSZ8863_HUGE_PACKET_ENABLE, ctrl2); 325 } 326 327 static int ksz88xx_change_mtu(struct dsa_switch *ds, int port, int mtu) 328 { 329 struct ksz_device *dev = ds->priv; 330 int frame_size; 331 u8 ctrl2 = 0; 332 333 if (!dsa_is_cpu_port(dev->ds, port)) 334 return 0; 335 336 frame_size = mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 337 338 if (frame_size <= KSZ8_LEGAL_PACKET_SIZE) 339 ctrl2 |= KSZ8863_LEGAL_PACKET_ENABLE; 340 else if (frame_size > KSZ8863_NORMAL_PACKET_SIZE) 341 ctrl2 |= KSZ8863_HUGE_PACKET_ENABLE; 342 343 return ksz_rmw8(dev, REG_SW_CTRL_2, KSZ8863_LEGAL_PACKET_ENABLE | 344 KSZ8863_HUGE_PACKET_ENABLE, ctrl2); 345 } 346 347 static int ksz87xx_change_mtu(struct dsa_switch *ds, int port, int mtu) 348 { 349 struct ksz_device *dev = ds->priv; 350 u8 ctrl1 = 0, ctrl2 = 0; 351 u16 frame_size; 352 int ret; 353 354 if (!dsa_is_cpu_port(dev->ds, port)) 355 return 0; 356 357 frame_size = mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 358 359 if (frame_size > KSZ8_LEGAL_PACKET_SIZE) 360 ctrl2 |= SW_LEGAL_PACKET_DISABLE; 361 if (frame_size > KSZ8863_NORMAL_PACKET_SIZE) 362 ctrl1 |= SW_HUGE_PACKET; 363 364 ret = ksz_rmw8(dev, REG_SW_CTRL_1, SW_HUGE_PACKET, ctrl1); 365 if (ret) 366 return ret; 367 368 return ksz_rmw8(dev, REG_SW_CTRL_2, SW_LEGAL_PACKET_DISABLE, ctrl2); 369 } 370 371 static int ksz87xx_max_mtu(struct dsa_switch *ds, int port) 372 { 373 return KSZ8795_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 374 } 375 376 static int ksz88xx_max_mtu(struct dsa_switch *ds, int port) 377 { 378 return KSZ8863_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 379 } 380 381 static int ksz8_port_queue_split(struct ksz_device *dev, int port, int queues) 382 { 383 u8 mask_4q = 0, mask_2q; 384 u8 reg_4q = 0, reg_2q; 385 u8 data_4q = 0; 386 u8 data_2q = 0; 387 int ret; 388 389 if (ksz_is_ksz88x3(dev)) { 390 mask_4q = KSZ8873_PORT_4QUEUE_SPLIT_EN; 391 mask_2q = KSZ8873_PORT_2QUEUE_SPLIT_EN; 392 reg_4q = REG_PORT_CTRL_0; 393 reg_2q = REG_PORT_CTRL_2; 394 395 /* KSZ8795 family switches have Weighted Fair Queueing (WFQ) 396 * enabled by default. Enable it for KSZ8873 family switches 397 * too. Default value for KSZ8873 family is strict priority, 398 * which should be enabled by using TC_SETUP_QDISC_ETS, not 399 * by default. 400 */ 401 ret = ksz_rmw8(dev, REG_SW_CTRL_3, WEIGHTED_FAIR_QUEUE_ENABLE, 402 WEIGHTED_FAIR_QUEUE_ENABLE); 403 if (ret) 404 return ret; 405 } else if (ksz_is_ksz8463(dev)) { 406 mask_4q = KSZ8873_PORT_4QUEUE_SPLIT_EN; 407 mask_2q = KSZ8873_PORT_2QUEUE_SPLIT_EN; 408 reg_4q = P1CR1; 409 reg_2q = P1CR1 + 1; 410 } else if (ksz_is_ksz8995xa(dev)) { 411 /* This switch has no 4way split support */ 412 mask_2q = KSZ8795_PORT_2QUEUE_SPLIT_EN; 413 reg_2q = REG_PORT_CTRL_0; 414 } else { 415 mask_4q = KSZ8795_PORT_4QUEUE_SPLIT_EN; 416 mask_2q = KSZ8795_PORT_2QUEUE_SPLIT_EN; 417 reg_4q = REG_PORT_CTRL_13; 418 reg_2q = REG_PORT_CTRL_0; 419 420 /* TODO: this is legacy from initial KSZ8795 driver, should be 421 * moved to appropriate place in the future. 422 */ 423 ret = ksz_rmw8(dev, REG_SW_CTRL_19, 424 SW_OUT_RATE_LIMIT_QUEUE_BASED, 425 SW_OUT_RATE_LIMIT_QUEUE_BASED); 426 if (ret) 427 return ret; 428 } 429 430 if (queues == 4) 431 data_4q = mask_4q; 432 else if (queues == 2) 433 data_2q = mask_2q; 434 435 if (mask_4q) { 436 ret = ksz_prmw8(dev, port, reg_4q, mask_4q, data_4q); 437 if (ret) 438 return ret; 439 } 440 441 return ksz_prmw8(dev, port, reg_2q, mask_2q, data_2q); 442 } 443 444 static void ksz8_r_mib_cnt(struct ksz_device *dev, int port, u16 addr, u64 *cnt) 445 { 446 const u32 *masks; 447 const u16 *regs; 448 u16 ctrl_addr; 449 u32 data; 450 u8 check; 451 int loop; 452 453 masks = dev->info->masks; 454 regs = dev->info->regs; 455 456 ctrl_addr = addr + dev->info->reg_mib_cnt * port; 457 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ); 458 459 mutex_lock(&dev->alu_mutex); 460 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 461 462 /* It is almost guaranteed to always read the valid bit because of 463 * slow SPI speed. 464 */ 465 for (loop = 2; loop > 0; loop--) { 466 ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check); 467 468 if (check & masks[MIB_COUNTER_VALID]) { 469 ksz_read32(dev, regs[REG_IND_DATA_LO], &data); 470 if (check & masks[MIB_COUNTER_OVERFLOW]) 471 *cnt += MIB_COUNTER_VALUE + 1; 472 *cnt += data & MIB_COUNTER_VALUE; 473 break; 474 } 475 } 476 mutex_unlock(&dev->alu_mutex); 477 } 478 479 static void ksz8795_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 480 u64 *dropped, u64 *cnt) 481 { 482 const u32 *masks; 483 const u16 *regs; 484 u16 ctrl_addr; 485 u32 data; 486 u8 check; 487 int loop; 488 489 masks = dev->info->masks; 490 regs = dev->info->regs; 491 492 addr -= dev->info->reg_mib_cnt; 493 ctrl_addr = (KSZ8795_MIB_TOTAL_RX_1 - KSZ8795_MIB_TOTAL_RX_0) * port; 494 ctrl_addr += addr + KSZ8795_MIB_TOTAL_RX_0; 495 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ); 496 497 mutex_lock(&dev->alu_mutex); 498 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 499 500 /* It is almost guaranteed to always read the valid bit because of 501 * slow SPI speed. 502 */ 503 for (loop = 2; loop > 0; loop--) { 504 ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check); 505 506 if (check & masks[MIB_COUNTER_VALID]) { 507 ksz_read32(dev, regs[REG_IND_DATA_LO], &data); 508 if (addr < 2) { 509 u64 total; 510 511 total = check & MIB_TOTAL_BYTES_H; 512 total <<= 32; 513 *cnt += total; 514 *cnt += data; 515 if (check & masks[MIB_COUNTER_OVERFLOW]) { 516 total = MIB_TOTAL_BYTES_H + 1; 517 total <<= 32; 518 *cnt += total; 519 } 520 } else { 521 if (check & masks[MIB_COUNTER_OVERFLOW]) 522 *cnt += MIB_PACKET_DROPPED + 1; 523 *cnt += data & MIB_PACKET_DROPPED; 524 } 525 break; 526 } 527 } 528 mutex_unlock(&dev->alu_mutex); 529 } 530 531 static void ksz8863_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 532 u64 *dropped, u64 *cnt) 533 { 534 u32 *last = (u32 *)dropped; 535 const u16 *regs; 536 u16 ctrl_addr; 537 u32 data; 538 u32 cur; 539 540 regs = dev->info->regs; 541 542 addr -= dev->info->reg_mib_cnt; 543 ctrl_addr = addr ? KSZ8863_MIB_PACKET_DROPPED_TX_0 : 544 KSZ8863_MIB_PACKET_DROPPED_RX_0; 545 if (ksz_is_8895_family(dev) && 546 ctrl_addr == KSZ8863_MIB_PACKET_DROPPED_RX_0) 547 ctrl_addr = KSZ8895_MIB_PACKET_DROPPED_RX_0; 548 ctrl_addr += port; 549 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ); 550 551 mutex_lock(&dev->alu_mutex); 552 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 553 ksz_read32(dev, regs[REG_IND_DATA_LO], &data); 554 mutex_unlock(&dev->alu_mutex); 555 556 data &= MIB_PACKET_DROPPED; 557 cur = last[addr]; 558 if (data != cur) { 559 last[addr] = data; 560 if (data < cur) 561 data += MIB_PACKET_DROPPED + 1; 562 data -= cur; 563 *cnt += data; 564 } 565 } 566 567 static void ksz8_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 568 u64 *dropped, u64 *cnt) 569 { 570 if (is_ksz88xx(dev)) 571 ksz8863_r_mib_pkt(dev, port, addr, dropped, cnt); 572 else 573 ksz8795_r_mib_pkt(dev, port, addr, dropped, cnt); 574 } 575 576 static void ksz8_freeze_mib(struct ksz_device *dev, int port, bool freeze) 577 { 578 if (is_ksz88xx(dev)) 579 return; 580 581 /* enable the port for flush/freeze function */ 582 if (freeze) 583 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true); 584 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FREEZE, freeze); 585 586 /* disable the port after freeze is done */ 587 if (!freeze) 588 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false); 589 } 590 591 static void ksz8_port_init_cnt(struct ksz_device *dev, int port) 592 { 593 struct ksz_port_mib *mib = &dev->ports[port].mib; 594 u64 *dropped; 595 596 /* For KSZ8795 family. */ 597 if (ksz_is_ksz87xx(dev)) { 598 /* flush all enabled port MIB counters */ 599 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true); 600 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FLUSH, true); 601 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false); 602 } 603 604 mib->cnt_ptr = 0; 605 606 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ 607 while (mib->cnt_ptr < dev->info->reg_mib_cnt) { 608 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, 609 &mib->counters[mib->cnt_ptr]); 610 ++mib->cnt_ptr; 611 } 612 613 /* last one in storage */ 614 dropped = &mib->counters[dev->info->mib_cnt]; 615 616 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ 617 while (mib->cnt_ptr < dev->info->mib_cnt) { 618 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, 619 dropped, &mib->counters[mib->cnt_ptr]); 620 ++mib->cnt_ptr; 621 } 622 } 623 624 static int ksz8_r_table(struct ksz_device *dev, int table, u16 addr, u64 *data) 625 { 626 const u16 *regs; 627 u16 ctrl_addr; 628 int ret; 629 630 regs = dev->info->regs; 631 632 ctrl_addr = IND_ACC_TABLE(table | TABLE_READ) | addr; 633 634 mutex_lock(&dev->alu_mutex); 635 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 636 if (ret) 637 goto unlock_alu; 638 639 ret = ksz_read64(dev, regs[REG_IND_DATA_HI], data); 640 unlock_alu: 641 mutex_unlock(&dev->alu_mutex); 642 643 return ret; 644 } 645 646 static int ksz8_w_table(struct ksz_device *dev, int table, u16 addr, u64 data) 647 { 648 const u16 *regs; 649 u16 ctrl_addr; 650 int ret; 651 652 regs = dev->info->regs; 653 654 ctrl_addr = IND_ACC_TABLE(table) | addr; 655 656 mutex_lock(&dev->alu_mutex); 657 ret = ksz_write64(dev, regs[REG_IND_DATA_HI], data); 658 if (ret) 659 goto unlock_alu; 660 661 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 662 unlock_alu: 663 mutex_unlock(&dev->alu_mutex); 664 665 return ret; 666 } 667 668 static int ksz8_valid_dyn_entry(struct ksz_device *dev, u8 *data) 669 { 670 int timeout = 100; 671 const u32 *masks; 672 const u16 *regs; 673 int ret; 674 675 masks = dev->info->masks; 676 regs = dev->info->regs; 677 678 do { 679 ret = ksz_read8(dev, regs[REG_IND_DATA_CHECK], data); 680 if (ret) 681 return ret; 682 683 timeout--; 684 } while ((*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) && timeout); 685 686 /* Entry is not ready for accessing. */ 687 if (*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) 688 return -ETIMEDOUT; 689 690 /* Entry is ready for accessing. */ 691 return ksz_read8(dev, regs[REG_IND_DATA_8], data); 692 } 693 694 static int ksz8_r_dyn_mac_table(struct ksz_device *dev, u16 addr, u8 *mac_addr, 695 u8 *fid, u8 *src_port, u16 *entries) 696 { 697 u32 data_hi, data_lo; 698 const u8 *shifts; 699 const u32 *masks; 700 const u16 *regs; 701 u16 ctrl_addr; 702 u64 buf = 0; 703 u8 data; 704 int cnt; 705 int ret; 706 707 shifts = dev->info->shifts; 708 masks = dev->info->masks; 709 regs = dev->info->regs; 710 711 ctrl_addr = IND_ACC_TABLE(TABLE_DYNAMIC_MAC | TABLE_READ) | addr; 712 713 mutex_lock(&dev->alu_mutex); 714 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 715 if (ret) 716 goto unlock_alu; 717 718 ret = ksz8_valid_dyn_entry(dev, &data); 719 if (ret) 720 goto unlock_alu; 721 722 if (data & masks[DYNAMIC_MAC_TABLE_MAC_EMPTY]) { 723 *entries = 0; 724 goto unlock_alu; 725 } 726 727 ret = ksz_read64(dev, regs[REG_IND_DATA_HI], &buf); 728 if (ret) 729 goto unlock_alu; 730 731 data_hi = (u32)(buf >> 32); 732 data_lo = (u32)buf; 733 734 /* Check out how many valid entry in the table. */ 735 cnt = data & masks[DYNAMIC_MAC_TABLE_ENTRIES_H]; 736 cnt <<= shifts[DYNAMIC_MAC_ENTRIES_H]; 737 cnt |= (data_hi & masks[DYNAMIC_MAC_TABLE_ENTRIES]) >> 738 shifts[DYNAMIC_MAC_ENTRIES]; 739 *entries = cnt + 1; 740 741 *fid = (data_hi & masks[DYNAMIC_MAC_TABLE_FID]) >> 742 shifts[DYNAMIC_MAC_FID]; 743 *src_port = (data_hi & masks[DYNAMIC_MAC_TABLE_SRC_PORT]) >> 744 shifts[DYNAMIC_MAC_SRC_PORT]; 745 746 mac_addr[5] = (u8)data_lo; 747 mac_addr[4] = (u8)(data_lo >> 8); 748 mac_addr[3] = (u8)(data_lo >> 16); 749 mac_addr[2] = (u8)(data_lo >> 24); 750 751 mac_addr[1] = (u8)data_hi; 752 mac_addr[0] = (u8)(data_hi >> 8); 753 754 unlock_alu: 755 mutex_unlock(&dev->alu_mutex); 756 757 return ret; 758 } 759 760 static int ksz8_r_sta_mac_table(struct ksz_device *dev, u16 addr, 761 struct alu_struct *alu, bool *valid) 762 { 763 u32 data_hi, data_lo; 764 const u8 *shifts; 765 const u32 *masks; 766 u64 data; 767 int ret; 768 769 shifts = dev->info->shifts; 770 masks = dev->info->masks; 771 772 ret = ksz8_r_table(dev, TABLE_STATIC_MAC, addr, &data); 773 if (ret) 774 return ret; 775 776 data_hi = data >> 32; 777 data_lo = (u32)data; 778 779 if (!(data_hi & (masks[STATIC_MAC_TABLE_VALID] | 780 masks[STATIC_MAC_TABLE_OVERRIDE]))) { 781 *valid = false; 782 return 0; 783 } 784 785 alu->mac[5] = (u8)data_lo; 786 alu->mac[4] = (u8)(data_lo >> 8); 787 alu->mac[3] = (u8)(data_lo >> 16); 788 alu->mac[2] = (u8)(data_lo >> 24); 789 alu->mac[1] = (u8)data_hi; 790 alu->mac[0] = (u8)(data_hi >> 8); 791 alu->port_forward = 792 (data_hi & masks[STATIC_MAC_TABLE_FWD_PORTS]) >> 793 shifts[STATIC_MAC_FWD_PORTS]; 794 alu->is_override = (data_hi & masks[STATIC_MAC_TABLE_OVERRIDE]) ? 1 : 0; 795 796 /* KSZ8795/KSZ8895 family switches have STATIC_MAC_TABLE_USE_FID and 797 * STATIC_MAC_TABLE_FID definitions off by 1 when doing read on the 798 * static MAC table compared to doing write. 799 */ 800 if (ksz_is_ksz87xx(dev) || ksz_is_8895_family(dev)) 801 data_hi >>= 1; 802 alu->is_static = true; 803 alu->is_use_fid = (data_hi & masks[STATIC_MAC_TABLE_USE_FID]) ? 1 : 0; 804 alu->fid = (data_hi & masks[STATIC_MAC_TABLE_FID]) >> 805 shifts[STATIC_MAC_FID]; 806 807 *valid = true; 808 809 return 0; 810 } 811 812 static int ksz8_w_sta_mac_table(struct ksz_device *dev, u16 addr, 813 struct alu_struct *alu) 814 { 815 u32 data_hi, data_lo; 816 const u8 *shifts; 817 const u32 *masks; 818 u64 data; 819 820 shifts = dev->info->shifts; 821 masks = dev->info->masks; 822 823 data_lo = ((u32)alu->mac[2] << 24) | 824 ((u32)alu->mac[3] << 16) | 825 ((u32)alu->mac[4] << 8) | alu->mac[5]; 826 data_hi = ((u32)alu->mac[0] << 8) | alu->mac[1]; 827 data_hi |= (u32)alu->port_forward << shifts[STATIC_MAC_FWD_PORTS]; 828 829 if (alu->is_override) 830 data_hi |= masks[STATIC_MAC_TABLE_OVERRIDE]; 831 if (alu->is_use_fid) { 832 data_hi |= masks[STATIC_MAC_TABLE_USE_FID]; 833 data_hi |= (u32)alu->fid << shifts[STATIC_MAC_FID]; 834 } 835 if (alu->is_static) 836 data_hi |= masks[STATIC_MAC_TABLE_VALID]; 837 else 838 data_hi &= ~masks[STATIC_MAC_TABLE_OVERRIDE]; 839 840 data = (u64)data_hi << 32 | data_lo; 841 842 return ksz8_w_table(dev, TABLE_STATIC_MAC, addr, data); 843 } 844 845 static void ksz8_from_vlan(struct ksz_device *dev, u32 vlan, u8 *fid, 846 u8 *member, u8 *valid) 847 { 848 const u8 *shifts; 849 const u32 *masks; 850 851 shifts = dev->info->shifts; 852 masks = dev->info->masks; 853 854 *fid = vlan & masks[VLAN_TABLE_FID]; 855 *member = (vlan & masks[VLAN_TABLE_MEMBERSHIP]) >> 856 shifts[VLAN_TABLE_MEMBERSHIP_S]; 857 *valid = !!(vlan & masks[VLAN_TABLE_VALID]); 858 } 859 860 static void ksz8_to_vlan(struct ksz_device *dev, u8 fid, u8 member, u8 valid, 861 u16 *vlan) 862 { 863 const u8 *shifts; 864 const u32 *masks; 865 866 shifts = dev->info->shifts; 867 masks = dev->info->masks; 868 869 *vlan = fid; 870 *vlan |= (u16)member << shifts[VLAN_TABLE_MEMBERSHIP_S]; 871 if (valid) 872 *vlan |= masks[VLAN_TABLE_VALID]; 873 } 874 875 static void ksz8_r_vlan_entries(struct ksz_device *dev, u16 addr) 876 { 877 const u8 *shifts; 878 u64 data; 879 int i; 880 881 shifts = dev->info->shifts; 882 883 ksz8_r_table(dev, TABLE_VLAN, addr, &data); 884 addr *= 4; 885 for (i = 0; i < 4; i++) { 886 dev->vlan_cache[addr + i].table[0] = (u16)data; 887 data >>= shifts[VLAN_TABLE]; 888 } 889 } 890 891 static void ksz8_r_vlan_table(struct ksz_device *dev, u16 vid, u16 *vlan) 892 { 893 int index; 894 u16 *data; 895 u16 addr; 896 u64 buf; 897 898 data = (u16 *)&buf; 899 addr = vid / 4; 900 index = vid & 3; 901 ksz8_r_table(dev, TABLE_VLAN, addr, &buf); 902 *vlan = data[index]; 903 } 904 905 static void ksz8_w_vlan_table(struct ksz_device *dev, u16 vid, u16 vlan) 906 { 907 int index; 908 u16 *data; 909 u16 addr; 910 u64 buf; 911 912 data = (u16 *)&buf; 913 addr = vid / 4; 914 index = vid & 3; 915 ksz8_r_table(dev, TABLE_VLAN, addr, &buf); 916 data[index] = vlan; 917 dev->vlan_cache[vid].table[0] = vlan; 918 ksz8_w_table(dev, TABLE_VLAN, addr, buf); 919 } 920 921 /** 922 * ksz879x_get_loopback - KSZ879x specific function to get loopback 923 * configuration status for a specific port 924 * @dev: Pointer to the device structure 925 * @port: Port number to query 926 * @val: Pointer to store the result 927 * 928 * This function reads the SMI registers to determine whether loopback mode 929 * is enabled for a specific port. 930 * 931 * Return: 0 on success, error code on failure. 932 */ 933 static int ksz879x_get_loopback(struct ksz_device *dev, u16 port, 934 u16 *val) 935 { 936 u8 stat3; 937 int ret; 938 939 ret = ksz_pread8(dev, port, REG_PORT_STATUS_3, &stat3); 940 if (ret) 941 return ret; 942 943 if (stat3 & PORT_PHY_LOOPBACK) 944 *val |= BMCR_LOOPBACK; 945 946 return 0; 947 } 948 949 /** 950 * ksz879x_set_loopback - KSZ879x specific function to set loopback mode for 951 * a specific port 952 * @dev: Pointer to the device structure. 953 * @port: Port number to modify. 954 * @val: Value indicating whether to enable or disable loopback mode. 955 * 956 * This function translates loopback bit of the BMCR register into the 957 * corresponding hardware register bit value and writes it to the SMI interface. 958 * 959 * Return: 0 on success, error code on failure. 960 */ 961 static int ksz879x_set_loopback(struct ksz_device *dev, u16 port, u16 val) 962 { 963 u8 stat3 = 0; 964 965 if (val & BMCR_LOOPBACK) 966 stat3 |= PORT_PHY_LOOPBACK; 967 968 return ksz_prmw8(dev, port, REG_PORT_STATUS_3, PORT_PHY_LOOPBACK, 969 stat3); 970 } 971 972 static int ksz87xx_apply_low_loss_preset(struct ksz_device *dev, bool enable) 973 { 974 /* Apply the Microchip erratum short-cable preset (LPF 62 MHz, EQ init 0) 975 * providing a conservative configuration for short or low-loss cables. 976 */ 977 u8 lpf_bw, eq_init; 978 int ret; 979 980 lpf_bw = KSZ87XX_PHY_LPF_62MHZ; 981 eq_init = KSZ87XX_DSP_EQ_INIT_LOW_LOSS; 982 983 if (!ksz_is_ksz87xx(dev)) 984 return -EOPNOTSUPP; 985 986 if (!enable) { 987 /* Restore default values (LPF 90 MHz, EQ init 15). */ 988 lpf_bw = KSZ87XX_PHY_LPF_90MHZ; 989 eq_init = KSZ87XX_DSP_EQ_INIT_FACTORY; 990 } 991 992 ret = ksz8_ind_write8(dev, TABLE_LINK_MD, KSZ87XX_REG_PHY_LPF, lpf_bw); 993 if (ret) 994 return ret; 995 996 dev->lpf_bw = lpf_bw; 997 ret = ksz8_ind_write8(dev, TABLE_LINK_MD, KSZ87XX_REG_DSP_EQ, eq_init); 998 if (ret) 999 return ret; 1000 1001 dev->eq_init = eq_init; 1002 1003 return ret; 1004 } 1005 1006 /** 1007 * ksz8_r_phy_ctrl - Translates and reads from the SMI interface to a MIIM PHY 1008 * Control register (Reg. 31). 1009 * @dev: The KSZ device instance. 1010 * @port: The port number to be read. 1011 * @val: The value read from the SMI interface. 1012 * 1013 * This function reads the SMI interface and translates the hardware register 1014 * bit values into their corresponding control settings for a MIIM PHY Control 1015 * register. 1016 * 1017 * Return: 0 on success, error code on failure. 1018 */ 1019 static int ksz8_r_phy_ctrl(struct ksz_device *dev, int port, u16 *val) 1020 { 1021 const u16 *regs = dev->info->regs; 1022 u8 reg_val; 1023 int ret; 1024 1025 *val = 0; 1026 1027 ret = ksz_pread8(dev, port, regs[P_LINK_STATUS], ®_val); 1028 if (ret < 0) 1029 return ret; 1030 1031 if (reg_val & PORT_MDIX_STATUS) 1032 *val |= KSZ886X_CTRL_MDIX_STAT; 1033 1034 /* KSZ8995XA has no fancy features in register 0xA */ 1035 if (ksz_is_ksz8995xa(dev)) 1036 return 0; 1037 1038 ret = ksz_pread8(dev, port, REG_PORT_LINK_MD_CTRL, ®_val); 1039 if (ret < 0) 1040 return ret; 1041 1042 if (reg_val & PORT_FORCE_LINK) 1043 *val |= KSZ886X_CTRL_FORCE_LINK; 1044 1045 if (reg_val & PORT_POWER_SAVING) 1046 *val |= KSZ886X_CTRL_PWRSAVE; 1047 1048 if (reg_val & PORT_PHY_REMOTE_LOOPBACK) 1049 *val |= KSZ886X_CTRL_REMOTE_LOOPBACK; 1050 1051 return 0; 1052 } 1053 1054 /** 1055 * ksz8_r_phy_bmcr - Translates and reads from the SMI interface to a MIIM PHY 1056 * Basic mode control register (Reg. 0). 1057 * @dev: The KSZ device instance. 1058 * @port: The port number to be read. 1059 * @val: The value read from the SMI interface. 1060 * 1061 * This function reads the SMI interface and translates the hardware register 1062 * bit values into their corresponding control settings for a MIIM PHY Basic 1063 * mode control register. 1064 * 1065 * MIIM Bit Mapping Comparison between KSZ8794 and KSZ8873 1066 * ------------------------------------------------------------------- 1067 * MIIM Bit | KSZ8794 Reg/Bit | KSZ8873 Reg/Bit 1068 * ----------------------------+-----------------------------+---------------- 1069 * Bit 15 - Soft Reset | 0xF/4 | Not supported 1070 * Bit 14 - Loopback | 0xD/0 (MAC), 0xF/7 (PHY) ~ 0xD/0 (PHY) 1071 * Bit 13 - Force 100 | 0xC/6 = 0xC/6 1072 * Bit 12 - AN Enable | 0xC/7 (reverse logic) ~ 0xC/7 1073 * Bit 11 - Power Down | 0xD/3 = 0xD/3 1074 * Bit 10 - PHY Isolate | 0xF/5 | Not supported 1075 * Bit 9 - Restart AN | 0xD/5 = 0xD/5 1076 * Bit 8 - Force Full-Duplex | 0xC/5 = 0xC/5 1077 * Bit 7 - Collision Test/Res. | Not supported | Not supported 1078 * Bit 6 - Reserved | Not supported | Not supported 1079 * Bit 5 - Hp_mdix | 0x9/7 ~ 0xF/7 1080 * Bit 4 - Force MDI | 0xD/1 = 0xD/1 1081 * Bit 3 - Disable MDIX | 0xD/2 = 0xD/2 1082 * Bit 2 - Disable Far-End F. | ???? | 0xD/4 1083 * Bit 1 - Disable Transmit | 0xD/6 = 0xD/6 1084 * Bit 0 - Disable LED | 0xD/7 = 0xD/7 1085 * ------------------------------------------------------------------- 1086 * 1087 * Return: 0 on success, error code on failure. 1088 */ 1089 static int ksz8_r_phy_bmcr(struct ksz_device *dev, u16 port, u16 *val) 1090 { 1091 const u16 *regs = dev->info->regs; 1092 u8 restart, speed, ctrl; 1093 int ret; 1094 1095 *val = 0; 1096 1097 ret = ksz_pread8(dev, port, regs[P_NEG_RESTART_CTRL], &restart); 1098 if (ret) 1099 return ret; 1100 1101 ret = ksz_pread8(dev, port, regs[P_SPEED_STATUS], &speed); 1102 if (ret) 1103 return ret; 1104 1105 ret = ksz_pread8(dev, port, regs[P_FORCE_CTRL], &ctrl); 1106 if (ret) 1107 return ret; 1108 1109 if (ctrl & PORT_FORCE_100_MBIT) 1110 *val |= BMCR_SPEED100; 1111 1112 if (ksz_is_ksz88x3(dev)) { 1113 if (restart & KSZ8873_PORT_PHY_LOOPBACK) 1114 *val |= BMCR_LOOPBACK; 1115 1116 if ((ctrl & PORT_AUTO_NEG_ENABLE)) 1117 *val |= BMCR_ANENABLE; 1118 } else { 1119 ret = ksz879x_get_loopback(dev, port, val); 1120 if (ret) 1121 return ret; 1122 1123 if (!(ctrl & PORT_AUTO_NEG_DISABLE)) 1124 *val |= BMCR_ANENABLE; 1125 } 1126 1127 if (restart & PORT_POWER_DOWN) 1128 *val |= BMCR_PDOWN; 1129 1130 if (restart & PORT_AUTO_NEG_RESTART) 1131 *val |= BMCR_ANRESTART; 1132 1133 if (ctrl & PORT_FORCE_FULL_DUPLEX) 1134 *val |= BMCR_FULLDPLX; 1135 1136 if (!ksz_is_ksz8995xa(dev)) { 1137 if (speed & PORT_HP_MDIX) 1138 *val |= KSZ886X_BMCR_HP_MDIX; 1139 } 1140 1141 if (restart & PORT_FORCE_MDIX) 1142 *val |= KSZ886X_BMCR_FORCE_MDI; 1143 1144 if (restart & PORT_AUTO_MDIX_DISABLE) 1145 *val |= KSZ886X_BMCR_DISABLE_AUTO_MDIX; 1146 1147 if (restart & PORT_TX_DISABLE) 1148 *val |= KSZ886X_BMCR_DISABLE_TRANSMIT; 1149 1150 if (restart & PORT_LED_OFF) 1151 *val |= KSZ886X_BMCR_DISABLE_LED; 1152 1153 return 0; 1154 } 1155 1156 static int ksz8_r_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 *val) 1157 { 1158 u8 ctrl, link, val1, val2; 1159 int processed = true; 1160 const u16 *regs; 1161 u16 data = 0; 1162 u16 p = phy; 1163 int ret; 1164 1165 regs = dev->info->regs; 1166 1167 switch (reg) { 1168 case MII_BMCR: 1169 ret = ksz8_r_phy_bmcr(dev, p, &data); 1170 if (ret) 1171 return ret; 1172 break; 1173 case MII_BMSR: 1174 ret = ksz_pread8(dev, p, regs[P_LINK_STATUS], &link); 1175 if (ret) 1176 return ret; 1177 1178 data = BMSR_100FULL | 1179 BMSR_100HALF | 1180 BMSR_10FULL | 1181 BMSR_10HALF | 1182 BMSR_ANEGCAPABLE; 1183 if (link & PORT_AUTO_NEG_COMPLETE) 1184 data |= BMSR_ANEGCOMPLETE; 1185 if (link & PORT_STAT_LINK_GOOD) 1186 data |= BMSR_LSTATUS; 1187 break; 1188 case MII_PHYSID1: 1189 data = KSZ8795_ID_HI; 1190 break; 1191 case MII_PHYSID2: 1192 if (ksz_is_ksz88x3(dev)) 1193 data = KSZ8863_ID_LO; 1194 else 1195 data = KSZ8795_ID_LO; 1196 break; 1197 case MII_ADVERTISE: 1198 ret = ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl); 1199 if (ret) 1200 return ret; 1201 1202 data = ADVERTISE_CSMA; 1203 if (ctrl & PORT_AUTO_NEG_SYM_PAUSE) 1204 data |= ADVERTISE_PAUSE_CAP; 1205 if (ctrl & PORT_AUTO_NEG_100BTX_FD) 1206 data |= ADVERTISE_100FULL; 1207 if (ctrl & PORT_AUTO_NEG_100BTX) 1208 data |= ADVERTISE_100HALF; 1209 if (ctrl & PORT_AUTO_NEG_10BT_FD) 1210 data |= ADVERTISE_10FULL; 1211 if (ctrl & PORT_AUTO_NEG_10BT) 1212 data |= ADVERTISE_10HALF; 1213 break; 1214 case MII_LPA: 1215 ret = ksz_pread8(dev, p, regs[P_REMOTE_STATUS], &link); 1216 if (ret) 1217 return ret; 1218 1219 data = LPA_SLCT; 1220 if (link & PORT_REMOTE_SYM_PAUSE) 1221 data |= LPA_PAUSE_CAP; 1222 if (link & PORT_REMOTE_100BTX_FD) 1223 data |= LPA_100FULL; 1224 if (link & PORT_REMOTE_100BTX) 1225 data |= LPA_100HALF; 1226 if (link & PORT_REMOTE_10BT_FD) 1227 data |= LPA_10FULL; 1228 if (link & PORT_REMOTE_10BT) 1229 data |= LPA_10HALF; 1230 if (data & ~LPA_SLCT) 1231 data |= LPA_LPACK; 1232 break; 1233 case PHY_REG_LINK_MD: 1234 if (ksz_is_ksz8995xa(dev)) 1235 return -EOPNOTSUPP; 1236 1237 ret = ksz_pread8(dev, p, REG_PORT_LINK_MD_CTRL, &val1); 1238 if (ret) 1239 return ret; 1240 1241 ret = ksz_pread8(dev, p, REG_PORT_LINK_MD_RESULT, &val2); 1242 if (ret) 1243 return ret; 1244 1245 if (val1 & PORT_START_CABLE_DIAG) 1246 data |= PHY_START_CABLE_DIAG; 1247 1248 if (val1 & PORT_CABLE_10M_SHORT) 1249 data |= PHY_CABLE_10M_SHORT; 1250 1251 data |= FIELD_PREP(PHY_CABLE_DIAG_RESULT_M, 1252 FIELD_GET(PORT_CABLE_DIAG_RESULT_M, val1)); 1253 1254 data |= FIELD_PREP(PHY_CABLE_FAULT_COUNTER_M, 1255 (FIELD_GET(PORT_CABLE_FAULT_COUNTER_H, val1) << 8) | 1256 FIELD_GET(PORT_CABLE_FAULT_COUNTER_L, val2)); 1257 break; 1258 case PHY_REG_PHY_CTRL: 1259 ret = ksz8_r_phy_ctrl(dev, p, &data); 1260 if (ret) 1261 return ret; 1262 1263 break; 1264 case PHY_REG_KSZ87XX_SHORT_CABLE: 1265 if (!ksz_is_ksz87xx(dev)) 1266 return -EOPNOTSUPP; 1267 data = !!(dev->lpf_bw == KSZ87XX_PHY_LPF_62MHZ && 1268 dev->eq_init == KSZ87XX_DSP_EQ_INIT_LOW_LOSS); 1269 break; 1270 case PHY_REG_KSZ87XX_LPF_BW: 1271 if (!ksz_is_ksz87xx(dev)) 1272 return -EOPNOTSUPP; 1273 data = dev->lpf_bw; 1274 break; 1275 case PHY_REG_KSZ87XX_EQ_INIT: 1276 if (!ksz_is_ksz87xx(dev)) 1277 return -EOPNOTSUPP; 1278 data = dev->eq_init; 1279 break; 1280 default: 1281 processed = false; 1282 break; 1283 } 1284 if (processed) 1285 *val = data; 1286 1287 return 0; 1288 } 1289 1290 static int ksz8_phy_read16(struct dsa_switch *ds, int addr, int reg) 1291 { 1292 struct ksz_device *dev = ds->priv; 1293 u16 val = 0xffff; 1294 int ret; 1295 1296 ret = ksz8_r_phy(dev, addr, reg, &val); 1297 if (ret) 1298 return ret; 1299 1300 return val; 1301 } 1302 1303 /** 1304 * ksz8_w_phy_ctrl - Translates and writes to the SMI interface from a MIIM PHY 1305 * Control register (Reg. 31). 1306 * @dev: The KSZ device instance. 1307 * @port: The port number to be configured. 1308 * @val: The register value to be written. 1309 * 1310 * This function translates control settings from a MIIM PHY Control register 1311 * into their corresponding hardware register bit values for the SMI 1312 * interface. 1313 * 1314 * Return: 0 on success, error code on failure. 1315 */ 1316 static int ksz8_w_phy_ctrl(struct ksz_device *dev, int port, u16 val) 1317 { 1318 u8 reg_val = 0; 1319 int ret; 1320 1321 if (val & KSZ886X_CTRL_FORCE_LINK) 1322 reg_val |= PORT_FORCE_LINK; 1323 1324 if (val & KSZ886X_CTRL_PWRSAVE) 1325 reg_val |= PORT_POWER_SAVING; 1326 1327 if (val & KSZ886X_CTRL_REMOTE_LOOPBACK) 1328 reg_val |= PORT_PHY_REMOTE_LOOPBACK; 1329 1330 ret = ksz_prmw8(dev, port, REG_PORT_LINK_MD_CTRL, PORT_FORCE_LINK | 1331 PORT_POWER_SAVING | PORT_PHY_REMOTE_LOOPBACK, reg_val); 1332 return ret; 1333 } 1334 1335 /** 1336 * ksz8_w_phy_bmcr - Translates and writes to the SMI interface from a MIIM PHY 1337 * Basic mode control register (Reg. 0). 1338 * @dev: The KSZ device instance. 1339 * @port: The port number to be configured. 1340 * @val: The register value to be written. 1341 * 1342 * This function translates control settings from a MIIM PHY Basic mode control 1343 * register into their corresponding hardware register bit values for the SMI 1344 * interface. 1345 * 1346 * MIIM Bit Mapping Comparison between KSZ8794 and KSZ8873 1347 * ------------------------------------------------------------------- 1348 * MIIM Bit | KSZ8794 Reg/Bit | KSZ8873 Reg/Bit 1349 * ----------------------------+-----------------------------+---------------- 1350 * Bit 15 - Soft Reset | 0xF/4 | Not supported 1351 * Bit 14 - Loopback | 0xD/0 (MAC), 0xF/7 (PHY) ~ 0xD/0 (PHY) 1352 * Bit 13 - Force 100 | 0xC/6 = 0xC/6 1353 * Bit 12 - AN Enable | 0xC/7 (reverse logic) ~ 0xC/7 1354 * Bit 11 - Power Down | 0xD/3 = 0xD/3 1355 * Bit 10 - PHY Isolate | 0xF/5 | Not supported 1356 * Bit 9 - Restart AN | 0xD/5 = 0xD/5 1357 * Bit 8 - Force Full-Duplex | 0xC/5 = 0xC/5 1358 * Bit 7 - Collision Test/Res. | Not supported | Not supported 1359 * Bit 6 - Reserved | Not supported | Not supported 1360 * Bit 5 - Hp_mdix | 0x9/7 ~ 0xF/7 1361 * Bit 4 - Force MDI | 0xD/1 = 0xD/1 1362 * Bit 3 - Disable MDIX | 0xD/2 = 0xD/2 1363 * Bit 2 - Disable Far-End F. | ???? | 0xD/4 1364 * Bit 1 - Disable Transmit | 0xD/6 = 0xD/6 1365 * Bit 0 - Disable LED | 0xD/7 = 0xD/7 1366 * ------------------------------------------------------------------- 1367 * 1368 * Return: 0 on success, error code on failure. 1369 */ 1370 static int ksz8_w_phy_bmcr(struct ksz_device *dev, u16 port, u16 val) 1371 { 1372 u8 restart, speed, ctrl, restart_mask; 1373 const u16 *regs = dev->info->regs; 1374 int ret; 1375 1376 /* Do not support PHY reset function. */ 1377 if (val & BMCR_RESET) 1378 return 0; 1379 1380 if (!ksz_is_ksz8995xa(dev)) { 1381 speed = 0; 1382 if (val & KSZ886X_BMCR_HP_MDIX) 1383 speed |= PORT_HP_MDIX; 1384 1385 ret = ksz_prmw8(dev, port, regs[P_SPEED_STATUS], PORT_HP_MDIX, speed); 1386 if (ret) 1387 return ret; 1388 } 1389 1390 ctrl = 0; 1391 if (ksz_is_ksz88x3(dev)) { 1392 if ((val & BMCR_ANENABLE)) 1393 ctrl |= PORT_AUTO_NEG_ENABLE; 1394 } else { 1395 if (!(val & BMCR_ANENABLE)) 1396 ctrl |= PORT_AUTO_NEG_DISABLE; 1397 1398 /* Fiber port does not support auto-negotiation. */ 1399 if (dev->ports[port].fiber) 1400 ctrl |= PORT_AUTO_NEG_DISABLE; 1401 } 1402 1403 if (val & BMCR_SPEED100) 1404 ctrl |= PORT_FORCE_100_MBIT; 1405 1406 if (val & BMCR_FULLDPLX) 1407 ctrl |= PORT_FORCE_FULL_DUPLEX; 1408 1409 ret = ksz_prmw8(dev, port, regs[P_FORCE_CTRL], PORT_FORCE_100_MBIT | 1410 /* PORT_AUTO_NEG_ENABLE and PORT_AUTO_NEG_DISABLE are the same 1411 * bits 1412 */ 1413 PORT_FORCE_FULL_DUPLEX | PORT_AUTO_NEG_ENABLE, ctrl); 1414 if (ret) 1415 return ret; 1416 1417 restart = 0; 1418 restart_mask = PORT_LED_OFF | PORT_TX_DISABLE | PORT_AUTO_NEG_RESTART | 1419 PORT_POWER_DOWN | PORT_AUTO_MDIX_DISABLE | PORT_FORCE_MDIX; 1420 1421 if (val & KSZ886X_BMCR_DISABLE_LED) 1422 restart |= PORT_LED_OFF; 1423 1424 if (val & KSZ886X_BMCR_DISABLE_TRANSMIT) 1425 restart |= PORT_TX_DISABLE; 1426 1427 if (val & BMCR_ANRESTART) 1428 restart |= PORT_AUTO_NEG_RESTART; 1429 1430 if (val & BMCR_PDOWN) 1431 restart |= PORT_POWER_DOWN; 1432 1433 if (val & KSZ886X_BMCR_DISABLE_AUTO_MDIX) 1434 restart |= PORT_AUTO_MDIX_DISABLE; 1435 1436 if (val & KSZ886X_BMCR_FORCE_MDI) 1437 restart |= PORT_FORCE_MDIX; 1438 1439 if (ksz_is_ksz88x3(dev)) { 1440 restart_mask |= KSZ8873_PORT_PHY_LOOPBACK; 1441 1442 if (val & BMCR_LOOPBACK) 1443 restart |= KSZ8873_PORT_PHY_LOOPBACK; 1444 } else { 1445 ret = ksz879x_set_loopback(dev, port, val); 1446 if (ret) 1447 return ret; 1448 } 1449 1450 return ksz_prmw8(dev, port, regs[P_NEG_RESTART_CTRL], restart_mask, 1451 restart); 1452 } 1453 1454 static int ksz8_w_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 val) 1455 { 1456 const u16 *regs; 1457 u8 ctrl, data; 1458 u16 p = phy; 1459 int ret; 1460 1461 regs = dev->info->regs; 1462 1463 switch (reg) { 1464 case MII_BMCR: 1465 ret = ksz8_w_phy_bmcr(dev, p, val); 1466 if (ret) 1467 return ret; 1468 break; 1469 case MII_ADVERTISE: 1470 ret = ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl); 1471 if (ret) 1472 return ret; 1473 1474 data = ctrl; 1475 data &= ~(PORT_AUTO_NEG_SYM_PAUSE | 1476 PORT_AUTO_NEG_100BTX_FD | 1477 PORT_AUTO_NEG_100BTX | 1478 PORT_AUTO_NEG_10BT_FD | 1479 PORT_AUTO_NEG_10BT); 1480 if (val & ADVERTISE_PAUSE_CAP) 1481 data |= PORT_AUTO_NEG_SYM_PAUSE; 1482 if (val & ADVERTISE_100FULL) 1483 data |= PORT_AUTO_NEG_100BTX_FD; 1484 if (val & ADVERTISE_100HALF) 1485 data |= PORT_AUTO_NEG_100BTX; 1486 if (val & ADVERTISE_10FULL) 1487 data |= PORT_AUTO_NEG_10BT_FD; 1488 if (val & ADVERTISE_10HALF) 1489 data |= PORT_AUTO_NEG_10BT; 1490 1491 if (data != ctrl) { 1492 ret = ksz_pwrite8(dev, p, regs[P_LOCAL_CTRL], data); 1493 if (ret) 1494 return ret; 1495 } 1496 break; 1497 case PHY_REG_LINK_MD: 1498 if (ksz_is_ksz8995xa(dev)) 1499 return -EOPNOTSUPP; 1500 1501 if (val & PHY_START_CABLE_DIAG) 1502 ksz_port_cfg(dev, p, REG_PORT_LINK_MD_CTRL, PORT_START_CABLE_DIAG, true); 1503 break; 1504 1505 case PHY_REG_PHY_CTRL: 1506 if (ksz_is_ksz8995xa(dev)) 1507 return -EOPNOTSUPP; 1508 1509 ret = ksz8_w_phy_ctrl(dev, p, val); 1510 if (ret) 1511 return ret; 1512 break; 1513 case PHY_REG_KSZ87XX_SHORT_CABLE: 1514 if (!ksz_is_ksz87xx(dev)) 1515 return -EOPNOTSUPP; 1516 dev_info_once(dev->dev, 1517 "KSZ87xx low-loss tuning is global, applied switch-wide\n"); 1518 ret = ksz87xx_apply_low_loss_preset(dev, !!val); 1519 if (ret) 1520 return ret; 1521 break; 1522 case PHY_REG_KSZ87XX_LPF_BW: 1523 if (!ksz_is_ksz87xx(dev)) 1524 return -EOPNOTSUPP; 1525 dev_info_once(dev->dev, 1526 "KSZ87xx low-loss tuning is global, applied switch-wide\n"); 1527 /* Only accept LPF bandwidth bits [7:6] */ 1528 if (val & ~KSZ87XX_PHY_LPF_MASK) 1529 return -EINVAL; 1530 ret = ksz8_ind_write8(dev, TABLE_LINK_MD, KSZ87XX_REG_PHY_LPF, (u8)val); 1531 if (ret) 1532 return ret; 1533 dev->lpf_bw = val; 1534 break; 1535 case PHY_REG_KSZ87XX_EQ_INIT: 1536 if (!ksz_is_ksz87xx(dev)) 1537 return -EOPNOTSUPP; 1538 dev_info_once(dev->dev, 1539 "KSZ87xx low-loss tuning is global, applied switch-wide\n"); 1540 /* Only accept DSP EQ initial value bits [5:0] */ 1541 if (val & ~KSZ87XX_DSP_EQ_VALID_MASK) 1542 return -EINVAL; 1543 ret = ksz8_ind_write8(dev, TABLE_LINK_MD, KSZ87XX_REG_DSP_EQ, (u8)val); 1544 if (ret) 1545 return ret; 1546 dev->eq_init = val; 1547 break; 1548 default: 1549 break; 1550 } 1551 1552 return 0; 1553 } 1554 1555 static int ksz8_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 1556 { 1557 struct ksz_device *dev = ds->priv; 1558 int ret; 1559 1560 ret = ksz8_w_phy(dev, addr, reg, val); 1561 if (ret) 1562 return ret; 1563 1564 return 0; 1565 } 1566 1567 static void ksz8_cfg_port_member(struct ksz_device *dev, int port, u8 member) 1568 { 1569 int offset = P_MIRROR_CTRL; 1570 u8 data; 1571 1572 if (ksz_is_ksz8463(dev)) 1573 offset = P1CR2; 1574 ksz_pread8(dev, port, offset, &data); 1575 data &= ~dev->port_mask; 1576 data |= (member & dev->port_mask); 1577 ksz_pwrite8(dev, port, offset, data); 1578 } 1579 1580 static void ksz8_flush_dyn_mac_table(struct dsa_switch *ds, int port) 1581 { 1582 struct ksz_device *dev = ds->priv; 1583 u8 learn[DSA_MAX_PORTS]; 1584 int first, index, cnt; 1585 const u16 *regs; 1586 int reg = S_FLUSH_TABLE_CTRL; 1587 int mask = SW_FLUSH_DYN_MAC_TABLE; 1588 1589 regs = dev->info->regs; 1590 1591 if ((uint)port < dev->info->port_cnt) { 1592 first = port; 1593 cnt = port + 1; 1594 } else { 1595 /* Flush all ports. */ 1596 first = 0; 1597 cnt = dev->info->port_cnt; 1598 } 1599 for (index = first; index < cnt; index++) { 1600 ksz_pread8(dev, index, regs[P_STP_CTRL], &learn[index]); 1601 if (!(learn[index] & PORT_LEARN_DISABLE)) 1602 ksz_pwrite8(dev, index, regs[P_STP_CTRL], 1603 learn[index] | PORT_LEARN_DISABLE); 1604 } 1605 if (ksz_is_ksz8463(dev)) { 1606 reg = KSZ8463_FLUSH_TABLE_CTRL; 1607 mask = KSZ8463_FLUSH_DYN_MAC_TABLE; 1608 } else if (ksz_is_ksz8995xa(dev)) { 1609 reg = REG_SW_CTRL_1; 1610 mask = SW_FAST_AGING; 1611 } 1612 ksz_cfg(dev, reg, mask, true); 1613 if (ksz_is_ksz8995xa(dev)) { 1614 /* Allow the 800 us fast-age cycle to finish before restoring 1615 * normal ageing and port learning. 1616 */ 1617 usleep_range(1000, 2000); 1618 ksz_cfg(dev, reg, mask, false); 1619 } 1620 for (index = first; index < cnt; index++) { 1621 if (!(learn[index] & PORT_LEARN_DISABLE)) 1622 ksz_pwrite8(dev, index, regs[P_STP_CTRL], learn[index]); 1623 } 1624 } 1625 1626 static int ksz8_fdb_dump(struct dsa_switch *ds, int port, 1627 dsa_fdb_dump_cb_t *cb, void *data) 1628 { 1629 struct ksz_device *dev = ds->priv; 1630 u8 mac[ETH_ALEN]; 1631 u8 src_port, fid; 1632 u16 entries = 0; 1633 int ret, i; 1634 1635 for (i = 0; i < KSZ8_DYN_MAC_ENTRIES; i++) { 1636 ret = ksz8_r_dyn_mac_table(dev, i, mac, &fid, &src_port, 1637 &entries); 1638 if (ret) 1639 return ret; 1640 1641 if (i >= entries) 1642 return 0; 1643 1644 if (port == src_port) { 1645 ret = cb(mac, fid, false, data); 1646 if (ret) 1647 return ret; 1648 } 1649 } 1650 1651 return 0; 1652 } 1653 1654 static int ksz8_add_sta_mac(struct ksz_device *dev, int port, 1655 const unsigned char *addr, u16 vid) 1656 { 1657 struct alu_struct alu; 1658 int index, ret; 1659 int empty = 0; 1660 1661 alu.port_forward = 0; 1662 for (index = 0; index < dev->info->num_statics; index++) { 1663 bool valid; 1664 1665 ret = ksz8_r_sta_mac_table(dev, index, &alu, &valid); 1666 if (ret) 1667 return ret; 1668 if (!valid) { 1669 /* Remember the first empty entry. */ 1670 if (!empty) 1671 empty = index + 1; 1672 continue; 1673 } 1674 1675 if (!memcmp(alu.mac, addr, ETH_ALEN) && alu.fid == vid) 1676 break; 1677 } 1678 1679 /* no available entry */ 1680 if (index == dev->info->num_statics && !empty) 1681 return -ENOSPC; 1682 1683 /* add entry */ 1684 if (index == dev->info->num_statics) { 1685 index = empty - 1; 1686 memset(&alu, 0, sizeof(alu)); 1687 memcpy(alu.mac, addr, ETH_ALEN); 1688 alu.is_static = true; 1689 } 1690 alu.port_forward |= BIT(port); 1691 if (vid) { 1692 alu.is_use_fid = true; 1693 1694 /* Need a way to map VID to FID. */ 1695 alu.fid = vid; 1696 } 1697 1698 return ksz8_w_sta_mac_table(dev, index, &alu); 1699 } 1700 1701 static int ksz8_del_sta_mac(struct ksz_device *dev, int port, 1702 const unsigned char *addr, u16 vid) 1703 { 1704 struct alu_struct alu; 1705 int index, ret; 1706 1707 for (index = 0; index < dev->info->num_statics; index++) { 1708 bool valid; 1709 1710 ret = ksz8_r_sta_mac_table(dev, index, &alu, &valid); 1711 if (ret) 1712 return ret; 1713 if (!valid) 1714 continue; 1715 1716 if (!memcmp(alu.mac, addr, ETH_ALEN) && alu.fid == vid) 1717 break; 1718 } 1719 1720 /* no available entry */ 1721 if (index == dev->info->num_statics) 1722 return 0; 1723 1724 /* clear port */ 1725 alu.port_forward &= ~BIT(port); 1726 if (!alu.port_forward) 1727 alu.is_static = false; 1728 1729 return ksz8_w_sta_mac_table(dev, index, &alu); 1730 } 1731 1732 static int ksz8_mdb_add(struct dsa_switch *ds, int port, 1733 const struct switchdev_obj_port_mdb *mdb, 1734 struct dsa_db db) 1735 { 1736 return ksz8_add_sta_mac(ds->priv, port, mdb->addr, mdb->vid); 1737 } 1738 1739 static int ksz8_mdb_del(struct dsa_switch *ds, int port, 1740 const struct switchdev_obj_port_mdb *mdb, 1741 struct dsa_db db) 1742 { 1743 return ksz8_del_sta_mac(ds->priv, port, mdb->addr, mdb->vid); 1744 } 1745 1746 static int ksz8_fdb_add(struct dsa_switch *ds, int port, 1747 const unsigned char *addr, u16 vid, struct dsa_db db) 1748 { 1749 return ksz8_add_sta_mac(ds->priv, port, addr, vid); 1750 } 1751 1752 static int ksz8_fdb_del(struct dsa_switch *ds, int port, 1753 const unsigned char *addr, u16 vid, struct dsa_db db) 1754 { 1755 return ksz8_del_sta_mac(ds->priv, port, addr, vid); 1756 } 1757 1758 static int ksz8_port_vlan_filtering(struct dsa_switch *ds, int port, bool flag, 1759 struct netlink_ext_ack *extack) 1760 { 1761 struct ksz_device *dev = ds->priv; 1762 1763 if (ksz_is_ksz88x3(dev)) 1764 return -ENOTSUPP; 1765 1766 /* Discard packets with VID not enabled on the switch */ 1767 ksz_cfg(dev, S_MIRROR_CTRL, SW_VLAN_ENABLE, flag); 1768 1769 /* Discard packets with VID not enabled on the ingress port */ 1770 for (port = 0; port < dev->phy_port_cnt; ++port) 1771 ksz_port_cfg(dev, port, REG_PORT_CTRL_2, PORT_INGRESS_FILTER, 1772 flag); 1773 1774 return 0; 1775 } 1776 1777 static void ksz8_port_enable_pvid(struct ksz_device *dev, int port, bool state) 1778 { 1779 if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev)) { 1780 int reg = REG_SW_INSERT_SRC_PVID; 1781 1782 if (ksz_is_ksz8463(dev)) 1783 reg = KSZ8463_REG_SW_CTRL_9; 1784 ksz_cfg(dev, reg, 0x03 << (4 - 2 * port), state); 1785 } else { 1786 ksz_pwrite8(dev, port, REG_PORT_CTRL_12, state ? 0x0f : 0x00); 1787 } 1788 } 1789 1790 static int ksz8_port_vlan_add(struct dsa_switch *ds, int port, 1791 const struct switchdev_obj_port_vlan *vlan, 1792 struct netlink_ext_ack *extack) 1793 { 1794 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1795 struct ksz_device *dev = ds->priv; 1796 struct ksz_port *p = &dev->ports[port]; 1797 u16 data, new_pvid = 0; 1798 u8 fid, member, valid; 1799 1800 if (ksz_is_ksz88x3(dev)) 1801 return -ENOTSUPP; 1802 1803 /* If a VLAN is added with untagged flag different from the 1804 * port's Remove Tag flag, we need to change the latter. 1805 * Ignore VID 0, which is always untagged. 1806 * Ignore CPU port, which will always be tagged. 1807 */ 1808 if (untagged != p->remove_tag && vlan->vid != 0 && 1809 port != dev->cpu_port) { 1810 unsigned int vid; 1811 1812 /* Reject attempts to add a VLAN that requires the 1813 * Remove Tag flag to be changed, unless there are no 1814 * other VLANs currently configured. 1815 */ 1816 for (vid = 1; vid < dev->info->num_vlans; ++vid) { 1817 /* Skip the VID we are going to add or reconfigure */ 1818 if (vid == vlan->vid) 1819 continue; 1820 1821 ksz8_from_vlan(dev, dev->vlan_cache[vid].table[0], 1822 &fid, &member, &valid); 1823 if (valid && (member & BIT(port))) 1824 return -EINVAL; 1825 } 1826 1827 ksz_port_cfg(dev, port, P_TAG_CTRL, PORT_REMOVE_TAG, untagged); 1828 p->remove_tag = untagged; 1829 } 1830 1831 ksz8_r_vlan_table(dev, vlan->vid, &data); 1832 ksz8_from_vlan(dev, data, &fid, &member, &valid); 1833 1834 /* First time to setup the VLAN entry. */ 1835 if (!valid) { 1836 /* Need to find a way to map VID to FID. */ 1837 fid = 1; 1838 valid = 1; 1839 } 1840 member |= BIT(port); 1841 1842 ksz8_to_vlan(dev, fid, member, valid, &data); 1843 ksz8_w_vlan_table(dev, vlan->vid, data); 1844 1845 /* change PVID */ 1846 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) 1847 new_pvid = vlan->vid; 1848 1849 if (new_pvid) { 1850 u16 vid; 1851 1852 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &vid); 1853 vid &= ~VLAN_VID_MASK; 1854 vid |= new_pvid; 1855 ksz_pwrite16(dev, port, REG_PORT_CTRL_VID, vid); 1856 1857 ksz8_port_enable_pvid(dev, port, true); 1858 } 1859 1860 return 0; 1861 } 1862 1863 static int ksz8_port_vlan_del(struct dsa_switch *ds, int port, 1864 const struct switchdev_obj_port_vlan *vlan) 1865 { 1866 struct ksz_device *dev = ds->priv; 1867 u8 fid, member, valid; 1868 u16 data, pvid; 1869 1870 if (ksz_is_ksz88x3(dev)) 1871 return -ENOTSUPP; 1872 1873 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &pvid); 1874 pvid = pvid & 0xFFF; 1875 1876 ksz8_r_vlan_table(dev, vlan->vid, &data); 1877 ksz8_from_vlan(dev, data, &fid, &member, &valid); 1878 1879 member &= ~BIT(port); 1880 1881 /* Invalidate the entry if no more member. */ 1882 if (!member) { 1883 fid = 0; 1884 valid = 0; 1885 } 1886 1887 ksz8_to_vlan(dev, fid, member, valid, &data); 1888 ksz8_w_vlan_table(dev, vlan->vid, data); 1889 1890 if (pvid == vlan->vid) 1891 ksz8_port_enable_pvid(dev, port, false); 1892 1893 return 0; 1894 } 1895 1896 static int ksz8_port_mirror_add(struct dsa_switch *ds, int port, 1897 struct dsa_mall_mirror_tc_entry *mirror, 1898 bool ingress, struct netlink_ext_ack *extack) 1899 { 1900 struct ksz_device *dev = ds->priv; 1901 int offset = P_MIRROR_CTRL; 1902 1903 if (ksz_is_ksz8463(dev)) 1904 offset = P1CR2; 1905 if (ingress) { 1906 ksz_port_cfg(dev, port, offset, PORT_MIRROR_RX, true); 1907 dev->mirror_rx |= BIT(port); 1908 } else { 1909 ksz_port_cfg(dev, port, offset, PORT_MIRROR_TX, true); 1910 dev->mirror_tx |= BIT(port); 1911 } 1912 1913 ksz_port_cfg(dev, port, offset, PORT_MIRROR_SNIFFER, false); 1914 1915 /* configure mirror port */ 1916 if (dev->mirror_rx || dev->mirror_tx) 1917 ksz_port_cfg(dev, mirror->to_local_port, offset, 1918 PORT_MIRROR_SNIFFER, true); 1919 1920 return 0; 1921 } 1922 1923 static void ksz8_port_mirror_del(struct dsa_switch *ds, int port, 1924 struct dsa_mall_mirror_tc_entry *mirror) 1925 { 1926 struct ksz_device *dev = ds->priv; 1927 int offset = P_MIRROR_CTRL; 1928 u8 data; 1929 1930 if (ksz_is_ksz8463(dev)) 1931 offset = P1CR2; 1932 if (mirror->ingress) { 1933 ksz_port_cfg(dev, port, offset, PORT_MIRROR_RX, false); 1934 dev->mirror_rx &= ~BIT(port); 1935 } else { 1936 ksz_port_cfg(dev, port, offset, PORT_MIRROR_TX, false); 1937 dev->mirror_tx &= ~BIT(port); 1938 } 1939 1940 ksz_pread8(dev, port, offset, &data); 1941 1942 if (!dev->mirror_rx && !dev->mirror_tx) 1943 ksz_port_cfg(dev, mirror->to_local_port, offset, 1944 PORT_MIRROR_SNIFFER, false); 1945 } 1946 1947 static u8 ksz8463_tc_ctrl(int port, int queue) 1948 { 1949 u8 reg; 1950 1951 reg = 0xC8 + port * 4; 1952 reg += ((3 - queue) / 2) * 2; 1953 reg++; 1954 reg -= (queue & 1); 1955 return reg; 1956 } 1957 1958 /** 1959 * ksz88x3_tc_ets_add - Configure ETS (Enhanced Transmission Selection) 1960 * for a port on KSZ88x3 switch 1961 * @dev: Pointer to the KSZ switch device structure 1962 * @port: Port number to configure 1963 * @p: Pointer to offload replace parameters describing ETS bands and mapping 1964 * 1965 * The KSZ88x3 supports two scheduling modes: Strict Priority and 1966 * Weighted Fair Queuing (WFQ). Both modes have fixed behavior: 1967 * - No configurable queue-to-priority mapping 1968 * - No weight adjustment in WFQ mode 1969 * 1970 * This function configures the switch to use strict priority mode by 1971 * clearing the WFQ enable bit for all queues associated with ETS bands. 1972 * If strict priority is not explicitly requested, the switch will default 1973 * to WFQ mode. 1974 * 1975 * Return: 0 on success, or a negative error code on failure 1976 */ 1977 static int ksz88x3_tc_ets_add(struct ksz_device *dev, int port, 1978 struct tc_ets_qopt_offload_replace_params *p) 1979 { 1980 int ret, band; 1981 1982 /* Only strict priority mode is supported for now. 1983 * WFQ is implicitly enabled when strict mode is disabled. 1984 */ 1985 for (band = 0; band < p->bands; band++) { 1986 int queue = ksz_ets_band_to_queue(p, band); 1987 u8 reg; 1988 1989 /* Calculate TXQ Split Control register address for this 1990 * port/queue 1991 */ 1992 reg = KSZ8873_TXQ_SPLIT_CTRL_REG(port, queue); 1993 if (ksz_is_ksz8463(dev)) 1994 reg = ksz8463_tc_ctrl(port, queue); 1995 1996 /* Clear WFQ enable bit to select strict priority scheduling */ 1997 ret = ksz_rmw8(dev, reg, KSZ8873_TXQ_WFQ_ENABLE, 0); 1998 if (ret) 1999 return ret; 2000 } 2001 2002 return 0; 2003 } 2004 2005 /** 2006 * ksz88x3_tc_ets_del - Reset ETS (Enhanced Transmission Selection) config 2007 * for a port on KSZ88x3 switch 2008 * @dev: Pointer to the KSZ switch device structure 2009 * @port: Port number to reset 2010 * 2011 * The KSZ88x3 supports only fixed scheduling modes: Strict Priority or 2012 * Weighted Fair Queuing (WFQ), with no reconfiguration of weights or 2013 * queue mapping. This function resets the port’s scheduling mode to 2014 * the default, which is WFQ, by enabling the WFQ bit for all queues. 2015 * 2016 * Return: 0 on success, or a negative error code on failure 2017 */ 2018 static int ksz88x3_tc_ets_del(struct ksz_device *dev, int port) 2019 { 2020 int ret, queue; 2021 2022 /* Iterate over all transmit queues for this port */ 2023 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 2024 u8 reg; 2025 2026 /* Calculate TXQ Split Control register address for this 2027 * port/queue 2028 */ 2029 reg = KSZ8873_TXQ_SPLIT_CTRL_REG(port, queue); 2030 if (ksz_is_ksz8463(dev)) 2031 reg = ksz8463_tc_ctrl(port, queue); 2032 2033 /* Set WFQ enable bit to revert back to default scheduling 2034 * mode 2035 */ 2036 ret = ksz_rmw8(dev, reg, KSZ8873_TXQ_WFQ_ENABLE, 2037 KSZ8873_TXQ_WFQ_ENABLE); 2038 if (ret) 2039 return ret; 2040 } 2041 2042 return 0; 2043 } 2044 2045 static int ksz8_tc_setup_qdisc_ets(struct dsa_switch *ds, int port, 2046 struct tc_ets_qopt_offload *qopt) 2047 { 2048 struct ksz_device *dev = ds->priv; 2049 int ret; 2050 2051 if (!(ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev))) 2052 return -EOPNOTSUPP; 2053 2054 if (qopt->parent != TC_H_ROOT) { 2055 dev_err(dev->dev, "Parent should be \"root\"\n"); 2056 return -EOPNOTSUPP; 2057 } 2058 2059 switch (qopt->command) { 2060 case TC_ETS_REPLACE: 2061 ret = ksz_tc_ets_validate(dev, port, &qopt->replace_params); 2062 if (ret) 2063 return ret; 2064 2065 return ksz88x3_tc_ets_add(dev, port, &qopt->replace_params); 2066 case TC_ETS_DESTROY: 2067 return ksz88x3_tc_ets_del(dev, port); 2068 case TC_ETS_STATS: 2069 case TC_ETS_GRAFT: 2070 return -EOPNOTSUPP; 2071 } 2072 2073 return -EOPNOTSUPP; 2074 } 2075 2076 static int ksz87xx_setup_tc(struct dsa_switch *ds, int port, 2077 enum tc_setup_type type, void *type_data) 2078 { 2079 switch (type) { 2080 case TC_SETUP_QDISC_CBS: 2081 return ksz_setup_tc_cbs(ds, port, type_data); 2082 default: 2083 return -EOPNOTSUPP; 2084 } 2085 } 2086 2087 static int ksz8_setup_tc(struct dsa_switch *ds, int port, 2088 enum tc_setup_type type, void *type_data) 2089 { 2090 switch (type) { 2091 case TC_SETUP_QDISC_CBS: 2092 return ksz_setup_tc_cbs(ds, port, type_data); 2093 case TC_SETUP_QDISC_ETS: 2094 return ksz8_tc_setup_qdisc_ets(ds, port, type_data); 2095 default: 2096 return -EOPNOTSUPP; 2097 } 2098 } 2099 2100 static void ksz8795_cpu_interface_select(struct ksz_device *dev, int port) 2101 { 2102 struct ksz_port *p = &dev->ports[port]; 2103 2104 if (!ksz_is_ksz87xx(dev)) 2105 return; 2106 2107 if (!p->interface && dev->compat_interface) { 2108 dev_warn(dev->dev, 2109 "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. " 2110 "Please update your device tree.\n", 2111 port); 2112 p->interface = dev->compat_interface; 2113 } 2114 } 2115 2116 static void ksz8_port_setup(struct ksz_device *dev, int port, bool cpu_port) 2117 { 2118 const u16 *regs = dev->info->regs; 2119 struct dsa_switch *ds = dev->ds; 2120 const u32 *masks; 2121 int offset; 2122 u8 member; 2123 2124 masks = dev->info->masks; 2125 2126 /* enable broadcast storm limit */ 2127 offset = P_BCAST_STORM_CTRL; 2128 if (ksz_is_ksz8463(dev)) 2129 offset = P1CR1; 2130 ksz_port_cfg(dev, port, offset, PORT_BROADCAST_STORM, true); 2131 2132 ksz8_port_queue_split(dev, port, dev->info->num_tx_queues); 2133 2134 if (!ksz_is_ksz8995xa(dev)) { 2135 /* replace priority */ 2136 offset = P_802_1P_CTRL; 2137 if (ksz_is_ksz8463(dev)) 2138 offset = P1CR2; 2139 ksz_port_cfg(dev, port, offset, 2140 masks[PORT_802_1P_REMAPPING], false); 2141 } 2142 2143 if (cpu_port) 2144 member = dsa_user_ports(ds); 2145 else 2146 member = BIT(dsa_upstream_port(ds, port)); 2147 2148 ksz8_cfg_port_member(dev, port, member); 2149 2150 if (ksz_is_ksz8995xa(dev)) { 2151 /* Use VID 0 to identify untagged frames in the special tag */ 2152 ksz_pwrite16(dev, port, REG_PORT_CTRL_VID, 0); 2153 2154 /* The KSZ8995XA has a special tag format in the front of the frame 2155 * that need to be inserted by the CPU and then removed by each 2156 * port. PORT_REMOVE_TAG simply means "remove tags coming from the 2157 * CPU port" it does not affect ingress packets. 2158 */ 2159 ksz_prmw8(dev, port, REG_PORT_CTRL_0, 2160 PORT_INSERT_TAG | PORT_REMOVE_TAG, 2161 cpu_port ? PORT_INSERT_TAG : PORT_REMOVE_TAG); 2162 } 2163 2164 /* Disable all WoL options by default. Otherwise 2165 * ksz_switch_macaddr_get/put logic will not work properly. 2166 * CPU port 4 has no WoL functionality. 2167 */ 2168 if (ksz_is_ksz87xx(dev) && !cpu_port) 2169 ksz8_pme_pwrite8(dev, port, regs[REG_PORT_PME_CTRL], 0); 2170 } 2171 2172 static int ksz8_dsa_port_setup(struct dsa_switch *ds, int port) 2173 { 2174 struct ksz_device *dev = ds->priv; 2175 2176 if (!dsa_is_user_port(ds, port)) 2177 return 0; 2178 2179 ksz8_port_setup(dev, port, false); 2180 2181 return ksz_dcb_init_port(dev, port); 2182 } 2183 2184 static void ksz88x3_config_rmii_clk(struct ksz_device *dev) 2185 { 2186 struct dsa_port *cpu_dp = dsa_to_port(dev->ds, dev->cpu_port); 2187 bool rmii_clk_internal; 2188 2189 if (!ksz_is_ksz88x3(dev)) 2190 return; 2191 2192 rmii_clk_internal = of_property_read_bool(cpu_dp->dn, 2193 "microchip,rmii-clk-internal"); 2194 2195 ksz_cfg(dev, KSZ88X3_REG_FVID_AND_HOST_MODE, 2196 KSZ88X3_PORT3_RMII_CLK_INTERNAL, rmii_clk_internal); 2197 } 2198 2199 static void ksz8463_config_cpu_port(struct dsa_switch *ds) 2200 { 2201 struct ksz_device *dev = ds->priv; 2202 struct ksz_port *p; 2203 u8 fiber_ports = 0; 2204 const u32 *masks; 2205 const u16 *regs; 2206 int i; 2207 2208 masks = dev->info->masks; 2209 regs = dev->info->regs; 2210 2211 ksz_cfg(dev, regs[S_TAIL_TAG_CTRL], masks[SW_TAIL_TAG_ENABLE], true); 2212 2213 ksz8_port_setup(dev, dev->cpu_port, true); 2214 2215 for (i = 0; i < dev->phy_port_cnt; i++) 2216 ksz_port_stp_state_set(ds, i, BR_STATE_DISABLED); 2217 2218 for (i = 0; i < dev->phy_port_cnt; i++) { 2219 p = &dev->ports[i]; 2220 ksz_port_cfg(dev, i, regs[P_STP_CTRL], PORT_FORCE_FLOW_CTRL, 2221 p->fiber); 2222 if (p->fiber) 2223 fiber_ports |= (1 << i); 2224 } 2225 2226 /* Setup fiber ports. */ 2227 if (fiber_ports) { 2228 fiber_ports &= 3; 2229 regmap_update_bits(ksz_regmap_16(dev), KSZ8463_REG_CFG_CTRL, 2230 fiber_ports << PORT_COPPER_MODE_S, 2231 0); 2232 regmap_update_bits(ksz_regmap_16(dev), KSZ8463_REG_DSP_CTRL_6, 2233 COPPER_RECEIVE_ADJUSTMENT, 0); 2234 } 2235 2236 /* Turn off PTP function as the switch enables it by default */ 2237 regmap_update_bits(ksz_regmap_16(dev), KSZ8463_PTP_MSG_CONF1, 2238 PTP_ENABLE, 0); 2239 regmap_update_bits(ksz_regmap_16(dev), KSZ8463_PTP_CLK_CTRL, 2240 PTP_CLK_ENABLE, 0); 2241 } 2242 2243 static void ksz8_config_cpu_port(struct dsa_switch *ds) 2244 { 2245 struct ksz_device *dev = ds->priv; 2246 struct ksz_port *p; 2247 const u32 *masks; 2248 const u16 *regs; 2249 u8 remote; 2250 int i; 2251 2252 masks = dev->info->masks; 2253 regs = dev->info->regs; 2254 2255 /* KSZ8995XA uses a tag in the header instead of the tail */ 2256 if (!ksz_is_ksz8995xa(dev)) 2257 ksz_cfg(dev, regs[S_TAIL_TAG_CTRL], masks[SW_TAIL_TAG_ENABLE], true); 2258 2259 ksz8_port_setup(dev, dev->cpu_port, true); 2260 2261 ksz8795_cpu_interface_select(dev, dev->cpu_port); 2262 ksz88x3_config_rmii_clk(dev); 2263 2264 for (i = 0; i < dev->phy_port_cnt; i++) { 2265 ksz_port_stp_state_set(ds, i, BR_STATE_DISABLED); 2266 } 2267 for (i = 0; i < dev->phy_port_cnt; i++) { 2268 p = &dev->ports[i]; 2269 2270 /* For KSZ8795 family. */ 2271 if (ksz_is_ksz87xx(dev)) { 2272 ksz_pread8(dev, i, regs[P_REMOTE_STATUS], &remote); 2273 if (remote & KSZ8_PORT_FIBER_MODE) 2274 p->fiber = 1; 2275 } 2276 if (p->fiber) 2277 ksz_port_cfg(dev, i, regs[P_STP_CTRL], 2278 PORT_FORCE_FLOW_CTRL, true); 2279 else 2280 ksz_port_cfg(dev, i, regs[P_STP_CTRL], 2281 PORT_FORCE_FLOW_CTRL, false); 2282 } 2283 } 2284 2285 /** 2286 * ksz8_phy_port_link_up - Configures ports with integrated PHYs 2287 * @dev: The KSZ device instance. 2288 * @port: The port number to configure. 2289 * @duplex: The desired duplex mode. 2290 * @tx_pause: If true, enables transmit pause. 2291 * @rx_pause: If true, enables receive pause. 2292 * 2293 * Description: 2294 * The function configures flow control settings for a given port based on the 2295 * desired settings and current duplex mode. 2296 * 2297 * According to the KSZ8873 datasheet, the PORT_FORCE_FLOW_CTRL bit in the 2298 * Port Control 2 register (0x1A for Port 1, 0x22 for Port 2, 0x32 for Port 3) 2299 * determines how flow control is handled on the port: 2300 * "1 = will always enable full-duplex flow control on the port, regardless 2301 * of AN result. 2302 * 0 = full-duplex flow control is enabled based on AN result." 2303 * 2304 * This means that the flow control behavior depends on the state of this bit: 2305 * - If PORT_FORCE_FLOW_CTRL is set to 1, the switch will ignore AN results and 2306 * force flow control on the port. 2307 * - If PORT_FORCE_FLOW_CTRL is set to 0, the switch will enable or disable 2308 * flow control based on the AN results. 2309 * 2310 * However, there is a potential limitation in this configuration. It is 2311 * currently not possible to force disable flow control on a port if we still 2312 * advertise pause support. While such a configuration is not currently 2313 * supported by Linux, and may not make practical sense, it's important to be 2314 * aware of this limitation when working with the KSZ8873 and similar devices. 2315 */ 2316 static void ksz8_phy_port_link_up(struct ksz_device *dev, int port, int duplex, 2317 bool tx_pause, bool rx_pause) 2318 { 2319 const u16 *regs = dev->info->regs; 2320 u8 sctrl = 0; 2321 2322 /* The KSZ8795 switch differs from the KSZ8873 by supporting 2323 * asymmetric pause control. However, since a single bit is used to 2324 * control both RX and TX pause, we can't enforce asymmetric pause 2325 * control - both TX and RX pause will be either enabled or disabled 2326 * together. 2327 * 2328 * If auto-negotiation is enabled, we usually allow the flow control to 2329 * be determined by the auto-negotiation process based on the 2330 * capabilities of both link partners. However, for KSZ8873, the 2331 * PORT_FORCE_FLOW_CTRL bit may be set by the hardware bootstrap, 2332 * ignoring the auto-negotiation result. Thus, even in auto-negotiation 2333 * mode, we need to ensure that the PORT_FORCE_FLOW_CTRL bit is 2334 * properly cleared. 2335 * 2336 * In the absence of pause auto-negotiation, we will enforce symmetric 2337 * pause control for both variants of switches - KSZ8873 and KSZ8795. 2338 * 2339 * Autoneg Pause Autoneg rx,tx PORT_FORCE_FLOW_CTRL 2340 * 1 1 x 0 2341 * 0 1 x 0 (flow control probably disabled) 2342 * x 0 1 1 (flow control force enabled) 2343 * 1 0 0 0 (flow control still depends on 2344 * aneg result due to hardware) 2345 * 0 0 0 0 (flow control probably disabled) 2346 */ 2347 if (dev->ports[port].manual_flow && tx_pause) 2348 sctrl |= PORT_FORCE_FLOW_CTRL; 2349 2350 ksz_prmw8(dev, port, regs[P_STP_CTRL], PORT_FORCE_FLOW_CTRL, sctrl); 2351 } 2352 2353 /** 2354 * ksz8_cpu_port_link_up - Configures the CPU port of the switch. 2355 * @dev: The KSZ device instance. 2356 * @speed: The desired link speed. 2357 * @duplex: The desired duplex mode. 2358 * @tx_pause: If true, enables transmit pause. 2359 * @rx_pause: If true, enables receive pause. 2360 * 2361 * Description: 2362 * The function configures flow control and speed settings for the CPU 2363 * port of the switch based on the desired settings, current duplex mode, and 2364 * speed. 2365 */ 2366 static void ksz8_cpu_port_link_up(struct ksz_device *dev, int speed, int duplex, 2367 bool tx_pause, bool rx_pause) 2368 { 2369 const u16 *regs = dev->info->regs; 2370 u8 ctrl = 0; 2371 2372 /* SW_FLOW_CTRL, SW_HALF_DUPLEX, and SW_10_MBIT bits are bootstrappable 2373 * at least on KSZ8873. They can have different values depending on your 2374 * board setup. 2375 */ 2376 if (tx_pause || rx_pause) 2377 ctrl |= SW_FLOW_CTRL; 2378 2379 if (duplex == DUPLEX_HALF) 2380 ctrl |= SW_HALF_DUPLEX; 2381 2382 /* This hardware only supports SPEED_10 and SPEED_100. For SPEED_10 2383 * we need to set the SW_10_MBIT bit. Otherwise, we can leave it 0. 2384 */ 2385 if (speed == SPEED_10) 2386 ctrl |= SW_10_MBIT; 2387 2388 ksz_rmw8(dev, regs[S_BROADCAST_CTRL], SW_HALF_DUPLEX | SW_FLOW_CTRL | 2389 SW_10_MBIT, ctrl); 2390 } 2391 2392 static void ksz8_phylink_mac_link_up(struct phylink_config *config, 2393 struct phy_device *phydev, 2394 unsigned int mode, 2395 phy_interface_t interface, 2396 int speed, int duplex, 2397 bool tx_pause, bool rx_pause) 2398 { 2399 struct dsa_port *dp = dsa_phylink_to_port(config); 2400 struct ksz_device *dev = dp->ds->priv; 2401 int port = dp->index; 2402 2403 /* If the port is the CPU port, apply special handling. Only the CPU 2404 * port is configured via global registers. 2405 */ 2406 if (dev->cpu_port == port) 2407 ksz8_cpu_port_link_up(dev, speed, duplex, tx_pause, rx_pause); 2408 else if (dev->info->internal_phy[port]) 2409 ksz8_phy_port_link_up(dev, port, duplex, tx_pause, rx_pause); 2410 } 2411 2412 static int ksz8_handle_global_errata(struct dsa_switch *ds) 2413 { 2414 struct ksz_device *dev = ds->priv; 2415 int ret = 0; 2416 2417 /* KSZ87xx Errata DS80000687C. 2418 * Module 2: Link drops with some EEE link partners. 2419 * An issue with the EEE next page exchange between the 2420 * KSZ879x/KSZ877x/KSZ876x and some EEE link partners may result in 2421 * the link dropping. 2422 */ 2423 if (dev->info->ksz87xx_eee_link_erratum) 2424 ret = ksz8_ind_write8(dev, TABLE_EEE, REG_IND_EEE_GLOB2_HI, 0); 2425 2426 return ret; 2427 } 2428 2429 static int ksz8_enable_stp_addr(struct ksz_device *dev) 2430 { 2431 struct alu_struct alu; 2432 2433 /* KSZ8995XA lacks STP */ 2434 if (ksz_is_ksz8995xa(dev)) 2435 return 0; 2436 2437 /* Setup STP address for STP operation. */ 2438 memset(&alu, 0, sizeof(alu)); 2439 ether_addr_copy(alu.mac, eth_stp_addr); 2440 alu.is_static = true; 2441 alu.is_override = true; 2442 alu.port_forward = dev->info->cpu_ports; 2443 2444 return ksz8_w_sta_mac_table(dev, 0, &alu); 2445 } 2446 2447 static void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port) 2448 { 2449 struct ethtool_pause_stats *pstats; 2450 struct rtnl_link_stats64 *stats; 2451 struct ksz88xx_stats_raw *raw; 2452 struct ksz_port_mib *mib; 2453 2454 mib = &dev->ports[port].mib; 2455 stats = &mib->stats64; 2456 pstats = &mib->pause_stats; 2457 raw = (struct ksz88xx_stats_raw *)mib->counters; 2458 2459 spin_lock(&mib->stats64_lock); 2460 2461 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 2462 raw->rx_pause; 2463 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 2464 raw->tx_pause; 2465 2466 /* HW counters are counting bytes + FCS which is not acceptable 2467 * for rtnl_link_stats64 interface 2468 */ 2469 stats->rx_bytes = raw->rx + raw->rx_hi - stats->rx_packets * ETH_FCS_LEN; 2470 stats->tx_bytes = raw->tx + raw->tx_hi - stats->tx_packets * ETH_FCS_LEN; 2471 2472 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 2473 raw->rx_oversize; 2474 2475 stats->rx_crc_errors = raw->rx_crc_err; 2476 stats->rx_frame_errors = raw->rx_align_err; 2477 stats->rx_dropped = raw->rx_discards; 2478 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 2479 stats->rx_frame_errors + stats->rx_dropped; 2480 2481 stats->tx_window_errors = raw->tx_late_col; 2482 stats->tx_fifo_errors = raw->tx_discards; 2483 stats->tx_aborted_errors = raw->tx_exc_col; 2484 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 2485 stats->tx_aborted_errors; 2486 2487 stats->multicast = raw->rx_mcast; 2488 stats->collisions = raw->tx_total_col; 2489 2490 pstats->tx_pause_frames = raw->tx_pause; 2491 pstats->rx_pause_frames = raw->rx_pause; 2492 2493 spin_unlock(&mib->stats64_lock); 2494 } 2495 2496 static int ksz8463_setup(struct dsa_switch *ds) 2497 { 2498 struct ksz_device *dev = ds->priv; 2499 u16 storm_mask, storm_rate; 2500 struct ksz_port *p; 2501 const u16 *regs; 2502 int i, ret; 2503 2504 regs = dev->info->regs; 2505 2506 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 2507 dev->info->num_vlans, GFP_KERNEL); 2508 if (!dev->vlan_cache) 2509 return -ENOMEM; 2510 2511 ret = ksz8463_reset_switch(dev); 2512 if (ret) { 2513 dev_err(ds->dev, "failed to reset switch\n"); 2514 return ret; 2515 } 2516 2517 /* set broadcast storm protection 10% rate */ 2518 storm_mask = BROADCAST_STORM_RATE; 2519 storm_rate = (BROADCAST_STORM_VALUE * BROADCAST_STORM_PROT_RATE) / 100; 2520 storm_mask = swab16(storm_mask); 2521 storm_rate = swab16(storm_rate); 2522 regmap_update_bits(ksz_regmap_16(dev), regs[S_BROADCAST_CTRL], 2523 storm_mask, storm_rate); 2524 2525 ksz8463_config_cpu_port(ds); 2526 2527 ksz8_enable_stp_addr(dev); 2528 2529 ds->num_tx_queues = dev->info->num_tx_queues; 2530 2531 regmap_update_bits(ksz_regmap_8(dev), regs[S_MULTICAST_CTRL], 2532 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE); 2533 2534 ksz_init_mib_timer(dev); 2535 2536 ds->configure_vlan_while_not_filtering = false; 2537 ds->dscp_prio_mapping_is_global = true; 2538 ds->mtu_enforcement_ingress = true; 2539 2540 /* We rely on software untagging on the CPU port, so that we 2541 * can support both tagged and untagged VLANs 2542 */ 2543 ds->untag_bridge_pvid = true; 2544 2545 /* VLAN filtering is partly controlled by the global VLAN 2546 * Enable flag 2547 */ 2548 ds->vlan_filtering_is_global = true; 2549 2550 /* Enable automatic fast aging when link changed detected. */ 2551 ksz_cfg(dev, S_LINK_AGING_CTRL, SW_LINK_AUTO_AGING, true); 2552 2553 /* Enable aggressive back off algorithm in half duplex mode. */ 2554 ret = ksz_rmw8(dev, REG_SW_CTRL_1, SW_AGGR_BACKOFF, SW_AGGR_BACKOFF); 2555 if (ret) 2556 return ret; 2557 2558 /* 2559 * Make sure unicast VLAN boundary is set as default and 2560 * enable no excessive collision drop. 2561 */ 2562 ret = ksz_rmw8(dev, REG_SW_CTRL_2, 2563 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP, 2564 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP); 2565 if (ret) 2566 return ret; 2567 2568 ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_REPLACE_VID, false); 2569 2570 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false); 2571 2572 for (i = 0; i < (dev->info->num_vlans / 4); i++) 2573 ksz8_r_vlan_entries(dev, i); 2574 2575 /* Start with learning disabled on standalone user ports, and enabled 2576 * on the CPU port. In lack of other finer mechanisms, learning on the 2577 * CPU port will avoid flooding bridge local addresses on the network 2578 * in some cases. 2579 */ 2580 p = &dev->ports[dev->cpu_port]; 2581 p->learning = true; 2582 2583 if (dev->irq > 0) { 2584 ret = ksz8463_girq_setup(dev); 2585 if (ret) 2586 return ret; 2587 2588 ret = ksz8463_ptp_irq_setup(ds); 2589 if (ret) 2590 goto free_girq; 2591 2592 ksz8463_ptp_set_caps(ds); 2593 ret = ksz_ptp_clock_register(ds); 2594 if (ret) { 2595 dev_err(dev->dev, "Failed to register PTP clock: %d\n", 2596 ret); 2597 goto free_ptp_irq; 2598 } 2599 } 2600 2601 ret = ksz_mdio_register(dev); 2602 if (ret < 0) { 2603 dev_err(dev->dev, "failed to register the mdio"); 2604 goto ptp_clock_unregister; 2605 } 2606 2607 ret = ksz_dcb_init(dev); 2608 if (ret) 2609 goto ptp_clock_unregister; 2610 2611 /* start switch */ 2612 regmap_update_bits(ksz_regmap_8(dev), regs[S_START_CTRL], 2613 SW_START, SW_START); 2614 2615 return 0; 2616 2617 ptp_clock_unregister: 2618 if (dev->irq > 0) 2619 ksz_ptp_clock_unregister(ds); 2620 free_ptp_irq: 2621 if (dev->irq > 0) 2622 ksz8463_ptp_irq_free(ds); 2623 free_girq: 2624 if (dev->irq > 0) 2625 ksz_irq_free(&dev->girq); 2626 2627 return ret; 2628 } 2629 2630 static void ksz8463_teardown(struct dsa_switch *ds) 2631 { 2632 struct ksz_device *dev = ds->priv; 2633 2634 if (dev->irq > 0) { 2635 ksz_ptp_clock_unregister(ds); 2636 ksz8463_ptp_irq_free(ds); 2637 ksz_irq_free(&dev->girq); 2638 } 2639 } 2640 2641 /** 2642 * ksz88x3_drive_strength_write() - Set the drive strength configuration for 2643 * KSZ8863 compatible chip variants. 2644 * @dev: ksz device 2645 * @props: Array of drive strength properties to be set 2646 * @num_props: Number of properties in the array 2647 * 2648 * This function applies the specified drive strength settings to KSZ88X3 chip 2649 * variants (KSZ8873, KSZ8863). 2650 * It ensures the configurations align with what the chip variant supports and 2651 * warns or errors out on unsupported settings. 2652 * 2653 * Return: 0 on success, error code otherwise 2654 */ 2655 static int ksz88x3_drive_strength_write(struct ksz_device *dev, 2656 struct ksz_driver_strength_prop *props, 2657 int num_props) 2658 { 2659 size_t array_size = ARRAY_SIZE(ksz88x3_drive_strengths); 2660 int microamp; 2661 int i, ret; 2662 2663 for (i = 0; i < num_props; i++) { 2664 if (props[i].value == -1 || i == KSZ_DRIVER_STRENGTH_IO) 2665 continue; 2666 2667 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 2668 props[i].name); 2669 } 2670 2671 microamp = props[KSZ_DRIVER_STRENGTH_IO].value; 2672 ret = ksz_drive_strength_to_reg(ksz88x3_drive_strengths, array_size, 2673 microamp); 2674 if (ret < 0) { 2675 ksz_drive_strength_error(dev, ksz88x3_drive_strengths, 2676 array_size, microamp); 2677 return ret; 2678 } 2679 2680 return ksz_rmw8(dev, KSZ8873_REG_GLOBAL_CTRL_12, 2681 KSZ8873_DRIVE_STRENGTH_16MA, ret); 2682 } 2683 2684 /** 2685 * ksz8_parse_drive_strength() - Extract and apply drive strength configurations 2686 * from device tree properties. 2687 * @dev: ksz device 2688 * 2689 * This function reads the specified drive strength properties from the 2690 * device tree, validates against the supported chip variants, and sets 2691 * them accordingly. An error should be critical here, as the drive strength 2692 * settings are crucial for EMI compliance. 2693 * 2694 * Return: 0 on success, error code otherwise 2695 */ 2696 static int ksz8_parse_drive_strength(struct ksz_device *dev) 2697 { 2698 struct ksz_driver_strength_prop of_props[] = { 2699 [KSZ_DRIVER_STRENGTH_HI] = { 2700 .name = "microchip,hi-drive-strength-microamp", 2701 .offset = SW_HI_SPEED_DRIVE_STRENGTH_S, 2702 .value = -1, 2703 }, 2704 [KSZ_DRIVER_STRENGTH_LO] = { 2705 .name = "microchip,lo-drive-strength-microamp", 2706 .offset = SW_LO_SPEED_DRIVE_STRENGTH_S, 2707 .value = -1, 2708 }, 2709 [KSZ_DRIVER_STRENGTH_IO] = { 2710 .name = "microchip,io-drive-strength-microamp", 2711 .offset = 0, /* don't care */ 2712 .value = -1, 2713 }, 2714 }; 2715 struct device_node *np = dev->dev->of_node; 2716 bool have_any_prop = false; 2717 int i, ret; 2718 2719 for (i = 0; i < ARRAY_SIZE(of_props); i++) { 2720 ret = of_property_read_u32(np, of_props[i].name, 2721 &of_props[i].value); 2722 if (ret && ret != -EINVAL) 2723 dev_warn(dev->dev, "Failed to read %s\n", 2724 of_props[i].name); 2725 if (ret) 2726 continue; 2727 2728 have_any_prop = true; 2729 } 2730 2731 if (!have_any_prop) 2732 return 0; 2733 2734 switch (dev->chip_id) { 2735 case KSZ88X3_CHIP_ID: 2736 return ksz88x3_drive_strength_write(dev, of_props, 2737 ARRAY_SIZE(of_props)); 2738 case KSZ8795_CHIP_ID: 2739 case KSZ8794_CHIP_ID: 2740 case KSZ8765_CHIP_ID: 2741 return ksz_drive_strength_write(dev, of_props, 2742 ARRAY_SIZE(of_props)); 2743 default: 2744 /* KSZ8864, KSZ8895 */ 2745 for (i = 0; i < ARRAY_SIZE(of_props); i++) { 2746 if (of_props[i].value == -1) 2747 continue; 2748 2749 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 2750 of_props[i].name); 2751 } 2752 } 2753 2754 return 0; 2755 } 2756 2757 static int ksz8_setup(struct dsa_switch *ds) 2758 { 2759 struct ksz_device *dev = ds->priv; 2760 u16 storm_mask, storm_rate; 2761 struct dsa_port *dp; 2762 struct ksz_port *p; 2763 const u16 *regs; 2764 int i, ret; 2765 u8 val; 2766 2767 regs = dev->info->regs; 2768 2769 /* KSZ8995XA has no SW controlled VLAN handling */ 2770 if (!ksz_is_ksz8995xa(dev)) { 2771 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 2772 dev->info->num_vlans, GFP_KERNEL); 2773 if (!dev->vlan_cache) 2774 return -ENOMEM; 2775 } 2776 2777 ret = ksz8_reset_switch(dev); 2778 if (ret) { 2779 dev_err(ds->dev, "failed to reset switch\n"); 2780 return ret; 2781 } 2782 2783 ret = ksz8_parse_drive_strength(dev); 2784 if (ret) 2785 return ret; 2786 2787 /* set broadcast storm protection 10% rate */ 2788 storm_mask = BROADCAST_STORM_RATE; 2789 storm_rate = (BROADCAST_STORM_VALUE * BROADCAST_STORM_PROT_RATE) / 100; 2790 regmap_update_bits(ksz_regmap_16(dev), regs[S_BROADCAST_CTRL], 2791 storm_mask, storm_rate); 2792 2793 ksz8_config_cpu_port(ds); 2794 2795 ksz8_enable_stp_addr(dev); 2796 2797 ds->num_tx_queues = dev->info->num_tx_queues; 2798 2799 regmap_update_bits(ksz_regmap_8(dev), regs[S_MULTICAST_CTRL], 2800 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE); 2801 2802 ksz_init_mib_timer(dev); 2803 2804 ds->dscp_prio_mapping_is_global = true; 2805 ds->mtu_enforcement_ingress = true; 2806 2807 if (!ksz_is_ksz8995xa(dev)) { 2808 ds->configure_vlan_while_not_filtering = false; 2809 2810 /* We rely on software untagging on the CPU port, so that we 2811 * can support both tagged and untagged VLANs 2812 */ 2813 ds->untag_bridge_pvid = true; 2814 2815 /* VLAN filtering is partly controlled by the global VLAN 2816 * Enable flag 2817 */ 2818 ds->vlan_filtering_is_global = true; 2819 } 2820 2821 /* Enable automatic fast aging when link changed detected. */ 2822 ksz_cfg(dev, S_LINK_AGING_CTRL, SW_LINK_AUTO_AGING, true); 2823 2824 /* Enable aggressive back off algorithm in half duplex mode. */ 2825 ret = ksz_rmw8(dev, REG_SW_CTRL_1, SW_AGGR_BACKOFF, SW_AGGR_BACKOFF); 2826 if (ret) 2827 return ret; 2828 2829 /* 2830 * Make sure unicast VLAN boundary is set as default and 2831 * enable no excessive collision drop. 2832 */ 2833 val = NO_EXC_COLLISION_DROP; 2834 if (!ksz_is_ksz8995xa(dev)) 2835 val |= UNICAST_VLAN_BOUNDARY; 2836 ret = ksz_rmw8(dev, REG_SW_CTRL_2, val, val); 2837 if (ret) 2838 return ret; 2839 2840 ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_REPLACE_VID, false); 2841 2842 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false); 2843 2844 if (ksz_is_ksz8995xa(dev)) 2845 ksz_cfg(dev, REG_SW_CTRL_9, SW_SPECIAL_TAG, true); 2846 else if (!ksz_is_ksz88x3(dev)) 2847 ksz_cfg(dev, REG_SW_CTRL_19, SW_INS_TAG_ENABLE, true); 2848 2849 if (!ksz_is_ksz8995xa(dev)) { 2850 for (i = 0; i < (dev->info->num_vlans / 4); i++) 2851 ksz8_r_vlan_entries(dev, i); 2852 } 2853 2854 /* Make sure PME (WoL) is not enabled. If requested, it will 2855 * be enabled by ksz_wol_pre_shutdown(). Otherwise, some PMICs 2856 * do not like PME events changes before shutdown. PME only 2857 * available on KSZ87xx family. 2858 */ 2859 if (ksz_is_ksz87xx(dev)) { 2860 ret = ksz8_pme_write8(dev, regs[REG_SW_PME_CTRL], 0); 2861 if (!ret) 2862 ret = ksz_rmw8(dev, REG_INT_ENABLE, INT_PME, 0); 2863 if (ret) 2864 return ret; 2865 } 2866 2867 /* Initialize KSZ87xx short-cable preset control */ 2868 dev->eq_init = KSZ87XX_DSP_EQ_INIT_FACTORY; 2869 dev->lpf_bw = KSZ87XX_PHY_LPF_90MHZ; 2870 2871 ret = ksz8_handle_global_errata(ds); 2872 if (ret) 2873 return ret; 2874 2875 /* Start with learning disabled on standalone user ports, and enabled 2876 * on the CPU port. In lack of other finer mechanisms, learning on the 2877 * CPU port will avoid flooding bridge local addresses on the network 2878 * in some cases. 2879 */ 2880 p = &dev->ports[dev->cpu_port]; 2881 p->learning = true; 2882 2883 if (dev->irq > 0) { 2884 ret = ksz_girq_setup(dev); 2885 if (ret) 2886 return ret; 2887 2888 dsa_switch_for_each_user_port(dp, dev->ds) { 2889 ret = ksz_pirq_setup(dev, dp->index); 2890 if (ret) 2891 goto port_release; 2892 2893 if (dev->info->ptp_capable) { 2894 ret = ksz_ptp_irq_setup(ds, dp->index); 2895 if (ret) 2896 goto pirq_release; 2897 } 2898 } 2899 } 2900 2901 if (dev->info->ptp_capable) { 2902 ksz_ptp_set_caps(ds); 2903 ret = ksz_ptp_clock_register(ds); 2904 if (ret) { 2905 dev_err(dev->dev, "Failed to register PTP clock: %d\n", 2906 ret); 2907 goto port_release; 2908 } 2909 } 2910 2911 ret = ksz_mdio_register(dev); 2912 if (ret < 0) { 2913 dev_err(dev->dev, "failed to register the mdio"); 2914 goto out_ptp_clock_unregister; 2915 } 2916 2917 ret = ksz_dcb_init(dev); 2918 if (ret) 2919 goto out_ptp_clock_unregister; 2920 2921 /* start switch */ 2922 regmap_update_bits(ksz_regmap_8(dev), regs[S_START_CTRL], 2923 SW_START, SW_START); 2924 2925 return 0; 2926 2927 out_ptp_clock_unregister: 2928 if (dev->info->ptp_capable) 2929 ksz_ptp_clock_unregister(ds); 2930 port_release: 2931 if (dev->irq > 0) { 2932 dsa_switch_for_each_user_port_continue_reverse(dp, dev->ds) { 2933 if (dev->info->ptp_capable) 2934 ksz_ptp_irq_free(ds, dp->index); 2935 pirq_release: 2936 ksz_irq_free(&dev->ports[dp->index].pirq); 2937 } 2938 ksz_irq_free(&dev->girq); 2939 } 2940 2941 return ret; 2942 } 2943 2944 static void ksz8_phylink_get_caps(struct dsa_switch *ds, int port, 2945 struct phylink_config *config) 2946 { 2947 struct ksz_device *dev = ds->priv; 2948 2949 config->mac_capabilities = MAC_10 | MAC_100; 2950 2951 /* Silicon Errata Sheet (DS80000830A): 2952 * "Port 1 does not respond to received flow control PAUSE frames" 2953 * So, disable Pause support on "Port 1" (port == 0) for all ksz88x3 2954 * switches. 2955 */ 2956 if (!ksz_is_ksz88x3(dev) || port) 2957 config->mac_capabilities |= MAC_SYM_PAUSE; 2958 2959 /* Asym pause is not supported on KSZ8863 and KSZ8873 */ 2960 if (!ksz_is_ksz88x3(dev)) 2961 config->mac_capabilities |= MAC_ASYM_PAUSE; 2962 2963 ksz_phylink_get_caps(ds, port, config); 2964 } 2965 2966 static u32 ksz8_get_port_addr(int port, int offset) 2967 { 2968 return PORT_CTRL_ADDR(port, offset); 2969 } 2970 2971 static u32 ksz8463_get_port_addr(int port, int offset) 2972 { 2973 if (offset >= KSZ8463_PTP_CLK_CTRL) 2974 return offset + 0x20 * port; 2975 2976 return offset + 0x18 * port; 2977 } 2978 2979 static u16 ksz8463_get_phy_addr(u16 phy, u16 reg, u16 offset) 2980 { 2981 return offset + reg * 2 + phy * (P2MBCR - P1MBCR); 2982 } 2983 2984 static int ksz8463_r_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 *val) 2985 { 2986 u16 sw_reg = 0; 2987 u16 data = 0; 2988 int ret; 2989 2990 if (phy > 1) 2991 return -ENOSPC; 2992 switch (reg) { 2993 case MII_PHYSID1: 2994 sw_reg = ksz8463_get_phy_addr(phy, 0, PHY1IHR); 2995 break; 2996 case MII_PHYSID2: 2997 sw_reg = ksz8463_get_phy_addr(phy, 0, PHY1ILR); 2998 break; 2999 case MII_BMCR: 3000 case MII_BMSR: 3001 case MII_ADVERTISE: 3002 case MII_LPA: 3003 sw_reg = ksz8463_get_phy_addr(phy, reg, P1MBCR); 3004 break; 3005 case MII_TPISTATUS: 3006 /* This register holds the PHY interrupt status for simulated 3007 * Micrel KSZ PHY. 3008 */ 3009 data = 0x0505; 3010 break; 3011 default: 3012 break; 3013 } 3014 if (sw_reg) { 3015 ret = ksz_read16(dev, sw_reg, &data); 3016 if (ret) 3017 return ret; 3018 } 3019 *val = data; 3020 3021 return 0; 3022 } 3023 3024 static int ksz8463_phy_read16(struct dsa_switch *ds, int addr, int reg) 3025 { 3026 struct ksz_device *dev = ds->priv; 3027 u16 val = 0xffff; 3028 int ret; 3029 3030 ret = ksz8463_r_phy(dev, addr, reg, &val); 3031 if (ret) 3032 return ret; 3033 3034 return val; 3035 } 3036 3037 static int ksz8463_w_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 val) 3038 { 3039 u16 sw_reg = 0; 3040 int ret; 3041 3042 if (phy > 1) 3043 return -ENOSPC; 3044 3045 /* No write to fiber port. */ 3046 if (dev->ports[phy].fiber) 3047 return 0; 3048 switch (reg) { 3049 case MII_BMCR: 3050 case MII_ADVERTISE: 3051 sw_reg = ksz8463_get_phy_addr(phy, reg, P1MBCR); 3052 break; 3053 default: 3054 break; 3055 } 3056 if (sw_reg) { 3057 ret = ksz_write16(dev, sw_reg, val); 3058 if (ret) 3059 return ret; 3060 } 3061 3062 return 0; 3063 } 3064 3065 static int ksz8463_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 3066 { 3067 struct ksz_device *dev = ds->priv; 3068 int ret; 3069 3070 ret = ksz8463_w_phy(dev, addr, reg, val); 3071 if (ret) 3072 return ret; 3073 3074 return 0; 3075 } 3076 3077 static u32 ksz88xx_get_phy_flags(struct dsa_switch *ds, int port) 3078 { 3079 struct ksz_device *dev = ds->priv; 3080 3081 switch (dev->chip_id) { 3082 case KSZ88X3_CHIP_ID: 3083 /* Silicon Errata Sheet (DS80000830A): 3084 * Port 1 does not work with LinkMD Cable-Testing. 3085 * Port 1 does not respond to received PAUSE control frames. 3086 */ 3087 if (!port) 3088 return MICREL_KSZ8_P1_ERRATA; 3089 break; 3090 } 3091 3092 return 0; 3093 } 3094 3095 static int ksz8_switch_init(struct ksz_device *dev) 3096 { 3097 dev->cpu_port = fls(dev->info->cpu_ports) - 1; 3098 dev->phy_port_cnt = dev->info->port_cnt - 1; 3099 dev->port_mask = (BIT(dev->phy_port_cnt) - 1) | dev->info->cpu_ports; 3100 3101 return 0; 3102 } 3103 3104 static enum dsa_tag_protocol ksz8995xa_get_tag_protocol(struct dsa_switch *ds, 3105 int port, 3106 enum dsa_tag_protocol mp) 3107 { 3108 return DSA_TAG_PROTO_KS8995; 3109 } 3110 3111 static enum dsa_tag_protocol ksz8463_get_tag_protocol(struct dsa_switch *ds, 3112 int port, 3113 enum dsa_tag_protocol mp) 3114 { 3115 return DSA_TAG_PROTO_KSZ8463; 3116 } 3117 3118 static int ksz8463_connect_tag_protocol(struct dsa_switch *ds, 3119 enum dsa_tag_protocol proto) 3120 { 3121 struct ksz_tagger_data *tagger_data; 3122 3123 if (proto != DSA_TAG_PROTO_KSZ8463) 3124 return -EPROTONOSUPPORT; 3125 3126 tagger_data = ksz_tagger_data(ds); 3127 tagger_data->xmit_work_fn = ksz_port_deferred_xmit; 3128 3129 return 0; 3130 } 3131 3132 static enum dsa_tag_protocol ksz87xx_get_tag_protocol(struct dsa_switch *ds, 3133 int port, 3134 enum dsa_tag_protocol mp) 3135 { 3136 return DSA_TAG_PROTO_KSZ8795; 3137 } 3138 3139 static int ksz87xx_connect_tag_protocol(struct dsa_switch *ds, 3140 enum dsa_tag_protocol proto) 3141 { 3142 if (proto != DSA_TAG_PROTO_KSZ8795) 3143 return -EPROTONOSUPPORT; 3144 3145 return 0; 3146 } 3147 3148 static enum dsa_tag_protocol ksz88xx_get_tag_protocol(struct dsa_switch *ds, 3149 int port, 3150 enum dsa_tag_protocol mp) 3151 { 3152 struct ksz_device *dev = ds->priv; 3153 3154 if (ksz_is_8895_family(dev)) /* KSZ8864, KSZ8895 */ 3155 return DSA_TAG_PROTO_KSZ8795; 3156 3157 return DSA_TAG_PROTO_KSZ9893; 3158 } 3159 3160 static int ksz88xx_connect_tag_protocol(struct dsa_switch *ds, 3161 enum dsa_tag_protocol proto) 3162 { 3163 struct ksz_tagger_data *tagger_data; 3164 3165 if (ksz_is_8895_family(ds->priv)) { /* KSZ8864, KSZ8895 */ 3166 if (proto != DSA_TAG_PROTO_KSZ8795) 3167 return -EPROTONOSUPPORT; 3168 3169 return 0; 3170 } 3171 3172 if (proto != DSA_TAG_PROTO_KSZ9893) 3173 return -EPROTONOSUPPORT; 3174 3175 tagger_data = ksz_tagger_data(ds); 3176 tagger_data->xmit_work_fn = ksz_port_deferred_xmit; 3177 3178 return 0; 3179 } 3180 3181 static void ksz88x3_phylink_mac_config(struct phylink_config *config, 3182 unsigned int mode, 3183 const struct phylink_link_state *state) 3184 { 3185 struct dsa_port *dp = dsa_phylink_to_port(config); 3186 struct ksz_device *dev = dp->ds->priv; 3187 3188 dev->ports[dp->index].manual_flow = !(state->pause & MLO_PAUSE_AN); 3189 } 3190 3191 const struct phylink_mac_ops ksz88x3_phylink_mac_ops = { 3192 .mac_config = ksz88x3_phylink_mac_config, 3193 .mac_link_down = ksz_phylink_mac_link_down, 3194 .mac_link_up = ksz8_phylink_mac_link_up, 3195 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi, 3196 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi, 3197 }; 3198 3199 const struct phylink_mac_ops ksz8_phylink_mac_ops = { 3200 .mac_config = ksz_phylink_mac_config, 3201 .mac_link_down = ksz_phylink_mac_link_down, 3202 .mac_link_up = ksz8_phylink_mac_link_up, 3203 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi, 3204 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi, 3205 }; 3206 3207 /* 3208 * The KS(Z)8995XA has no indirect access, meaning no MIB counters, 3209 * no FDB access, and no VLAN handling. 3210 */ 3211 const struct ksz_dev_ops ksz8995xa_dev_ops = { 3212 .get_port_addr = ksz8_get_port_addr, 3213 .cfg_port_member = ksz8_cfg_port_member, 3214 .init = ksz8_switch_init, 3215 }; 3216 3217 const struct ksz_dev_ops ksz8463_dev_ops = { 3218 .get_port_addr = ksz8463_get_port_addr, 3219 .cfg_port_member = ksz8_cfg_port_member, 3220 .r_mib_cnt = ksz8_r_mib_cnt, 3221 .r_mib_pkt = ksz8_r_mib_pkt, 3222 .r_mib_stat64 = ksz88xx_r_mib_stats64, 3223 .freeze_mib = ksz8_freeze_mib, 3224 .port_init_cnt = ksz8_port_init_cnt, 3225 .init = ksz8_switch_init, 3226 }; 3227 3228 const struct ksz_dev_ops ksz87xx_dev_ops = { 3229 .get_port_addr = ksz8_get_port_addr, 3230 .cfg_port_member = ksz8_cfg_port_member, 3231 .r_mib_cnt = ksz8_r_mib_cnt, 3232 .r_mib_pkt = ksz8_r_mib_pkt, 3233 .r_mib_stat64 = ksz_r_mib_stats64, 3234 .freeze_mib = ksz8_freeze_mib, 3235 .port_init_cnt = ksz8_port_init_cnt, 3236 .init = ksz8_switch_init, 3237 .pme_write8 = ksz8_pme_write8, 3238 .pme_pread8 = ksz8_pme_pread8, 3239 .pme_pwrite8 = ksz8_pme_pwrite8, 3240 }; 3241 3242 const struct ksz_dev_ops ksz88xx_dev_ops = { 3243 .get_port_addr = ksz8_get_port_addr, 3244 .cfg_port_member = ksz8_cfg_port_member, 3245 .r_mib_cnt = ksz8_r_mib_cnt, 3246 .r_mib_pkt = ksz8_r_mib_pkt, 3247 .r_mib_stat64 = ksz88xx_r_mib_stats64, 3248 .freeze_mib = ksz8_freeze_mib, 3249 .port_init_cnt = ksz8_port_init_cnt, 3250 .init = ksz8_switch_init, 3251 .pme_write8 = ksz8_pme_write8, 3252 .pme_pread8 = ksz8_pme_pread8, 3253 .pme_pwrite8 = ksz8_pme_pwrite8, 3254 }; 3255 3256 /* 3257 * Restricted operations for KSZ8995XA, so many things are not supported 3258 * by this old switch that we need diet DSA operations. 3259 */ 3260 const struct dsa_switch_ops ksz8995xa_switch_ops = { 3261 .get_tag_protocol = ksz8995xa_get_tag_protocol, 3262 .setup = ksz8_setup, 3263 .teardown = ksz_teardown, 3264 .phy_read = ksz8_phy_read16, 3265 .phy_write = ksz8_phy_write16, 3266 .phylink_get_caps = ksz8_phylink_get_caps, 3267 .port_setup = ksz8_dsa_port_setup, 3268 .port_bridge_join = ksz_port_bridge_join, 3269 .port_bridge_leave = ksz_port_bridge_leave, 3270 .port_set_mac_address = ksz_port_set_mac_address, 3271 .port_stp_state_set = ksz_port_stp_state_set, 3272 .port_pre_bridge_flags = ksz_port_pre_bridge_flags, 3273 .port_bridge_flags = ksz_port_bridge_flags, 3274 .port_fast_age = ksz8_flush_dyn_mac_table, 3275 .port_mirror_add = ksz8_port_mirror_add, 3276 .port_mirror_del = ksz8_port_mirror_del, 3277 .port_change_mtu = ksz8995xa_change_mtu, 3278 .port_max_mtu = ksz88xx_max_mtu, 3279 .port_get_default_prio = ksz_port_get_default_prio, 3280 .port_set_default_prio = ksz_port_set_default_prio, 3281 .port_get_dscp_prio = ksz_port_get_dscp_prio, 3282 .port_add_dscp_prio = ksz_port_add_dscp_prio, 3283 .port_del_dscp_prio = ksz_port_del_dscp_prio, 3284 .port_get_apptrust = ksz_port_get_apptrust, 3285 .port_set_apptrust = ksz_port_set_apptrust, 3286 }; 3287 3288 const struct dsa_switch_ops ksz8463_switch_ops = { 3289 .get_tag_protocol = ksz8463_get_tag_protocol, 3290 .connect_tag_protocol = ksz8463_connect_tag_protocol, 3291 .setup = ksz8463_setup, 3292 .teardown = ksz8463_teardown, 3293 .phy_read = ksz8463_phy_read16, 3294 .phy_write = ksz8463_phy_write16, 3295 .phylink_get_caps = ksz8_phylink_get_caps, 3296 .port_setup = ksz8_dsa_port_setup, 3297 .get_strings = ksz_get_strings, 3298 .get_ethtool_stats = ksz_get_ethtool_stats, 3299 .get_sset_count = ksz_sset_count, 3300 .port_bridge_join = ksz_port_bridge_join, 3301 .port_bridge_leave = ksz_port_bridge_leave, 3302 .port_set_mac_address = ksz_port_set_mac_address, 3303 .port_stp_state_set = ksz_port_stp_state_set, 3304 .port_pre_bridge_flags = ksz_port_pre_bridge_flags, 3305 .port_bridge_flags = ksz_port_bridge_flags, 3306 .port_fast_age = ksz8_flush_dyn_mac_table, 3307 .port_fdb_dump = ksz8_fdb_dump, 3308 .port_fdb_add = ksz8_fdb_add, 3309 .port_fdb_del = ksz8_fdb_del, 3310 .port_mdb_add = ksz8_mdb_add, 3311 .port_mdb_del = ksz8_mdb_del, 3312 .port_mirror_add = ksz8_port_mirror_add, 3313 .port_mirror_del = ksz8_port_mirror_del, 3314 .get_stats64 = ksz_get_stats64, 3315 .get_pause_stats = ksz_get_pause_stats, 3316 .port_change_mtu = ksz88xx_change_mtu, 3317 .port_max_mtu = ksz88xx_max_mtu, 3318 .suspend = ksz_suspend, 3319 .resume = ksz_resume, 3320 .get_ts_info = ksz8463_get_ts_info, 3321 .port_hwtstamp_get = ksz_hwtstamp_get, 3322 .port_hwtstamp_set = ksz8463_hwtstamp_set, 3323 .port_txtstamp = ksz_port_txtstamp, 3324 .port_rxtstamp = ksz_port_rxtstamp, 3325 .port_setup_tc = ksz8_setup_tc, 3326 .port_get_default_prio = ksz_port_get_default_prio, 3327 .port_set_default_prio = ksz_port_set_default_prio, 3328 .port_get_dscp_prio = ksz_port_get_dscp_prio, 3329 .port_add_dscp_prio = ksz_port_add_dscp_prio, 3330 .port_del_dscp_prio = ksz_port_del_dscp_prio, 3331 .port_get_apptrust = ksz_port_get_apptrust, 3332 .port_set_apptrust = ksz_port_set_apptrust, 3333 }; 3334 3335 const struct dsa_switch_ops ksz87xx_switch_ops = { 3336 .get_tag_protocol = ksz87xx_get_tag_protocol, 3337 .connect_tag_protocol = ksz87xx_connect_tag_protocol, 3338 .setup = ksz8_setup, 3339 .teardown = ksz_teardown, 3340 .phy_read = ksz8_phy_read16, 3341 .phy_write = ksz8_phy_write16, 3342 .phylink_get_caps = ksz8_phylink_get_caps, 3343 .port_setup = ksz8_dsa_port_setup, 3344 .get_strings = ksz_get_strings, 3345 .get_ethtool_stats = ksz_get_ethtool_stats, 3346 .get_sset_count = ksz_sset_count, 3347 .port_bridge_join = ksz_port_bridge_join, 3348 .port_bridge_leave = ksz_port_bridge_leave, 3349 .port_set_mac_address = ksz_port_set_mac_address, 3350 .port_stp_state_set = ksz_port_stp_state_set, 3351 .port_pre_bridge_flags = ksz_port_pre_bridge_flags, 3352 .port_bridge_flags = ksz_port_bridge_flags, 3353 .port_fast_age = ksz8_flush_dyn_mac_table, 3354 .port_vlan_filtering = ksz8_port_vlan_filtering, 3355 .port_vlan_add = ksz8_port_vlan_add, 3356 .port_vlan_del = ksz8_port_vlan_del, 3357 .port_fdb_dump = ksz8_fdb_dump, 3358 .port_fdb_add = ksz8_fdb_add, 3359 .port_fdb_del = ksz8_fdb_del, 3360 .port_mdb_add = ksz8_mdb_add, 3361 .port_mdb_del = ksz8_mdb_del, 3362 .port_mirror_add = ksz8_port_mirror_add, 3363 .port_mirror_del = ksz8_port_mirror_del, 3364 .get_stats64 = ksz_get_stats64, 3365 .get_pause_stats = ksz_get_pause_stats, 3366 .port_change_mtu = ksz87xx_change_mtu, 3367 .port_max_mtu = ksz87xx_max_mtu, 3368 .suspend = ksz_suspend, 3369 .resume = ksz_resume, 3370 .get_ts_info = ksz_get_ts_info, 3371 .port_hwtstamp_get = ksz_hwtstamp_get, 3372 .port_hwtstamp_set = ksz_hwtstamp_set, 3373 .port_txtstamp = ksz_port_txtstamp, 3374 .port_rxtstamp = ksz_port_rxtstamp, 3375 .port_setup_tc = ksz87xx_setup_tc, 3376 .port_get_default_prio = ksz_port_get_default_prio, 3377 .port_set_default_prio = ksz_port_set_default_prio, 3378 .port_get_dscp_prio = ksz_port_get_dscp_prio, 3379 .port_add_dscp_prio = ksz_port_add_dscp_prio, 3380 .port_del_dscp_prio = ksz_port_del_dscp_prio, 3381 .port_get_apptrust = ksz_port_get_apptrust, 3382 .port_set_apptrust = ksz_port_set_apptrust, 3383 }; 3384 3385 const struct dsa_switch_ops ksz88xx_switch_ops = { 3386 .get_tag_protocol = ksz88xx_get_tag_protocol, 3387 .connect_tag_protocol = ksz88xx_connect_tag_protocol, 3388 .get_phy_flags = ksz88xx_get_phy_flags, 3389 .setup = ksz8_setup, 3390 .teardown = ksz_teardown, 3391 .phy_read = ksz8_phy_read16, 3392 .phy_write = ksz8_phy_write16, 3393 .phylink_get_caps = ksz8_phylink_get_caps, 3394 .port_setup = ksz8_dsa_port_setup, 3395 .get_strings = ksz_get_strings, 3396 .get_ethtool_stats = ksz_get_ethtool_stats, 3397 .get_sset_count = ksz_sset_count, 3398 .port_bridge_join = ksz_port_bridge_join, 3399 .port_bridge_leave = ksz_port_bridge_leave, 3400 .port_set_mac_address = ksz_port_set_mac_address, 3401 .port_stp_state_set = ksz_port_stp_state_set, 3402 .port_pre_bridge_flags = ksz_port_pre_bridge_flags, 3403 .port_bridge_flags = ksz_port_bridge_flags, 3404 .port_fast_age = ksz8_flush_dyn_mac_table, 3405 .port_vlan_filtering = ksz8_port_vlan_filtering, 3406 .port_vlan_add = ksz8_port_vlan_add, 3407 .port_vlan_del = ksz8_port_vlan_del, 3408 .port_fdb_dump = ksz8_fdb_dump, 3409 .port_fdb_add = ksz8_fdb_add, 3410 .port_fdb_del = ksz8_fdb_del, 3411 .port_mdb_add = ksz8_mdb_add, 3412 .port_mdb_del = ksz8_mdb_del, 3413 .port_mirror_add = ksz8_port_mirror_add, 3414 .port_mirror_del = ksz8_port_mirror_del, 3415 .get_stats64 = ksz_get_stats64, 3416 .get_pause_stats = ksz_get_pause_stats, 3417 .port_change_mtu = ksz88xx_change_mtu, 3418 .port_max_mtu = ksz88xx_max_mtu, 3419 .get_wol = ksz_get_wol, 3420 .set_wol = ksz_set_wol, 3421 .suspend = ksz_suspend, 3422 .resume = ksz_resume, 3423 .get_ts_info = ksz_get_ts_info, 3424 .port_hwtstamp_get = ksz_hwtstamp_get, 3425 .port_hwtstamp_set = ksz_hwtstamp_set, 3426 .port_txtstamp = ksz_port_txtstamp, 3427 .port_rxtstamp = ksz_port_rxtstamp, 3428 .port_setup_tc = ksz8_setup_tc, 3429 .port_get_default_prio = ksz_port_get_default_prio, 3430 .port_set_default_prio = ksz_port_set_default_prio, 3431 .port_get_dscp_prio = ksz_port_get_dscp_prio, 3432 .port_add_dscp_prio = ksz_port_add_dscp_prio, 3433 .port_del_dscp_prio = ksz_port_del_dscp_prio, 3434 .port_get_apptrust = ksz_port_get_apptrust, 3435 .port_set_apptrust = ksz_port_set_apptrust, 3436 }; 3437 3438 MODULE_AUTHOR("Tristram Ha <Tristram.Ha@microchip.com>"); 3439 MODULE_DESCRIPTION("Microchip KSZ8795 Series Switch DSA Driver"); 3440 MODULE_LICENSE("GPL"); 3441