1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Analog Devices Generic AXI DAC IP core
4 * Link: https://wiki.analog.com/resources/fpga/docs/axi_dac_ip
5 *
6 * Copyright 2016-2024 Analog Devices Inc.
7 */
8 #include <linux/adi-axi-common.h>
9 #include <linux/bitfield.h>
10 #include <linux/bits.h>
11 #include <linux/cleanup.h>
12 #include <linux/clk.h>
13 #include <linux/device.h>
14 #include <linux/err.h>
15 #include <linux/limits.h>
16 #include <linux/kstrtox.h>
17 #include <linux/math.h>
18 #include <linux/math64.h>
19 #include <linux/module.h>
20 #include <linux/mutex.h>
21 #include <linux/platform_device.h>
22 #include <linux/property.h>
23 #include <linux/regmap.h>
24 #include <linux/units.h>
25
26 #include <linux/iio/backend.h>
27 #include <linux/iio/buffer-dmaengine.h>
28 #include <linux/iio/buffer.h>
29 #include <linux/iio/iio.h>
30
31 #include "ad3552r-hs.h"
32
33 /*
34 * Register definitions:
35 * https://wiki.analog.com/resources/fpga/docs/axi_dac_ip#register_map
36 */
37
38 /* Base controls */
39 #define AXI_DAC_CONFIG_REG 0x0c
40 #define AXI_DAC_CONFIG_DDS_DISABLE BIT(6)
41
42 /* DAC controls */
43 #define AXI_DAC_RSTN_REG 0x0040
44 #define AXI_DAC_RSTN_CE_N BIT(2)
45 #define AXI_DAC_RSTN_MMCM_RSTN BIT(1)
46 #define AXI_DAC_RSTN_RSTN BIT(0)
47 #define AXI_DAC_CNTRL_1_REG 0x0044
48 #define AXI_DAC_CNTRL_1_SYNC BIT(0)
49 #define AXI_DAC_CNTRL_2_REG 0x0048
50 #define AXI_DAC_CNTRL_2_SDR_DDR_N BIT(16)
51 #define AXI_DAC_CNTRL_2_SYMB_8B BIT(14)
52 #define ADI_DAC_CNTRL_2_R1_MODE BIT(5)
53 #define AXI_DAC_CNTRL_2_UNSIGNED_DATA BIT(4)
54 #define AXI_DAC_STATUS_1_REG 0x0054
55 #define AXI_DAC_STATUS_2_REG 0x0058
56 #define AXI_DAC_DRP_STATUS_REG 0x0074
57 #define AXI_DAC_DRP_STATUS_DRP_LOCKED BIT(17)
58 #define AXI_DAC_CUSTOM_RD_REG 0x0080
59 #define AXI_DAC_CUSTOM_WR_REG 0x0084
60 #define AXI_DAC_CUSTOM_WR_DATA_8 GENMASK(23, 16)
61 #define AXI_DAC_CUSTOM_WR_DATA_16 GENMASK(23, 8)
62 #define AXI_DAC_UI_STATUS_REG 0x0088
63 #define AXI_DAC_UI_STATUS_IF_BUSY BIT(4)
64 #define AXI_DAC_CUSTOM_CTRL_REG 0x008C
65 #define AXI_DAC_CUSTOM_CTRL_ADDRESS GENMASK(31, 24)
66 #define AXI_DAC_CUSTOM_CTRL_MULTI_IO_MODE GENMASK(3, 2)
67 #define AXI_DAC_CUSTOM_CTRL_STREAM BIT(1)
68 #define AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA BIT(0)
69
70 #define AXI_DAC_CUSTOM_CTRL_STREAM_ENABLE (AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA | \
71 AXI_DAC_CUSTOM_CTRL_STREAM)
72
73 /* DAC Channel controls */
74 #define AXI_DAC_CHAN_CNTRL_1_REG(c) (0x0400 + (c) * 0x40)
75 #define AXI_DAC_CHAN_CNTRL_3_REG(c) (0x0408 + (c) * 0x40)
76 #define AXI_DAC_CHAN_CNTRL_3_SCALE_SIGN BIT(15)
77 #define AXI_DAC_CHAN_CNTRL_3_SCALE_INT BIT(14)
78 #define AXI_DAC_CHAN_CNTRL_3_SCALE GENMASK(14, 0)
79 #define AXI_DAC_CHAN_CNTRL_2_REG(c) (0x0404 + (c) * 0x40)
80 #define AXI_DAC_CHAN_CNTRL_2_PHASE GENMASK(31, 16)
81 #define AXI_DAC_CHAN_CNTRL_2_FREQUENCY GENMASK(15, 0)
82 #define AXI_DAC_CHAN_CNTRL_4_REG(c) (0x040c + (c) * 0x40)
83 #define AXI_DAC_CHAN_CNTRL_7_REG(c) (0x0418 + (c) * 0x40)
84 #define AXI_DAC_CHAN_CNTRL_7_DATA_SEL GENMASK(3, 0)
85
86 #define AXI_DAC_CHAN_CNTRL_MAX 15
87 #define AXI_DAC_RD_ADDR(x) (BIT(7) | (x))
88
89 /* 360 degrees in rad */
90 #define AXI_DAC_2_PI_MEGA 6283190
91
92 enum {
93 AXI_DAC_DATA_INTERNAL_TONE,
94 AXI_DAC_DATA_DMA = 2,
95 AXI_DAC_DATA_INTERNAL_RAMP_16BIT = 11,
96 };
97
98 struct axi_dac_info {
99 unsigned int version;
100 const struct iio_backend_info *backend_info;
101 bool has_dac_clk;
102 bool has_child_nodes;
103 };
104
105 struct axi_dac_state {
106 struct regmap *regmap;
107 struct device *dev;
108 /*
109 * lock to protect multiple accesses to the device registers and global
110 * data/variables.
111 */
112 struct mutex lock;
113 const struct axi_dac_info *info;
114 u64 dac_clk;
115 u32 reg_config;
116 int dac_clk_rate;
117 };
118
axi_dac_enable(struct iio_backend * back)119 static int axi_dac_enable(struct iio_backend *back)
120 {
121 struct axi_dac_state *st = iio_backend_get_priv(back);
122 unsigned int __val;
123 int ret;
124
125 guard(mutex)(&st->lock);
126 ret = regmap_set_bits(st->regmap, AXI_DAC_RSTN_REG,
127 AXI_DAC_RSTN_MMCM_RSTN);
128 if (ret)
129 return ret;
130 /*
131 * Make sure the DRP (Dynamic Reconfiguration Port) is locked. Not all
132 * designs really use it but if they don't we still get the lock bit
133 * set. So let's do it all the time so the code is generic.
134 */
135 ret = regmap_read_poll_timeout(st->regmap, AXI_DAC_DRP_STATUS_REG,
136 __val,
137 __val & AXI_DAC_DRP_STATUS_DRP_LOCKED,
138 100, 1000);
139 if (ret)
140 return ret;
141
142 return regmap_set_bits(st->regmap, AXI_DAC_RSTN_REG,
143 AXI_DAC_RSTN_RSTN | AXI_DAC_RSTN_MMCM_RSTN);
144 }
145
axi_dac_disable(struct iio_backend * back)146 static void axi_dac_disable(struct iio_backend *back)
147 {
148 struct axi_dac_state *st = iio_backend_get_priv(back);
149
150 guard(mutex)(&st->lock);
151 regmap_write(st->regmap, AXI_DAC_RSTN_REG, 0);
152 }
153
axi_dac_request_buffer(struct iio_backend * back,struct iio_dev * indio_dev)154 static struct iio_buffer *axi_dac_request_buffer(struct iio_backend *back,
155 struct iio_dev *indio_dev)
156 {
157 struct axi_dac_state *st = iio_backend_get_priv(back);
158 const char *dma_name;
159
160 if (device_property_read_string(st->dev, "dma-names", &dma_name))
161 dma_name = "tx";
162
163 return iio_dmaengine_buffer_setup_ext(st->dev, indio_dev, dma_name,
164 IIO_BUFFER_DIRECTION_OUT);
165 }
166
axi_dac_free_buffer(struct iio_backend * back,struct iio_buffer * buffer)167 static void axi_dac_free_buffer(struct iio_backend *back,
168 struct iio_buffer *buffer)
169 {
170 iio_dmaengine_buffer_teardown(buffer);
171 }
172
173 enum {
174 AXI_DAC_FREQ_TONE_1,
175 AXI_DAC_FREQ_TONE_2,
176 AXI_DAC_SCALE_TONE_1,
177 AXI_DAC_SCALE_TONE_2,
178 AXI_DAC_PHASE_TONE_1,
179 AXI_DAC_PHASE_TONE_2,
180 };
181
__axi_dac_frequency_get(struct axi_dac_state * st,unsigned int chan,unsigned int tone_2,unsigned int * freq)182 static int __axi_dac_frequency_get(struct axi_dac_state *st, unsigned int chan,
183 unsigned int tone_2, unsigned int *freq)
184 {
185 u32 reg, raw;
186 int ret;
187
188 if (chan > AXI_DAC_CHAN_CNTRL_MAX)
189 return -EINVAL;
190
191 if (!st->dac_clk) {
192 dev_err(st->dev, "Sampling rate is 0...\n");
193 return -EINVAL;
194 }
195
196 if (tone_2)
197 reg = AXI_DAC_CHAN_CNTRL_4_REG(chan);
198 else
199 reg = AXI_DAC_CHAN_CNTRL_2_REG(chan);
200
201 ret = regmap_read(st->regmap, reg, &raw);
202 if (ret)
203 return ret;
204
205 raw = FIELD_GET(AXI_DAC_CHAN_CNTRL_2_FREQUENCY, raw);
206 *freq = DIV_ROUND_CLOSEST_ULL(raw * st->dac_clk, BIT(16));
207
208 return 0;
209 }
210
axi_dac_frequency_get(struct axi_dac_state * st,const struct iio_chan_spec * chan,char * buf,unsigned int tone_2)211 static int axi_dac_frequency_get(struct axi_dac_state *st,
212 const struct iio_chan_spec *chan, char *buf,
213 unsigned int tone_2)
214 {
215 unsigned int freq;
216 int ret;
217
218 scoped_guard(mutex, &st->lock) {
219 ret = __axi_dac_frequency_get(st, chan->channel, tone_2, &freq);
220 if (ret)
221 return ret;
222 }
223
224 return sysfs_emit(buf, "%u\n", freq);
225 }
226
axi_dac_scale_get(struct axi_dac_state * st,const struct iio_chan_spec * chan,char * buf,unsigned int tone_2)227 static int axi_dac_scale_get(struct axi_dac_state *st,
228 const struct iio_chan_spec *chan, char *buf,
229 unsigned int tone_2)
230 {
231 unsigned int scale, sign;
232 int ret, vals[2];
233 u32 reg, raw;
234
235 if (chan->channel > AXI_DAC_CHAN_CNTRL_MAX)
236 return -EINVAL;
237
238 if (tone_2)
239 reg = AXI_DAC_CHAN_CNTRL_3_REG(chan->channel);
240 else
241 reg = AXI_DAC_CHAN_CNTRL_1_REG(chan->channel);
242
243 ret = regmap_read(st->regmap, reg, &raw);
244 if (ret)
245 return ret;
246
247 sign = FIELD_GET(AXI_DAC_CHAN_CNTRL_3_SCALE_SIGN, raw);
248 raw = FIELD_GET(AXI_DAC_CHAN_CNTRL_3_SCALE, raw);
249 scale = DIV_ROUND_CLOSEST_ULL((u64)raw * MEGA,
250 AXI_DAC_CHAN_CNTRL_3_SCALE_INT);
251
252 vals[0] = scale / MEGA;
253 vals[1] = scale % MEGA;
254
255 if (sign) {
256 vals[0] *= -1;
257 if (!vals[0])
258 vals[1] *= -1;
259 }
260
261 return iio_format_value(buf, IIO_VAL_INT_PLUS_MICRO, ARRAY_SIZE(vals),
262 vals);
263 }
264
axi_dac_phase_get(struct axi_dac_state * st,const struct iio_chan_spec * chan,char * buf,unsigned int tone_2)265 static int axi_dac_phase_get(struct axi_dac_state *st,
266 const struct iio_chan_spec *chan, char *buf,
267 unsigned int tone_2)
268 {
269 u32 reg, raw, phase;
270 int ret, vals[2];
271
272 if (chan->channel > AXI_DAC_CHAN_CNTRL_MAX)
273 return -EINVAL;
274
275 if (tone_2)
276 reg = AXI_DAC_CHAN_CNTRL_4_REG(chan->channel);
277 else
278 reg = AXI_DAC_CHAN_CNTRL_2_REG(chan->channel);
279
280 ret = regmap_read(st->regmap, reg, &raw);
281 if (ret)
282 return ret;
283
284 raw = FIELD_GET(AXI_DAC_CHAN_CNTRL_2_PHASE, raw);
285 phase = DIV_ROUND_CLOSEST_ULL((u64)raw * AXI_DAC_2_PI_MEGA, U16_MAX);
286
287 vals[0] = phase / MEGA;
288 vals[1] = phase % MEGA;
289
290 return iio_format_value(buf, IIO_VAL_INT_PLUS_MICRO, ARRAY_SIZE(vals),
291 vals);
292 }
293
__axi_dac_frequency_set(struct axi_dac_state * st,unsigned int chan,u64 sample_rate,unsigned int freq,unsigned int tone_2)294 static int __axi_dac_frequency_set(struct axi_dac_state *st, unsigned int chan,
295 u64 sample_rate, unsigned int freq,
296 unsigned int tone_2)
297 {
298 u32 reg;
299 u16 raw;
300 int ret;
301
302 if (chan > AXI_DAC_CHAN_CNTRL_MAX)
303 return -EINVAL;
304
305 if (!sample_rate || freq > sample_rate / 2) {
306 dev_err(st->dev, "Invalid frequency(%u) dac_clk(%llu)\n",
307 freq, sample_rate);
308 return -EINVAL;
309 }
310
311 if (tone_2)
312 reg = AXI_DAC_CHAN_CNTRL_4_REG(chan);
313 else
314 reg = AXI_DAC_CHAN_CNTRL_2_REG(chan);
315
316 raw = DIV64_U64_ROUND_CLOSEST((u64)freq * BIT(16), sample_rate);
317
318 ret = regmap_update_bits(st->regmap, reg,
319 AXI_DAC_CHAN_CNTRL_2_FREQUENCY, raw);
320 if (ret)
321 return ret;
322
323 /* synchronize channels */
324 return regmap_set_bits(st->regmap, AXI_DAC_CNTRL_1_REG,
325 AXI_DAC_CNTRL_1_SYNC);
326 }
327
axi_dac_frequency_set(struct axi_dac_state * st,const struct iio_chan_spec * chan,const char * buf,size_t len,unsigned int tone_2)328 static int axi_dac_frequency_set(struct axi_dac_state *st,
329 const struct iio_chan_spec *chan,
330 const char *buf, size_t len, unsigned int tone_2)
331 {
332 unsigned int freq;
333 int ret;
334
335 ret = kstrtou32(buf, 10, &freq);
336 if (ret)
337 return ret;
338
339 guard(mutex)(&st->lock);
340 ret = __axi_dac_frequency_set(st, chan->channel, st->dac_clk, freq,
341 tone_2);
342 if (ret)
343 return ret;
344
345 return len;
346 }
347
axi_dac_scale_set(struct axi_dac_state * st,const struct iio_chan_spec * chan,const char * buf,size_t len,unsigned int tone_2)348 static int axi_dac_scale_set(struct axi_dac_state *st,
349 const struct iio_chan_spec *chan,
350 const char *buf, size_t len, unsigned int tone_2)
351 {
352 int integer, frac, scale;
353 u32 raw = 0, reg;
354 int ret;
355
356 if (chan->channel > AXI_DAC_CHAN_CNTRL_MAX)
357 return -EINVAL;
358
359 ret = iio_str_to_fixpoint(buf, 100000, &integer, &frac);
360 if (ret)
361 return ret;
362
363 scale = integer * MEGA + frac;
364 if (scale <= -2 * (int)MEGA || scale >= 2 * (int)MEGA)
365 return -EINVAL;
366
367 /* format is 1.1.14 (sign, integer and fractional bits) */
368 if (scale < 0) {
369 raw = FIELD_PREP(AXI_DAC_CHAN_CNTRL_3_SCALE_SIGN, 1);
370 scale *= -1;
371 }
372
373 raw |= div_u64((u64)scale * AXI_DAC_CHAN_CNTRL_3_SCALE_INT, MEGA);
374
375 if (tone_2)
376 reg = AXI_DAC_CHAN_CNTRL_3_REG(chan->channel);
377 else
378 reg = AXI_DAC_CHAN_CNTRL_1_REG(chan->channel);
379
380 guard(mutex)(&st->lock);
381 ret = regmap_write(st->regmap, reg, raw);
382 if (ret)
383 return ret;
384
385 /* synchronize channels */
386 ret = regmap_set_bits(st->regmap, AXI_DAC_CNTRL_1_REG,
387 AXI_DAC_CNTRL_1_SYNC);
388 if (ret)
389 return ret;
390
391 return len;
392 }
393
axi_dac_phase_set(struct axi_dac_state * st,const struct iio_chan_spec * chan,const char * buf,size_t len,unsigned int tone_2)394 static int axi_dac_phase_set(struct axi_dac_state *st,
395 const struct iio_chan_spec *chan,
396 const char *buf, size_t len, unsigned int tone_2)
397 {
398 int integer, frac, phase;
399 u32 raw, reg;
400 int ret;
401
402 if (chan->channel > AXI_DAC_CHAN_CNTRL_MAX)
403 return -EINVAL;
404
405 ret = iio_str_to_fixpoint(buf, 100000, &integer, &frac);
406 if (ret)
407 return ret;
408
409 phase = integer * MEGA + frac;
410 if (phase < 0 || phase > AXI_DAC_2_PI_MEGA)
411 return -EINVAL;
412
413 raw = DIV_ROUND_CLOSEST_ULL((u64)phase * U16_MAX, AXI_DAC_2_PI_MEGA);
414
415 if (tone_2)
416 reg = AXI_DAC_CHAN_CNTRL_4_REG(chan->channel);
417 else
418 reg = AXI_DAC_CHAN_CNTRL_2_REG(chan->channel);
419
420 guard(mutex)(&st->lock);
421 ret = regmap_update_bits(st->regmap, reg, AXI_DAC_CHAN_CNTRL_2_PHASE,
422 FIELD_PREP(AXI_DAC_CHAN_CNTRL_2_PHASE, raw));
423 if (ret)
424 return ret;
425
426 /* synchronize channels */
427 ret = regmap_set_bits(st->regmap, AXI_DAC_CNTRL_1_REG,
428 AXI_DAC_CNTRL_1_SYNC);
429 if (ret)
430 return ret;
431
432 return len;
433 }
434
axi_dac_ext_info_set(struct iio_backend * back,uintptr_t private,const struct iio_chan_spec * chan,const char * buf,size_t len)435 static int axi_dac_ext_info_set(struct iio_backend *back, uintptr_t private,
436 const struct iio_chan_spec *chan,
437 const char *buf, size_t len)
438 {
439 struct axi_dac_state *st = iio_backend_get_priv(back);
440
441 switch (private) {
442 case AXI_DAC_FREQ_TONE_1:
443 case AXI_DAC_FREQ_TONE_2:
444 return axi_dac_frequency_set(st, chan, buf, len,
445 private == AXI_DAC_FREQ_TONE_2);
446 case AXI_DAC_SCALE_TONE_1:
447 case AXI_DAC_SCALE_TONE_2:
448 return axi_dac_scale_set(st, chan, buf, len,
449 private == AXI_DAC_SCALE_TONE_2);
450 case AXI_DAC_PHASE_TONE_1:
451 case AXI_DAC_PHASE_TONE_2:
452 return axi_dac_phase_set(st, chan, buf, len,
453 private == AXI_DAC_PHASE_TONE_2);
454 default:
455 return -EOPNOTSUPP;
456 }
457 }
458
axi_dac_ext_info_get(struct iio_backend * back,uintptr_t private,const struct iio_chan_spec * chan,char * buf)459 static int axi_dac_ext_info_get(struct iio_backend *back, uintptr_t private,
460 const struct iio_chan_spec *chan, char *buf)
461 {
462 struct axi_dac_state *st = iio_backend_get_priv(back);
463
464 switch (private) {
465 case AXI_DAC_FREQ_TONE_1:
466 case AXI_DAC_FREQ_TONE_2:
467 return axi_dac_frequency_get(st, chan, buf,
468 private - AXI_DAC_FREQ_TONE_1);
469 case AXI_DAC_SCALE_TONE_1:
470 case AXI_DAC_SCALE_TONE_2:
471 return axi_dac_scale_get(st, chan, buf,
472 private - AXI_DAC_SCALE_TONE_1);
473 case AXI_DAC_PHASE_TONE_1:
474 case AXI_DAC_PHASE_TONE_2:
475 return axi_dac_phase_get(st, chan, buf,
476 private - AXI_DAC_PHASE_TONE_1);
477 default:
478 return -EOPNOTSUPP;
479 }
480 }
481
482 static const struct iio_chan_spec_ext_info axi_dac_ext_info[] = {
483 IIO_BACKEND_EX_INFO("frequency0", IIO_SEPARATE, AXI_DAC_FREQ_TONE_1),
484 IIO_BACKEND_EX_INFO("frequency1", IIO_SEPARATE, AXI_DAC_FREQ_TONE_2),
485 IIO_BACKEND_EX_INFO("scale0", IIO_SEPARATE, AXI_DAC_SCALE_TONE_1),
486 IIO_BACKEND_EX_INFO("scale1", IIO_SEPARATE, AXI_DAC_SCALE_TONE_2),
487 IIO_BACKEND_EX_INFO("phase0", IIO_SEPARATE, AXI_DAC_PHASE_TONE_1),
488 IIO_BACKEND_EX_INFO("phase1", IIO_SEPARATE, AXI_DAC_PHASE_TONE_2),
489 { }
490 };
491
axi_dac_extend_chan(struct iio_backend * back,struct iio_chan_spec * chan)492 static int axi_dac_extend_chan(struct iio_backend *back,
493 struct iio_chan_spec *chan)
494 {
495 struct axi_dac_state *st = iio_backend_get_priv(back);
496
497 if (chan->type != IIO_ALTVOLTAGE)
498 return -EINVAL;
499 if (st->reg_config & AXI_DAC_CONFIG_DDS_DISABLE)
500 /* nothing to extend */
501 return 0;
502
503 chan->ext_info = axi_dac_ext_info;
504
505 return 0;
506 }
507
axi_dac_data_source_set(struct iio_backend * back,unsigned int chan,enum iio_backend_data_source data)508 static int axi_dac_data_source_set(struct iio_backend *back, unsigned int chan,
509 enum iio_backend_data_source data)
510 {
511 struct axi_dac_state *st = iio_backend_get_priv(back);
512
513 if (chan > AXI_DAC_CHAN_CNTRL_MAX)
514 return -EINVAL;
515
516 switch (data) {
517 case IIO_BACKEND_INTERNAL_CONTINUOUS_WAVE:
518 return regmap_update_bits(st->regmap,
519 AXI_DAC_CHAN_CNTRL_7_REG(chan),
520 AXI_DAC_CHAN_CNTRL_7_DATA_SEL,
521 AXI_DAC_DATA_INTERNAL_TONE);
522 case IIO_BACKEND_EXTERNAL:
523 return regmap_update_bits(st->regmap,
524 AXI_DAC_CHAN_CNTRL_7_REG(chan),
525 AXI_DAC_CHAN_CNTRL_7_DATA_SEL,
526 AXI_DAC_DATA_DMA);
527 case IIO_BACKEND_INTERNAL_RAMP_16BIT:
528 return regmap_update_bits(st->regmap,
529 AXI_DAC_CHAN_CNTRL_7_REG(chan),
530 AXI_DAC_CHAN_CNTRL_7_DATA_SEL,
531 AXI_DAC_DATA_INTERNAL_RAMP_16BIT);
532 default:
533 return -EINVAL;
534 }
535 }
536
axi_dac_data_source_get(struct iio_backend * back,unsigned int chan,enum iio_backend_data_source * data)537 static int axi_dac_data_source_get(struct iio_backend *back, unsigned int chan,
538 enum iio_backend_data_source *data)
539 {
540 struct axi_dac_state *st = iio_backend_get_priv(back);
541 int ret;
542 u32 val;
543
544 if (chan > AXI_DAC_CHAN_CNTRL_MAX)
545 return -EINVAL;
546
547 ret = regmap_read(st->regmap, AXI_DAC_CHAN_CNTRL_7_REG(chan), &val);
548 if (ret)
549 return ret;
550
551 switch (val) {
552 case AXI_DAC_DATA_INTERNAL_TONE:
553 *data = IIO_BACKEND_INTERNAL_CONTINUOUS_WAVE;
554 return 0;
555 case AXI_DAC_DATA_DMA:
556 *data = IIO_BACKEND_EXTERNAL;
557 return 0;
558 case AXI_DAC_DATA_INTERNAL_RAMP_16BIT:
559 *data = IIO_BACKEND_INTERNAL_RAMP_16BIT;
560 return 0;
561 default:
562 return -EIO;
563 }
564 }
565
axi_dac_set_sample_rate(struct iio_backend * back,unsigned int chan,u64 sample_rate)566 static int axi_dac_set_sample_rate(struct iio_backend *back, unsigned int chan,
567 u64 sample_rate)
568 {
569 struct axi_dac_state *st = iio_backend_get_priv(back);
570 unsigned int freq;
571 int ret, tone;
572
573 if (chan > AXI_DAC_CHAN_CNTRL_MAX)
574 return -EINVAL;
575 if (!sample_rate)
576 return -EINVAL;
577 if (st->reg_config & AXI_DAC_CONFIG_DDS_DISABLE)
578 /* sample_rate has no meaning if DDS is disabled */
579 return 0;
580
581 guard(mutex)(&st->lock);
582 /*
583 * If dac_clk is 0 then this must be the first time we're being notified
584 * about the interface sample rate. Hence, just update our internal
585 * variable and bail... If it's not 0, then we get the current DDS
586 * frequency (for the old rate) and update the registers for the new
587 * sample rate.
588 */
589 if (!st->dac_clk) {
590 st->dac_clk = sample_rate;
591 return 0;
592 }
593
594 for (tone = 0; tone <= AXI_DAC_FREQ_TONE_2; tone++) {
595 ret = __axi_dac_frequency_get(st, chan, tone, &freq);
596 if (ret)
597 return ret;
598
599 ret = __axi_dac_frequency_set(st, chan, sample_rate, tone, freq);
600 if (ret)
601 return ret;
602 }
603
604 st->dac_clk = sample_rate;
605
606 return 0;
607 }
608
axi_dac_reg_access(struct iio_backend * back,unsigned int reg,unsigned int writeval,unsigned int * readval)609 static int axi_dac_reg_access(struct iio_backend *back, unsigned int reg,
610 unsigned int writeval, unsigned int *readval)
611 {
612 struct axi_dac_state *st = iio_backend_get_priv(back);
613
614 if (readval)
615 return regmap_read(st->regmap, reg, readval);
616
617 return regmap_write(st->regmap, reg, writeval);
618 }
619
axi_dac_ddr_enable(struct iio_backend * back)620 static int axi_dac_ddr_enable(struct iio_backend *back)
621 {
622 struct axi_dac_state *st = iio_backend_get_priv(back);
623
624 return regmap_clear_bits(st->regmap, AXI_DAC_CNTRL_2_REG,
625 AXI_DAC_CNTRL_2_SDR_DDR_N);
626 }
627
axi_dac_ddr_disable(struct iio_backend * back)628 static int axi_dac_ddr_disable(struct iio_backend *back)
629 {
630 struct axi_dac_state *st = iio_backend_get_priv(back);
631
632 return regmap_set_bits(st->regmap, AXI_DAC_CNTRL_2_REG,
633 AXI_DAC_CNTRL_2_SDR_DDR_N);
634 }
635
axi_dac_wait_bus_free(struct axi_dac_state * st)636 static int axi_dac_wait_bus_free(struct axi_dac_state *st)
637 {
638 u32 val;
639 int ret;
640
641 ret = regmap_read_poll_timeout(st->regmap, AXI_DAC_UI_STATUS_REG, val,
642 FIELD_GET(AXI_DAC_UI_STATUS_IF_BUSY, val) == 0, 10,
643 100 * KILO);
644 if (ret == -ETIMEDOUT)
645 dev_err(st->dev, "AXI bus timeout\n");
646
647 return ret;
648 }
649
axi_dac_data_stream_enable(struct iio_backend * back)650 static int axi_dac_data_stream_enable(struct iio_backend *back)
651 {
652 struct axi_dac_state *st = iio_backend_get_priv(back);
653 int ret;
654
655 ret = axi_dac_wait_bus_free(st);
656 if (ret)
657 return ret;
658
659 return regmap_set_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG,
660 AXI_DAC_CUSTOM_CTRL_STREAM_ENABLE);
661 }
662
axi_dac_data_stream_disable(struct iio_backend * back)663 static int axi_dac_data_stream_disable(struct iio_backend *back)
664 {
665 struct axi_dac_state *st = iio_backend_get_priv(back);
666
667 return regmap_clear_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG,
668 AXI_DAC_CUSTOM_CTRL_STREAM_ENABLE);
669 }
670
axi_dac_data_transfer_addr(struct iio_backend * back,u32 address)671 static int axi_dac_data_transfer_addr(struct iio_backend *back, u32 address)
672 {
673 struct axi_dac_state *st = iio_backend_get_priv(back);
674
675 if (address > FIELD_MAX(AXI_DAC_CUSTOM_CTRL_ADDRESS))
676 return -EINVAL;
677
678 /*
679 * Sample register address, when the DAC is configured, or stream
680 * start address when the FSM is in stream state.
681 */
682 return regmap_update_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG,
683 AXI_DAC_CUSTOM_CTRL_ADDRESS,
684 FIELD_PREP(AXI_DAC_CUSTOM_CTRL_ADDRESS,
685 address));
686 }
687
axi_dac_data_format_set(struct iio_backend * back,unsigned int ch,const struct iio_backend_data_fmt * data)688 static int axi_dac_data_format_set(struct iio_backend *back, unsigned int ch,
689 const struct iio_backend_data_fmt *data)
690 {
691 struct axi_dac_state *st = iio_backend_get_priv(back);
692
693 switch (data->type) {
694 case IIO_BACKEND_DATA_UNSIGNED:
695 return regmap_clear_bits(st->regmap, AXI_DAC_CNTRL_2_REG,
696 AXI_DAC_CNTRL_2_UNSIGNED_DATA);
697 default:
698 return -EINVAL;
699 }
700 }
701
__axi_dac_bus_reg_write(struct iio_backend * back,u32 reg,u32 val,size_t data_size)702 static int __axi_dac_bus_reg_write(struct iio_backend *back, u32 reg,
703 u32 val, size_t data_size)
704 {
705 struct axi_dac_state *st = iio_backend_get_priv(back);
706 int ret;
707 u32 ival;
708
709 /*
710 * Both AXI_DAC_CNTRL_2_REG and AXI_DAC_CUSTOM_WR_REG need to know
711 * the data size. So keeping data size control here only,
712 * since data size is mandatory for the current transfer.
713 * DDR state handled separately by specific backend calls,
714 * generally all raw register writes are SDR.
715 */
716 if (data_size == sizeof(u16))
717 ival = FIELD_PREP(AXI_DAC_CUSTOM_WR_DATA_16, val);
718 else
719 ival = FIELD_PREP(AXI_DAC_CUSTOM_WR_DATA_8, val);
720
721 ret = regmap_write(st->regmap, AXI_DAC_CUSTOM_WR_REG, ival);
722 if (ret)
723 return ret;
724
725 if (data_size == sizeof(u8))
726 ret = regmap_set_bits(st->regmap, AXI_DAC_CNTRL_2_REG,
727 AXI_DAC_CNTRL_2_SYMB_8B);
728 else
729 ret = regmap_clear_bits(st->regmap, AXI_DAC_CNTRL_2_REG,
730 AXI_DAC_CNTRL_2_SYMB_8B);
731 if (ret)
732 return ret;
733
734 ret = regmap_update_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG,
735 AXI_DAC_CUSTOM_CTRL_ADDRESS,
736 FIELD_PREP(AXI_DAC_CUSTOM_CTRL_ADDRESS, reg));
737 if (ret)
738 return ret;
739
740 ret = regmap_update_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG,
741 AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA,
742 AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA);
743 if (ret)
744 return ret;
745
746 ret = axi_dac_wait_bus_free(st);
747 if (ret)
748 return ret;
749
750 /* Cleaning always AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA */
751 return regmap_clear_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG,
752 AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA);
753 }
754
axi_dac_bus_reg_write(struct iio_backend * back,u32 reg,u32 val,size_t data_size)755 static int axi_dac_bus_reg_write(struct iio_backend *back, u32 reg,
756 u32 val, size_t data_size)
757 {
758 struct axi_dac_state *st = iio_backend_get_priv(back);
759
760 guard(mutex)(&st->lock);
761 return __axi_dac_bus_reg_write(back, reg, val, data_size);
762 }
763
axi_dac_bus_reg_read(struct iio_backend * back,u32 reg,u32 * val,size_t data_size)764 static int axi_dac_bus_reg_read(struct iio_backend *back, u32 reg, u32 *val,
765 size_t data_size)
766 {
767 struct axi_dac_state *st = iio_backend_get_priv(back);
768 int ret;
769
770 guard(mutex)(&st->lock);
771
772 /*
773 * SPI, we write with read flag, then we read just at the AXI
774 * io address space to get data read.
775 */
776 ret = __axi_dac_bus_reg_write(back, AXI_DAC_RD_ADDR(reg), 0,
777 data_size);
778 if (ret)
779 return ret;
780
781 ret = axi_dac_wait_bus_free(st);
782 if (ret)
783 return ret;
784
785 return regmap_read(st->regmap, AXI_DAC_CUSTOM_RD_REG, val);
786 }
787
axi_dac_bus_set_io_mode(struct iio_backend * back,enum ad3552r_io_mode mode)788 static int axi_dac_bus_set_io_mode(struct iio_backend *back,
789 enum ad3552r_io_mode mode)
790 {
791 struct axi_dac_state *st = iio_backend_get_priv(back);
792 int ret;
793
794 if (mode > AD3552R_IO_MODE_QSPI)
795 return -EINVAL;
796
797 guard(mutex)(&st->lock);
798
799 ret = regmap_update_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG,
800 AXI_DAC_CUSTOM_CTRL_MULTI_IO_MODE,
801 FIELD_PREP(AXI_DAC_CUSTOM_CTRL_MULTI_IO_MODE, mode));
802 if (ret)
803 return ret;
804
805 return axi_dac_wait_bus_free(st);
806 }
807
axi_dac_child_remove(void * data)808 static void axi_dac_child_remove(void *data)
809 {
810 platform_device_unregister(data);
811 }
812
axi_dac_create_platform_device(struct axi_dac_state * st,struct fwnode_handle * child)813 static int axi_dac_create_platform_device(struct axi_dac_state *st,
814 struct fwnode_handle *child)
815 {
816 struct ad3552r_hs_platform_data pdata = {
817 .bus_reg_read = axi_dac_bus_reg_read,
818 .bus_reg_write = axi_dac_bus_reg_write,
819 .bus_set_io_mode = axi_dac_bus_set_io_mode,
820 .bus_sample_data_clock_hz = st->dac_clk_rate,
821 };
822 struct platform_device_info pi = {
823 .parent = st->dev,
824 .name = fwnode_get_name(child),
825 .id = PLATFORM_DEVID_AUTO,
826 .fwnode = child,
827 .data = &pdata,
828 .size_data = sizeof(pdata),
829 };
830 struct platform_device *pdev;
831
832 pdev = platform_device_register_full(&pi);
833 if (IS_ERR(pdev))
834 return PTR_ERR(pdev);
835
836 return devm_add_action_or_reset(st->dev, axi_dac_child_remove, pdev);
837 }
838
839 static const struct iio_backend_ops axi_dac_generic_ops = {
840 .enable = axi_dac_enable,
841 .disable = axi_dac_disable,
842 .request_buffer = axi_dac_request_buffer,
843 .free_buffer = axi_dac_free_buffer,
844 .extend_chan_spec = axi_dac_extend_chan,
845 .ext_info_set = axi_dac_ext_info_set,
846 .ext_info_get = axi_dac_ext_info_get,
847 .data_source_set = axi_dac_data_source_set,
848 .set_sample_rate = axi_dac_set_sample_rate,
849 .debugfs_reg_access = iio_backend_debugfs_ptr(axi_dac_reg_access),
850 };
851
852 static const struct iio_backend_ops axi_ad3552r_ops = {
853 .enable = axi_dac_enable,
854 .disable = axi_dac_disable,
855 .request_buffer = axi_dac_request_buffer,
856 .free_buffer = axi_dac_free_buffer,
857 .data_source_set = axi_dac_data_source_set,
858 .data_source_get = axi_dac_data_source_get,
859 .ddr_enable = axi_dac_ddr_enable,
860 .ddr_disable = axi_dac_ddr_disable,
861 .data_stream_enable = axi_dac_data_stream_enable,
862 .data_stream_disable = axi_dac_data_stream_disable,
863 .data_format_set = axi_dac_data_format_set,
864 .data_transfer_addr = axi_dac_data_transfer_addr,
865 };
866
867 static const struct iio_backend_info axi_dac_generic = {
868 .name = "axi-dac",
869 .ops = &axi_dac_generic_ops,
870 .caps = IIO_BACKEND_CAP_BUFFER | IIO_BACKEND_CAP_ENABLE,
871 };
872
873 static const struct iio_backend_info axi_ad3552r = {
874 .name = "axi-ad3552r",
875 .ops = &axi_ad3552r_ops,
876 .caps = IIO_BACKEND_CAP_BUFFER | IIO_BACKEND_CAP_ENABLE,
877 };
878
879 static const struct regmap_config axi_dac_regmap_config = {
880 .val_bits = 32,
881 .reg_bits = 32,
882 .reg_stride = 4,
883 .max_register = 0x0800,
884 };
885
axi_dac_probe(struct platform_device * pdev)886 static int axi_dac_probe(struct platform_device *pdev)
887 {
888 struct device *dev = &pdev->dev;
889 struct axi_dac_state *st;
890 void __iomem *base;
891 unsigned int ver;
892 struct clk *clk;
893 int ret;
894
895 st = devm_kzalloc(dev, sizeof(*st), GFP_KERNEL);
896 if (!st)
897 return -ENOMEM;
898
899 st->info = device_get_match_data(dev);
900 if (!st->info)
901 return -ENODEV;
902 clk = devm_clk_get_enabled(dev, "s_axi_aclk");
903 if (IS_ERR(clk)) {
904 /* Backward compat., old fdt versions without clock-names. */
905 clk = devm_clk_get_enabled(dev, NULL);
906 if (IS_ERR(clk))
907 return dev_err_probe(dev, PTR_ERR(clk),
908 "failed to get clock\n");
909 }
910
911 if (st->info->has_dac_clk) {
912 struct clk *dac_clk;
913
914 dac_clk = devm_clk_get_enabled(dev, "dac_clk");
915 if (IS_ERR(dac_clk))
916 return dev_err_probe(dev, PTR_ERR(dac_clk),
917 "failed to get dac_clk clock\n");
918
919 /* We only care about the streaming mode rate */
920 st->dac_clk_rate = clk_get_rate(dac_clk) / 2;
921 }
922
923 base = devm_platform_ioremap_resource(pdev, 0);
924 if (IS_ERR(base))
925 return PTR_ERR(base);
926
927 st->dev = dev;
928 st->regmap = devm_regmap_init_mmio(dev, base, &axi_dac_regmap_config);
929 if (IS_ERR(st->regmap))
930 return dev_err_probe(dev, PTR_ERR(st->regmap),
931 "failed to init register map\n");
932
933 /*
934 * Force disable the core. Up to the frontend to enable us. And we can
935 * still read/write registers...
936 */
937 ret = regmap_write(st->regmap, AXI_DAC_RSTN_REG, 0);
938 if (ret)
939 return ret;
940
941 ret = regmap_read(st->regmap, ADI_AXI_REG_VERSION, &ver);
942 if (ret)
943 return ret;
944
945 if (ADI_AXI_PCORE_VER_MAJOR(ver) != ADI_AXI_PCORE_VER_MAJOR(st->info->version))
946 return dev_err_probe(dev, -ENODEV,
947 "Major version mismatch. Expected %d.%.2d.%c, Reported %d.%.2d.%c\n",
948 ADI_AXI_PCORE_VER_MAJOR(st->info->version),
949 ADI_AXI_PCORE_VER_MINOR(st->info->version),
950 ADI_AXI_PCORE_VER_PATCH(st->info->version),
951 ADI_AXI_PCORE_VER_MAJOR(ver),
952 ADI_AXI_PCORE_VER_MINOR(ver),
953 ADI_AXI_PCORE_VER_PATCH(ver));
954
955 /* Let's get the core read only configuration */
956 ret = regmap_read(st->regmap, AXI_DAC_CONFIG_REG, &st->reg_config);
957 if (ret)
958 return ret;
959
960 /*
961 * In some designs, setting the R1_MODE bit to 0 (which is the default
962 * value) causes all channels of the frontend to be routed to the same
963 * DMA (so they are sampled together). This is for things like
964 * Multiple-Input and Multiple-Output (MIMO). As most of the times we
965 * want independent channels let's override the core's default value and
966 * set the R1_MODE bit.
967 */
968 ret = regmap_set_bits(st->regmap, AXI_DAC_CNTRL_2_REG,
969 ADI_DAC_CNTRL_2_R1_MODE);
970 if (ret)
971 return ret;
972
973 mutex_init(&st->lock);
974
975 ret = devm_iio_backend_register(dev, st->info->backend_info, st);
976 if (ret)
977 return dev_err_probe(dev, ret,
978 "failed to register iio backend\n");
979
980 device_for_each_child_node_scoped(dev, child) {
981 int val;
982
983 if (!st->info->has_child_nodes)
984 return dev_err_probe(dev, -EINVAL,
985 "invalid fdt axi-dac compatible.");
986
987 /* Processing only reg 0 node */
988 ret = fwnode_property_read_u32(child, "reg", &val);
989 if (ret)
990 return dev_err_probe(dev, ret, "invalid reg property.");
991 if (val != 0)
992 return dev_err_probe(dev, -EINVAL,
993 "invalid node address.");
994
995 ret = axi_dac_create_platform_device(st, child);
996 if (ret)
997 return dev_err_probe(dev, -EINVAL,
998 "cannot create device.");
999 }
1000
1001 dev_info(dev, "AXI DAC IP core (%d.%.2d.%c) probed\n",
1002 ADI_AXI_PCORE_VER_MAJOR(ver),
1003 ADI_AXI_PCORE_VER_MINOR(ver),
1004 ADI_AXI_PCORE_VER_PATCH(ver));
1005
1006 return 0;
1007 }
1008
1009 static const struct axi_dac_info dac_generic = {
1010 .version = ADI_AXI_PCORE_VER(9, 1, 'b'),
1011 .backend_info = &axi_dac_generic,
1012 };
1013
1014 static const struct axi_dac_info dac_ad3552r = {
1015 .version = ADI_AXI_PCORE_VER(9, 1, 'b'),
1016 .backend_info = &axi_ad3552r,
1017 .has_dac_clk = true,
1018 .has_child_nodes = true,
1019 };
1020
1021 static const struct of_device_id axi_dac_of_match[] = {
1022 { .compatible = "adi,axi-dac-9.1.b", .data = &dac_generic },
1023 { .compatible = "adi,axi-ad3552r", .data = &dac_ad3552r },
1024 { }
1025 };
1026 MODULE_DEVICE_TABLE(of, axi_dac_of_match);
1027
1028 static struct platform_driver axi_dac_driver = {
1029 .driver = {
1030 .name = "adi-axi-dac",
1031 .of_match_table = axi_dac_of_match,
1032 },
1033 .probe = axi_dac_probe,
1034 };
1035 module_platform_driver(axi_dac_driver);
1036
1037 MODULE_AUTHOR("Nuno Sa <nuno.sa@analog.com>");
1038 MODULE_DESCRIPTION("Analog Devices Generic AXI DAC IP core driver");
1039 MODULE_LICENSE("GPL");
1040 MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER");
1041 MODULE_IMPORT_NS("IIO_BACKEND");
1042