1 /* SPDX-License-Identifier: GPL-2.0-only 2 * SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION. All rights reserved. 3 * 4 * tegra210_adx.h - Definitions for Tegra210 ADX driver 5 * 6 */ 7 8 #ifndef __TEGRA210_ADX_H__ 9 #define __TEGRA210_ADX_H__ 10 11 #include <linux/types.h> 12 13 /* Register offsets from TEGRA210_ADX*_BASE */ 14 #define TEGRA210_ADX_RX_STATUS 0x0c 15 #define TEGRA210_ADX_RX_INT_STATUS 0x10 16 #define TEGRA210_ADX_RX_INT_MASK 0x14 17 #define TEGRA210_ADX_RX_INT_SET 0x18 18 #define TEGRA210_ADX_RX_INT_CLEAR 0x1c 19 #define TEGRA210_ADX_RX_CIF_CTRL 0x20 20 #define TEGRA210_ADX_TX_STATUS 0x4c 21 #define TEGRA210_ADX_TX_INT_STATUS 0x50 22 #define TEGRA210_ADX_TX_INT_MASK 0x54 23 #define TEGRA210_ADX_TX_INT_SET 0x58 24 #define TEGRA210_ADX_TX_INT_CLEAR 0x5c 25 #define TEGRA210_ADX_TX1_CIF_CTRL 0x60 26 #define TEGRA210_ADX_TX2_CIF_CTRL 0x64 27 #define TEGRA210_ADX_TX3_CIF_CTRL 0x68 28 #define TEGRA210_ADX_TX4_CIF_CTRL 0x6c 29 #define TEGRA210_ADX_ENABLE 0x80 30 #define TEGRA210_ADX_SOFT_RESET 0x84 31 #define TEGRA210_ADX_CG 0x88 32 #define TEGRA210_ADX_STATUS 0x8c 33 #define TEGRA210_ADX_INT_STATUS 0x90 34 #define TEGRA210_ADX_CTRL 0xa4 35 #define TEGRA210_ADX_IN_BYTE_EN0 0xa8 36 #define TEGRA210_ADX_IN_BYTE_EN1 0xac 37 #define TEGRA210_ADX_CFG_RAM_CTRL 0xb8 38 #define TEGRA210_ADX_CFG_RAM_DATA 0xbc 39 40 #define TEGRA264_ADX_CYA 0xb8 41 #define TEGRA264_ADX_CFG_RAM_CTRL 0xc0 42 #define TEGRA264_ADX_CFG_RAM_DATA 0xc4 43 44 /* Fields in TEGRA210_ADX_ENABLE */ 45 #define TEGRA210_ADX_ENABLE_SHIFT 0 46 47 /* Fields in TEGRA210_ADX_CFG_RAM_CTRL */ 48 #define TEGRA210_ADX_CFG_RAM_CTRL_RAM_ADDR_SHIFT 0 49 50 #define TEGRA210_ADX_CFG_RAM_CTRL_RW_SHIFT 14 51 #define TEGRA210_ADX_CFG_RAM_CTRL_RW_WRITE (1 << TEGRA210_ADX_CFG_RAM_CTRL_RW_SHIFT) 52 53 #define TEGRA210_ADX_CFG_RAM_CTRL_ADDR_INIT_EN_SHIFT 13 54 #define TEGRA210_ADX_CFG_RAM_CTRL_ADDR_INIT_EN (1 << TEGRA210_ADX_CFG_RAM_CTRL_ADDR_INIT_EN_SHIFT) 55 56 #define TEGRA210_ADX_CFG_RAM_CTRL_SEQ_ACCESS_EN_SHIFT 12 57 #define TEGRA210_ADX_CFG_RAM_CTRL_SEQ_ACCESS_EN (1 << TEGRA210_ADX_CFG_RAM_CTRL_SEQ_ACCESS_EN_SHIFT) 58 59 /* Fields in TEGRA210_ADX_SOFT_RESET */ 60 #define TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT 0 61 #define TEGRA210_ADX_SOFT_RESET_SOFT_RESET_MASK (1 << TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT) 62 #define TEGRA210_ADX_SOFT_RESET_SOFT_EN (1 << TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT) 63 #define TEGRA210_ADX_SOFT_RESET_SOFT_DEFAULT (0 << TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT) 64 65 #define TEGRA210_ADX_AUDIOCIF_CH_STRIDE 4 66 #define TEGRA_ADX_SLOTS_PER_WORD 4 67 #define TEGRA210_ADX_RAM_DEPTH 16 68 #define TEGRA210_ADX_MAP_STREAM_NUMBER_SHIFT 6 69 #define TEGRA210_ADX_MAP_WORD_NUMBER_SHIFT 2 70 #define TEGRA210_ADX_MAP_BYTE_NUMBER_SHIFT 0 71 #define TEGRA210_ADX_BYTE_MASK_COUNT 2 72 #define TEGRA210_ADX_MAX_CHANNEL 16 73 #define TEGRA210_ADX_CYA_OFFSET 0 74 75 #define TEGRA264_ADX_RAM_DEPTH 32 76 #define TEGRA264_ADX_BYTE_MASK_COUNT 4 77 #define TEGRA264_ADX_MAX_CHANNEL 32 78 #define TEGRA264_ADX_CYA_OFFSET 8 79 80 #define TEGRA_ADX_IN_DAI_ID 4 81 82 struct tegra210_adx_soc_data { 83 const struct regmap_config *regmap_conf; 84 const struct snd_kcontrol_new *controls; 85 unsigned int num_controls; 86 unsigned int max_ch; 87 unsigned int ram_depth; 88 unsigned int byte_mask_size; 89 unsigned int cya_offset; 90 }; 91 92 struct tegra210_adx { 93 struct regmap *regmap; 94 unsigned int *byte_mask; 95 u16 *map; 96 const struct tegra210_adx_soc_data *soc_data; 97 }; 98 99 #endif 100