1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2023, Collabora 4 * 5 * Author: Benjamin Gaignard <benjamin.gaignard@collabora.com> 6 */ 7 8 #include <media/v4l2-mem2mem.h> 9 #include "hantro.h" 10 #include "hantro_v4l2.h" 11 #include "rockchip_vpu981_regs.h" 12 13 #define AV1_DEC_MODE 17 14 #define GM_GLOBAL_MODELS_PER_FRAME 7 15 #define GLOBAL_MODEL_TOTAL_SIZE (6 * 4 + 4 * 2) 16 #define GLOBAL_MODEL_SIZE ALIGN(GM_GLOBAL_MODELS_PER_FRAME * GLOBAL_MODEL_TOTAL_SIZE, 2048) 17 #define AV1_MAX_TILES 128 18 #define AV1_TILE_INFO_SIZE (AV1_MAX_TILES * 16) 19 #define AV1DEC_MAX_PIC_BUFFERS 24 20 #define AV1_REF_SCALE_SHIFT 14 21 #define AV1_INVALID_IDX -1 22 #define MAX_FRAME_DISTANCE 31 23 #define AV1_PRIMARY_REF_NONE 7 24 #define AV1_TILE_SIZE ALIGN(32 * 128, 4096) 25 /* 26 * These 3 values aren't defined enum v4l2_av1_segment_feature because 27 * they are not part of the specification 28 */ 29 #define V4L2_AV1_SEG_LVL_ALT_LF_Y_H 2 30 #define V4L2_AV1_SEG_LVL_ALT_LF_U 3 31 #define V4L2_AV1_SEG_LVL_ALT_LF_V 4 32 33 #define SUPERRES_SCALE_BITS 3 34 #define SCALE_NUMERATOR 8 35 #define SUPERRES_SCALE_DENOMINATOR_MIN (SCALE_NUMERATOR + 1) 36 37 #define RS_SUBPEL_BITS 6 38 #define RS_SUBPEL_MASK ((1 << RS_SUBPEL_BITS) - 1) 39 #define RS_SCALE_SUBPEL_BITS 14 40 #define RS_SCALE_SUBPEL_MASK ((1 << RS_SCALE_SUBPEL_BITS) - 1) 41 #define RS_SCALE_EXTRA_BITS (RS_SCALE_SUBPEL_BITS - RS_SUBPEL_BITS) 42 #define RS_SCALE_EXTRA_OFF (1 << (RS_SCALE_EXTRA_BITS - 1)) 43 44 #define IS_INTRA(type) ((type == V4L2_AV1_KEY_FRAME) || (type == V4L2_AV1_INTRA_ONLY_FRAME)) 45 46 #define LST_BUF_IDX (V4L2_AV1_REF_LAST_FRAME - V4L2_AV1_REF_LAST_FRAME) 47 #define LST2_BUF_IDX (V4L2_AV1_REF_LAST2_FRAME - V4L2_AV1_REF_LAST_FRAME) 48 #define LST3_BUF_IDX (V4L2_AV1_REF_LAST3_FRAME - V4L2_AV1_REF_LAST_FRAME) 49 #define GLD_BUF_IDX (V4L2_AV1_REF_GOLDEN_FRAME - V4L2_AV1_REF_LAST_FRAME) 50 #define BWD_BUF_IDX (V4L2_AV1_REF_BWDREF_FRAME - V4L2_AV1_REF_LAST_FRAME) 51 #define ALT2_BUF_IDX (V4L2_AV1_REF_ALTREF2_FRAME - V4L2_AV1_REF_LAST_FRAME) 52 #define ALT_BUF_IDX (V4L2_AV1_REF_ALTREF_FRAME - V4L2_AV1_REF_LAST_FRAME) 53 54 #define DIV_LUT_PREC_BITS 14 55 #define DIV_LUT_BITS 8 56 #define DIV_LUT_NUM BIT(DIV_LUT_BITS) 57 #define WARP_PARAM_REDUCE_BITS 6 58 #define WARPEDMODEL_PREC_BITS 16 59 60 #define AV1_DIV_ROUND_UP_POW2(value, n) \ 61 ({ \ 62 typeof(n) _n = n; \ 63 typeof(value) _value = value; \ 64 (_value + (BIT(_n) >> 1)) >> _n; \ 65 }) 66 67 #define AV1_DIV_ROUND_UP_POW2_SIGNED(value, n) \ 68 ({ \ 69 typeof(n) _n_ = n; \ 70 typeof(value) _value_ = value; \ 71 (((_value_) < 0) ? -AV1_DIV_ROUND_UP_POW2(-(_value_), (_n_)) \ 72 : AV1_DIV_ROUND_UP_POW2((_value_), (_n_))); \ 73 }) 74 75 enum rockchip_av1_tx_mode { 76 ROCKCHIP_AV1_TX_MODE_ONLY_4X4 = 0, 77 ROCKCHIP_AV1_TX_MODE_8X8 = 1, 78 ROCKCHIP_AV1_TX_MODE_16x16 = 2, 79 ROCKCHIP_AV1_TX_MODE_32x32 = 3, 80 ROCKCHIP_AV1_TX_MODE_SELECT = 4, 81 }; 82 83 struct rockchip_av1_film_grain { 84 u8 scaling_lut_y[256]; 85 u8 scaling_lut_cb[256]; 86 u8 scaling_lut_cr[256]; 87 s16 cropped_luma_grain_block[4096]; 88 s16 cropped_chroma_grain_block[1024 * 2]; 89 }; 90 91 static const short div_lut[DIV_LUT_NUM + 1] = { 92 16384, 16320, 16257, 16194, 16132, 16070, 16009, 15948, 15888, 15828, 15768, 93 15709, 15650, 15592, 15534, 15477, 15420, 15364, 15308, 15252, 15197, 15142, 94 15087, 15033, 14980, 14926, 14873, 14821, 14769, 14717, 14665, 14614, 14564, 95 14513, 14463, 14413, 14364, 14315, 14266, 14218, 14170, 14122, 14075, 14028, 96 13981, 13935, 13888, 13843, 13797, 13752, 13707, 13662, 13618, 13574, 13530, 97 13487, 13443, 13400, 13358, 13315, 13273, 13231, 13190, 13148, 13107, 13066, 98 13026, 12985, 12945, 12906, 12866, 12827, 12788, 12749, 12710, 12672, 12633, 99 12596, 12558, 12520, 12483, 12446, 12409, 12373, 12336, 12300, 12264, 12228, 100 12193, 12157, 12122, 12087, 12053, 12018, 11984, 11950, 11916, 11882, 11848, 101 11815, 11782, 11749, 11716, 11683, 11651, 11619, 11586, 11555, 11523, 11491, 102 11460, 11429, 11398, 11367, 11336, 11305, 11275, 11245, 11215, 11185, 11155, 103 11125, 11096, 11067, 11038, 11009, 10980, 10951, 10923, 10894, 10866, 10838, 104 10810, 10782, 10755, 10727, 10700, 10673, 10645, 10618, 10592, 10565, 10538, 105 10512, 10486, 10460, 10434, 10408, 10382, 10356, 10331, 10305, 10280, 10255, 106 10230, 10205, 10180, 10156, 10131, 10107, 10082, 10058, 10034, 10010, 9986, 107 9963, 9939, 9916, 9892, 9869, 9846, 9823, 9800, 9777, 9754, 9732, 108 9709, 9687, 9664, 9642, 9620, 9598, 9576, 9554, 9533, 9511, 9489, 109 9468, 9447, 9425, 9404, 9383, 9362, 9341, 9321, 9300, 9279, 9259, 110 9239, 9218, 9198, 9178, 9158, 9138, 9118, 9098, 9079, 9059, 9039, 111 9020, 9001, 8981, 8962, 8943, 8924, 8905, 8886, 8867, 8849, 8830, 112 8812, 8793, 8775, 8756, 8738, 8720, 8702, 8684, 8666, 8648, 8630, 113 8613, 8595, 8577, 8560, 8542, 8525, 8508, 8490, 8473, 8456, 8439, 114 8422, 8405, 8389, 8372, 8355, 8339, 8322, 8306, 8289, 8273, 8257, 115 8240, 8224, 8208, 8192, 116 }; 117 118 static int rockchip_vpu981_get_frame_index(struct hantro_ctx *ctx, int ref) 119 { 120 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 121 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 122 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; 123 u64 timestamp; 124 int i, idx = frame->ref_frame_idx[ref]; 125 126 if (idx >= V4L2_AV1_TOTAL_REFS_PER_FRAME || idx < 0) 127 return AV1_INVALID_IDX; 128 129 timestamp = frame->reference_frame_ts[idx]; 130 for (i = 0; i < AV1_MAX_FRAME_BUF_COUNT; i++) { 131 if (!av1_dec->frame_refs[i].used) 132 continue; 133 if (av1_dec->frame_refs[i].timestamp == timestamp) 134 return i; 135 } 136 137 return AV1_INVALID_IDX; 138 } 139 140 static int rockchip_vpu981_get_order_hint(struct hantro_ctx *ctx, int ref) 141 { 142 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 143 int idx = rockchip_vpu981_get_frame_index(ctx, ref); 144 145 if (idx != AV1_INVALID_IDX) 146 return av1_dec->frame_refs[idx].order_hint; 147 148 return 0; 149 } 150 151 static int rockchip_vpu981_av1_dec_frame_ref(struct hantro_ctx *ctx, 152 u64 timestamp) 153 { 154 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 155 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 156 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; 157 int i; 158 159 for (i = 0; i < AV1_MAX_FRAME_BUF_COUNT; i++) { 160 int j; 161 162 if (av1_dec->frame_refs[i].used) 163 continue; 164 165 av1_dec->frame_refs[i].width = frame->frame_width_minus_1 + 1; 166 av1_dec->frame_refs[i].height = frame->frame_height_minus_1 + 1; 167 av1_dec->frame_refs[i].mi_cols = DIV_ROUND_UP(frame->frame_width_minus_1 + 1, 8); 168 av1_dec->frame_refs[i].mi_rows = DIV_ROUND_UP(frame->frame_height_minus_1 + 1, 8); 169 av1_dec->frame_refs[i].timestamp = timestamp; 170 av1_dec->frame_refs[i].frame_type = frame->frame_type; 171 av1_dec->frame_refs[i].order_hint = frame->order_hint; 172 av1_dec->frame_refs[i].vb2_ref = hantro_get_dst_buf(ctx); 173 174 for (j = 0; j < V4L2_AV1_TOTAL_REFS_PER_FRAME; j++) 175 av1_dec->frame_refs[i].order_hints[j] = frame->order_hints[j]; 176 av1_dec->frame_refs[i].used = true; 177 av1_dec->current_frame_index = i; 178 179 return i; 180 } 181 182 return AV1_INVALID_IDX; 183 } 184 185 static void rockchip_vpu981_av1_dec_frame_unref(struct hantro_ctx *ctx, int idx) 186 { 187 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 188 189 if (idx >= 0) 190 av1_dec->frame_refs[idx].used = false; 191 } 192 193 static void rockchip_vpu981_av1_dec_clean_refs(struct hantro_ctx *ctx) 194 { 195 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 196 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 197 198 int ref, idx; 199 200 for (idx = 0; idx < AV1_MAX_FRAME_BUF_COUNT; idx++) { 201 u64 timestamp = av1_dec->frame_refs[idx].timestamp; 202 bool used = false; 203 204 if (!av1_dec->frame_refs[idx].used) 205 continue; 206 207 for (ref = 0; ref < V4L2_AV1_TOTAL_REFS_PER_FRAME; ref++) { 208 if (ctrls->frame->reference_frame_ts[ref] == timestamp) 209 used = true; 210 } 211 212 if (!used) 213 rockchip_vpu981_av1_dec_frame_unref(ctx, idx); 214 } 215 } 216 217 static size_t rockchip_vpu981_av1_dec_luma_size(struct hantro_ctx *ctx) 218 { 219 return ctx->dst_fmt.width * ctx->dst_fmt.height * ctx->bit_depth / 8; 220 } 221 222 static size_t rockchip_vpu981_av1_dec_chroma_size(struct hantro_ctx *ctx) 223 { 224 size_t cr_offset = rockchip_vpu981_av1_dec_luma_size(ctx); 225 226 return ALIGN((cr_offset * 3) / 2, 64); 227 } 228 229 static void rockchip_vpu981_av1_dec_tiles_free(struct hantro_ctx *ctx) 230 { 231 struct hantro_dev *vpu = ctx->dev; 232 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 233 234 if (av1_dec->db_data_col.cpu) 235 dma_free_coherent(vpu->dev, av1_dec->db_data_col.size, 236 av1_dec->db_data_col.cpu, 237 av1_dec->db_data_col.dma); 238 av1_dec->db_data_col.cpu = NULL; 239 240 if (av1_dec->db_ctrl_col.cpu) 241 dma_free_coherent(vpu->dev, av1_dec->db_ctrl_col.size, 242 av1_dec->db_ctrl_col.cpu, 243 av1_dec->db_ctrl_col.dma); 244 av1_dec->db_ctrl_col.cpu = NULL; 245 246 if (av1_dec->cdef_col.cpu) 247 dma_free_coherent(vpu->dev, av1_dec->cdef_col.size, 248 av1_dec->cdef_col.cpu, av1_dec->cdef_col.dma); 249 av1_dec->cdef_col.cpu = NULL; 250 251 if (av1_dec->sr_col.cpu) 252 dma_free_coherent(vpu->dev, av1_dec->sr_col.size, 253 av1_dec->sr_col.cpu, av1_dec->sr_col.dma); 254 av1_dec->sr_col.cpu = NULL; 255 256 if (av1_dec->lr_col.cpu) 257 dma_free_coherent(vpu->dev, av1_dec->lr_col.size, 258 av1_dec->lr_col.cpu, av1_dec->lr_col.dma); 259 av1_dec->lr_col.cpu = NULL; 260 } 261 262 static int rockchip_vpu981_av1_dec_tiles_reallocate(struct hantro_ctx *ctx) 263 { 264 struct hantro_dev *vpu = ctx->dev; 265 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 266 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 267 const struct v4l2_av1_tile_info *tile_info = &ctrls->frame->tile_info; 268 unsigned int num_tile_cols = tile_info->tile_cols; 269 unsigned int height = ALIGN(ctrls->frame->frame_height_minus_1 + 1, 64); 270 unsigned int height_in_sb = height / 64; 271 unsigned int stripe_num = ((height + 8) + 63) / 64; 272 size_t size; 273 274 if (av1_dec->db_data_col.size >= 275 ALIGN(height * 12 * ctx->bit_depth / 8, 128) * num_tile_cols) 276 return 0; 277 278 rockchip_vpu981_av1_dec_tiles_free(ctx); 279 280 size = ALIGN(height * 12 * ctx->bit_depth / 8, 128) * num_tile_cols; 281 av1_dec->db_data_col.cpu = dma_alloc_coherent(vpu->dev, size, 282 &av1_dec->db_data_col.dma, 283 GFP_KERNEL); 284 if (!av1_dec->db_data_col.cpu) 285 goto buffer_allocation_error; 286 av1_dec->db_data_col.size = size; 287 288 size = ALIGN(height * 2 * 16 / 4, 128) * num_tile_cols; 289 av1_dec->db_ctrl_col.cpu = dma_alloc_coherent(vpu->dev, size, 290 &av1_dec->db_ctrl_col.dma, 291 GFP_KERNEL); 292 if (!av1_dec->db_ctrl_col.cpu) 293 goto buffer_allocation_error; 294 av1_dec->db_ctrl_col.size = size; 295 296 size = ALIGN(height_in_sb * 44 * ctx->bit_depth * 16 / 8, 128) * num_tile_cols; 297 av1_dec->cdef_col.cpu = dma_alloc_coherent(vpu->dev, size, 298 &av1_dec->cdef_col.dma, 299 GFP_KERNEL); 300 if (!av1_dec->cdef_col.cpu) 301 goto buffer_allocation_error; 302 av1_dec->cdef_col.size = size; 303 304 size = ALIGN(height_in_sb * (3040 + 1280), 128) * num_tile_cols; 305 av1_dec->sr_col.cpu = dma_alloc_coherent(vpu->dev, size, 306 &av1_dec->sr_col.dma, 307 GFP_KERNEL); 308 if (!av1_dec->sr_col.cpu) 309 goto buffer_allocation_error; 310 av1_dec->sr_col.size = size; 311 312 size = ALIGN(stripe_num * 1536 * ctx->bit_depth / 8, 128) * num_tile_cols; 313 av1_dec->lr_col.cpu = dma_alloc_coherent(vpu->dev, size, 314 &av1_dec->lr_col.dma, 315 GFP_KERNEL); 316 if (!av1_dec->lr_col.cpu) 317 goto buffer_allocation_error; 318 av1_dec->lr_col.size = size; 319 320 av1_dec->num_tile_cols_allocated = num_tile_cols; 321 return 0; 322 323 buffer_allocation_error: 324 rockchip_vpu981_av1_dec_tiles_free(ctx); 325 return -ENOMEM; 326 } 327 328 void rockchip_vpu981_av1_dec_exit(struct hantro_ctx *ctx) 329 { 330 struct hantro_dev *vpu = ctx->dev; 331 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 332 333 if (av1_dec->global_model.cpu) 334 dma_free_coherent(vpu->dev, av1_dec->global_model.size, 335 av1_dec->global_model.cpu, 336 av1_dec->global_model.dma); 337 av1_dec->global_model.cpu = NULL; 338 339 if (av1_dec->tile_info.cpu) 340 dma_free_coherent(vpu->dev, av1_dec->tile_info.size, 341 av1_dec->tile_info.cpu, 342 av1_dec->tile_info.dma); 343 av1_dec->tile_info.cpu = NULL; 344 345 if (av1_dec->film_grain.cpu) 346 dma_free_coherent(vpu->dev, av1_dec->film_grain.size, 347 av1_dec->film_grain.cpu, 348 av1_dec->film_grain.dma); 349 av1_dec->film_grain.cpu = NULL; 350 351 if (av1_dec->prob_tbl.cpu) 352 dma_free_coherent(vpu->dev, av1_dec->prob_tbl.size, 353 av1_dec->prob_tbl.cpu, av1_dec->prob_tbl.dma); 354 av1_dec->prob_tbl.cpu = NULL; 355 356 if (av1_dec->prob_tbl_out.cpu) 357 dma_free_coherent(vpu->dev, av1_dec->prob_tbl_out.size, 358 av1_dec->prob_tbl_out.cpu, 359 av1_dec->prob_tbl_out.dma); 360 av1_dec->prob_tbl_out.cpu = NULL; 361 362 if (av1_dec->tile_buf.cpu) 363 dma_free_coherent(vpu->dev, av1_dec->tile_buf.size, 364 av1_dec->tile_buf.cpu, av1_dec->tile_buf.dma); 365 av1_dec->tile_buf.cpu = NULL; 366 367 rockchip_vpu981_av1_dec_tiles_free(ctx); 368 } 369 370 int rockchip_vpu981_av1_dec_init(struct hantro_ctx *ctx) 371 { 372 int ret = 0; 373 struct hantro_dev *vpu = ctx->dev; 374 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 375 376 memset(av1_dec, 0, sizeof(*av1_dec)); 377 378 av1_dec->global_model.cpu = dma_alloc_coherent(vpu->dev, GLOBAL_MODEL_SIZE, 379 &av1_dec->global_model.dma, 380 GFP_KERNEL); 381 if (!av1_dec->global_model.cpu) { 382 ret = -ENOMEM; 383 goto global_model_cpu_err; 384 } 385 386 av1_dec->global_model.size = GLOBAL_MODEL_SIZE; 387 388 av1_dec->tile_info.cpu = dma_alloc_coherent(vpu->dev, AV1_TILE_INFO_SIZE, 389 &av1_dec->tile_info.dma, 390 GFP_KERNEL); 391 if (!av1_dec->tile_info.cpu) { 392 ret = -ENOMEM; 393 goto tile_info_cpu_err; 394 } 395 396 av1_dec->tile_info.size = AV1_TILE_INFO_SIZE; 397 398 av1_dec->film_grain.cpu = dma_alloc_coherent(vpu->dev, 399 ALIGN(sizeof(struct rockchip_av1_film_grain), 2048), 400 &av1_dec->film_grain.dma, 401 GFP_KERNEL); 402 if (!av1_dec->film_grain.cpu) { 403 ret = -ENOMEM; 404 goto film_grain_cpu_err; 405 } 406 407 av1_dec->film_grain.size = ALIGN(sizeof(struct rockchip_av1_film_grain), 2048); 408 409 av1_dec->prob_tbl.cpu = dma_alloc_coherent(vpu->dev, 410 ALIGN(sizeof(struct av1cdfs), 2048), 411 &av1_dec->prob_tbl.dma, 412 GFP_KERNEL); 413 if (!av1_dec->prob_tbl.cpu) { 414 ret = -ENOMEM; 415 goto prob_tbl_cpu_err; 416 } 417 418 av1_dec->prob_tbl.size = ALIGN(sizeof(struct av1cdfs), 2048); 419 420 av1_dec->prob_tbl_out.cpu = dma_alloc_coherent(vpu->dev, 421 ALIGN(sizeof(struct av1cdfs), 2048), 422 &av1_dec->prob_tbl_out.dma, 423 GFP_KERNEL); 424 if (!av1_dec->prob_tbl_out.cpu) { 425 ret = -ENOMEM; 426 goto prob_tbl_out_cpu_err; 427 } 428 429 av1_dec->prob_tbl_out.size = ALIGN(sizeof(struct av1cdfs), 2048); 430 av1_dec->cdfs = &av1_dec->default_cdfs; 431 av1_dec->cdfs_ndvc = &av1_dec->default_cdfs_ndvc; 432 433 rockchip_av1_set_default_cdfs(av1_dec->cdfs, av1_dec->cdfs_ndvc); 434 435 av1_dec->tile_buf.cpu = dma_alloc_coherent(vpu->dev, 436 AV1_TILE_SIZE, 437 &av1_dec->tile_buf.dma, 438 GFP_KERNEL); 439 if (!av1_dec->tile_buf.cpu) { 440 ret = -ENOMEM; 441 goto tile_buf_cpu_err; 442 } 443 444 av1_dec->tile_buf.size = AV1_TILE_SIZE; 445 446 return ret; 447 448 tile_buf_cpu_err: 449 dma_free_coherent(vpu->dev, av1_dec->prob_tbl_out.size, 450 av1_dec->prob_tbl_out.cpu, 451 av1_dec->prob_tbl_out.dma); 452 prob_tbl_out_cpu_err: 453 dma_free_coherent(vpu->dev, av1_dec->prob_tbl.size, 454 av1_dec->prob_tbl.cpu, 455 av1_dec->prob_tbl.dma); 456 prob_tbl_cpu_err: 457 dma_free_coherent(vpu->dev, av1_dec->film_grain.size, 458 av1_dec->film_grain.cpu, 459 av1_dec->film_grain.dma); 460 film_grain_cpu_err: 461 dma_free_coherent(vpu->dev, av1_dec->tile_info.size, 462 av1_dec->tile_info.cpu, 463 av1_dec->tile_info.dma); 464 tile_info_cpu_err: 465 dma_free_coherent(vpu->dev, av1_dec->global_model.size, 466 av1_dec->global_model.cpu, 467 av1_dec->global_model.dma); 468 global_model_cpu_err: 469 return ret; 470 } 471 472 static int rockchip_vpu981_av1_dec_prepare_run(struct hantro_ctx *ctx) 473 { 474 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 475 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 476 const struct v4l2_av1_tile_info *tile_info; 477 struct v4l2_ctrl *tge; 478 u32 num_tiles; 479 480 ctrls->sequence = hantro_get_ctrl(ctx, V4L2_CID_STATELESS_AV1_SEQUENCE); 481 if (WARN_ON(!ctrls->sequence)) 482 return -EINVAL; 483 484 tge = v4l2_ctrl_find(&ctx->ctrl_handler, 485 V4L2_CID_STATELESS_AV1_TILE_GROUP_ENTRY); 486 if (WARN_ON(!tge)) 487 return -EINVAL; 488 ctrls->tile_group_entry = tge->p_cur.p; 489 490 ctrls->frame = hantro_get_ctrl(ctx, V4L2_CID_STATELESS_AV1_FRAME); 491 if (WARN_ON(!ctrls->frame)) 492 return -EINVAL; 493 494 /* 495 * rockchip_vpu981_av1_dec_set_tile_info() indexes the tile group 496 * entry array by tile1 * tile_cols + tile0, so it reads up to 497 * tile_cols * tile_rows entries, and lays out one descriptor per tile 498 * in the AV1_MAX_TILES tile_info buffer while programming the real 499 * tile geometry into the hardware. Reject a frame that claims more 500 * tiles than userspace submitted, or more than the hardware tile 501 * buffer holds, so the read stays in bounds and the programmed 502 * geometry matches the descriptors written. 503 */ 504 tile_info = &ctrls->frame->tile_info; 505 num_tiles = (u32)tile_info->tile_cols * tile_info->tile_rows; 506 if (num_tiles > tge->elems || num_tiles > AV1_MAX_TILES) 507 return -EINVAL; 508 509 ctrls->film_grain = 510 hantro_get_ctrl(ctx, V4L2_CID_STATELESS_AV1_FILM_GRAIN); 511 512 return rockchip_vpu981_av1_dec_tiles_reallocate(ctx); 513 } 514 515 static inline int rockchip_vpu981_av1_dec_get_msb(u32 n) 516 { 517 if (n == 0) 518 return 0; 519 return 31 ^ __builtin_clz(n); 520 } 521 522 static short rockchip_vpu981_av1_dec_resolve_divisor_32(u32 d, short *shift) 523 { 524 int f; 525 u64 e; 526 527 *shift = rockchip_vpu981_av1_dec_get_msb(d); 528 /* e is obtained from D after resetting the most significant 1 bit. */ 529 e = d - ((u32)1 << *shift); 530 /* Get the most significant DIV_LUT_BITS (8) bits of e into f */ 531 if (*shift > DIV_LUT_BITS) 532 f = AV1_DIV_ROUND_UP_POW2(e, *shift - DIV_LUT_BITS); 533 else 534 f = e << (DIV_LUT_BITS - *shift); 535 if (f > DIV_LUT_NUM) 536 return -1; 537 *shift += DIV_LUT_PREC_BITS; 538 /* Use f as lookup into the precomputed table of multipliers */ 539 return div_lut[f]; 540 } 541 542 static void 543 rockchip_vpu981_av1_dec_get_shear_params(const u32 *params, s64 *alpha, 544 s64 *beta, s64 *gamma, s64 *delta) 545 { 546 const int *mat = params; 547 short shift; 548 short y; 549 long long gv, dv; 550 551 if (mat[2] <= 0) 552 return; 553 554 *alpha = clamp_val(mat[2] - (1 << WARPEDMODEL_PREC_BITS), S16_MIN, S16_MAX); 555 *beta = clamp_val(mat[3], S16_MIN, S16_MAX); 556 557 y = rockchip_vpu981_av1_dec_resolve_divisor_32(abs(mat[2]), &shift) * (mat[2] < 0 ? -1 : 1); 558 559 gv = ((long long)mat[4] * (1 << WARPEDMODEL_PREC_BITS)) * y; 560 561 *gamma = clamp_val((int)AV1_DIV_ROUND_UP_POW2_SIGNED(gv, shift), S16_MIN, S16_MAX); 562 563 dv = ((long long)mat[3] * mat[4]) * y; 564 *delta = clamp_val(mat[5] - 565 (int)AV1_DIV_ROUND_UP_POW2_SIGNED(dv, shift) - (1 << WARPEDMODEL_PREC_BITS), 566 S16_MIN, S16_MAX); 567 568 *alpha = AV1_DIV_ROUND_UP_POW2_SIGNED(*alpha, WARP_PARAM_REDUCE_BITS) 569 * (1 << WARP_PARAM_REDUCE_BITS); 570 *beta = AV1_DIV_ROUND_UP_POW2_SIGNED(*beta, WARP_PARAM_REDUCE_BITS) 571 * (1 << WARP_PARAM_REDUCE_BITS); 572 *gamma = AV1_DIV_ROUND_UP_POW2_SIGNED(*gamma, WARP_PARAM_REDUCE_BITS) 573 * (1 << WARP_PARAM_REDUCE_BITS); 574 *delta = AV1_DIV_ROUND_UP_POW2_SIGNED(*delta, WARP_PARAM_REDUCE_BITS) 575 * (1 << WARP_PARAM_REDUCE_BITS); 576 } 577 578 static void rockchip_vpu981_av1_dec_set_global_model(struct hantro_ctx *ctx) 579 { 580 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 581 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 582 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; 583 const struct v4l2_av1_global_motion *gm = &frame->global_motion; 584 u8 *dst = av1_dec->global_model.cpu; 585 struct hantro_dev *vpu = ctx->dev; 586 int ref_frame, i; 587 588 memset(dst, 0, GLOBAL_MODEL_SIZE); 589 for (ref_frame = 0; ref_frame < V4L2_AV1_REFS_PER_FRAME; ++ref_frame) { 590 s64 alpha = 0, beta = 0, gamma = 0, delta = 0; 591 592 for (i = 0; i < 6; ++i) { 593 if (i == 2) 594 *(s32 *)dst = 595 gm->params[V4L2_AV1_REF_LAST_FRAME + ref_frame][3]; 596 else if (i == 3) 597 *(s32 *)dst = 598 gm->params[V4L2_AV1_REF_LAST_FRAME + ref_frame][2]; 599 else 600 *(s32 *)dst = 601 gm->params[V4L2_AV1_REF_LAST_FRAME + ref_frame][i]; 602 dst += 4; 603 } 604 605 if (gm->type[V4L2_AV1_REF_LAST_FRAME + ref_frame] <= V4L2_AV1_WARP_MODEL_AFFINE) 606 rockchip_vpu981_av1_dec_get_shear_params(&gm->params[V4L2_AV1_REF_LAST_FRAME + ref_frame][0], 607 &alpha, &beta, &gamma, &delta); 608 609 *(s16 *)dst = alpha; 610 dst += 2; 611 *(s16 *)dst = beta; 612 dst += 2; 613 *(s16 *)dst = gamma; 614 dst += 2; 615 *(s16 *)dst = delta; 616 dst += 2; 617 } 618 619 hantro_write_addr(vpu, AV1_GLOBAL_MODEL, av1_dec->global_model.dma); 620 } 621 622 static int rockchip_vpu981_av1_tile_log2(int target) 623 { 624 int k; 625 626 /* 627 * returns the smallest value for k such that 1 << k is greater 628 * than or equal to target 629 */ 630 for (k = 0; (1 << k) < target; k++); 631 632 return k; 633 } 634 635 static void rockchip_vpu981_av1_dec_set_tile_info(struct hantro_ctx *ctx) 636 { 637 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 638 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 639 const struct v4l2_av1_tile_info *tile_info = &ctrls->frame->tile_info; 640 const struct v4l2_ctrl_av1_tile_group_entry *group_entry = 641 ctrls->tile_group_entry; 642 int context_update_y = 0; 643 int context_update_x = 0; 644 int context_update_tile_id = 0; 645 u8 *dst = av1_dec->tile_info.cpu; 646 u8 *dst_end = dst + av1_dec->tile_info.size; 647 struct hantro_dev *vpu = ctx->dev; 648 int tile0, tile1; 649 650 /* 651 * tile_cols and tile_rows are bounded by the V4L2 control validation 652 * (V4L2_AV1_MAX_TILE_{COLS,ROWS} and V4L2_AV1_MAX_TILE_COUNT). Guard 653 * the divisor here, and keep the descriptor writes within the 654 * AV1_MAX_TILES tile_info buffer below; the register values use the 655 * unmodified tile geometry. 656 */ 657 if (tile_info->tile_cols) { 658 context_update_y = 659 tile_info->context_update_tile_id / tile_info->tile_cols; 660 context_update_x = 661 tile_info->context_update_tile_id % tile_info->tile_cols; 662 context_update_tile_id = 663 context_update_x * tile_info->tile_rows + context_update_y; 664 } 665 666 memset(dst, 0, av1_dec->tile_info.size); 667 668 for (tile0 = 0; tile0 < tile_info->tile_cols; tile0++) { 669 for (tile1 = 0; tile1 < tile_info->tile_rows; tile1++) { 670 int tile_id = tile1 * tile_info->tile_cols + tile0; 671 u32 start, end; 672 u32 y0 = 673 tile_info->height_in_sbs_minus_1[tile1] + 1; 674 u32 x0 = tile_info->width_in_sbs_minus_1[tile0] + 1; 675 676 /* Stop once the tile_info descriptor buffer is full. */ 677 if (dst + 16 > dst_end) 678 break; 679 680 /* tile size in SB units (width,height) */ 681 *dst++ = x0; 682 *dst++ = 0; 683 *dst++ = 0; 684 *dst++ = 0; 685 *dst++ = y0; 686 *dst++ = 0; 687 *dst++ = 0; 688 *dst++ = 0; 689 690 /* tile start position */ 691 start = group_entry[tile_id].tile_offset - group_entry[0].tile_offset; 692 *dst++ = start & 255; 693 *dst++ = (start >> 8) & 255; 694 *dst++ = (start >> 16) & 255; 695 *dst++ = (start >> 24) & 255; 696 697 /* number of bytes in tile data */ 698 end = start + group_entry[tile_id].tile_size; 699 *dst++ = end & 255; 700 *dst++ = (end >> 8) & 255; 701 *dst++ = (end >> 16) & 255; 702 *dst++ = (end >> 24) & 255; 703 } 704 if (dst + 16 > dst_end) 705 break; 706 } 707 708 hantro_reg_write(vpu, &av1_multicore_expect_context_update, !!(context_update_x == 0)); 709 hantro_reg_write(vpu, &av1_tile_enable, 710 !!((tile_info->tile_cols > 1) || (tile_info->tile_rows > 1))); 711 hantro_reg_write(vpu, &av1_num_tile_cols_8k, tile_info->tile_cols); 712 hantro_reg_write(vpu, &av1_num_tile_rows_8k, tile_info->tile_rows); 713 hantro_reg_write(vpu, &av1_context_update_tile_id, context_update_tile_id); 714 hantro_reg_write(vpu, &av1_tile_transpose, 1); 715 if (rockchip_vpu981_av1_tile_log2(tile_info->tile_cols) || 716 rockchip_vpu981_av1_tile_log2(tile_info->tile_rows)) 717 hantro_reg_write(vpu, &av1_dec_tile_size_mag, tile_info->tile_size_bytes - 1); 718 else 719 hantro_reg_write(vpu, &av1_dec_tile_size_mag, 3); 720 721 hantro_write_addr(vpu, AV1_TILE_BASE, av1_dec->tile_info.dma); 722 } 723 724 static int rockchip_vpu981_av1_dec_get_dist(struct hantro_ctx *ctx, 725 int a, int b) 726 { 727 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 728 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 729 int bits = ctrls->sequence->order_hint_bits - 1; 730 int diff, m; 731 732 if (!ctrls->sequence->order_hint_bits) 733 return 0; 734 735 diff = a - b; 736 m = 1 << bits; 737 diff = (diff & (m - 1)) - (diff & m); 738 739 return diff; 740 } 741 742 static void rockchip_vpu981_av1_dec_set_frame_sign_bias(struct hantro_ctx *ctx) 743 { 744 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 745 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 746 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; 747 const struct v4l2_ctrl_av1_sequence *sequence = ctrls->sequence; 748 int i; 749 750 if (!sequence->order_hint_bits || IS_INTRA(frame->frame_type)) { 751 for (i = 0; i < V4L2_AV1_TOTAL_REFS_PER_FRAME; i++) 752 av1_dec->ref_frame_sign_bias[i] = 0; 753 754 return; 755 } 756 // Identify the nearest forward and backward references. 757 for (i = 0; i < V4L2_AV1_TOTAL_REFS_PER_FRAME - 1; i++) { 758 if (rockchip_vpu981_get_frame_index(ctx, i) >= 0) { 759 int rel_off = 760 rockchip_vpu981_av1_dec_get_dist(ctx, 761 rockchip_vpu981_get_order_hint(ctx, i), 762 frame->order_hint); 763 av1_dec->ref_frame_sign_bias[i + 1] = (rel_off <= 0) ? 0 : 1; 764 } 765 } 766 } 767 768 static bool 769 rockchip_vpu981_av1_dec_set_ref(struct hantro_ctx *ctx, int ref, int idx, 770 int width, int height) 771 { 772 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 773 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 774 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; 775 struct hantro_dev *vpu = ctx->dev; 776 struct hantro_decoded_buffer *dst; 777 dma_addr_t luma_addr, chroma_addr, mv_addr = 0; 778 int cur_width = frame->frame_width_minus_1 + 1; 779 int cur_height = frame->frame_height_minus_1 + 1; 780 int scale_width = 781 ((width << AV1_REF_SCALE_SHIFT) + cur_width / 2) / cur_width; 782 int scale_height = 783 ((height << AV1_REF_SCALE_SHIFT) + cur_height / 2) / cur_height; 784 785 switch (ref) { 786 case 0: 787 hantro_reg_write(vpu, &av1_ref0_height, height); 788 hantro_reg_write(vpu, &av1_ref0_width, width); 789 hantro_reg_write(vpu, &av1_ref0_ver_scale, scale_width); 790 hantro_reg_write(vpu, &av1_ref0_hor_scale, scale_height); 791 break; 792 case 1: 793 hantro_reg_write(vpu, &av1_ref1_height, height); 794 hantro_reg_write(vpu, &av1_ref1_width, width); 795 hantro_reg_write(vpu, &av1_ref1_ver_scale, scale_width); 796 hantro_reg_write(vpu, &av1_ref1_hor_scale, scale_height); 797 break; 798 case 2: 799 hantro_reg_write(vpu, &av1_ref2_height, height); 800 hantro_reg_write(vpu, &av1_ref2_width, width); 801 hantro_reg_write(vpu, &av1_ref2_ver_scale, scale_width); 802 hantro_reg_write(vpu, &av1_ref2_hor_scale, scale_height); 803 break; 804 case 3: 805 hantro_reg_write(vpu, &av1_ref3_height, height); 806 hantro_reg_write(vpu, &av1_ref3_width, width); 807 hantro_reg_write(vpu, &av1_ref3_ver_scale, scale_width); 808 hantro_reg_write(vpu, &av1_ref3_hor_scale, scale_height); 809 break; 810 case 4: 811 hantro_reg_write(vpu, &av1_ref4_height, height); 812 hantro_reg_write(vpu, &av1_ref4_width, width); 813 hantro_reg_write(vpu, &av1_ref4_ver_scale, scale_width); 814 hantro_reg_write(vpu, &av1_ref4_hor_scale, scale_height); 815 break; 816 case 5: 817 hantro_reg_write(vpu, &av1_ref5_height, height); 818 hantro_reg_write(vpu, &av1_ref5_width, width); 819 hantro_reg_write(vpu, &av1_ref5_ver_scale, scale_width); 820 hantro_reg_write(vpu, &av1_ref5_hor_scale, scale_height); 821 break; 822 case 6: 823 hantro_reg_write(vpu, &av1_ref6_height, height); 824 hantro_reg_write(vpu, &av1_ref6_width, width); 825 hantro_reg_write(vpu, &av1_ref6_ver_scale, scale_width); 826 hantro_reg_write(vpu, &av1_ref6_hor_scale, scale_height); 827 break; 828 default: 829 pr_warn("AV1 invalid reference frame index\n"); 830 } 831 832 dst = vb2_to_hantro_decoded_buf(&av1_dec->frame_refs[idx].vb2_ref->vb2_buf); 833 luma_addr = hantro_get_dec_buf_addr(ctx, &dst->base.vb.vb2_buf); 834 chroma_addr = luma_addr + dst->av1.chroma_offset; 835 mv_addr = luma_addr + dst->av1.mv_offset; 836 837 hantro_write_addr(vpu, AV1_REFERENCE_Y(ref), luma_addr); 838 hantro_write_addr(vpu, AV1_REFERENCE_CB(ref), chroma_addr); 839 hantro_write_addr(vpu, AV1_REFERENCE_MV(ref), mv_addr); 840 841 return (scale_width != (1 << AV1_REF_SCALE_SHIFT)) || 842 (scale_height != (1 << AV1_REF_SCALE_SHIFT)); 843 } 844 845 static void rockchip_vpu981_av1_dec_set_sign_bias(struct hantro_ctx *ctx, 846 int ref, int val) 847 { 848 struct hantro_dev *vpu = ctx->dev; 849 850 switch (ref) { 851 case 0: 852 hantro_reg_write(vpu, &av1_ref0_sign_bias, val); 853 break; 854 case 1: 855 hantro_reg_write(vpu, &av1_ref1_sign_bias, val); 856 break; 857 case 2: 858 hantro_reg_write(vpu, &av1_ref2_sign_bias, val); 859 break; 860 case 3: 861 hantro_reg_write(vpu, &av1_ref3_sign_bias, val); 862 break; 863 case 4: 864 hantro_reg_write(vpu, &av1_ref4_sign_bias, val); 865 break; 866 case 5: 867 hantro_reg_write(vpu, &av1_ref5_sign_bias, val); 868 break; 869 case 6: 870 hantro_reg_write(vpu, &av1_ref6_sign_bias, val); 871 break; 872 default: 873 pr_warn("AV1 invalid sign bias index\n"); 874 break; 875 } 876 } 877 878 static void rockchip_vpu981_av1_dec_set_segmentation(struct hantro_ctx *ctx) 879 { 880 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 881 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 882 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; 883 const struct v4l2_av1_segmentation *seg = &frame->segmentation; 884 u32 segval[V4L2_AV1_MAX_SEGMENTS][V4L2_AV1_SEG_LVL_MAX] = { 0 }; 885 struct hantro_dev *vpu = ctx->dev; 886 u8 segsign = 0, preskip_segid = 0, last_active_seg = 0, i, j; 887 888 if (!!(seg->flags & V4L2_AV1_SEGMENTATION_FLAG_ENABLED) && 889 frame->primary_ref_frame < V4L2_AV1_REFS_PER_FRAME) { 890 int idx = rockchip_vpu981_get_frame_index(ctx, frame->primary_ref_frame); 891 892 if (idx >= 0) { 893 dma_addr_t luma_addr, mv_addr = 0; 894 struct hantro_decoded_buffer *seg; 895 size_t mv_offset = rockchip_vpu981_av1_dec_chroma_size(ctx); 896 897 seg = vb2_to_hantro_decoded_buf(&av1_dec->frame_refs[idx].vb2_ref->vb2_buf); 898 luma_addr = hantro_get_dec_buf_addr(ctx, &seg->base.vb.vb2_buf); 899 mv_addr = luma_addr + mv_offset; 900 901 hantro_write_addr(vpu, AV1_SEGMENTATION, mv_addr); 902 hantro_reg_write(vpu, &av1_use_temporal3_mvs, 1); 903 } 904 } 905 906 hantro_reg_write(vpu, &av1_segment_temp_upd_e, 907 !!(seg->flags & V4L2_AV1_SEGMENTATION_FLAG_TEMPORAL_UPDATE)); 908 hantro_reg_write(vpu, &av1_segment_upd_e, 909 !!(seg->flags & V4L2_AV1_SEGMENTATION_FLAG_UPDATE_MAP)); 910 hantro_reg_write(vpu, &av1_segment_e, 911 !!(seg->flags & V4L2_AV1_SEGMENTATION_FLAG_ENABLED)); 912 913 hantro_reg_write(vpu, &av1_error_resilient, 914 !!(frame->flags & V4L2_AV1_FRAME_FLAG_ERROR_RESILIENT_MODE)); 915 916 if (IS_INTRA(frame->frame_type) || 917 !!(frame->flags & V4L2_AV1_FRAME_FLAG_ERROR_RESILIENT_MODE)) { 918 hantro_reg_write(vpu, &av1_use_temporal3_mvs, 0); 919 } 920 921 if (seg->flags & V4L2_AV1_SEGMENTATION_FLAG_ENABLED) { 922 int s; 923 924 for (s = 0; s < V4L2_AV1_MAX_SEGMENTS; s++) { 925 if (seg->feature_enabled[s] & 926 V4L2_AV1_SEGMENT_FEATURE_ENABLED(V4L2_AV1_SEG_LVL_ALT_Q)) { 927 segval[s][V4L2_AV1_SEG_LVL_ALT_Q] = 928 clamp(abs(seg->feature_data[s][V4L2_AV1_SEG_LVL_ALT_Q]), 929 0, 255); 930 segsign |= 931 (seg->feature_data[s][V4L2_AV1_SEG_LVL_ALT_Q] < 0) << s; 932 } 933 934 if (seg->feature_enabled[s] & 935 V4L2_AV1_SEGMENT_FEATURE_ENABLED(V4L2_AV1_SEG_LVL_ALT_LF_Y_V)) 936 segval[s][V4L2_AV1_SEG_LVL_ALT_LF_Y_V] = 937 clamp(abs(seg->feature_data[s][V4L2_AV1_SEG_LVL_ALT_LF_Y_V]), 938 -63, 63); 939 940 if (seg->feature_enabled[s] & 941 V4L2_AV1_SEGMENT_FEATURE_ENABLED(V4L2_AV1_SEG_LVL_ALT_LF_Y_H)) 942 segval[s][V4L2_AV1_SEG_LVL_ALT_LF_Y_H] = 943 clamp(abs(seg->feature_data[s][V4L2_AV1_SEG_LVL_ALT_LF_Y_H]), 944 -63, 63); 945 946 if (seg->feature_enabled[s] & 947 V4L2_AV1_SEGMENT_FEATURE_ENABLED(V4L2_AV1_SEG_LVL_ALT_LF_U)) 948 segval[s][V4L2_AV1_SEG_LVL_ALT_LF_U] = 949 clamp(abs(seg->feature_data[s][V4L2_AV1_SEG_LVL_ALT_LF_U]), 950 -63, 63); 951 952 if (seg->feature_enabled[s] & 953 V4L2_AV1_SEGMENT_FEATURE_ENABLED(V4L2_AV1_SEG_LVL_ALT_LF_V)) 954 segval[s][V4L2_AV1_SEG_LVL_ALT_LF_V] = 955 clamp(abs(seg->feature_data[s][V4L2_AV1_SEG_LVL_ALT_LF_V]), 956 -63, 63); 957 958 if (frame->frame_type && seg->feature_enabled[s] & 959 V4L2_AV1_SEGMENT_FEATURE_ENABLED(V4L2_AV1_SEG_LVL_REF_FRAME)) 960 segval[s][V4L2_AV1_SEG_LVL_REF_FRAME]++; 961 962 if (seg->feature_enabled[s] & 963 V4L2_AV1_SEGMENT_FEATURE_ENABLED(V4L2_AV1_SEG_LVL_REF_SKIP)) 964 segval[s][V4L2_AV1_SEG_LVL_REF_SKIP] = 1; 965 966 if (seg->feature_enabled[s] & 967 V4L2_AV1_SEGMENT_FEATURE_ENABLED(V4L2_AV1_SEG_LVL_REF_GLOBALMV)) 968 segval[s][V4L2_AV1_SEG_LVL_REF_GLOBALMV] = 1; 969 } 970 } 971 972 for (i = 0; i < V4L2_AV1_MAX_SEGMENTS; i++) { 973 for (j = 0; j < V4L2_AV1_SEG_LVL_MAX; j++) { 974 if (seg->feature_enabled[i] 975 & V4L2_AV1_SEGMENT_FEATURE_ENABLED(j)) { 976 preskip_segid |= (j >= V4L2_AV1_SEG_LVL_REF_FRAME); 977 last_active_seg = max(i, last_active_seg); 978 } 979 } 980 } 981 982 hantro_reg_write(vpu, &av1_last_active_seg, last_active_seg); 983 hantro_reg_write(vpu, &av1_preskip_segid, preskip_segid); 984 985 hantro_reg_write(vpu, &av1_seg_quant_sign, segsign); 986 987 /* Write QP, filter level, ref frame and skip for every segment */ 988 hantro_reg_write(vpu, &av1_quant_seg0, 989 segval[0][V4L2_AV1_SEG_LVL_ALT_Q]); 990 hantro_reg_write(vpu, &av1_filt_level_delta0_seg0, 991 segval[0][V4L2_AV1_SEG_LVL_ALT_LF_Y_V]); 992 hantro_reg_write(vpu, &av1_filt_level_delta1_seg0, 993 segval[0][V4L2_AV1_SEG_LVL_ALT_LF_Y_H]); 994 hantro_reg_write(vpu, &av1_filt_level_delta2_seg0, 995 segval[0][V4L2_AV1_SEG_LVL_ALT_LF_U]); 996 hantro_reg_write(vpu, &av1_filt_level_delta3_seg0, 997 segval[0][V4L2_AV1_SEG_LVL_ALT_LF_V]); 998 hantro_reg_write(vpu, &av1_refpic_seg0, 999 segval[0][V4L2_AV1_SEG_LVL_REF_FRAME]); 1000 hantro_reg_write(vpu, &av1_skip_seg0, 1001 segval[0][V4L2_AV1_SEG_LVL_REF_SKIP]); 1002 hantro_reg_write(vpu, &av1_global_mv_seg0, 1003 segval[0][V4L2_AV1_SEG_LVL_REF_GLOBALMV]); 1004 1005 hantro_reg_write(vpu, &av1_quant_seg1, 1006 segval[1][V4L2_AV1_SEG_LVL_ALT_Q]); 1007 hantro_reg_write(vpu, &av1_filt_level_delta0_seg1, 1008 segval[1][V4L2_AV1_SEG_LVL_ALT_LF_Y_V]); 1009 hantro_reg_write(vpu, &av1_filt_level_delta1_seg1, 1010 segval[1][V4L2_AV1_SEG_LVL_ALT_LF_Y_H]); 1011 hantro_reg_write(vpu, &av1_filt_level_delta2_seg1, 1012 segval[1][V4L2_AV1_SEG_LVL_ALT_LF_U]); 1013 hantro_reg_write(vpu, &av1_filt_level_delta3_seg1, 1014 segval[1][V4L2_AV1_SEG_LVL_ALT_LF_V]); 1015 hantro_reg_write(vpu, &av1_refpic_seg1, 1016 segval[1][V4L2_AV1_SEG_LVL_REF_FRAME]); 1017 hantro_reg_write(vpu, &av1_skip_seg1, 1018 segval[1][V4L2_AV1_SEG_LVL_REF_SKIP]); 1019 hantro_reg_write(vpu, &av1_global_mv_seg1, 1020 segval[1][V4L2_AV1_SEG_LVL_REF_GLOBALMV]); 1021 1022 hantro_reg_write(vpu, &av1_quant_seg2, 1023 segval[2][V4L2_AV1_SEG_LVL_ALT_Q]); 1024 hantro_reg_write(vpu, &av1_filt_level_delta0_seg2, 1025 segval[2][V4L2_AV1_SEG_LVL_ALT_LF_Y_V]); 1026 hantro_reg_write(vpu, &av1_filt_level_delta1_seg2, 1027 segval[2][V4L2_AV1_SEG_LVL_ALT_LF_Y_H]); 1028 hantro_reg_write(vpu, &av1_filt_level_delta2_seg2, 1029 segval[2][V4L2_AV1_SEG_LVL_ALT_LF_U]); 1030 hantro_reg_write(vpu, &av1_filt_level_delta3_seg2, 1031 segval[2][V4L2_AV1_SEG_LVL_ALT_LF_V]); 1032 hantro_reg_write(vpu, &av1_refpic_seg2, 1033 segval[2][V4L2_AV1_SEG_LVL_REF_FRAME]); 1034 hantro_reg_write(vpu, &av1_skip_seg2, 1035 segval[2][V4L2_AV1_SEG_LVL_REF_SKIP]); 1036 hantro_reg_write(vpu, &av1_global_mv_seg2, 1037 segval[2][V4L2_AV1_SEG_LVL_REF_GLOBALMV]); 1038 1039 hantro_reg_write(vpu, &av1_quant_seg3, 1040 segval[3][V4L2_AV1_SEG_LVL_ALT_Q]); 1041 hantro_reg_write(vpu, &av1_filt_level_delta0_seg3, 1042 segval[3][V4L2_AV1_SEG_LVL_ALT_LF_Y_V]); 1043 hantro_reg_write(vpu, &av1_filt_level_delta1_seg3, 1044 segval[3][V4L2_AV1_SEG_LVL_ALT_LF_Y_H]); 1045 hantro_reg_write(vpu, &av1_filt_level_delta2_seg3, 1046 segval[3][V4L2_AV1_SEG_LVL_ALT_LF_U]); 1047 hantro_reg_write(vpu, &av1_filt_level_delta3_seg3, 1048 segval[3][V4L2_AV1_SEG_LVL_ALT_LF_V]); 1049 hantro_reg_write(vpu, &av1_refpic_seg3, 1050 segval[3][V4L2_AV1_SEG_LVL_REF_FRAME]); 1051 hantro_reg_write(vpu, &av1_skip_seg3, 1052 segval[3][V4L2_AV1_SEG_LVL_REF_SKIP]); 1053 hantro_reg_write(vpu, &av1_global_mv_seg3, 1054 segval[3][V4L2_AV1_SEG_LVL_REF_GLOBALMV]); 1055 1056 hantro_reg_write(vpu, &av1_quant_seg4, 1057 segval[4][V4L2_AV1_SEG_LVL_ALT_Q]); 1058 hantro_reg_write(vpu, &av1_filt_level_delta0_seg4, 1059 segval[4][V4L2_AV1_SEG_LVL_ALT_LF_Y_V]); 1060 hantro_reg_write(vpu, &av1_filt_level_delta1_seg4, 1061 segval[4][V4L2_AV1_SEG_LVL_ALT_LF_Y_H]); 1062 hantro_reg_write(vpu, &av1_filt_level_delta2_seg4, 1063 segval[4][V4L2_AV1_SEG_LVL_ALT_LF_U]); 1064 hantro_reg_write(vpu, &av1_filt_level_delta3_seg4, 1065 segval[4][V4L2_AV1_SEG_LVL_ALT_LF_V]); 1066 hantro_reg_write(vpu, &av1_refpic_seg4, 1067 segval[4][V4L2_AV1_SEG_LVL_REF_FRAME]); 1068 hantro_reg_write(vpu, &av1_skip_seg4, 1069 segval[4][V4L2_AV1_SEG_LVL_REF_SKIP]); 1070 hantro_reg_write(vpu, &av1_global_mv_seg4, 1071 segval[4][V4L2_AV1_SEG_LVL_REF_GLOBALMV]); 1072 1073 hantro_reg_write(vpu, &av1_quant_seg5, 1074 segval[5][V4L2_AV1_SEG_LVL_ALT_Q]); 1075 hantro_reg_write(vpu, &av1_filt_level_delta0_seg5, 1076 segval[5][V4L2_AV1_SEG_LVL_ALT_LF_Y_V]); 1077 hantro_reg_write(vpu, &av1_filt_level_delta1_seg5, 1078 segval[5][V4L2_AV1_SEG_LVL_ALT_LF_Y_H]); 1079 hantro_reg_write(vpu, &av1_filt_level_delta2_seg5, 1080 segval[5][V4L2_AV1_SEG_LVL_ALT_LF_U]); 1081 hantro_reg_write(vpu, &av1_filt_level_delta3_seg5, 1082 segval[5][V4L2_AV1_SEG_LVL_ALT_LF_V]); 1083 hantro_reg_write(vpu, &av1_refpic_seg5, 1084 segval[5][V4L2_AV1_SEG_LVL_REF_FRAME]); 1085 hantro_reg_write(vpu, &av1_skip_seg5, 1086 segval[5][V4L2_AV1_SEG_LVL_REF_SKIP]); 1087 hantro_reg_write(vpu, &av1_global_mv_seg5, 1088 segval[5][V4L2_AV1_SEG_LVL_REF_GLOBALMV]); 1089 1090 hantro_reg_write(vpu, &av1_quant_seg6, 1091 segval[6][V4L2_AV1_SEG_LVL_ALT_Q]); 1092 hantro_reg_write(vpu, &av1_filt_level_delta0_seg6, 1093 segval[6][V4L2_AV1_SEG_LVL_ALT_LF_Y_V]); 1094 hantro_reg_write(vpu, &av1_filt_level_delta1_seg6, 1095 segval[6][V4L2_AV1_SEG_LVL_ALT_LF_Y_H]); 1096 hantro_reg_write(vpu, &av1_filt_level_delta2_seg6, 1097 segval[6][V4L2_AV1_SEG_LVL_ALT_LF_U]); 1098 hantro_reg_write(vpu, &av1_filt_level_delta3_seg6, 1099 segval[6][V4L2_AV1_SEG_LVL_ALT_LF_V]); 1100 hantro_reg_write(vpu, &av1_refpic_seg6, 1101 segval[6][V4L2_AV1_SEG_LVL_REF_FRAME]); 1102 hantro_reg_write(vpu, &av1_skip_seg6, 1103 segval[6][V4L2_AV1_SEG_LVL_REF_SKIP]); 1104 hantro_reg_write(vpu, &av1_global_mv_seg6, 1105 segval[6][V4L2_AV1_SEG_LVL_REF_GLOBALMV]); 1106 1107 hantro_reg_write(vpu, &av1_quant_seg7, 1108 segval[7][V4L2_AV1_SEG_LVL_ALT_Q]); 1109 hantro_reg_write(vpu, &av1_filt_level_delta0_seg7, 1110 segval[7][V4L2_AV1_SEG_LVL_ALT_LF_Y_V]); 1111 hantro_reg_write(vpu, &av1_filt_level_delta1_seg7, 1112 segval[7][V4L2_AV1_SEG_LVL_ALT_LF_Y_H]); 1113 hantro_reg_write(vpu, &av1_filt_level_delta2_seg7, 1114 segval[7][V4L2_AV1_SEG_LVL_ALT_LF_U]); 1115 hantro_reg_write(vpu, &av1_filt_level_delta3_seg7, 1116 segval[7][V4L2_AV1_SEG_LVL_ALT_LF_V]); 1117 hantro_reg_write(vpu, &av1_refpic_seg7, 1118 segval[7][V4L2_AV1_SEG_LVL_REF_FRAME]); 1119 hantro_reg_write(vpu, &av1_skip_seg7, 1120 segval[7][V4L2_AV1_SEG_LVL_REF_SKIP]); 1121 hantro_reg_write(vpu, &av1_global_mv_seg7, 1122 segval[7][V4L2_AV1_SEG_LVL_REF_GLOBALMV]); 1123 } 1124 1125 static bool rockchip_vpu981_av1_dec_is_lossless(struct hantro_ctx *ctx) 1126 { 1127 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 1128 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 1129 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; 1130 const struct v4l2_av1_segmentation *segmentation = &frame->segmentation; 1131 const struct v4l2_av1_quantization *quantization = &frame->quantization; 1132 int i; 1133 1134 for (i = 0; i < V4L2_AV1_MAX_SEGMENTS; i++) { 1135 int qindex = quantization->base_q_idx; 1136 1137 if (segmentation->feature_enabled[i] & 1138 V4L2_AV1_SEGMENT_FEATURE_ENABLED(V4L2_AV1_SEG_LVL_ALT_Q)) { 1139 qindex += segmentation->feature_data[i][V4L2_AV1_SEG_LVL_ALT_Q]; 1140 } 1141 qindex = clamp(qindex, 0, 255); 1142 1143 if (qindex || 1144 quantization->delta_q_y_dc || 1145 quantization->delta_q_u_dc || 1146 quantization->delta_q_u_ac || 1147 quantization->delta_q_v_dc || 1148 quantization->delta_q_v_ac) 1149 return false; 1150 } 1151 return true; 1152 } 1153 1154 static void rockchip_vpu981_av1_dec_set_loopfilter(struct hantro_ctx *ctx) 1155 { 1156 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 1157 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 1158 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; 1159 const struct v4l2_av1_loop_filter *loop_filter = &frame->loop_filter; 1160 bool filtering_dis = (loop_filter->level[0] == 0) && (loop_filter->level[1] == 0); 1161 struct hantro_dev *vpu = ctx->dev; 1162 1163 hantro_reg_write(vpu, &av1_filtering_dis, filtering_dis); 1164 hantro_reg_write(vpu, &av1_filt_level_base_gt32, loop_filter->level[0] > 32); 1165 hantro_reg_write(vpu, &av1_filt_sharpness, loop_filter->sharpness); 1166 1167 hantro_reg_write(vpu, &av1_filt_level0, loop_filter->level[0]); 1168 hantro_reg_write(vpu, &av1_filt_level1, loop_filter->level[1]); 1169 hantro_reg_write(vpu, &av1_filt_level2, loop_filter->level[2]); 1170 hantro_reg_write(vpu, &av1_filt_level3, loop_filter->level[3]); 1171 1172 if (loop_filter->flags & V4L2_AV1_LOOP_FILTER_FLAG_DELTA_ENABLED && 1173 !rockchip_vpu981_av1_dec_is_lossless(ctx) && 1174 !(frame->flags & V4L2_AV1_FRAME_FLAG_ALLOW_INTRABC)) { 1175 hantro_reg_write(vpu, &av1_filt_ref_adj_0, 1176 loop_filter->ref_deltas[0]); 1177 hantro_reg_write(vpu, &av1_filt_ref_adj_1, 1178 loop_filter->ref_deltas[1]); 1179 hantro_reg_write(vpu, &av1_filt_ref_adj_2, 1180 loop_filter->ref_deltas[2]); 1181 hantro_reg_write(vpu, &av1_filt_ref_adj_3, 1182 loop_filter->ref_deltas[3]); 1183 hantro_reg_write(vpu, &av1_filt_ref_adj_4, 1184 loop_filter->ref_deltas[4]); 1185 hantro_reg_write(vpu, &av1_filt_ref_adj_5, 1186 loop_filter->ref_deltas[5]); 1187 hantro_reg_write(vpu, &av1_filt_ref_adj_6, 1188 loop_filter->ref_deltas[6]); 1189 hantro_reg_write(vpu, &av1_filt_ref_adj_7, 1190 loop_filter->ref_deltas[7]); 1191 hantro_reg_write(vpu, &av1_filt_mb_adj_0, 1192 loop_filter->mode_deltas[0]); 1193 hantro_reg_write(vpu, &av1_filt_mb_adj_1, 1194 loop_filter->mode_deltas[1]); 1195 } else { 1196 hantro_reg_write(vpu, &av1_filt_ref_adj_0, 0); 1197 hantro_reg_write(vpu, &av1_filt_ref_adj_1, 0); 1198 hantro_reg_write(vpu, &av1_filt_ref_adj_2, 0); 1199 hantro_reg_write(vpu, &av1_filt_ref_adj_3, 0); 1200 hantro_reg_write(vpu, &av1_filt_ref_adj_4, 0); 1201 hantro_reg_write(vpu, &av1_filt_ref_adj_5, 0); 1202 hantro_reg_write(vpu, &av1_filt_ref_adj_6, 0); 1203 hantro_reg_write(vpu, &av1_filt_ref_adj_7, 0); 1204 hantro_reg_write(vpu, &av1_filt_mb_adj_0, 0); 1205 hantro_reg_write(vpu, &av1_filt_mb_adj_1, 0); 1206 } 1207 1208 hantro_write_addr(vpu, AV1_DB_DATA_COL, av1_dec->db_data_col.dma); 1209 hantro_write_addr(vpu, AV1_DB_CTRL_COL, av1_dec->db_ctrl_col.dma); 1210 } 1211 1212 static void rockchip_vpu981_av1_dec_update_prob(struct hantro_ctx *ctx) 1213 { 1214 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 1215 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 1216 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; 1217 bool frame_is_intra = IS_INTRA(frame->frame_type); 1218 struct av1cdfs *out_cdfs = (struct av1cdfs *)av1_dec->prob_tbl_out.cpu; 1219 int i; 1220 1221 if (frame->flags & V4L2_AV1_FRAME_FLAG_DISABLE_FRAME_END_UPDATE_CDF) 1222 return; 1223 1224 for (i = 0; i < NUM_REF_FRAMES; i++) { 1225 if (frame->refresh_frame_flags & BIT(i)) { 1226 struct mvcdfs stored_mv_cdf; 1227 1228 rockchip_av1_get_cdfs(ctx, i); 1229 stored_mv_cdf = av1_dec->cdfs->mv_cdf; 1230 *av1_dec->cdfs = *out_cdfs; 1231 if (frame_is_intra) { 1232 av1_dec->cdfs->mv_cdf = stored_mv_cdf; 1233 *av1_dec->cdfs_ndvc = out_cdfs->mv_cdf; 1234 } 1235 rockchip_av1_store_cdfs(ctx, 1236 frame->refresh_frame_flags); 1237 break; 1238 } 1239 } 1240 } 1241 1242 void rockchip_vpu981_av1_dec_done(struct hantro_ctx *ctx) 1243 { 1244 rockchip_vpu981_av1_dec_update_prob(ctx); 1245 } 1246 1247 static void rockchip_vpu981_av1_dec_set_prob(struct hantro_ctx *ctx) 1248 { 1249 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 1250 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 1251 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; 1252 const struct v4l2_av1_quantization *quantization = &frame->quantization; 1253 struct hantro_dev *vpu = ctx->dev; 1254 bool error_resilient_mode = 1255 !!(frame->flags & V4L2_AV1_FRAME_FLAG_ERROR_RESILIENT_MODE); 1256 bool frame_is_intra = IS_INTRA(frame->frame_type); 1257 1258 if (error_resilient_mode || frame_is_intra || 1259 frame->primary_ref_frame == AV1_PRIMARY_REF_NONE) { 1260 av1_dec->cdfs = &av1_dec->default_cdfs; 1261 av1_dec->cdfs_ndvc = &av1_dec->default_cdfs_ndvc; 1262 rockchip_av1_default_coeff_probs(quantization->base_q_idx, 1263 av1_dec->cdfs); 1264 } else { 1265 rockchip_av1_get_cdfs(ctx, frame->ref_frame_idx[frame->primary_ref_frame]); 1266 } 1267 rockchip_av1_store_cdfs(ctx, frame->refresh_frame_flags); 1268 1269 memcpy(av1_dec->prob_tbl.cpu, av1_dec->cdfs, sizeof(struct av1cdfs)); 1270 1271 if (frame_is_intra) { 1272 int mv_offset = offsetof(struct av1cdfs, mv_cdf); 1273 /* Overwrite MV context area with intrabc MV context */ 1274 memcpy(av1_dec->prob_tbl.cpu + mv_offset, av1_dec->cdfs_ndvc, 1275 sizeof(struct mvcdfs)); 1276 } 1277 1278 hantro_write_addr(vpu, AV1_PROP_TABLE_OUT, av1_dec->prob_tbl_out.dma); 1279 hantro_write_addr(vpu, AV1_PROP_TABLE, av1_dec->prob_tbl.dma); 1280 } 1281 1282 static void 1283 rockchip_vpu981_av1_dec_init_scaling_function(const u8 *values, const u8 *scaling, 1284 u8 num_points, u8 *scaling_lut) 1285 { 1286 int i, point; 1287 1288 if (num_points == 0) { 1289 memset(scaling_lut, 0, 256); 1290 return; 1291 } 1292 1293 for (point = 0; point < num_points - 1; point++) { 1294 int x; 1295 s32 delta_y = scaling[point + 1] - scaling[point]; 1296 s32 delta_x = values[point + 1] - values[point]; 1297 s64 delta = 1298 delta_x ? delta_y * ((65536 + (delta_x >> 1)) / 1299 delta_x) : 0; 1300 1301 for (x = 0; x < delta_x; x++) { 1302 scaling_lut[values[point] + x] = 1303 scaling[point] + 1304 (s32)((x * delta + 32768) >> 16); 1305 } 1306 } 1307 1308 for (i = values[num_points - 1]; i < 256; i++) 1309 scaling_lut[i] = scaling[num_points - 1]; 1310 } 1311 1312 static void rockchip_vpu981_av1_dec_set_fgs(struct hantro_ctx *ctx) 1313 { 1314 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 1315 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 1316 const struct v4l2_ctrl_av1_film_grain *film_grain = ctrls->film_grain; 1317 struct rockchip_av1_film_grain *fgmem = av1_dec->film_grain.cpu; 1318 struct hantro_dev *vpu = ctx->dev; 1319 bool scaling_from_luma = 1320 !!(film_grain->flags & V4L2_AV1_FILM_GRAIN_FLAG_CHROMA_SCALING_FROM_LUMA); 1321 s32 (*ar_coeffs_y)[24]; 1322 s32 (*ar_coeffs_cb)[25]; 1323 s32 (*ar_coeffs_cr)[25]; 1324 s32 (*luma_grain_block)[73][82]; 1325 s32 (*cb_grain_block)[38][44]; 1326 s32 (*cr_grain_block)[38][44]; 1327 s32 ar_coeff_lag, ar_coeff_shift; 1328 s32 grain_scale_shift, bitdepth; 1329 s32 grain_center, grain_min, grain_max; 1330 int i, j; 1331 1332 hantro_reg_write(vpu, &av1_apply_grain, 0); 1333 1334 if (!(film_grain->flags & V4L2_AV1_FILM_GRAIN_FLAG_APPLY_GRAIN)) { 1335 hantro_reg_write(vpu, &av1_num_y_points_b, 0); 1336 hantro_reg_write(vpu, &av1_num_cb_points_b, 0); 1337 hantro_reg_write(vpu, &av1_num_cr_points_b, 0); 1338 hantro_reg_write(vpu, &av1_scaling_shift, 0); 1339 hantro_reg_write(vpu, &av1_cb_mult, 0); 1340 hantro_reg_write(vpu, &av1_cb_luma_mult, 0); 1341 hantro_reg_write(vpu, &av1_cb_offset, 0); 1342 hantro_reg_write(vpu, &av1_cr_mult, 0); 1343 hantro_reg_write(vpu, &av1_cr_luma_mult, 0); 1344 hantro_reg_write(vpu, &av1_cr_offset, 0); 1345 hantro_reg_write(vpu, &av1_overlap_flag, 0); 1346 hantro_reg_write(vpu, &av1_clip_to_restricted_range, 0); 1347 hantro_reg_write(vpu, &av1_chroma_scaling_from_luma, 0); 1348 hantro_reg_write(vpu, &av1_random_seed, 0); 1349 hantro_write_addr(vpu, AV1_FILM_GRAIN, 0); 1350 return; 1351 } 1352 1353 ar_coeffs_y = kzalloc(sizeof(int32_t) * 24, GFP_KERNEL); 1354 ar_coeffs_cb = kzalloc(sizeof(int32_t) * 25, GFP_KERNEL); 1355 ar_coeffs_cr = kzalloc(sizeof(int32_t) * 25, GFP_KERNEL); 1356 luma_grain_block = kzalloc(sizeof(int32_t) * 73 * 82, GFP_KERNEL); 1357 cb_grain_block = kzalloc(sizeof(int32_t) * 38 * 44, GFP_KERNEL); 1358 cr_grain_block = kzalloc(sizeof(int32_t) * 38 * 44, GFP_KERNEL); 1359 1360 if (!ar_coeffs_y || !ar_coeffs_cb || !ar_coeffs_cr || 1361 !luma_grain_block || !cb_grain_block || !cr_grain_block) { 1362 pr_warn("Fail allocating memory for film grain parameters\n"); 1363 goto alloc_fail; 1364 } 1365 1366 hantro_reg_write(vpu, &av1_apply_grain, 1); 1367 1368 hantro_reg_write(vpu, &av1_num_y_points_b, 1369 film_grain->num_y_points > 0); 1370 hantro_reg_write(vpu, &av1_num_cb_points_b, 1371 film_grain->num_cb_points > 0); 1372 hantro_reg_write(vpu, &av1_num_cr_points_b, 1373 film_grain->num_cr_points > 0); 1374 hantro_reg_write(vpu, &av1_scaling_shift, 1375 film_grain->grain_scaling_minus_8 + 8); 1376 1377 if (!scaling_from_luma) { 1378 hantro_reg_write(vpu, &av1_cb_mult, film_grain->cb_mult - 128); 1379 hantro_reg_write(vpu, &av1_cb_luma_mult, film_grain->cb_luma_mult - 128); 1380 hantro_reg_write(vpu, &av1_cb_offset, film_grain->cb_offset - 256); 1381 hantro_reg_write(vpu, &av1_cr_mult, film_grain->cr_mult - 128); 1382 hantro_reg_write(vpu, &av1_cr_luma_mult, film_grain->cr_luma_mult - 128); 1383 hantro_reg_write(vpu, &av1_cr_offset, film_grain->cr_offset - 256); 1384 } else { 1385 hantro_reg_write(vpu, &av1_cb_mult, 0); 1386 hantro_reg_write(vpu, &av1_cb_luma_mult, 0); 1387 hantro_reg_write(vpu, &av1_cb_offset, 0); 1388 hantro_reg_write(vpu, &av1_cr_mult, 0); 1389 hantro_reg_write(vpu, &av1_cr_luma_mult, 0); 1390 hantro_reg_write(vpu, &av1_cr_offset, 0); 1391 } 1392 1393 hantro_reg_write(vpu, &av1_overlap_flag, 1394 !!(film_grain->flags & V4L2_AV1_FILM_GRAIN_FLAG_OVERLAP)); 1395 hantro_reg_write(vpu, &av1_clip_to_restricted_range, 1396 !!(film_grain->flags & V4L2_AV1_FILM_GRAIN_FLAG_CLIP_TO_RESTRICTED_RANGE)); 1397 hantro_reg_write(vpu, &av1_chroma_scaling_from_luma, scaling_from_luma); 1398 hantro_reg_write(vpu, &av1_random_seed, film_grain->grain_seed); 1399 1400 rockchip_vpu981_av1_dec_init_scaling_function(film_grain->point_y_value, 1401 film_grain->point_y_scaling, 1402 film_grain->num_y_points, 1403 fgmem->scaling_lut_y); 1404 1405 if (film_grain->flags & 1406 V4L2_AV1_FILM_GRAIN_FLAG_CHROMA_SCALING_FROM_LUMA) { 1407 memcpy(fgmem->scaling_lut_cb, fgmem->scaling_lut_y, 1408 sizeof(*fgmem->scaling_lut_y) * 256); 1409 memcpy(fgmem->scaling_lut_cr, fgmem->scaling_lut_y, 1410 sizeof(*fgmem->scaling_lut_y) * 256); 1411 } else { 1412 rockchip_vpu981_av1_dec_init_scaling_function 1413 (film_grain->point_cb_value, film_grain->point_cb_scaling, 1414 film_grain->num_cb_points, fgmem->scaling_lut_cb); 1415 rockchip_vpu981_av1_dec_init_scaling_function 1416 (film_grain->point_cr_value, film_grain->point_cr_scaling, 1417 film_grain->num_cr_points, fgmem->scaling_lut_cr); 1418 } 1419 1420 for (i = 0; i < V4L2_AV1_AR_COEFFS_SIZE; i++) { 1421 if (i < 24) 1422 (*ar_coeffs_y)[i] = film_grain->ar_coeffs_y_plus_128[i] - 128; 1423 (*ar_coeffs_cb)[i] = film_grain->ar_coeffs_cb_plus_128[i] - 128; 1424 (*ar_coeffs_cr)[i] = film_grain->ar_coeffs_cr_plus_128[i] - 128; 1425 } 1426 1427 ar_coeff_lag = film_grain->ar_coeff_lag; 1428 ar_coeff_shift = film_grain->ar_coeff_shift_minus_6 + 6; 1429 grain_scale_shift = film_grain->grain_scale_shift; 1430 bitdepth = ctx->bit_depth; 1431 grain_center = 128 << (bitdepth - 8); 1432 grain_min = 0 - grain_center; 1433 grain_max = (256 << (bitdepth - 8)) - 1 - grain_center; 1434 1435 rockchip_av1_generate_luma_grain_block(luma_grain_block, bitdepth, 1436 film_grain->num_y_points, grain_scale_shift, 1437 ar_coeff_lag, ar_coeffs_y, ar_coeff_shift, 1438 grain_min, grain_max, film_grain->grain_seed); 1439 1440 rockchip_av1_generate_chroma_grain_block(luma_grain_block, cb_grain_block, 1441 cr_grain_block, bitdepth, 1442 film_grain->num_y_points, 1443 film_grain->num_cb_points, 1444 film_grain->num_cr_points, 1445 grain_scale_shift, ar_coeff_lag, ar_coeffs_cb, 1446 ar_coeffs_cr, ar_coeff_shift, grain_min, 1447 grain_max, 1448 scaling_from_luma, 1449 film_grain->grain_seed); 1450 1451 for (i = 0; i < 64; i++) { 1452 for (j = 0; j < 64; j++) 1453 fgmem->cropped_luma_grain_block[i * 64 + j] = 1454 (*luma_grain_block)[i + 9][j + 9]; 1455 } 1456 1457 for (i = 0; i < 32; i++) { 1458 for (j = 0; j < 32; j++) { 1459 fgmem->cropped_chroma_grain_block[i * 64 + 2 * j] = 1460 (*cb_grain_block)[i + 6][j + 6]; 1461 fgmem->cropped_chroma_grain_block[i * 64 + 2 * j + 1] = 1462 (*cr_grain_block)[i + 6][j + 6]; 1463 } 1464 } 1465 1466 hantro_write_addr(vpu, AV1_FILM_GRAIN, av1_dec->film_grain.dma); 1467 1468 alloc_fail: 1469 kfree(ar_coeffs_y); 1470 kfree(ar_coeffs_cb); 1471 kfree(ar_coeffs_cr); 1472 kfree(luma_grain_block); 1473 kfree(cb_grain_block); 1474 kfree(cr_grain_block); 1475 } 1476 1477 static void rockchip_vpu981_av1_dec_set_cdef(struct hantro_ctx *ctx) 1478 { 1479 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 1480 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 1481 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; 1482 const struct v4l2_av1_cdef *cdef = &frame->cdef; 1483 struct hantro_dev *vpu = ctx->dev; 1484 u32 luma_pri_strength = 0; 1485 u16 luma_sec_strength = 0; 1486 u32 chroma_pri_strength = 0; 1487 u16 chroma_sec_strength = 0; 1488 bool enable_cdef; 1489 int i; 1490 1491 enable_cdef = !(cdef->bits == 0 && 1492 cdef->damping_minus_3 == 0 && 1493 cdef->y_pri_strength[0] == 0 && 1494 cdef->y_sec_strength[0] == 0 && 1495 cdef->uv_pri_strength[0] == 0 && 1496 cdef->uv_sec_strength[0] == 0); 1497 hantro_reg_write(vpu, &av1_enable_cdef, enable_cdef); 1498 hantro_reg_write(vpu, &av1_cdef_bits, cdef->bits); 1499 hantro_reg_write(vpu, &av1_cdef_damping, cdef->damping_minus_3); 1500 1501 for (i = 0; i < BIT(cdef->bits); i++) { 1502 luma_pri_strength |= cdef->y_pri_strength[i] << (i * 4); 1503 if (cdef->y_sec_strength[i] == 4) 1504 luma_sec_strength |= 3 << (i * 2); 1505 else 1506 luma_sec_strength |= cdef->y_sec_strength[i] << (i * 2); 1507 1508 chroma_pri_strength |= cdef->uv_pri_strength[i] << (i * 4); 1509 if (cdef->uv_sec_strength[i] == 4) 1510 chroma_sec_strength |= 3 << (i * 2); 1511 else 1512 chroma_sec_strength |= cdef->uv_sec_strength[i] << (i * 2); 1513 } 1514 1515 hantro_reg_write(vpu, &av1_cdef_luma_primary_strength, 1516 luma_pri_strength); 1517 hantro_reg_write(vpu, &av1_cdef_luma_secondary_strength, 1518 luma_sec_strength); 1519 hantro_reg_write(vpu, &av1_cdef_chroma_primary_strength, 1520 chroma_pri_strength); 1521 hantro_reg_write(vpu, &av1_cdef_chroma_secondary_strength, 1522 chroma_sec_strength); 1523 1524 hantro_write_addr(vpu, AV1_CDEF_COL, av1_dec->cdef_col.dma); 1525 } 1526 1527 static void rockchip_vpu981_av1_dec_set_lr(struct hantro_ctx *ctx) 1528 { 1529 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 1530 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 1531 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; 1532 const struct v4l2_av1_loop_restoration *loop_restoration = 1533 &frame->loop_restoration; 1534 struct hantro_dev *vpu = ctx->dev; 1535 u16 lr_type = 0, lr_unit_size = 0; 1536 u8 restoration_unit_size[V4L2_AV1_NUM_PLANES_MAX] = { 3, 3, 3 }; 1537 int i; 1538 1539 if (loop_restoration->flags & V4L2_AV1_LOOP_RESTORATION_FLAG_USES_LR) { 1540 restoration_unit_size[0] = 1 + loop_restoration->lr_unit_shift; 1541 restoration_unit_size[1] = 1542 1 + loop_restoration->lr_unit_shift - loop_restoration->lr_uv_shift; 1543 restoration_unit_size[2] = 1544 1 + loop_restoration->lr_unit_shift - loop_restoration->lr_uv_shift; 1545 } 1546 1547 for (i = 0; i < V4L2_AV1_NUM_PLANES_MAX; i++) { 1548 lr_type |= 1549 loop_restoration->frame_restoration_type[i] << (i * 2); 1550 lr_unit_size |= restoration_unit_size[i] << (i * 2); 1551 } 1552 1553 hantro_reg_write(vpu, &av1_lr_type, lr_type); 1554 hantro_reg_write(vpu, &av1_lr_unit_size, lr_unit_size); 1555 hantro_write_addr(vpu, AV1_LR_COL, av1_dec->lr_col.dma); 1556 } 1557 1558 static void rockchip_vpu981_av1_dec_set_superres_params(struct hantro_ctx *ctx) 1559 { 1560 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 1561 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 1562 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; 1563 struct hantro_dev *vpu = ctx->dev; 1564 u8 superres_scale_denominator = SCALE_NUMERATOR; 1565 int superres_luma_step = RS_SCALE_SUBPEL_BITS; 1566 int superres_chroma_step = RS_SCALE_SUBPEL_BITS; 1567 int superres_luma_step_invra = RS_SCALE_SUBPEL_BITS; 1568 int superres_chroma_step_invra = RS_SCALE_SUBPEL_BITS; 1569 int superres_init_luma_subpel_x = 0; 1570 int superres_init_chroma_subpel_x = 0; 1571 int superres_is_scaled = 0; 1572 int min_w = min_t(uint32_t, 16, frame->upscaled_width); 1573 int upscaled_luma, downscaled_luma; 1574 int downscaled_chroma, upscaled_chroma; 1575 int step_luma, step_chroma; 1576 int err_luma, err_chroma; 1577 int initial_luma, initial_chroma; 1578 int width = 0; 1579 1580 if (frame->flags & V4L2_AV1_FRAME_FLAG_USE_SUPERRES) 1581 superres_scale_denominator = frame->superres_denom; 1582 1583 if (superres_scale_denominator <= SCALE_NUMERATOR) 1584 goto set_regs; 1585 1586 width = (frame->upscaled_width * SCALE_NUMERATOR + 1587 (superres_scale_denominator / 2)) / superres_scale_denominator; 1588 1589 if (width < min_w) 1590 width = min_w; 1591 1592 if (width == frame->upscaled_width) 1593 goto set_regs; 1594 1595 superres_is_scaled = 1; 1596 upscaled_luma = frame->upscaled_width; 1597 downscaled_luma = width; 1598 downscaled_chroma = (downscaled_luma + 1) >> 1; 1599 upscaled_chroma = (upscaled_luma + 1) >> 1; 1600 step_luma = 1601 ((downscaled_luma << RS_SCALE_SUBPEL_BITS) + 1602 (upscaled_luma / 2)) / upscaled_luma; 1603 step_chroma = 1604 ((downscaled_chroma << RS_SCALE_SUBPEL_BITS) + 1605 (upscaled_chroma / 2)) / upscaled_chroma; 1606 err_luma = 1607 (upscaled_luma * step_luma) 1608 - (downscaled_luma << RS_SCALE_SUBPEL_BITS); 1609 err_chroma = 1610 (upscaled_chroma * step_chroma) 1611 - (downscaled_chroma << RS_SCALE_SUBPEL_BITS); 1612 initial_luma = 1613 ((-((upscaled_luma - downscaled_luma) << (RS_SCALE_SUBPEL_BITS - 1)) 1614 + upscaled_luma / 2) 1615 / upscaled_luma + (1 << (RS_SCALE_EXTRA_BITS - 1)) - err_luma / 2) 1616 & RS_SCALE_SUBPEL_MASK; 1617 initial_chroma = 1618 ((-((upscaled_chroma - downscaled_chroma) << (RS_SCALE_SUBPEL_BITS - 1)) 1619 + upscaled_chroma / 2) 1620 / upscaled_chroma + (1 << (RS_SCALE_EXTRA_BITS - 1)) - err_chroma / 2) 1621 & RS_SCALE_SUBPEL_MASK; 1622 superres_luma_step = step_luma; 1623 superres_chroma_step = step_chroma; 1624 superres_luma_step_invra = 1625 ((upscaled_luma << RS_SCALE_SUBPEL_BITS) + (downscaled_luma / 2)) 1626 / downscaled_luma; 1627 superres_chroma_step_invra = 1628 ((upscaled_chroma << RS_SCALE_SUBPEL_BITS) + (downscaled_chroma / 2)) 1629 / downscaled_chroma; 1630 superres_init_luma_subpel_x = initial_luma; 1631 superres_init_chroma_subpel_x = initial_chroma; 1632 1633 set_regs: 1634 hantro_reg_write(vpu, &av1_superres_pic_width, frame->upscaled_width); 1635 1636 if (frame->flags & V4L2_AV1_FRAME_FLAG_USE_SUPERRES) 1637 hantro_reg_write(vpu, &av1_scale_denom_minus9, 1638 frame->superres_denom - SUPERRES_SCALE_DENOMINATOR_MIN); 1639 else 1640 hantro_reg_write(vpu, &av1_scale_denom_minus9, frame->superres_denom); 1641 1642 hantro_reg_write(vpu, &av1_superres_luma_step, superres_luma_step); 1643 hantro_reg_write(vpu, &av1_superres_chroma_step, superres_chroma_step); 1644 hantro_reg_write(vpu, &av1_superres_luma_step_invra, 1645 superres_luma_step_invra); 1646 hantro_reg_write(vpu, &av1_superres_chroma_step_invra, 1647 superres_chroma_step_invra); 1648 hantro_reg_write(vpu, &av1_superres_init_luma_subpel_x, 1649 superres_init_luma_subpel_x); 1650 hantro_reg_write(vpu, &av1_superres_init_chroma_subpel_x, 1651 superres_init_chroma_subpel_x); 1652 hantro_reg_write(vpu, &av1_superres_is_scaled, superres_is_scaled); 1653 1654 hantro_write_addr(vpu, AV1_SR_COL, av1_dec->sr_col.dma); 1655 } 1656 1657 static void rockchip_vpu981_av1_dec_set_picture_dimensions(struct hantro_ctx *ctx) 1658 { 1659 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 1660 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 1661 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; 1662 struct hantro_dev *vpu = ctx->dev; 1663 int pic_width_in_cbs = DIV_ROUND_UP(frame->frame_width_minus_1 + 1, 8); 1664 int pic_height_in_cbs = DIV_ROUND_UP(frame->frame_height_minus_1 + 1, 8); 1665 int pic_width_pad = ALIGN(frame->frame_width_minus_1 + 1, 8) 1666 - (frame->frame_width_minus_1 + 1); 1667 int pic_height_pad = ALIGN(frame->frame_height_minus_1 + 1, 8) 1668 - (frame->frame_height_minus_1 + 1); 1669 1670 hantro_reg_write(vpu, &av1_pic_width_in_cbs, pic_width_in_cbs); 1671 hantro_reg_write(vpu, &av1_pic_height_in_cbs, pic_height_in_cbs); 1672 hantro_reg_write(vpu, &av1_pic_width_pad, pic_width_pad); 1673 hantro_reg_write(vpu, &av1_pic_height_pad, pic_height_pad); 1674 1675 rockchip_vpu981_av1_dec_set_superres_params(ctx); 1676 } 1677 1678 static void rockchip_vpu981_av1_dec_set_other_frames(struct hantro_ctx *ctx) 1679 { 1680 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 1681 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 1682 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; 1683 struct hantro_dev *vpu = ctx->dev; 1684 bool use_ref_frame_mvs = 1685 !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_USE_REF_FRAME_MVS); 1686 int cur_frame_offset = frame->order_hint; 1687 int alt_frame_offset = 0; 1688 int gld_frame_offset = 0; 1689 int bwd_frame_offset = 0; 1690 int alt2_frame_offset = 0; 1691 int refs_selected[3] = { 0, 0, 0 }; 1692 int cur_mi_cols = DIV_ROUND_UP(frame->frame_width_minus_1 + 1, 8); 1693 int cur_mi_rows = DIV_ROUND_UP(frame->frame_height_minus_1 + 1, 8); 1694 int cur_offset[V4L2_AV1_TOTAL_REFS_PER_FRAME - 1]; 1695 int cur_roffset[V4L2_AV1_TOTAL_REFS_PER_FRAME - 1]; 1696 int mf_types[3] = { 0, 0, 0 }; 1697 int ref_stamp = 2; 1698 int ref_ind = 0; 1699 int rf, idx; 1700 1701 alt_frame_offset = rockchip_vpu981_get_order_hint(ctx, ALT_BUF_IDX); 1702 gld_frame_offset = rockchip_vpu981_get_order_hint(ctx, GLD_BUF_IDX); 1703 bwd_frame_offset = rockchip_vpu981_get_order_hint(ctx, BWD_BUF_IDX); 1704 alt2_frame_offset = rockchip_vpu981_get_order_hint(ctx, ALT2_BUF_IDX); 1705 1706 idx = rockchip_vpu981_get_frame_index(ctx, LST_BUF_IDX); 1707 if (idx >= 0) { 1708 int alt_frame_offset_in_lst = 1709 av1_dec->frame_refs[idx].order_hints[V4L2_AV1_REF_ALTREF_FRAME]; 1710 bool is_lst_overlay = 1711 (alt_frame_offset_in_lst == gld_frame_offset); 1712 1713 if (!is_lst_overlay) { 1714 int lst_mi_cols = av1_dec->frame_refs[idx].mi_cols; 1715 int lst_mi_rows = av1_dec->frame_refs[idx].mi_rows; 1716 bool lst_intra_only = 1717 IS_INTRA(av1_dec->frame_refs[idx].frame_type); 1718 1719 if (lst_mi_cols == cur_mi_cols && 1720 lst_mi_rows == cur_mi_rows && !lst_intra_only) { 1721 mf_types[ref_ind] = V4L2_AV1_REF_LAST_FRAME; 1722 refs_selected[ref_ind++] = LST_BUF_IDX; 1723 } 1724 } 1725 ref_stamp--; 1726 } 1727 1728 idx = rockchip_vpu981_get_frame_index(ctx, BWD_BUF_IDX); 1729 if (rockchip_vpu981_av1_dec_get_dist(ctx, bwd_frame_offset, cur_frame_offset) > 0) { 1730 int bwd_mi_cols = av1_dec->frame_refs[idx].mi_cols; 1731 int bwd_mi_rows = av1_dec->frame_refs[idx].mi_rows; 1732 bool bwd_intra_only = 1733 IS_INTRA(av1_dec->frame_refs[idx].frame_type); 1734 1735 if (bwd_mi_cols == cur_mi_cols && bwd_mi_rows == cur_mi_rows && 1736 !bwd_intra_only) { 1737 mf_types[ref_ind] = V4L2_AV1_REF_BWDREF_FRAME; 1738 refs_selected[ref_ind++] = BWD_BUF_IDX; 1739 ref_stamp--; 1740 } 1741 } 1742 1743 idx = rockchip_vpu981_get_frame_index(ctx, ALT2_BUF_IDX); 1744 if (rockchip_vpu981_av1_dec_get_dist(ctx, alt2_frame_offset, cur_frame_offset) > 0) { 1745 int alt2_mi_cols = av1_dec->frame_refs[idx].mi_cols; 1746 int alt2_mi_rows = av1_dec->frame_refs[idx].mi_rows; 1747 bool alt2_intra_only = 1748 IS_INTRA(av1_dec->frame_refs[idx].frame_type); 1749 1750 if (alt2_mi_cols == cur_mi_cols && alt2_mi_rows == cur_mi_rows && 1751 !alt2_intra_only) { 1752 mf_types[ref_ind] = V4L2_AV1_REF_ALTREF2_FRAME; 1753 refs_selected[ref_ind++] = ALT2_BUF_IDX; 1754 ref_stamp--; 1755 } 1756 } 1757 1758 idx = rockchip_vpu981_get_frame_index(ctx, ALT_BUF_IDX); 1759 if (rockchip_vpu981_av1_dec_get_dist(ctx, alt_frame_offset, cur_frame_offset) > 0 && 1760 ref_stamp >= 0) { 1761 int alt_mi_cols = av1_dec->frame_refs[idx].mi_cols; 1762 int alt_mi_rows = av1_dec->frame_refs[idx].mi_rows; 1763 bool alt_intra_only = 1764 IS_INTRA(av1_dec->frame_refs[idx].frame_type); 1765 1766 if (alt_mi_cols == cur_mi_cols && alt_mi_rows == cur_mi_rows && 1767 !alt_intra_only) { 1768 mf_types[ref_ind] = V4L2_AV1_REF_ALTREF_FRAME; 1769 refs_selected[ref_ind++] = ALT_BUF_IDX; 1770 ref_stamp--; 1771 } 1772 } 1773 1774 idx = rockchip_vpu981_get_frame_index(ctx, LST2_BUF_IDX); 1775 if (idx >= 0 && ref_stamp >= 0) { 1776 int lst2_mi_cols = av1_dec->frame_refs[idx].mi_cols; 1777 int lst2_mi_rows = av1_dec->frame_refs[idx].mi_rows; 1778 bool lst2_intra_only = 1779 IS_INTRA(av1_dec->frame_refs[idx].frame_type); 1780 1781 if (lst2_mi_cols == cur_mi_cols && lst2_mi_rows == cur_mi_rows && 1782 !lst2_intra_only) { 1783 mf_types[ref_ind] = V4L2_AV1_REF_LAST2_FRAME; 1784 refs_selected[ref_ind++] = LST2_BUF_IDX; 1785 ref_stamp--; 1786 } 1787 } 1788 1789 for (rf = 0; rf < V4L2_AV1_TOTAL_REFS_PER_FRAME - 1; ++rf) { 1790 idx = rockchip_vpu981_get_frame_index(ctx, rf); 1791 if (idx >= 0) { 1792 int rf_order_hint = rockchip_vpu981_get_order_hint(ctx, rf); 1793 1794 cur_offset[rf] = 1795 rockchip_vpu981_av1_dec_get_dist(ctx, cur_frame_offset, rf_order_hint); 1796 cur_roffset[rf] = 1797 rockchip_vpu981_av1_dec_get_dist(ctx, rf_order_hint, cur_frame_offset); 1798 } else { 1799 cur_offset[rf] = 0; 1800 cur_roffset[rf] = 0; 1801 } 1802 } 1803 1804 hantro_reg_write(vpu, &av1_use_temporal0_mvs, 0); 1805 hantro_reg_write(vpu, &av1_use_temporal1_mvs, 0); 1806 hantro_reg_write(vpu, &av1_use_temporal2_mvs, 0); 1807 hantro_reg_write(vpu, &av1_use_temporal3_mvs, 0); 1808 1809 hantro_reg_write(vpu, &av1_mf1_last_offset, 0); 1810 hantro_reg_write(vpu, &av1_mf1_last2_offset, 0); 1811 hantro_reg_write(vpu, &av1_mf1_last3_offset, 0); 1812 hantro_reg_write(vpu, &av1_mf1_golden_offset, 0); 1813 hantro_reg_write(vpu, &av1_mf1_bwdref_offset, 0); 1814 hantro_reg_write(vpu, &av1_mf1_altref2_offset, 0); 1815 hantro_reg_write(vpu, &av1_mf1_altref_offset, 0); 1816 1817 if (use_ref_frame_mvs && ref_ind > 0 && 1818 cur_offset[mf_types[0] - V4L2_AV1_REF_LAST_FRAME] <= MAX_FRAME_DISTANCE && 1819 cur_offset[mf_types[0] - V4L2_AV1_REF_LAST_FRAME] >= -MAX_FRAME_DISTANCE) { 1820 int rf = rockchip_vpu981_get_order_hint(ctx, refs_selected[0]); 1821 int idx = rockchip_vpu981_get_frame_index(ctx, refs_selected[0]); 1822 u32 *oh = av1_dec->frame_refs[idx].order_hints; 1823 int val; 1824 1825 hantro_reg_write(vpu, &av1_use_temporal0_mvs, 1); 1826 1827 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_LAST_FRAME]); 1828 hantro_reg_write(vpu, &av1_mf1_last_offset, val); 1829 1830 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_LAST2_FRAME]); 1831 hantro_reg_write(vpu, &av1_mf1_last2_offset, val); 1832 1833 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_LAST3_FRAME]); 1834 hantro_reg_write(vpu, &av1_mf1_last3_offset, val); 1835 1836 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_GOLDEN_FRAME]); 1837 hantro_reg_write(vpu, &av1_mf1_golden_offset, val); 1838 1839 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_BWDREF_FRAME]); 1840 hantro_reg_write(vpu, &av1_mf1_bwdref_offset, val); 1841 1842 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_ALTREF2_FRAME]); 1843 hantro_reg_write(vpu, &av1_mf1_altref2_offset, val); 1844 1845 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_ALTREF_FRAME]); 1846 hantro_reg_write(vpu, &av1_mf1_altref_offset, val); 1847 } 1848 1849 hantro_reg_write(vpu, &av1_mf2_last_offset, 0); 1850 hantro_reg_write(vpu, &av1_mf2_last2_offset, 0); 1851 hantro_reg_write(vpu, &av1_mf2_last3_offset, 0); 1852 hantro_reg_write(vpu, &av1_mf2_golden_offset, 0); 1853 hantro_reg_write(vpu, &av1_mf2_bwdref_offset, 0); 1854 hantro_reg_write(vpu, &av1_mf2_altref2_offset, 0); 1855 hantro_reg_write(vpu, &av1_mf2_altref_offset, 0); 1856 1857 if (use_ref_frame_mvs && ref_ind > 1 && 1858 cur_offset[mf_types[1] - V4L2_AV1_REF_LAST_FRAME] <= MAX_FRAME_DISTANCE && 1859 cur_offset[mf_types[1] - V4L2_AV1_REF_LAST_FRAME] >= -MAX_FRAME_DISTANCE) { 1860 int rf = rockchip_vpu981_get_order_hint(ctx, refs_selected[1]); 1861 int idx = rockchip_vpu981_get_frame_index(ctx, refs_selected[1]); 1862 u32 *oh = av1_dec->frame_refs[idx].order_hints; 1863 int val; 1864 1865 hantro_reg_write(vpu, &av1_use_temporal1_mvs, 1); 1866 1867 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_LAST_FRAME]); 1868 hantro_reg_write(vpu, &av1_mf2_last_offset, val); 1869 1870 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_LAST2_FRAME]); 1871 hantro_reg_write(vpu, &av1_mf2_last2_offset, val); 1872 1873 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_LAST3_FRAME]); 1874 hantro_reg_write(vpu, &av1_mf2_last3_offset, val); 1875 1876 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_GOLDEN_FRAME]); 1877 hantro_reg_write(vpu, &av1_mf2_golden_offset, val); 1878 1879 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_BWDREF_FRAME]); 1880 hantro_reg_write(vpu, &av1_mf2_bwdref_offset, val); 1881 1882 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_ALTREF2_FRAME]); 1883 hantro_reg_write(vpu, &av1_mf2_altref2_offset, val); 1884 1885 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_ALTREF_FRAME]); 1886 hantro_reg_write(vpu, &av1_mf2_altref_offset, val); 1887 } 1888 1889 hantro_reg_write(vpu, &av1_mf3_last_offset, 0); 1890 hantro_reg_write(vpu, &av1_mf3_last2_offset, 0); 1891 hantro_reg_write(vpu, &av1_mf3_last3_offset, 0); 1892 hantro_reg_write(vpu, &av1_mf3_golden_offset, 0); 1893 hantro_reg_write(vpu, &av1_mf3_bwdref_offset, 0); 1894 hantro_reg_write(vpu, &av1_mf3_altref2_offset, 0); 1895 hantro_reg_write(vpu, &av1_mf3_altref_offset, 0); 1896 1897 if (use_ref_frame_mvs && ref_ind > 2 && 1898 cur_offset[mf_types[2] - V4L2_AV1_REF_LAST_FRAME] <= MAX_FRAME_DISTANCE && 1899 cur_offset[mf_types[2] - V4L2_AV1_REF_LAST_FRAME] >= -MAX_FRAME_DISTANCE) { 1900 int rf = rockchip_vpu981_get_order_hint(ctx, refs_selected[2]); 1901 int idx = rockchip_vpu981_get_frame_index(ctx, refs_selected[2]); 1902 u32 *oh = av1_dec->frame_refs[idx].order_hints; 1903 int val; 1904 1905 hantro_reg_write(vpu, &av1_use_temporal2_mvs, 1); 1906 1907 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_LAST_FRAME]); 1908 hantro_reg_write(vpu, &av1_mf3_last_offset, val); 1909 1910 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_LAST2_FRAME]); 1911 hantro_reg_write(vpu, &av1_mf3_last2_offset, val); 1912 1913 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_LAST3_FRAME]); 1914 hantro_reg_write(vpu, &av1_mf3_last3_offset, val); 1915 1916 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_GOLDEN_FRAME]); 1917 hantro_reg_write(vpu, &av1_mf3_golden_offset, val); 1918 1919 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_BWDREF_FRAME]); 1920 hantro_reg_write(vpu, &av1_mf3_bwdref_offset, val); 1921 1922 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_ALTREF2_FRAME]); 1923 hantro_reg_write(vpu, &av1_mf3_altref2_offset, val); 1924 1925 val = rockchip_vpu981_av1_dec_get_dist(ctx, rf, oh[V4L2_AV1_REF_ALTREF_FRAME]); 1926 hantro_reg_write(vpu, &av1_mf3_altref_offset, val); 1927 } 1928 1929 hantro_reg_write(vpu, &av1_cur_last_offset, cur_offset[0]); 1930 hantro_reg_write(vpu, &av1_cur_last2_offset, cur_offset[1]); 1931 hantro_reg_write(vpu, &av1_cur_last3_offset, cur_offset[2]); 1932 hantro_reg_write(vpu, &av1_cur_golden_offset, cur_offset[3]); 1933 hantro_reg_write(vpu, &av1_cur_bwdref_offset, cur_offset[4]); 1934 hantro_reg_write(vpu, &av1_cur_altref2_offset, cur_offset[5]); 1935 hantro_reg_write(vpu, &av1_cur_altref_offset, cur_offset[6]); 1936 1937 hantro_reg_write(vpu, &av1_cur_last_roffset, cur_roffset[0]); 1938 hantro_reg_write(vpu, &av1_cur_last2_roffset, cur_roffset[1]); 1939 hantro_reg_write(vpu, &av1_cur_last3_roffset, cur_roffset[2]); 1940 hantro_reg_write(vpu, &av1_cur_golden_roffset, cur_roffset[3]); 1941 hantro_reg_write(vpu, &av1_cur_bwdref_roffset, cur_roffset[4]); 1942 hantro_reg_write(vpu, &av1_cur_altref2_roffset, cur_roffset[5]); 1943 hantro_reg_write(vpu, &av1_cur_altref_roffset, cur_roffset[6]); 1944 1945 hantro_reg_write(vpu, &av1_mf1_type, mf_types[0] - V4L2_AV1_REF_LAST_FRAME); 1946 hantro_reg_write(vpu, &av1_mf2_type, mf_types[1] - V4L2_AV1_REF_LAST_FRAME); 1947 hantro_reg_write(vpu, &av1_mf3_type, mf_types[2] - V4L2_AV1_REF_LAST_FRAME); 1948 } 1949 1950 static void rockchip_vpu981_av1_dec_set_reference_frames(struct hantro_ctx *ctx) 1951 { 1952 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 1953 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 1954 const struct v4l2_ctrl_av1_frame *frame = ctrls->frame; 1955 int frame_type = frame->frame_type; 1956 bool allow_intrabc = !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_ALLOW_INTRABC); 1957 int ref_count[AV1DEC_MAX_PIC_BUFFERS] = { 0 }; 1958 struct hantro_dev *vpu = ctx->dev; 1959 int i, ref_frames = 0; 1960 bool scale_enable = false; 1961 1962 if (IS_INTRA(frame_type) && !allow_intrabc) 1963 return; 1964 1965 if (!allow_intrabc) { 1966 for (i = 0; i < V4L2_AV1_REFS_PER_FRAME; i++) { 1967 int idx = rockchip_vpu981_get_frame_index(ctx, i); 1968 1969 if (idx >= 0) 1970 ref_count[idx]++; 1971 } 1972 1973 for (i = 0; i < AV1DEC_MAX_PIC_BUFFERS; i++) { 1974 if (ref_count[i]) 1975 ref_frames++; 1976 } 1977 } else { 1978 ref_frames = 1; 1979 } 1980 hantro_reg_write(vpu, &av1_ref_frames, ref_frames); 1981 1982 rockchip_vpu981_av1_dec_set_frame_sign_bias(ctx); 1983 1984 for (i = V4L2_AV1_REF_LAST_FRAME; i < V4L2_AV1_TOTAL_REFS_PER_FRAME; i++) { 1985 u32 ref = i - 1; 1986 int idx = 0; 1987 int width, height; 1988 1989 if (allow_intrabc) { 1990 idx = av1_dec->current_frame_index; 1991 width = frame->frame_width_minus_1 + 1; 1992 height = frame->frame_height_minus_1 + 1; 1993 } else { 1994 if (rockchip_vpu981_get_frame_index(ctx, ref) > 0) 1995 idx = rockchip_vpu981_get_frame_index(ctx, ref); 1996 width = av1_dec->frame_refs[idx].width; 1997 height = av1_dec->frame_refs[idx].height; 1998 } 1999 2000 scale_enable |= 2001 rockchip_vpu981_av1_dec_set_ref(ctx, ref, idx, width, 2002 height); 2003 2004 rockchip_vpu981_av1_dec_set_sign_bias(ctx, ref, 2005 av1_dec->ref_frame_sign_bias[i]); 2006 } 2007 hantro_reg_write(vpu, &av1_ref_scaling_enable, scale_enable); 2008 2009 hantro_reg_write(vpu, &av1_ref0_gm_mode, 2010 frame->global_motion.type[V4L2_AV1_REF_LAST_FRAME]); 2011 hantro_reg_write(vpu, &av1_ref1_gm_mode, 2012 frame->global_motion.type[V4L2_AV1_REF_LAST2_FRAME]); 2013 hantro_reg_write(vpu, &av1_ref2_gm_mode, 2014 frame->global_motion.type[V4L2_AV1_REF_LAST3_FRAME]); 2015 hantro_reg_write(vpu, &av1_ref3_gm_mode, 2016 frame->global_motion.type[V4L2_AV1_REF_GOLDEN_FRAME]); 2017 hantro_reg_write(vpu, &av1_ref4_gm_mode, 2018 frame->global_motion.type[V4L2_AV1_REF_BWDREF_FRAME]); 2019 hantro_reg_write(vpu, &av1_ref5_gm_mode, 2020 frame->global_motion.type[V4L2_AV1_REF_ALTREF2_FRAME]); 2021 hantro_reg_write(vpu, &av1_ref6_gm_mode, 2022 frame->global_motion.type[V4L2_AV1_REF_ALTREF_FRAME]); 2023 2024 rockchip_vpu981_av1_dec_set_other_frames(ctx); 2025 } 2026 2027 static int rockchip_vpu981_av1_get_hardware_tx_mode(enum v4l2_av1_tx_mode tx_mode) 2028 { 2029 switch (tx_mode) { 2030 case V4L2_AV1_TX_MODE_ONLY_4X4: 2031 return ROCKCHIP_AV1_TX_MODE_ONLY_4X4; 2032 case V4L2_AV1_TX_MODE_LARGEST: 2033 return ROCKCHIP_AV1_TX_MODE_32x32; 2034 case V4L2_AV1_TX_MODE_SELECT: 2035 return ROCKCHIP_AV1_TX_MODE_SELECT; 2036 } 2037 2038 return ROCKCHIP_AV1_TX_MODE_32x32; 2039 } 2040 2041 static void rockchip_vpu981_av1_dec_set_parameters(struct hantro_ctx *ctx) 2042 { 2043 struct hantro_dev *vpu = ctx->dev; 2044 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 2045 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 2046 int tx_mode; 2047 2048 hantro_reg_write(vpu, &av1_skip_mode, 2049 !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_SKIP_MODE_PRESENT)); 2050 hantro_reg_write(vpu, &av1_tempor_mvp_e, 2051 !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_USE_REF_FRAME_MVS)); 2052 hantro_reg_write(vpu, &av1_delta_lf_res_log, 2053 ctrls->frame->loop_filter.delta_lf_res); 2054 hantro_reg_write(vpu, &av1_delta_lf_multi, 2055 !!(ctrls->frame->loop_filter.flags 2056 & V4L2_AV1_LOOP_FILTER_FLAG_DELTA_LF_MULTI)); 2057 hantro_reg_write(vpu, &av1_delta_lf_present, 2058 !!(ctrls->frame->loop_filter.flags 2059 & V4L2_AV1_LOOP_FILTER_FLAG_DELTA_LF_PRESENT)); 2060 hantro_reg_write(vpu, &av1_disable_cdf_update, 2061 !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_DISABLE_CDF_UPDATE)); 2062 hantro_reg_write(vpu, &av1_allow_warp, 2063 !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_ALLOW_WARPED_MOTION)); 2064 hantro_reg_write(vpu, &av1_show_frame, 2065 !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_SHOW_FRAME)); 2066 hantro_reg_write(vpu, &av1_switchable_motion_mode, 2067 !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_IS_MOTION_MODE_SWITCHABLE)); 2068 hantro_reg_write(vpu, &av1_allow_masked_compound, 2069 !!(ctrls->sequence->flags 2070 & V4L2_AV1_SEQUENCE_FLAG_ENABLE_MASKED_COMPOUND)); 2071 hantro_reg_write(vpu, &av1_allow_interintra, 2072 !!(ctrls->sequence->flags 2073 & V4L2_AV1_SEQUENCE_FLAG_ENABLE_INTERINTRA_COMPOUND)); 2074 hantro_reg_write(vpu, &av1_enable_intra_edge_filter, 2075 !!(ctrls->sequence->flags 2076 & V4L2_AV1_SEQUENCE_FLAG_ENABLE_INTRA_EDGE_FILTER)); 2077 hantro_reg_write(vpu, &av1_allow_filter_intra, 2078 !!(ctrls->sequence->flags & V4L2_AV1_SEQUENCE_FLAG_ENABLE_FILTER_INTRA)); 2079 hantro_reg_write(vpu, &av1_enable_jnt_comp, 2080 !!(ctrls->sequence->flags & V4L2_AV1_SEQUENCE_FLAG_ENABLE_JNT_COMP)); 2081 hantro_reg_write(vpu, &av1_enable_dual_filter, 2082 !!(ctrls->sequence->flags & V4L2_AV1_SEQUENCE_FLAG_ENABLE_DUAL_FILTER)); 2083 hantro_reg_write(vpu, &av1_reduced_tx_set_used, 2084 !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_REDUCED_TX_SET)); 2085 hantro_reg_write(vpu, &av1_allow_screen_content_tools, 2086 !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_ALLOW_SCREEN_CONTENT_TOOLS)); 2087 hantro_reg_write(vpu, &av1_allow_intrabc, 2088 !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_ALLOW_INTRABC)); 2089 2090 if (!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_ALLOW_SCREEN_CONTENT_TOOLS)) 2091 hantro_reg_write(vpu, &av1_force_interger_mv, 0); 2092 else 2093 hantro_reg_write(vpu, &av1_force_interger_mv, 2094 !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_FORCE_INTEGER_MV)); 2095 2096 hantro_reg_write(vpu, &av1_blackwhite_e, 0); 2097 hantro_reg_write(vpu, &av1_delta_q_res_log, ctrls->frame->quantization.delta_q_res); 2098 hantro_reg_write(vpu, &av1_delta_q_present, 2099 !!(ctrls->frame->quantization.flags 2100 & V4L2_AV1_QUANTIZATION_FLAG_DELTA_Q_PRESENT)); 2101 2102 hantro_reg_write(vpu, &av1_idr_pic_e, IS_INTRA(ctrls->frame->frame_type)); 2103 hantro_reg_write(vpu, &av1_quant_base_qindex, ctrls->frame->quantization.base_q_idx); 2104 hantro_reg_write(vpu, &av1_bit_depth_y_minus8, ctx->bit_depth - 8); 2105 hantro_reg_write(vpu, &av1_bit_depth_c_minus8, ctx->bit_depth - 8); 2106 2107 hantro_reg_write(vpu, &av1_mcomp_filt_type, ctrls->frame->interpolation_filter); 2108 hantro_reg_write(vpu, &av1_high_prec_mv_e, 2109 !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_ALLOW_HIGH_PRECISION_MV)); 2110 hantro_reg_write(vpu, &av1_comp_pred_mode, 2111 (ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_REFERENCE_SELECT) ? 2 : 0); 2112 2113 tx_mode = rockchip_vpu981_av1_get_hardware_tx_mode(ctrls->frame->tx_mode); 2114 hantro_reg_write(vpu, &av1_transform_mode, tx_mode); 2115 hantro_reg_write(vpu, &av1_max_cb_size, 2116 (ctrls->sequence->flags 2117 & V4L2_AV1_SEQUENCE_FLAG_USE_128X128_SUPERBLOCK) ? 7 : 6); 2118 hantro_reg_write(vpu, &av1_min_cb_size, 3); 2119 2120 hantro_reg_write(vpu, &av1_comp_pred_fixed_ref, 0); 2121 hantro_reg_write(vpu, &av1_comp_pred_var_ref0_av1, 0); 2122 hantro_reg_write(vpu, &av1_comp_pred_var_ref1_av1, 0); 2123 hantro_reg_write(vpu, &av1_filt_level_seg0, 0); 2124 hantro_reg_write(vpu, &av1_filt_level_seg1, 0); 2125 hantro_reg_write(vpu, &av1_filt_level_seg2, 0); 2126 hantro_reg_write(vpu, &av1_filt_level_seg3, 0); 2127 hantro_reg_write(vpu, &av1_filt_level_seg4, 0); 2128 hantro_reg_write(vpu, &av1_filt_level_seg5, 0); 2129 hantro_reg_write(vpu, &av1_filt_level_seg6, 0); 2130 hantro_reg_write(vpu, &av1_filt_level_seg7, 0); 2131 2132 hantro_reg_write(vpu, &av1_qp_delta_y_dc_av1, ctrls->frame->quantization.delta_q_y_dc); 2133 hantro_reg_write(vpu, &av1_qp_delta_ch_dc_av1, ctrls->frame->quantization.delta_q_u_dc); 2134 hantro_reg_write(vpu, &av1_qp_delta_ch_ac_av1, ctrls->frame->quantization.delta_q_u_ac); 2135 if (ctrls->frame->quantization.flags & V4L2_AV1_QUANTIZATION_FLAG_USING_QMATRIX) { 2136 hantro_reg_write(vpu, &av1_qmlevel_y, ctrls->frame->quantization.qm_y); 2137 hantro_reg_write(vpu, &av1_qmlevel_u, ctrls->frame->quantization.qm_u); 2138 hantro_reg_write(vpu, &av1_qmlevel_v, ctrls->frame->quantization.qm_v); 2139 } else { 2140 hantro_reg_write(vpu, &av1_qmlevel_y, 0xff); 2141 hantro_reg_write(vpu, &av1_qmlevel_u, 0xff); 2142 hantro_reg_write(vpu, &av1_qmlevel_v, 0xff); 2143 } 2144 2145 hantro_reg_write(vpu, &av1_lossless_e, rockchip_vpu981_av1_dec_is_lossless(ctx)); 2146 hantro_reg_write(vpu, &av1_quant_delta_v_dc, ctrls->frame->quantization.delta_q_v_dc); 2147 hantro_reg_write(vpu, &av1_quant_delta_v_ac, ctrls->frame->quantization.delta_q_v_ac); 2148 2149 hantro_reg_write(vpu, &av1_skip_ref0, 2150 (ctrls->frame->skip_mode_frame[0]) ? ctrls->frame->skip_mode_frame[0] : 1); 2151 hantro_reg_write(vpu, &av1_skip_ref1, 2152 (ctrls->frame->skip_mode_frame[1]) ? ctrls->frame->skip_mode_frame[1] : 1); 2153 2154 hantro_write_addr(vpu, AV1_MC_SYNC_CURR, av1_dec->tile_buf.dma); 2155 hantro_write_addr(vpu, AV1_MC_SYNC_LEFT, av1_dec->tile_buf.dma); 2156 } 2157 2158 static void 2159 rockchip_vpu981_av1_dec_set_input_buffer(struct hantro_ctx *ctx, 2160 struct vb2_v4l2_buffer *vb2_src) 2161 { 2162 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 2163 struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls; 2164 const struct v4l2_ctrl_av1_tile_group_entry *group_entry = 2165 ctrls->tile_group_entry; 2166 struct hantro_dev *vpu = ctx->dev; 2167 dma_addr_t src_dma; 2168 u32 src_len, src_buf_len; 2169 int start_bit, offset; 2170 2171 src_dma = vb2_dma_contig_plane_dma_addr(&vb2_src->vb2_buf, 0); 2172 src_len = vb2_get_plane_payload(&vb2_src->vb2_buf, 0); 2173 src_buf_len = vb2_plane_size(&vb2_src->vb2_buf, 0); 2174 2175 start_bit = (group_entry[0].tile_offset & 0xf) * 8; 2176 offset = group_entry[0].tile_offset & ~0xf; 2177 2178 hantro_reg_write(vpu, &av1_strm_buffer_len, src_buf_len); 2179 hantro_reg_write(vpu, &av1_strm_start_bit, start_bit); 2180 hantro_reg_write(vpu, &av1_stream_len, src_len); 2181 hantro_reg_write(vpu, &av1_strm_start_offset, 0); 2182 hantro_write_addr(vpu, AV1_INPUT_STREAM, src_dma + offset); 2183 } 2184 2185 static void 2186 rockchip_vpu981_av1_dec_set_output_buffer(struct hantro_ctx *ctx) 2187 { 2188 struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec; 2189 struct hantro_dev *vpu = ctx->dev; 2190 struct hantro_decoded_buffer *dst; 2191 struct vb2_v4l2_buffer *vb2_dst; 2192 dma_addr_t luma_addr, chroma_addr, mv_addr = 0; 2193 size_t cr_offset = rockchip_vpu981_av1_dec_luma_size(ctx); 2194 size_t mv_offset = rockchip_vpu981_av1_dec_chroma_size(ctx); 2195 2196 vb2_dst = av1_dec->frame_refs[av1_dec->current_frame_index].vb2_ref; 2197 dst = vb2_to_hantro_decoded_buf(&vb2_dst->vb2_buf); 2198 luma_addr = hantro_get_dec_buf_addr(ctx, &dst->base.vb.vb2_buf); 2199 chroma_addr = luma_addr + cr_offset; 2200 mv_addr = luma_addr + mv_offset; 2201 2202 dst->av1.chroma_offset = cr_offset; 2203 dst->av1.mv_offset = mv_offset; 2204 2205 hantro_write_addr(vpu, AV1_TILE_OUT_LU, luma_addr); 2206 hantro_write_addr(vpu, AV1_TILE_OUT_CH, chroma_addr); 2207 hantro_write_addr(vpu, AV1_TILE_OUT_MV, mv_addr); 2208 } 2209 2210 int rockchip_vpu981_av1_dec_run(struct hantro_ctx *ctx) 2211 { 2212 struct hantro_dev *vpu = ctx->dev; 2213 struct vb2_v4l2_buffer *vb2_src; 2214 int ret; 2215 2216 hantro_start_prepare_run(ctx); 2217 2218 ret = rockchip_vpu981_av1_dec_prepare_run(ctx); 2219 if (ret) 2220 goto prepare_error; 2221 2222 vb2_src = hantro_get_src_buf(ctx); 2223 if (!vb2_src) { 2224 ret = -EINVAL; 2225 goto prepare_error; 2226 } 2227 2228 rockchip_vpu981_av1_dec_clean_refs(ctx); 2229 rockchip_vpu981_av1_dec_frame_ref(ctx, vb2_src->vb2_buf.timestamp); 2230 2231 rockchip_vpu981_av1_dec_set_parameters(ctx); 2232 rockchip_vpu981_av1_dec_set_global_model(ctx); 2233 rockchip_vpu981_av1_dec_set_tile_info(ctx); 2234 rockchip_vpu981_av1_dec_set_reference_frames(ctx); 2235 rockchip_vpu981_av1_dec_set_segmentation(ctx); 2236 rockchip_vpu981_av1_dec_set_loopfilter(ctx); 2237 rockchip_vpu981_av1_dec_set_picture_dimensions(ctx); 2238 rockchip_vpu981_av1_dec_set_cdef(ctx); 2239 rockchip_vpu981_av1_dec_set_lr(ctx); 2240 rockchip_vpu981_av1_dec_set_fgs(ctx); 2241 rockchip_vpu981_av1_dec_set_prob(ctx); 2242 2243 hantro_reg_write(vpu, &av1_dec_mode, AV1_DEC_MODE); 2244 hantro_reg_write(vpu, &av1_dec_out_ec_byte_word, 0); 2245 hantro_reg_write(vpu, &av1_write_mvs_e, 1); 2246 hantro_reg_write(vpu, &av1_dec_out_ec_bypass, 1); 2247 hantro_reg_write(vpu, &av1_dec_clk_gate_e, 1); 2248 2249 hantro_reg_write(vpu, &av1_dec_abort_e, 0); 2250 hantro_reg_write(vpu, &av1_dec_tile_int_e, 0); 2251 2252 hantro_reg_write(vpu, &av1_dec_alignment, 64); 2253 hantro_reg_write(vpu, &av1_apf_disable, 0); 2254 hantro_reg_write(vpu, &av1_apf_threshold, 8); 2255 hantro_reg_write(vpu, &av1_dec_buswidth, 2); 2256 hantro_reg_write(vpu, &av1_dec_max_burst, 16); 2257 hantro_reg_write(vpu, &av1_error_conceal_e, 0); 2258 hantro_reg_write(vpu, &av1_axi_rd_ostd_threshold, 64); 2259 hantro_reg_write(vpu, &av1_axi_wr_ostd_threshold, 64); 2260 2261 hantro_reg_write(vpu, &av1_ext_timeout_cycles, 0xfffffff); 2262 hantro_reg_write(vpu, &av1_ext_timeout_override_e, 1); 2263 hantro_reg_write(vpu, &av1_timeout_cycles, 0xfffffff); 2264 hantro_reg_write(vpu, &av1_timeout_override_e, 1); 2265 2266 rockchip_vpu981_av1_dec_set_output_buffer(ctx); 2267 rockchip_vpu981_av1_dec_set_input_buffer(ctx, vb2_src); 2268 2269 hantro_end_prepare_run(ctx); 2270 2271 hantro_reg_write(vpu, &av1_dec_e, 1); 2272 2273 return 0; 2274 2275 prepare_error: 2276 hantro_end_prepare_run(ctx); 2277 hantro_irq_done(vpu, VB2_BUF_STATE_ERROR); 2278 return ret; 2279 } 2280 2281 static void rockchip_vpu981_postproc_enable(struct hantro_ctx *ctx) 2282 { 2283 struct hantro_dev *vpu = ctx->dev; 2284 int width = ctx->dst_fmt.width; 2285 int height = ctx->dst_fmt.height; 2286 struct vb2_v4l2_buffer *vb2_dst; 2287 size_t chroma_offset; 2288 dma_addr_t dst_dma; 2289 2290 vb2_dst = hantro_get_dst_buf(ctx); 2291 2292 dst_dma = vb2_dma_contig_plane_dma_addr(&vb2_dst->vb2_buf, 0); 2293 chroma_offset = ctx->dst_fmt.plane_fmt[0].bytesperline * 2294 ctx->dst_fmt.height; 2295 2296 /* enable post processor */ 2297 hantro_reg_write(vpu, &av1_pp_out_e, 1); 2298 hantro_reg_write(vpu, &av1_pp_in_format, 0); 2299 hantro_reg_write(vpu, &av1_pp0_dup_hor, 1); 2300 hantro_reg_write(vpu, &av1_pp0_dup_ver, 1); 2301 2302 hantro_reg_write(vpu, &av1_pp_in_height, height / 2); 2303 hantro_reg_write(vpu, &av1_pp_in_width, width / 2); 2304 hantro_reg_write(vpu, &av1_pp_out_height, height); 2305 hantro_reg_write(vpu, &av1_pp_out_width, width); 2306 hantro_reg_write(vpu, &av1_pp_out_y_stride, 2307 ctx->dst_fmt.plane_fmt[0].bytesperline); 2308 hantro_reg_write(vpu, &av1_pp_out_c_stride, 2309 ctx->dst_fmt.plane_fmt[0].bytesperline); 2310 switch (ctx->dst_fmt.pixelformat) { 2311 case V4L2_PIX_FMT_P010: 2312 hantro_reg_write(vpu, &av1_pp_out_format, 1); 2313 break; 2314 case V4L2_PIX_FMT_NV12: 2315 hantro_reg_write(vpu, &av1_pp_out_format, 3); 2316 break; 2317 case V4L2_PIX_FMT_NV15: 2318 /* this mapping is RK specific */ 2319 hantro_reg_write(vpu, &av1_pp_out_format, 10); 2320 break; 2321 default: 2322 hantro_reg_write(vpu, &av1_pp_out_format, 0); 2323 } 2324 2325 hantro_reg_write(vpu, &av1_ppd_blend_exist, 0); 2326 hantro_reg_write(vpu, &av1_ppd_dith_exist, 0); 2327 hantro_reg_write(vpu, &av1_ablend_crop_e, 0); 2328 hantro_reg_write(vpu, &av1_pp_format_customer1_e, 0); 2329 hantro_reg_write(vpu, &av1_pp_crop_exist, 0); 2330 hantro_reg_write(vpu, &av1_pp_up_level, 0); 2331 hantro_reg_write(vpu, &av1_pp_down_level, 0); 2332 hantro_reg_write(vpu, &av1_pp_exist, 0); 2333 2334 hantro_write_addr(vpu, AV1_PP_OUT_LU, dst_dma); 2335 hantro_write_addr(vpu, AV1_PP_OUT_CH, dst_dma + chroma_offset); 2336 } 2337 2338 static void rockchip_vpu981_postproc_disable(struct hantro_ctx *ctx) 2339 { 2340 struct hantro_dev *vpu = ctx->dev; 2341 2342 /* disable post processor */ 2343 hantro_reg_write(vpu, &av1_pp_out_e, 0); 2344 } 2345 2346 const struct hantro_postproc_ops rockchip_vpu981_postproc_ops = { 2347 .enable = rockchip_vpu981_postproc_enable, 2348 .disable = rockchip_vpu981_postproc_disable, 2349 }; 2350