1 /*
2 * 8259 interrupt controller emulation
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2007 Intel Corporation
6 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 * Authors:
26 * Yaozu (Eddie) Dong <Eddie.dong@intel.com>
27 * Port from Qemu.
28 */
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <linux/mm.h>
32 #include <linux/slab.h>
33 #include <linux/bitops.h>
34
35 #include "ioapic.h"
36 #include "irq.h"
37
38 #include <linux/kvm_host.h>
39 #include "trace.h"
40
41 #define pr_pic_unimpl(fmt, ...) \
42 pr_err_ratelimited("pic: " fmt, ## __VA_ARGS__)
43
44 static void pic_irq_request(struct kvm *kvm, int level);
45
pic_lock(struct kvm_pic * s)46 static void pic_lock(struct kvm_pic *s)
47 __acquires(&s->lock)
48 {
49 spin_lock(&s->lock);
50 }
51
pic_unlock(struct kvm_pic * s)52 static void pic_unlock(struct kvm_pic *s)
53 __releases(&s->lock)
54 {
55 bool wakeup = s->wakeup_needed;
56 struct kvm_vcpu *vcpu;
57 unsigned long i;
58
59 s->wakeup_needed = false;
60
61 spin_unlock(&s->lock);
62
63 if (wakeup) {
64 kvm_for_each_vcpu(i, vcpu, s->kvm) {
65 if (kvm_apic_accept_pic_intr(vcpu)) {
66 kvm_make_request(KVM_REQ_EVENT, vcpu);
67 kvm_vcpu_kick(vcpu);
68 return;
69 }
70 }
71 }
72 }
73
pic_clear_isr(struct kvm_kpic_state * s,int irq)74 static void pic_clear_isr(struct kvm_kpic_state *s, int irq)
75 {
76 s->isr &= ~(1 << irq);
77 if (s != &s->pics_state->pics[0])
78 irq += 8;
79 /*
80 * We are dropping lock while calling ack notifiers since ack
81 * notifier callbacks for assigned devices call into PIC recursively.
82 * Other interrupt may be delivered to PIC while lock is dropped but
83 * it should be safe since PIC state is already updated at this stage.
84 */
85 pic_unlock(s->pics_state);
86 kvm_notify_acked_irq(s->pics_state->kvm, SELECT_PIC(irq), irq);
87 pic_lock(s->pics_state);
88 }
89
90 /*
91 * set irq level. If an edge is detected, then the IRR is set to 1
92 */
pic_set_irq1(struct kvm_kpic_state * s,int irq,int level)93 static inline int pic_set_irq1(struct kvm_kpic_state *s, int irq, int level)
94 {
95 int mask, ret = 1;
96 mask = 1 << irq;
97 if (s->elcr & mask) /* level triggered */
98 if (level) {
99 ret = !(s->irr & mask);
100 s->irr |= mask;
101 s->last_irr |= mask;
102 } else {
103 s->irr &= ~mask;
104 s->last_irr &= ~mask;
105 }
106 else /* edge triggered */
107 if (level) {
108 if ((s->last_irr & mask) == 0) {
109 ret = !(s->irr & mask);
110 s->irr |= mask;
111 }
112 s->last_irr |= mask;
113 } else
114 s->last_irr &= ~mask;
115
116 return (s->imr & mask) ? -1 : ret;
117 }
118
119 /*
120 * return the highest priority found in mask (highest = smallest
121 * number). Return 8 if no irq
122 */
get_priority(struct kvm_kpic_state * s,int mask)123 static inline int get_priority(struct kvm_kpic_state *s, int mask)
124 {
125 int priority;
126 if (mask == 0)
127 return 8;
128 priority = 0;
129 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
130 priority++;
131 return priority;
132 }
133
134 /*
135 * return the pic wanted interrupt. return -1 if none
136 */
pic_get_irq(struct kvm_kpic_state * s)137 static int pic_get_irq(struct kvm_kpic_state *s)
138 {
139 int mask, cur_priority, priority;
140
141 mask = s->irr & ~s->imr;
142 priority = get_priority(s, mask);
143 if (priority == 8)
144 return -1;
145 /*
146 * compute current priority. If special fully nested mode on the
147 * master, the IRQ coming from the slave is not taken into account
148 * for the priority computation.
149 */
150 mask = s->isr;
151 if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
152 mask &= ~(1 << 2);
153 cur_priority = get_priority(s, mask);
154 if (priority < cur_priority)
155 /*
156 * higher priority found: an irq should be generated
157 */
158 return (priority + s->priority_add) & 7;
159 else
160 return -1;
161 }
162
163 /*
164 * raise irq to CPU if necessary. must be called every time the active
165 * irq may change
166 */
pic_update_irq(struct kvm_pic * s)167 static void pic_update_irq(struct kvm_pic *s)
168 {
169 int irq2, irq;
170
171 irq2 = pic_get_irq(&s->pics[1]);
172 if (irq2 >= 0) {
173 /*
174 * if irq request by slave pic, signal master PIC
175 */
176 pic_set_irq1(&s->pics[0], 2, 1);
177 pic_set_irq1(&s->pics[0], 2, 0);
178 }
179 irq = pic_get_irq(&s->pics[0]);
180 pic_irq_request(s->kvm, irq >= 0);
181 }
182
kvm_pic_update_irq(struct kvm_pic * s)183 void kvm_pic_update_irq(struct kvm_pic *s)
184 {
185 pic_lock(s);
186 pic_update_irq(s);
187 pic_unlock(s);
188 }
189
kvm_pic_set_irq(struct kvm_kernel_irq_routing_entry * e,struct kvm * kvm,int irq_source_id,int level,bool line_status)190 int kvm_pic_set_irq(struct kvm_kernel_irq_routing_entry *e, struct kvm *kvm,
191 int irq_source_id, int level, bool line_status)
192 {
193 struct kvm_pic *s = kvm->arch.vpic;
194 int irq = e->irqchip.pin;
195 int ret, irq_level;
196
197 if (WARN_ON_ONCE(irq < 0 || irq >= PIC_NUM_PINS))
198 return -1;
199
200 pic_lock(s);
201 irq_level = __kvm_irq_line_state(&s->irq_states[irq],
202 irq_source_id, level);
203 ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, irq_level);
204 pic_update_irq(s);
205 trace_kvm_pic_set_irq(irq >> 3, irq & 7, s->pics[irq >> 3].elcr,
206 s->pics[irq >> 3].imr, ret == 0);
207 pic_unlock(s);
208
209 return ret;
210 }
211
212 /*
213 * acknowledge interrupt 'irq'
214 */
pic_intack(struct kvm_kpic_state * s,int irq)215 static inline void pic_intack(struct kvm_kpic_state *s, int irq)
216 {
217 s->isr |= 1 << irq;
218 /*
219 * We don't clear a level sensitive interrupt here
220 */
221 if (!(s->elcr & (1 << irq)))
222 s->irr &= ~(1 << irq);
223
224 if (s->auto_eoi) {
225 if (s->rotate_on_auto_eoi)
226 s->priority_add = (irq + 1) & 7;
227 pic_clear_isr(s, irq);
228 }
229
230 }
231
kvm_pic_read_irq(struct kvm * kvm)232 int kvm_pic_read_irq(struct kvm *kvm)
233 {
234 int irq, irq2, intno;
235 struct kvm_pic *s = kvm->arch.vpic;
236
237 s->output = 0;
238
239 pic_lock(s);
240 irq = pic_get_irq(&s->pics[0]);
241 if (irq >= 0) {
242 pic_intack(&s->pics[0], irq);
243 if (irq == 2) {
244 irq2 = pic_get_irq(&s->pics[1]);
245 if (irq2 >= 0)
246 pic_intack(&s->pics[1], irq2);
247 else
248 /*
249 * spurious IRQ on slave controller
250 */
251 irq2 = 7;
252 intno = s->pics[1].irq_base + irq2;
253 } else
254 intno = s->pics[0].irq_base + irq;
255 } else {
256 /*
257 * spurious IRQ on host controller
258 */
259 irq = 7;
260 intno = s->pics[0].irq_base + irq;
261 }
262 pic_update_irq(s);
263 pic_unlock(s);
264
265 return intno;
266 }
267
kvm_pic_reset(struct kvm_kpic_state * s)268 static void kvm_pic_reset(struct kvm_kpic_state *s)
269 {
270 int irq;
271 unsigned long i;
272 struct kvm_vcpu *vcpu;
273 u8 edge_irr = s->irr & ~s->elcr;
274 bool found = false;
275
276 s->last_irr = 0;
277 s->irr &= s->elcr;
278 s->imr = 0;
279 s->priority_add = 0;
280 s->special_mask = 0;
281 s->read_reg_select = 0;
282 if (!s->init4) {
283 s->special_fully_nested_mode = 0;
284 s->auto_eoi = 0;
285 }
286 s->init_state = 1;
287
288 kvm_for_each_vcpu(i, vcpu, s->pics_state->kvm)
289 if (kvm_apic_accept_pic_intr(vcpu)) {
290 found = true;
291 break;
292 }
293
294
295 if (!found)
296 return;
297
298 for (irq = 0; irq < PIC_NUM_PINS/2; irq++)
299 if (edge_irr & (1 << irq))
300 pic_clear_isr(s, irq);
301 }
302
pic_ioport_write(void * opaque,u32 addr,u32 val)303 static void pic_ioport_write(void *opaque, u32 addr, u32 val)
304 {
305 struct kvm_kpic_state *s = opaque;
306 int priority, cmd, irq;
307
308 addr &= 1;
309 if (addr == 0) {
310 if (val & 0x10) {
311 s->init4 = val & 1;
312 if (val & 0x02)
313 pr_pic_unimpl("single mode not supported");
314 if (val & 0x08)
315 pr_pic_unimpl(
316 "level sensitive irq not supported");
317 kvm_pic_reset(s);
318 } else if (val & 0x08) {
319 if (val & 0x04)
320 s->poll = 1;
321 if (val & 0x02)
322 s->read_reg_select = val & 1;
323 if (val & 0x40)
324 s->special_mask = (val >> 5) & 1;
325 } else {
326 cmd = val >> 5;
327 switch (cmd) {
328 case 0:
329 case 4:
330 s->rotate_on_auto_eoi = cmd >> 2;
331 break;
332 case 1: /* end of interrupt */
333 case 5:
334 priority = get_priority(s, s->isr);
335 if (priority != 8) {
336 irq = (priority + s->priority_add) & 7;
337 if (cmd == 5)
338 s->priority_add = (irq + 1) & 7;
339 pic_clear_isr(s, irq);
340 pic_update_irq(s->pics_state);
341 }
342 break;
343 case 3:
344 irq = val & 7;
345 pic_clear_isr(s, irq);
346 pic_update_irq(s->pics_state);
347 break;
348 case 6:
349 s->priority_add = (val + 1) & 7;
350 pic_update_irq(s->pics_state);
351 break;
352 case 7:
353 irq = val & 7;
354 s->priority_add = (irq + 1) & 7;
355 pic_clear_isr(s, irq);
356 pic_update_irq(s->pics_state);
357 break;
358 default:
359 break; /* no operation */
360 }
361 }
362 } else
363 switch (s->init_state) {
364 case 0: { /* normal mode */
365 u8 imr_diff = s->imr ^ val,
366 off = (s == &s->pics_state->pics[0]) ? 0 : 8;
367 s->imr = val;
368 for (irq = 0; irq < PIC_NUM_PINS/2; irq++)
369 if (imr_diff & (1 << irq))
370 kvm_fire_mask_notifiers(
371 s->pics_state->kvm,
372 SELECT_PIC(irq + off),
373 irq + off,
374 !!(s->imr & (1 << irq)));
375 pic_update_irq(s->pics_state);
376 break;
377 }
378 case 1:
379 s->irq_base = val & 0xf8;
380 s->init_state = 2;
381 break;
382 case 2:
383 if (s->init4)
384 s->init_state = 3;
385 else
386 s->init_state = 0;
387 break;
388 case 3:
389 s->special_fully_nested_mode = (val >> 4) & 1;
390 s->auto_eoi = (val >> 1) & 1;
391 s->init_state = 0;
392 break;
393 }
394 }
395
pic_poll_read(struct kvm_kpic_state * s,u32 addr1)396 static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1)
397 {
398 int ret;
399
400 ret = pic_get_irq(s);
401 if (ret >= 0) {
402 if (addr1 >> 7) {
403 s->pics_state->pics[0].isr &= ~(1 << 2);
404 s->pics_state->pics[0].irr &= ~(1 << 2);
405 }
406 s->irr &= ~(1 << ret);
407 pic_clear_isr(s, ret);
408 if (addr1 >> 7 || ret != 2)
409 pic_update_irq(s->pics_state);
410 /* Bit 7 is 1, means there's an interrupt */
411 ret |= 0x80;
412 } else {
413 /* Bit 7 is 0, means there's no interrupt */
414 ret = 0x07;
415 pic_update_irq(s->pics_state);
416 }
417
418 return ret;
419 }
420
pic_ioport_read(void * opaque,u32 addr)421 static u32 pic_ioport_read(void *opaque, u32 addr)
422 {
423 struct kvm_kpic_state *s = opaque;
424 int ret;
425
426 if (s->poll) {
427 ret = pic_poll_read(s, addr);
428 s->poll = 0;
429 } else
430 if ((addr & 1) == 0)
431 if (s->read_reg_select)
432 ret = s->isr;
433 else
434 ret = s->irr;
435 else
436 ret = s->imr;
437 return ret;
438 }
439
elcr_ioport_write(void * opaque,u32 val)440 static void elcr_ioport_write(void *opaque, u32 val)
441 {
442 struct kvm_kpic_state *s = opaque;
443 s->elcr = val & s->elcr_mask;
444 }
445
elcr_ioport_read(void * opaque)446 static u32 elcr_ioport_read(void *opaque)
447 {
448 struct kvm_kpic_state *s = opaque;
449 return s->elcr;
450 }
451
picdev_write(struct kvm_pic * s,gpa_t addr,int len,const void * val)452 static int picdev_write(struct kvm_pic *s,
453 gpa_t addr, int len, const void *val)
454 {
455 unsigned char data = *(unsigned char *)val;
456
457 if (len != 1) {
458 pr_pic_unimpl("non byte write\n");
459 return 0;
460 }
461 switch (addr) {
462 case 0x20:
463 case 0x21:
464 pic_lock(s);
465 pic_ioport_write(&s->pics[0], addr, data);
466 pic_unlock(s);
467 break;
468 case 0xa0:
469 case 0xa1:
470 pic_lock(s);
471 pic_ioport_write(&s->pics[1], addr, data);
472 pic_unlock(s);
473 break;
474 case 0x4d0:
475 case 0x4d1:
476 pic_lock(s);
477 elcr_ioport_write(&s->pics[addr & 1], data);
478 pic_unlock(s);
479 break;
480 default:
481 return -EOPNOTSUPP;
482 }
483 return 0;
484 }
485
picdev_read(struct kvm_pic * s,gpa_t addr,int len,void * val)486 static int picdev_read(struct kvm_pic *s,
487 gpa_t addr, int len, void *val)
488 {
489 unsigned char *data = (unsigned char *)val;
490
491 if (len != 1) {
492 memset(val, 0, len);
493 pr_pic_unimpl("non byte read\n");
494 return 0;
495 }
496 switch (addr) {
497 case 0x20:
498 case 0x21:
499 case 0xa0:
500 case 0xa1:
501 pic_lock(s);
502 *data = pic_ioport_read(&s->pics[addr >> 7], addr);
503 pic_unlock(s);
504 break;
505 case 0x4d0:
506 case 0x4d1:
507 pic_lock(s);
508 *data = elcr_ioport_read(&s->pics[addr & 1]);
509 pic_unlock(s);
510 break;
511 default:
512 return -EOPNOTSUPP;
513 }
514 return 0;
515 }
516
picdev_master_write(struct kvm_vcpu * vcpu,struct kvm_io_device * dev,gpa_t addr,int len,const void * val)517 static int picdev_master_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
518 gpa_t addr, int len, const void *val)
519 {
520 return picdev_write(container_of(dev, struct kvm_pic, dev_master),
521 addr, len, val);
522 }
523
picdev_master_read(struct kvm_vcpu * vcpu,struct kvm_io_device * dev,gpa_t addr,int len,void * val)524 static int picdev_master_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
525 gpa_t addr, int len, void *val)
526 {
527 return picdev_read(container_of(dev, struct kvm_pic, dev_master),
528 addr, len, val);
529 }
530
picdev_slave_write(struct kvm_vcpu * vcpu,struct kvm_io_device * dev,gpa_t addr,int len,const void * val)531 static int picdev_slave_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
532 gpa_t addr, int len, const void *val)
533 {
534 return picdev_write(container_of(dev, struct kvm_pic, dev_slave),
535 addr, len, val);
536 }
537
picdev_slave_read(struct kvm_vcpu * vcpu,struct kvm_io_device * dev,gpa_t addr,int len,void * val)538 static int picdev_slave_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
539 gpa_t addr, int len, void *val)
540 {
541 return picdev_read(container_of(dev, struct kvm_pic, dev_slave),
542 addr, len, val);
543 }
544
picdev_elcr_write(struct kvm_vcpu * vcpu,struct kvm_io_device * dev,gpa_t addr,int len,const void * val)545 static int picdev_elcr_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
546 gpa_t addr, int len, const void *val)
547 {
548 return picdev_write(container_of(dev, struct kvm_pic, dev_elcr),
549 addr, len, val);
550 }
551
picdev_elcr_read(struct kvm_vcpu * vcpu,struct kvm_io_device * dev,gpa_t addr,int len,void * val)552 static int picdev_elcr_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
553 gpa_t addr, int len, void *val)
554 {
555 return picdev_read(container_of(dev, struct kvm_pic, dev_elcr),
556 addr, len, val);
557 }
558
559 /*
560 * callback when PIC0 irq status changed
561 */
pic_irq_request(struct kvm * kvm,int level)562 static void pic_irq_request(struct kvm *kvm, int level)
563 {
564 struct kvm_pic *s = kvm->arch.vpic;
565
566 if (!s->output && level)
567 s->wakeup_needed = true;
568 s->output = level;
569 }
570
571 static const struct kvm_io_device_ops picdev_master_ops = {
572 .read = picdev_master_read,
573 .write = picdev_master_write,
574 };
575
576 static const struct kvm_io_device_ops picdev_slave_ops = {
577 .read = picdev_slave_read,
578 .write = picdev_slave_write,
579 };
580
581 static const struct kvm_io_device_ops picdev_elcr_ops = {
582 .read = picdev_elcr_read,
583 .write = picdev_elcr_write,
584 };
585
kvm_pic_init(struct kvm * kvm)586 int kvm_pic_init(struct kvm *kvm)
587 {
588 struct kvm_pic *s;
589 int ret;
590
591 s = kzalloc_obj(struct kvm_pic, GFP_KERNEL_ACCOUNT);
592 if (!s)
593 return -ENOMEM;
594 spin_lock_init(&s->lock);
595 s->kvm = kvm;
596 s->pics[0].elcr_mask = 0xf8;
597 s->pics[1].elcr_mask = 0xde;
598 s->pics[0].pics_state = s;
599 s->pics[1].pics_state = s;
600
601 /*
602 * Initialize PIO device
603 */
604 kvm_iodevice_init(&s->dev_master, &picdev_master_ops);
605 kvm_iodevice_init(&s->dev_slave, &picdev_slave_ops);
606 kvm_iodevice_init(&s->dev_elcr, &picdev_elcr_ops);
607 mutex_lock(&kvm->slots_lock);
608 ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, 0x20, 2,
609 &s->dev_master);
610 if (ret < 0)
611 goto fail_unlock;
612
613 ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, 0xa0, 2, &s->dev_slave);
614 if (ret < 0)
615 goto fail_unreg_2;
616
617 ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, 0x4d0, 2, &s->dev_elcr);
618 if (ret < 0)
619 goto fail_unreg_1;
620
621 mutex_unlock(&kvm->slots_lock);
622
623 kvm->arch.vpic = s;
624
625 return 0;
626
627 fail_unreg_1:
628 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &s->dev_slave);
629
630 fail_unreg_2:
631 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &s->dev_master);
632
633 fail_unlock:
634 mutex_unlock(&kvm->slots_lock);
635
636 kfree(s);
637
638 return ret;
639 }
640
kvm_pic_destroy(struct kvm * kvm)641 void kvm_pic_destroy(struct kvm *kvm)
642 {
643 struct kvm_pic *vpic = kvm->arch.vpic;
644
645 if (!vpic)
646 return;
647
648 mutex_lock(&kvm->slots_lock);
649 kvm_io_bus_unregister_dev(vpic->kvm, KVM_PIO_BUS, &vpic->dev_master);
650 kvm_io_bus_unregister_dev(vpic->kvm, KVM_PIO_BUS, &vpic->dev_slave);
651 kvm_io_bus_unregister_dev(vpic->kvm, KVM_PIO_BUS, &vpic->dev_elcr);
652 mutex_unlock(&kvm->slots_lock);
653
654 kvm->arch.vpic = NULL;
655 kfree(vpic);
656 }
657