1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * OPEN Alliance 10BASE‑T1x MAC‑PHY Serial Interface framework 4 * 5 * Author: Parthiban Veerasooran <parthiban.veerasooran@microchip.com> 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/delay.h> 10 #include <linux/gpio/consumer.h> 11 #include <linux/iopoll.h> 12 #include <linux/interrupt.h> 13 #include <linux/mdio.h> 14 #include <linux/phy.h> 15 #include <linux/oa_tc6.h> 16 17 /* Control command header */ 18 #define OA_TC6_CTRL_HEADER_DATA_NOT_CTRL BIT(31) 19 #define OA_TC6_CTRL_HEADER_WRITE_NOT_READ BIT(29) 20 #define OA_TC6_CTRL_HEADER_MEM_MAP_SELECTOR GENMASK(27, 24) 21 #define OA_TC6_CTRL_HEADER_ADDR GENMASK(23, 8) 22 #define OA_TC6_CTRL_HEADER_LENGTH GENMASK(7, 1) 23 #define OA_TC6_CTRL_HEADER_PARITY BIT(0) 24 25 /* Data header */ 26 #define OA_TC6_DATA_HEADER_DATA_NOT_CTRL BIT(31) 27 #define OA_TC6_DATA_HEADER_DATA_VALID BIT(21) 28 #define OA_TC6_DATA_HEADER_START_VALID BIT(20) 29 #define OA_TC6_DATA_HEADER_START_WORD_OFFSET GENMASK(19, 16) 30 #define OA_TC6_DATA_HEADER_END_VALID BIT(14) 31 #define OA_TC6_DATA_HEADER_END_BYTE_OFFSET GENMASK(13, 8) 32 #define OA_TC6_DATA_HEADER_PARITY BIT(0) 33 34 /* Data footer */ 35 #define OA_TC6_DATA_FOOTER_EXTENDED_STS BIT(31) 36 #define OA_TC6_DATA_FOOTER_RXD_HEADER_BAD BIT(30) 37 #define OA_TC6_DATA_FOOTER_CONFIG_SYNC BIT(29) 38 #define OA_TC6_DATA_FOOTER_RX_CHUNKS GENMASK(28, 24) 39 #define OA_TC6_DATA_FOOTER_DATA_VALID BIT(21) 40 #define OA_TC6_DATA_FOOTER_START_VALID BIT(20) 41 #define OA_TC6_DATA_FOOTER_START_WORD_OFFSET GENMASK(19, 16) 42 #define OA_TC6_DATA_FOOTER_END_VALID BIT(14) 43 #define OA_TC6_DATA_FOOTER_END_BYTE_OFFSET GENMASK(13, 8) 44 #define OA_TC6_DATA_FOOTER_TX_CREDITS GENMASK(5, 1) 45 46 #define OA_TC6_CTRL_PROT_REPLY_SIZE 4 47 #define OA_TC6_CTRL_HEADER_SIZE 4 48 #define OA_TC6_CTRL_REG_VALUE_SIZE 4 49 #define OA_TC6_CTRL_IGNORED_SIZE 4 50 #define OA_TC6_CTRL_MAX_REGISTERS 128 51 #define OA_TC6_CTRL_SPI_BUF_SIZE (OA_TC6_CTRL_HEADER_SIZE +\ 52 (OA_TC6_CTRL_MAX_REGISTERS *\ 53 (OA_TC6_CTRL_REG_VALUE_SIZE +\ 54 OA_TC6_CTRL_PROT_REPLY_SIZE)) +\ 55 OA_TC6_CTRL_IGNORED_SIZE) 56 57 #define OA_TC6_CHUNK_PAYLOAD_SIZE 64 58 #define OA_TC6_DATA_HEADER_SIZE 4 59 #define OA_TC6_CHUNK_SIZE (OA_TC6_DATA_HEADER_SIZE +\ 60 OA_TC6_CHUNK_PAYLOAD_SIZE) 61 #define OA_TC6_MAX_TX_CHUNKS 48 62 #define OA_TC6_SPI_DATA_BUF_SIZE (OA_TC6_MAX_TX_CHUNKS *\ 63 OA_TC6_CHUNK_SIZE) 64 #define STATUS0_RESETC_POLL_DELAY 1000 65 #define STATUS0_RESETC_POLL_TIMEOUT 1000000 66 67 #define OA_TC6_REG_MMS_MASK GENMASK(19, 16) 68 69 /* Internal structure for MAC-PHY drivers */ 70 struct oa_tc6 { 71 struct net_device *netdev; 72 struct phy_device *phydev; 73 struct mii_bus *mdiobus; 74 struct spi_device *spi; 75 struct mutex spi_ctrl_lock; /* Protects spi control transfer */ 76 spinlock_t tx_skb_lock; /* Protects tx skb handling */ 77 void *spi_ctrl_tx_buf; 78 void *spi_ctrl_rx_buf; 79 void *spi_data_tx_buf; 80 void *spi_data_rx_buf; 81 struct sk_buff *ongoing_tx_skb; 82 struct sk_buff *waiting_tx_skb; 83 struct sk_buff *rx_skb; 84 u16 tx_skb_offset; 85 u16 spi_data_tx_buf_offset; 86 u16 tx_credits; 87 u8 rx_chunks_available; 88 bool wait_until_start_valid; 89 bool int_flag; 90 bool disable_traffic; 91 bool prot_ctrl; 92 enum oa_tc6_quirk_flag quirk_flags; 93 struct gpio_desc *reset_gpio; 94 }; 95 96 enum oa_tc6_header_type { 97 OA_TC6_CTRL_HEADER, 98 OA_TC6_DATA_HEADER, 99 }; 100 101 enum oa_tc6_register_op { 102 OA_TC6_CTRL_REG_READ = 0, 103 OA_TC6_CTRL_REG_WRITE = 1, 104 }; 105 106 enum oa_tc6_data_valid_info { 107 OA_TC6_DATA_INVALID, 108 OA_TC6_DATA_VALID, 109 }; 110 111 enum oa_tc6_data_start_valid_info { 112 OA_TC6_DATA_START_INVALID, 113 OA_TC6_DATA_START_VALID, 114 }; 115 116 enum oa_tc6_data_end_valid_info { 117 OA_TC6_DATA_END_INVALID, 118 OA_TC6_DATA_END_VALID, 119 }; 120 121 static int oa_tc6_spi_transfer(struct oa_tc6 *tc6, 122 enum oa_tc6_header_type header_type, u16 length) 123 { 124 struct spi_transfer xfer = { 0 }; 125 struct spi_message msg; 126 127 if (header_type == OA_TC6_DATA_HEADER) { 128 xfer.tx_buf = tc6->spi_data_tx_buf; 129 xfer.rx_buf = tc6->spi_data_rx_buf; 130 } else { 131 xfer.tx_buf = tc6->spi_ctrl_tx_buf; 132 xfer.rx_buf = tc6->spi_ctrl_rx_buf; 133 } 134 xfer.len = length; 135 136 spi_message_init(&msg); 137 spi_message_add_tail(&xfer, &msg); 138 139 return spi_sync(tc6->spi, &msg); 140 } 141 142 static int oa_tc6_get_parity(u32 p) 143 { 144 /* Public domain code snippet, lifted from 145 * http://www-graphics.stanford.edu/~seander/bithacks.html 146 */ 147 p ^= p >> 1; 148 p ^= p >> 2; 149 p = (p & 0x11111111U) * 0x11111111U; 150 151 /* Odd parity is used here */ 152 return !((p >> 28) & 1); 153 } 154 155 static __be32 oa_tc6_prepare_ctrl_header(u32 addr, u8 length, 156 enum oa_tc6_register_op reg_op) 157 { 158 u32 header; 159 160 header = FIELD_PREP(OA_TC6_CTRL_HEADER_DATA_NOT_CTRL, 161 OA_TC6_CTRL_HEADER) | 162 FIELD_PREP(OA_TC6_CTRL_HEADER_WRITE_NOT_READ, reg_op) | 163 FIELD_PREP(OA_TC6_CTRL_HEADER_MEM_MAP_SELECTOR, addr >> 16) | 164 FIELD_PREP(OA_TC6_CTRL_HEADER_ADDR, addr) | 165 FIELD_PREP(OA_TC6_CTRL_HEADER_LENGTH, length - 1); 166 header |= FIELD_PREP(OA_TC6_CTRL_HEADER_PARITY, 167 oa_tc6_get_parity(header)); 168 169 return cpu_to_be32(header); 170 } 171 172 static void oa_tc6_update_ctrl_write_data(struct oa_tc6 *tc6, u32 value[], 173 u8 length) 174 { 175 __be32 *tx_buf = tc6->spi_ctrl_tx_buf + OA_TC6_CTRL_HEADER_SIZE; 176 177 for (int i = 0; i < length; i++) { 178 *tx_buf++ = cpu_to_be32(value[i]); 179 if (tc6->prot_ctrl) 180 *tx_buf++ = cpu_to_be32(~value[i]); 181 } 182 } 183 184 static u16 oa_tc6_calculate_ctrl_buf_size(u8 length, bool ctrl_prot) 185 { 186 u32 reply_size = OA_TC6_CTRL_REG_VALUE_SIZE; 187 188 if (ctrl_prot) 189 reply_size += OA_TC6_CTRL_PROT_REPLY_SIZE; 190 191 /* Control command consists 4 bytes header + 4 bytes register value for 192 * each register (+ 4 bytes for the register value complement in case 193 * protected mode is used) + 4 bytes ignored value. 194 */ 195 return OA_TC6_CTRL_HEADER_SIZE + reply_size * length + 196 OA_TC6_CTRL_IGNORED_SIZE; 197 } 198 199 static void oa_tc6_prepare_ctrl_spi_buf(struct oa_tc6 *tc6, u32 address, 200 u32 value[], u8 length, 201 enum oa_tc6_register_op reg_op, 202 u16 buf_size) 203 { 204 __be32 *tx_buf = tc6->spi_ctrl_tx_buf; 205 206 memset(tx_buf, 0, buf_size); 207 *tx_buf = oa_tc6_prepare_ctrl_header(address, length, reg_op); 208 209 if (reg_op == OA_TC6_CTRL_REG_WRITE) 210 oa_tc6_update_ctrl_write_data(tc6, value, length); 211 } 212 213 static int oa_tc6_check_ctrl_write_reply(struct oa_tc6 *tc6, u8 size) 214 { 215 u8 *tx_buf = tc6->spi_ctrl_tx_buf; 216 u8 *rx_buf = tc6->spi_ctrl_rx_buf; 217 218 rx_buf += OA_TC6_CTRL_IGNORED_SIZE; 219 220 /* The echoed control write must match with the one that was 221 * transmitted. 222 */ 223 if (memcmp(tx_buf, rx_buf, size - OA_TC6_CTRL_IGNORED_SIZE)) 224 return -EPROTO; 225 226 return 0; 227 } 228 229 static int oa_tc6_check_ctrl_read_reply(struct oa_tc6 *tc6, u8 length) 230 { 231 __be32 *rx_buf = tc6->spi_ctrl_rx_buf + OA_TC6_CTRL_IGNORED_SIZE; 232 __be32 *tx_buf = tc6->spi_ctrl_tx_buf; 233 u32 complement; 234 u32 reply; 235 236 /* The echoed control read header must match with the one that was 237 * transmitted. 238 */ 239 if (*tx_buf != *rx_buf) 240 return -EPROTO; 241 242 if (tc6->prot_ctrl) { 243 /* Skip past the echoed header to the value/complement pairs */ 244 rx_buf += 1; 245 for (int i = 0; i < length; i++) { 246 reply = be32_to_cpu(rx_buf[0]); 247 complement = be32_to_cpu(rx_buf[1]); 248 249 if (complement != ~reply) 250 return -EPROTO; 251 252 rx_buf += 2; 253 } 254 } 255 256 return 0; 257 } 258 259 static void oa_tc6_copy_ctrl_read_data(struct oa_tc6 *tc6, u32 value[], 260 u8 length) 261 { 262 __be32 *rx_buf = tc6->spi_ctrl_rx_buf + OA_TC6_CTRL_IGNORED_SIZE + 263 OA_TC6_CTRL_HEADER_SIZE; 264 265 for (int i = 0; i < length; i++) { 266 value[i] = be32_to_cpu(*rx_buf++); 267 268 /* skip complement word */ 269 if (tc6->prot_ctrl) 270 rx_buf++; 271 } 272 } 273 274 static int oa_tc6_perform_ctrl(struct oa_tc6 *tc6, u32 address, u32 value[], 275 u8 length, enum oa_tc6_register_op reg_op) 276 { 277 u16 size; 278 int ret; 279 280 size = oa_tc6_calculate_ctrl_buf_size(length, tc6->prot_ctrl); 281 282 /* Prepare control command and copy to SPI control buffer */ 283 oa_tc6_prepare_ctrl_spi_buf(tc6, address, value, length, reg_op, size); 284 285 /* Perform SPI transfer */ 286 ret = oa_tc6_spi_transfer(tc6, OA_TC6_CTRL_HEADER, size); 287 if (ret) { 288 dev_err(&tc6->spi->dev, "SPI transfer failed for control: %d\n", 289 ret); 290 return ret; 291 } 292 293 /* Check echoed/received control write command reply for errors */ 294 if (reg_op == OA_TC6_CTRL_REG_WRITE) 295 return oa_tc6_check_ctrl_write_reply(tc6, size); 296 297 /* Check echoed/received control read command reply for errors */ 298 ret = oa_tc6_check_ctrl_read_reply(tc6, length); 299 if (ret) 300 return ret; 301 302 oa_tc6_copy_ctrl_read_data(tc6, value, length); 303 304 return 0; 305 } 306 307 /** 308 * oa_tc6_read_registers - function for reading multiple consecutive registers. 309 * @tc6: oa_tc6 struct. 310 * @address: address of the first register to be read in the MAC-PHY. 311 * @value: values to be read from the starting register address @address. 312 * @length: number of consecutive registers to be read from @address. 313 * 314 * Maximum of 128 consecutive registers can be read starting at @address. 315 * 316 * Return: 0 on success otherwise failed. 317 */ 318 int oa_tc6_read_registers(struct oa_tc6 *tc6, u32 address, u32 value[], 319 u8 length) 320 { 321 int ret; 322 323 if (!length || length > OA_TC6_CTRL_MAX_REGISTERS) { 324 dev_err(&tc6->spi->dev, "Invalid register length parameter\n"); 325 return -EINVAL; 326 } 327 328 mutex_lock(&tc6->spi_ctrl_lock); 329 ret = oa_tc6_perform_ctrl(tc6, address, value, length, 330 OA_TC6_CTRL_REG_READ); 331 mutex_unlock(&tc6->spi_ctrl_lock); 332 333 return ret; 334 } 335 EXPORT_SYMBOL_GPL(oa_tc6_read_registers); 336 337 /** 338 * oa_tc6_read_register - function for reading a MAC-PHY register. 339 * @tc6: oa_tc6 struct. 340 * @address: register address of the MAC-PHY to be read. 341 * @value: value read from the @address register address of the MAC-PHY. 342 * 343 * Return: 0 on success otherwise failed. 344 */ 345 int oa_tc6_read_register(struct oa_tc6 *tc6, u32 address, u32 *value) 346 { 347 return oa_tc6_read_registers(tc6, address, value, 1); 348 } 349 EXPORT_SYMBOL_GPL(oa_tc6_read_register); 350 351 /** 352 * oa_tc6_read_register_mms - function for reading a MAC-PHY register in a 353 * specified memory map. 354 * @tc6: oa_tc6 struct. 355 * @mms: Memory map selector for the register. 356 * @address: register address of the MAC-PHY to be read. 357 * @value: value read from the @address register address of the MAC-PHY. 358 * 359 * Return: 0 on success or a negative error code on failure. 360 */ 361 int oa_tc6_read_register_mms(struct oa_tc6 *tc6, u8 mms, u16 address, 362 u32 *value) 363 { 364 u32 mms_reg; 365 366 mms_reg = FIELD_PREP(OA_TC6_REG_MMS_MASK, mms) | address; 367 368 return oa_tc6_read_registers(tc6, mms_reg, value, 1); 369 } 370 EXPORT_SYMBOL_GPL(oa_tc6_read_register_mms); 371 372 /** 373 * oa_tc6_write_registers - function for writing multiple consecutive registers. 374 * @tc6: oa_tc6 struct. 375 * @address: address of the first register to be written in the MAC-PHY. 376 * @value: values to be written from the starting register address @address. 377 * @length: number of consecutive registers to be written from @address. 378 * 379 * Maximum of 128 consecutive registers can be written starting at @address. 380 * 381 * Return: 0 on success otherwise failed. 382 */ 383 int oa_tc6_write_registers(struct oa_tc6 *tc6, u32 address, u32 value[], 384 u8 length) 385 { 386 int ret; 387 388 if (!length || length > OA_TC6_CTRL_MAX_REGISTERS) { 389 dev_err(&tc6->spi->dev, "Invalid register length parameter\n"); 390 return -EINVAL; 391 } 392 393 mutex_lock(&tc6->spi_ctrl_lock); 394 ret = oa_tc6_perform_ctrl(tc6, address, value, length, 395 OA_TC6_CTRL_REG_WRITE); 396 mutex_unlock(&tc6->spi_ctrl_lock); 397 398 return ret; 399 } 400 EXPORT_SYMBOL_GPL(oa_tc6_write_registers); 401 402 /** 403 * oa_tc6_write_register - function for writing a MAC-PHY register. 404 * @tc6: oa_tc6 struct. 405 * @address: register address of the MAC-PHY to be written. 406 * @value: value to be written in the @address register address of the MAC-PHY. 407 * 408 * Return: 0 on success otherwise failed. 409 */ 410 int oa_tc6_write_register(struct oa_tc6 *tc6, u32 address, u32 value) 411 { 412 return oa_tc6_write_registers(tc6, address, &value, 1); 413 } 414 EXPORT_SYMBOL_GPL(oa_tc6_write_register); 415 416 /** 417 * oa_tc6_write_register_mms - function for writing a MAC-PHY register in a 418 * specified memory map. 419 * @tc6: oa_tc6 struct. 420 * @mms: Memory map selector for the register. 421 * @address: register address of the MAC-PHY to be written. 422 * @value: value to be written in the @address register address of the MAC-PHY. 423 * 424 * Return: 0 on success or a negative error code on failure. 425 */ 426 int oa_tc6_write_register_mms(struct oa_tc6 *tc6, u8 mms, u16 address, 427 u32 value) 428 { 429 u32 mms_reg; 430 431 mms_reg = FIELD_PREP(OA_TC6_REG_MMS_MASK, mms) | address; 432 433 return oa_tc6_write_registers(tc6, mms_reg, &value, 1); 434 } 435 EXPORT_SYMBOL_GPL(oa_tc6_write_register_mms); 436 437 static int oa_tc6_check_phy_reg_direct_access_capability(struct oa_tc6 *tc6) 438 { 439 u32 regval; 440 int ret; 441 442 ret = oa_tc6_read_register(tc6, OA_TC6_REG_STDCAP, ®val); 443 if (ret) 444 return ret; 445 446 if (!(regval & OA_TC6_STDCAP_DIRECT_PHY_REG_ACCESS)) 447 return -ENODEV; 448 449 return 0; 450 } 451 452 static void oa_tc6_handle_link_change(struct net_device *netdev) 453 { 454 phy_print_status(netdev->phydev); 455 } 456 457 static int oa_tc6_mdiobus_read(struct mii_bus *bus, int addr, int regnum) 458 { 459 struct oa_tc6 *tc6 = bus->priv; 460 u32 regval; 461 int ret; 462 463 ret = oa_tc6_read_register(tc6, OA_TC6_PHY_STD_REG_ADDR_BASE | 464 (regnum & OA_TC6_PHY_STD_REG_ADDR_MASK), 465 ®val); 466 if (ret) 467 return ret; 468 469 return regval; 470 } 471 472 static int oa_tc6_mdiobus_write(struct mii_bus *bus, int addr, int regnum, 473 u16 val) 474 { 475 struct oa_tc6 *tc6 = bus->priv; 476 477 return oa_tc6_write_register(tc6, OA_TC6_PHY_STD_REG_ADDR_BASE | 478 (regnum & OA_TC6_PHY_STD_REG_ADDR_MASK), 479 val); 480 } 481 482 static int oa_tc6_get_phy_c45_mms(int devnum) 483 { 484 switch (devnum) { 485 case MDIO_MMD_PCS: 486 return OA_TC6_PHY_C45_PCS_MMS2; 487 case MDIO_MMD_PMAPMD: 488 return OA_TC6_PHY_C45_PMA_PMD_MMS3; 489 case MDIO_MMD_VEND2: 490 return OA_TC6_PHY_C45_VS_PLCA_MMS4; 491 case MDIO_MMD_AN: 492 return OA_TC6_PHY_C45_AUTO_NEG_MMS5; 493 case MDIO_MMD_POWER_UNIT: 494 return OA_TC6_PHY_C45_POWER_UNIT_MMS6; 495 default: 496 return -EOPNOTSUPP; 497 } 498 } 499 500 int oa_tc6_mdiobus_read_c45(struct mii_bus *bus, int addr, int devnum, 501 int regnum) 502 { 503 struct oa_tc6 *tc6 = bus->priv; 504 u32 regval; 505 int mms; 506 int ret; 507 508 mms = oa_tc6_get_phy_c45_mms(devnum); 509 if (mms < 0) 510 return mms; 511 512 ret = oa_tc6_read_register_mms(tc6, mms, regnum, ®val); 513 if (ret) 514 return ret; 515 516 return regval; 517 } 518 EXPORT_SYMBOL_GPL(oa_tc6_mdiobus_read_c45); 519 520 int oa_tc6_mdiobus_write_c45(struct mii_bus *bus, int addr, int devnum, 521 int regnum, u16 val) 522 { 523 struct oa_tc6 *tc6 = bus->priv; 524 int mms; 525 526 mms = oa_tc6_get_phy_c45_mms(devnum); 527 if (mms < 0) 528 return mms; 529 530 return oa_tc6_write_register_mms(tc6, mms, regnum, val); 531 } 532 EXPORT_SYMBOL_GPL(oa_tc6_mdiobus_write_c45); 533 534 static int oa_tc6_mdiobus_register(struct oa_tc6 *tc6) 535 { 536 int ret; 537 538 tc6->mdiobus = mdiobus_alloc(); 539 if (!tc6->mdiobus) { 540 netdev_err(tc6->netdev, "MDIO bus alloc failed\n"); 541 return -ENOMEM; 542 } 543 544 tc6->mdiobus->priv = tc6; 545 tc6->mdiobus->read = oa_tc6_mdiobus_read; 546 tc6->mdiobus->write = oa_tc6_mdiobus_write; 547 /* OPEN Alliance 10BASE-T1x compliance MAC-PHYs will have both C22 and 548 * C45 registers space. If the PHY is discovered via C22 bus protocol it 549 * assumes it uses C22 protocol and always uses C22 registers indirect 550 * access to access C45 registers. This is because, we don't have a 551 * clean separation between C22/C45 register space and C22/C45 MDIO bus 552 * protocols. Resulting, PHY C45 registers direct access can't be used 553 * which can save multiple SPI bus access. To support this feature, PHY 554 * drivers can set .read_mmd/.write_mmd in the PHY driver to call 555 * .read_c45/.write_c45. Ex: drivers/net/phy/microchip_t1s.c 556 */ 557 tc6->mdiobus->read_c45 = oa_tc6_mdiobus_read_c45; 558 tc6->mdiobus->write_c45 = oa_tc6_mdiobus_write_c45; 559 tc6->mdiobus->name = "oa-tc6-mdiobus"; 560 tc6->mdiobus->parent = &tc6->spi->dev; 561 562 snprintf(tc6->mdiobus->id, ARRAY_SIZE(tc6->mdiobus->id), "%s", 563 dev_name(&tc6->spi->dev)); 564 565 ret = mdiobus_register(tc6->mdiobus); 566 if (ret) { 567 netdev_err(tc6->netdev, "Could not register MDIO bus\n"); 568 mdiobus_free(tc6->mdiobus); 569 return ret; 570 } 571 572 return 0; 573 } 574 575 static void oa_tc6_mdiobus_unregister(struct oa_tc6 *tc6) 576 { 577 mdiobus_unregister(tc6->mdiobus); 578 mdiobus_free(tc6->mdiobus); 579 } 580 581 static int oa_tc6_phy_init(struct oa_tc6 *tc6) 582 { 583 int ret; 584 585 if (tc6->quirk_flags & OA_TC6_BROKEN_PHY) 586 return 0; 587 588 ret = oa_tc6_check_phy_reg_direct_access_capability(tc6); 589 if (ret) { 590 netdev_err(tc6->netdev, 591 "Direct PHY register access is not supported by the MAC-PHY\n"); 592 return ret; 593 } 594 595 ret = oa_tc6_mdiobus_register(tc6); 596 if (ret) 597 return ret; 598 599 tc6->phydev = phy_find_first(tc6->mdiobus); 600 if (!tc6->phydev) { 601 netdev_err(tc6->netdev, "No PHY found\n"); 602 oa_tc6_mdiobus_unregister(tc6); 603 return -ENODEV; 604 } 605 606 tc6->phydev->is_internal = true; 607 ret = phy_connect_direct(tc6->netdev, tc6->phydev, 608 &oa_tc6_handle_link_change, 609 PHY_INTERFACE_MODE_INTERNAL); 610 if (ret) { 611 netdev_err(tc6->netdev, "Can't attach PHY to %s\n", 612 tc6->mdiobus->id); 613 oa_tc6_mdiobus_unregister(tc6); 614 return ret; 615 } 616 617 phy_attached_info(tc6->netdev->phydev); 618 619 return 0; 620 } 621 622 static void oa_tc6_phy_exit(struct oa_tc6 *tc6) 623 { 624 if (tc6->quirk_flags & OA_TC6_BROKEN_PHY) 625 return; 626 627 phy_disconnect(tc6->phydev); 628 oa_tc6_mdiobus_unregister(tc6); 629 } 630 631 static int oa_tc6_read_status0(struct oa_tc6 *tc6) 632 { 633 u32 regval; 634 int ret; 635 636 ret = oa_tc6_read_register(tc6, OA_TC6_REG_STATUS0, ®val); 637 if (ret) { 638 dev_err(&tc6->spi->dev, "STATUS0 register read failed: %d\n", 639 ret); 640 return 0; 641 } 642 643 return regval; 644 } 645 646 static int oa_tc6_sw_reset_macphy(struct oa_tc6 *tc6) 647 { 648 u32 regval = OA_TC6_RESET_SWRESET; 649 int ret; 650 651 ret = oa_tc6_write_register(tc6, OA_TC6_REG_RESET, regval); 652 if (ret) 653 return ret; 654 655 /* Poll for soft reset complete for every 1ms until 1s timeout */ 656 ret = readx_poll_timeout(oa_tc6_read_status0, tc6, regval, 657 regval & OA_TC6_STATUS0_RESETC, 658 STATUS0_RESETC_POLL_DELAY, 659 STATUS0_RESETC_POLL_TIMEOUT); 660 if (ret) 661 return -ENODEV; 662 663 /* Clear the reset complete status */ 664 return oa_tc6_write_register(tc6, OA_TC6_REG_STATUS0, regval); 665 } 666 667 static int oa_tc6_unmask_macphy_error_interrupts(struct oa_tc6 *tc6) 668 { 669 u32 regval; 670 int ret; 671 672 ret = oa_tc6_read_register(tc6, OA_TC6_REG_INT_MASK0, ®val); 673 if (ret) 674 return ret; 675 676 regval &= ~(OA_TC6_INT_MASK0_TX_PROTOCOL_ERR_MASK | 677 OA_TC6_INT_MASK0_RX_BUFFER_OVERFLOW_ERR_MASK | 678 OA_TC6_INT_MASK0_LOSS_OF_FRAME_ERR_MASK | 679 OA_TC6_INT_MASK0_HEADER_ERR_MASK); 680 681 return oa_tc6_write_register(tc6, OA_TC6_REG_INT_MASK0, regval); 682 } 683 684 static int oa_tc6_enable_data_transfer(struct oa_tc6 *tc6) 685 { 686 u32 value; 687 int ret; 688 689 ret = oa_tc6_read_register(tc6, OA_TC6_REG_CONFIG0, &value); 690 if (ret) 691 return ret; 692 693 /* Enable configuration synchronization for data transfer */ 694 value |= OA_TC6_CONFIG0_SYNC; 695 696 return oa_tc6_write_register(tc6, OA_TC6_REG_CONFIG0, value); 697 } 698 699 /* Called when a frame that is meant to be transmitted, is dropped. */ 700 static void oa_tc6_drop_tx_skb(struct oa_tc6 *tc6, struct sk_buff *skb) 701 { 702 if (skb) { 703 tc6->netdev->stats.tx_dropped++; 704 dev_kfree_skb_any(skb); 705 } 706 } 707 708 static struct sk_buff *oa_tc6_detach_waiting_tx_skb(struct oa_tc6 *tc6) 709 { 710 struct sk_buff *skb; 711 712 lockdep_assert_held(&tc6->tx_skb_lock); 713 skb = tc6->waiting_tx_skb; 714 tc6->waiting_tx_skb = NULL; 715 716 return skb; 717 } 718 719 static void oa_tc6_cleanup_ongoing_rx_skb(struct oa_tc6 *tc6) 720 { 721 if (tc6->rx_skb) { 722 tc6->netdev->stats.rx_dropped++; 723 kfree_skb(tc6->rx_skb); 724 tc6->rx_skb = NULL; 725 } 726 } 727 728 static void oa_tc6_cleanup_ongoing_tx_skb(struct oa_tc6 *tc6) 729 { 730 oa_tc6_drop_tx_skb(tc6, tc6->ongoing_tx_skb); 731 tc6->ongoing_tx_skb = NULL; 732 } 733 734 static void oa_tc6_cleanup_waiting_tx_skb(struct oa_tc6 *tc6) 735 { 736 struct sk_buff *skb; 737 738 spin_lock_bh(&tc6->tx_skb_lock); 739 skb = oa_tc6_detach_waiting_tx_skb(tc6); 740 spin_unlock_bh(&tc6->tx_skb_lock); 741 742 oa_tc6_drop_tx_skb(tc6, skb); 743 } 744 745 static void oa_tc6_free_ongoing_skbs(struct oa_tc6 *tc6) 746 { 747 oa_tc6_cleanup_ongoing_tx_skb(tc6); 748 oa_tc6_cleanup_ongoing_rx_skb(tc6); 749 } 750 751 static void oa_tc6_free_pending_skbs(struct oa_tc6 *tc6) 752 { 753 oa_tc6_free_ongoing_skbs(tc6); 754 oa_tc6_cleanup_waiting_tx_skb(tc6); 755 } 756 757 static void oa_tc6_look_for_new_frame(struct oa_tc6 *tc6) 758 { 759 tc6->wait_until_start_valid = true; 760 oa_tc6_cleanup_ongoing_rx_skb(tc6); 761 } 762 763 /* If the failure is at SPI interface level, masking and clearing 764 * the interrupt of the device won't work. Since SPI interrupt is 765 * disabled, it should stop the repeated interrupts. 766 */ 767 static void oa_tc6_disable_traffic(struct oa_tc6 *tc6) 768 { 769 u32 regval = OA_TC6_INT_MASK0_ALL_INTERRUPTS; 770 struct sk_buff *skb; 771 772 spin_lock_bh(&tc6->tx_skb_lock); 773 tc6->disable_traffic = true; 774 skb = oa_tc6_detach_waiting_tx_skb(tc6); 775 spin_unlock_bh(&tc6->tx_skb_lock); 776 777 /* disable_traffic, when set, is a point of no return to 778 * working state. Keeping the TX queues disabled. 779 */ 780 netif_tx_disable(tc6->netdev); 781 oa_tc6_drop_tx_skb(tc6, skb); 782 oa_tc6_free_ongoing_skbs(tc6); 783 oa_tc6_write_register(tc6, OA_TC6_REG_INT_MASK0, regval); 784 oa_tc6_read_register(tc6, OA_TC6_REG_STATUS0, ®val); 785 oa_tc6_write_register(tc6, OA_TC6_REG_STATUS0, regval); 786 dev_err(&tc6->spi->dev, "Device interrupt disabled to avoid interrupt storm"); 787 } 788 789 static int oa_tc6_process_extended_status(struct oa_tc6 *tc6) 790 { 791 u32 value; 792 int ret; 793 794 ret = oa_tc6_read_register(tc6, OA_TC6_REG_STATUS0, &value); 795 if (ret) { 796 netdev_err(tc6->netdev, "STATUS0 register read failed: %d\n", 797 ret); 798 return ret; 799 } 800 801 /* This function is called for each chunk received in a given SPI 802 * transaction. In case, extended status bit is set in more than 803 * one chunk, skip the write, if status0 is already cleared. 804 */ 805 if (!value) 806 return 0; 807 808 /* Clear the error interrupts status */ 809 ret = oa_tc6_write_register(tc6, OA_TC6_REG_STATUS0, value); 810 if (ret) { 811 netdev_err(tc6->netdev, "STATUS0 register write failed: %d\n", 812 ret); 813 return ret; 814 } 815 816 if (FIELD_GET(OA_TC6_STATUS0_RX_BUFFER_OVERFLOW_ERROR, value)) { 817 oa_tc6_look_for_new_frame(tc6); 818 net_err_ratelimited("%s: Receive buffer overflow error\n", 819 tc6->netdev->name); 820 return -EAGAIN; 821 } 822 if (FIELD_GET(OA_TC6_STATUS0_TX_PROTOCOL_ERROR, value)) { 823 netdev_err(tc6->netdev, "Transmit protocol error\n"); 824 return -ENODEV; 825 } 826 /* TODO: Currently loss of frame and header errors are treated as 827 * non-recoverable errors. They will be handled in the next version. 828 */ 829 if (FIELD_GET(OA_TC6_STATUS0_LOSS_OF_FRAME_ERROR, value)) { 830 netdev_err(tc6->netdev, "Loss of frame error\n"); 831 return -ENODEV; 832 } 833 if (FIELD_GET(OA_TC6_STATUS0_HEADER_ERROR, value)) { 834 netdev_err(tc6->netdev, "Header error\n"); 835 return -ENODEV; 836 } 837 838 return 0; 839 } 840 841 static int oa_tc6_process_rx_chunk_footer(struct oa_tc6 *tc6, u32 footer) 842 { 843 int ret = 0; 844 845 /* Process rx chunk footer for the following, 846 * 1. tx credits 847 * 2. errors if any from MAC-PHY 848 * 3. receive chunks available 849 */ 850 tc6->tx_credits = FIELD_GET(OA_TC6_DATA_FOOTER_TX_CREDITS, footer); 851 tc6->rx_chunks_available = FIELD_GET(OA_TC6_DATA_FOOTER_RX_CHUNKS, 852 footer); 853 854 if (FIELD_GET(OA_TC6_DATA_FOOTER_EXTENDED_STS, footer)) { 855 ret = oa_tc6_process_extended_status(tc6); 856 /* EAGAIN error is recoverable. Move on to check 857 * HEADER and SYNC errors before returning. 858 */ 859 if (ret && ret != -EAGAIN) 860 return ret; 861 } 862 863 /* TODO: Currently received header bad and configuration unsync errors 864 * are treated as non-recoverable errors. They will be handled in the 865 * next version. 866 */ 867 if (FIELD_GET(OA_TC6_DATA_FOOTER_RXD_HEADER_BAD, footer)) { 868 netdev_err(tc6->netdev, "Rxd header bad error\n"); 869 return -ENODEV; 870 } 871 872 if (!FIELD_GET(OA_TC6_DATA_FOOTER_CONFIG_SYNC, footer)) { 873 netdev_err(tc6->netdev, "Config unsync error\n"); 874 return -ENODEV; 875 } 876 877 return ret; 878 } 879 880 static void oa_tc6_submit_rx_skb(struct oa_tc6 *tc6) 881 { 882 /* MAC-PHY delivers each frame with its Ethernet FCS attached. 883 * Strip it before handing over to the stack, unless the user 884 * has asked to keep it via NETIF_F_RXFCS. Keeping the FCS 885 * in the frame is harmless for IP traffic, but is parsed as 886 * a (malformed) suffix TLV by PTP, which makes ptp4l reject 887 * every message with "bad message" error. 888 */ 889 if (!(tc6->netdev->features & NETIF_F_RXFCS) && 890 tc6->rx_skb->len > ETH_FCS_LEN) 891 skb_trim(tc6->rx_skb, tc6->rx_skb->len - ETH_FCS_LEN); 892 893 tc6->rx_skb->protocol = eth_type_trans(tc6->rx_skb, tc6->netdev); 894 tc6->netdev->stats.rx_packets++; 895 tc6->netdev->stats.rx_bytes += tc6->rx_skb->len; 896 897 netif_rx(tc6->rx_skb); 898 899 tc6->rx_skb = NULL; 900 } 901 902 /* On oversubscribed traffic condition, particularly with overwhelming rx 903 * buffer overflow errors, there could be data chunk loss. If tail + length 904 * goes beyond end pointer, that is an indication that the data chunk with 905 * end_valid bit is lost. Time to look for a data chunk with start_valid bit. 906 * 907 * If rx_skb is NULL, it is time to start looking for data chunk with 908 * start_bit. 909 */ 910 static int oa_tc6_update_rx_skb(struct oa_tc6 *tc6, u8 *payload, u8 length) 911 { 912 if (!tc6->rx_skb || 913 skb_tailroom(tc6->rx_skb) < length) { 914 oa_tc6_look_for_new_frame(tc6); 915 return -EAGAIN; 916 } 917 918 memcpy(skb_put(tc6->rx_skb, length), payload, length); 919 return 0; 920 } 921 922 /* On overwhelming rx buffer overflow errors, due to data chunk loss, it is 923 * possible that we get two data chunks with start_valid bit set, without 924 * end_valid bit set in between. In this case, rx_skb would have a valid 925 * buffer pointer. We should release, if a valid pointer is found before 926 * allocating a new one. 927 */ 928 static int oa_tc6_allocate_rx_skb(struct oa_tc6 *tc6) 929 { 930 oa_tc6_cleanup_ongoing_rx_skb(tc6); 931 tc6->rx_skb = netdev_alloc_skb_ip_align(tc6->netdev, tc6->netdev->mtu + 932 ETH_HLEN + ETH_FCS_LEN); 933 if (!tc6->rx_skb) { 934 tc6->netdev->stats.rx_dropped++; 935 return -ENOMEM; 936 } 937 938 return 0; 939 } 940 941 static int oa_tc6_prcs_complete_rx_frame(struct oa_tc6 *tc6, u8 *payload, 942 u16 size) 943 { 944 int ret; 945 946 ret = oa_tc6_allocate_rx_skb(tc6); 947 if (ret) 948 return ret; 949 950 ret = oa_tc6_update_rx_skb(tc6, payload, size); 951 if (ret) 952 return ret; 953 954 oa_tc6_submit_rx_skb(tc6); 955 956 return 0; 957 } 958 959 static int oa_tc6_prcs_rx_frame_start(struct oa_tc6 *tc6, u8 *payload, u16 size) 960 { 961 int ret; 962 963 ret = oa_tc6_allocate_rx_skb(tc6); 964 if (ret) 965 return ret; 966 967 return oa_tc6_update_rx_skb(tc6, payload, size); 968 } 969 970 static int oa_tc6_prcs_rx_frame_end(struct oa_tc6 *tc6, u8 *payload, u16 size) 971 { 972 int ret; 973 974 ret = oa_tc6_update_rx_skb(tc6, payload, size); 975 if (!ret) 976 oa_tc6_submit_rx_skb(tc6); 977 return ret; 978 } 979 980 static int oa_tc6_prcs_ongoing_rx_frame(struct oa_tc6 *tc6, u8 *payload, 981 u32 footer) 982 { 983 return oa_tc6_update_rx_skb(tc6, payload, 984 OA_TC6_CHUNK_PAYLOAD_SIZE); 985 } 986 987 static int oa_tc6_prcs_rx_chunk_payload(struct oa_tc6 *tc6, u8 *data, 988 u32 footer) 989 { 990 u8 start_byte_offset = FIELD_GET(OA_TC6_DATA_FOOTER_START_WORD_OFFSET, 991 footer) * sizeof(u32); 992 u8 end_byte_offset = FIELD_GET(OA_TC6_DATA_FOOTER_END_BYTE_OFFSET, 993 footer); 994 bool start_valid = FIELD_GET(OA_TC6_DATA_FOOTER_START_VALID, footer); 995 bool end_valid = FIELD_GET(OA_TC6_DATA_FOOTER_END_VALID, footer); 996 u16 size; 997 998 /* Restart the new rx frame after receiving rx buffer overflow error */ 999 if (start_valid && tc6->wait_until_start_valid) 1000 tc6->wait_until_start_valid = false; 1001 1002 if (tc6->wait_until_start_valid) 1003 return 0; 1004 1005 /* Process the chunk with complete rx frame */ 1006 if (start_valid && end_valid && start_byte_offset < end_byte_offset) { 1007 size = end_byte_offset + 1 - start_byte_offset; 1008 return oa_tc6_prcs_complete_rx_frame(tc6, 1009 &data[start_byte_offset], 1010 size); 1011 } 1012 1013 /* Process the chunk with only rx frame start */ 1014 if (start_valid && !end_valid) { 1015 size = OA_TC6_CHUNK_PAYLOAD_SIZE - start_byte_offset; 1016 return oa_tc6_prcs_rx_frame_start(tc6, 1017 &data[start_byte_offset], 1018 size); 1019 } 1020 1021 /* Process the chunk with only rx frame end */ 1022 if (end_valid && !start_valid) { 1023 size = end_byte_offset + 1; 1024 return oa_tc6_prcs_rx_frame_end(tc6, data, size); 1025 } 1026 1027 /* Process the chunk with previous rx frame end and next rx frame 1028 * start. 1029 */ 1030 if (start_valid && end_valid && start_byte_offset > end_byte_offset) { 1031 /* After rx buffer overflow error received, there might be a 1032 * possibility of getting an end valid of a previously 1033 * incomplete rx frame along with the new rx frame start valid. 1034 */ 1035 if (tc6->rx_skb) { 1036 size = end_byte_offset + 1; 1037 oa_tc6_prcs_rx_frame_end(tc6, data, size); 1038 1039 /* Return value from oa_tc6_prcs_rx_frame_end is not 1040 * checked. If it returned an error, it is to make 1041 * the code to look for new frame. At this stage, 1042 * code below is going to process a new frame. So, 1043 * error condition is set to false, in case it is 1044 * set before proceeding. 1045 */ 1046 tc6->wait_until_start_valid = false; 1047 } 1048 size = OA_TC6_CHUNK_PAYLOAD_SIZE - start_byte_offset; 1049 return oa_tc6_prcs_rx_frame_start(tc6, 1050 &data[start_byte_offset], 1051 size); 1052 } 1053 1054 /* Process the chunk with ongoing rx frame data */ 1055 return oa_tc6_prcs_ongoing_rx_frame(tc6, data, footer); 1056 } 1057 1058 static u32 oa_tc6_get_rx_chunk_footer(struct oa_tc6 *tc6, u16 footer_offset) 1059 { 1060 u8 *rx_buf = tc6->spi_data_rx_buf; 1061 __be32 footer; 1062 1063 footer = *((__be32 *)&rx_buf[footer_offset]); 1064 1065 return be32_to_cpu(footer); 1066 } 1067 1068 static int oa_tc6_process_spi_data_rx_buf(struct oa_tc6 *tc6, u16 length) 1069 { 1070 u16 no_of_rx_chunks = length / OA_TC6_CHUNK_SIZE; 1071 bool retry = false; 1072 int ret = 0; 1073 u32 footer; 1074 1075 /* All the rx chunks in the receive SPI data buffer are examined here */ 1076 for (int i = 0; i < no_of_rx_chunks; i++) { 1077 /* Last 4 bytes in each received chunk consist footer info */ 1078 footer = oa_tc6_get_rx_chunk_footer(tc6, i * OA_TC6_CHUNK_SIZE + 1079 OA_TC6_CHUNK_PAYLOAD_SIZE); 1080 1081 ret = oa_tc6_process_rx_chunk_footer(tc6, footer); 1082 if (ret) { 1083 if (ret != -EAGAIN) 1084 return ret; 1085 retry = true; 1086 } 1087 1088 /* If there is a data valid chunks then process it for the 1089 * information needed to determine the validity and the location 1090 * of the receive frame data. 1091 */ 1092 if (FIELD_GET(OA_TC6_DATA_FOOTER_DATA_VALID, footer)) { 1093 u8 *payload = tc6->spi_data_rx_buf + i * 1094 OA_TC6_CHUNK_SIZE; 1095 1096 ret = oa_tc6_prcs_rx_chunk_payload(tc6, payload, 1097 footer); 1098 if (ret) { 1099 if (ret != -ENOMEM && ret != -EAGAIN) 1100 return ret; 1101 retry = true; 1102 } 1103 } 1104 } 1105 1106 /* Not bailing out on recoverable error codes, -EAGAIN and 1107 * -ENOMEM. If subsequent loop iterations, if any, succeeds, 1108 * error code would be overwritten. retry flag helps to 1109 * make the caller to continue and retry. Since recovery 1110 * action for -ENOMEM and -EAGAIN are same, we are returning 1111 * one of the error codes, that is -EAGAIN. 1112 * 1113 * Successful recovery depends on how small the frames are, 1114 * how many chunks, among the received chunks triggered the 1115 * error, whether data is intact even with error conditions. 1116 * As a result, there is no single, best method to recover 1117 * most data when error conditions hit. We do our best by 1118 * processing all the chunks with good "footer header" and 1119 * "data valid" bit set. 1120 */ 1121 if (retry) { 1122 ret = -EAGAIN; 1123 oa_tc6_look_for_new_frame(tc6); 1124 } 1125 1126 return ret; 1127 } 1128 1129 static __be32 oa_tc6_prepare_data_header(bool data_valid, bool start_valid, 1130 bool end_valid, u8 end_byte_offset) 1131 { 1132 u32 header = FIELD_PREP(OA_TC6_DATA_HEADER_DATA_NOT_CTRL, 1133 OA_TC6_DATA_HEADER) | 1134 FIELD_PREP(OA_TC6_DATA_HEADER_DATA_VALID, data_valid) | 1135 FIELD_PREP(OA_TC6_DATA_HEADER_START_VALID, start_valid) | 1136 FIELD_PREP(OA_TC6_DATA_HEADER_END_VALID, end_valid) | 1137 FIELD_PREP(OA_TC6_DATA_HEADER_END_BYTE_OFFSET, 1138 end_byte_offset); 1139 1140 header |= FIELD_PREP(OA_TC6_DATA_HEADER_PARITY, 1141 oa_tc6_get_parity(header)); 1142 1143 return cpu_to_be32(header); 1144 } 1145 1146 static void oa_tc6_add_tx_skb_to_spi_buf(struct oa_tc6 *tc6) 1147 { 1148 enum oa_tc6_data_end_valid_info end_valid = OA_TC6_DATA_END_INVALID; 1149 __be32 *tx_buf = tc6->spi_data_tx_buf + tc6->spi_data_tx_buf_offset; 1150 u16 remaining_len = tc6->ongoing_tx_skb->len - tc6->tx_skb_offset; 1151 u8 *tx_skb_data = tc6->ongoing_tx_skb->data + tc6->tx_skb_offset; 1152 enum oa_tc6_data_start_valid_info start_valid; 1153 u8 end_byte_offset = 0; 1154 u16 length_to_copy; 1155 1156 /* Initial value is assigned here to avoid more than 80 characters in 1157 * the declaration place. 1158 */ 1159 start_valid = OA_TC6_DATA_START_INVALID; 1160 1161 /* Set start valid if the current tx chunk contains the start of the tx 1162 * ethernet frame. 1163 */ 1164 if (!tc6->tx_skb_offset) 1165 start_valid = OA_TC6_DATA_START_VALID; 1166 1167 /* If the remaining tx skb length is more than the chunk payload size of 1168 * 64 bytes then copy only 64 bytes and leave the ongoing tx skb for 1169 * next tx chunk. 1170 */ 1171 length_to_copy = min_t(u16, remaining_len, OA_TC6_CHUNK_PAYLOAD_SIZE); 1172 1173 /* Copy the tx skb data to the tx chunk payload buffer */ 1174 memcpy(tx_buf + 1, tx_skb_data, length_to_copy); 1175 tc6->tx_skb_offset += length_to_copy; 1176 1177 /* Set end valid if the current tx chunk contains the end of the tx 1178 * ethernet frame. 1179 */ 1180 if (tc6->ongoing_tx_skb->len == tc6->tx_skb_offset) { 1181 end_valid = OA_TC6_DATA_END_VALID; 1182 end_byte_offset = length_to_copy - 1; 1183 tc6->tx_skb_offset = 0; 1184 tc6->netdev->stats.tx_bytes += tc6->ongoing_tx_skb->len; 1185 tc6->netdev->stats.tx_packets++; 1186 kfree_skb(tc6->ongoing_tx_skb); 1187 tc6->ongoing_tx_skb = NULL; 1188 } 1189 1190 *tx_buf = oa_tc6_prepare_data_header(OA_TC6_DATA_VALID, start_valid, 1191 end_valid, end_byte_offset); 1192 tc6->spi_data_tx_buf_offset += OA_TC6_CHUNK_SIZE; 1193 } 1194 1195 static u16 oa_tc6_prepare_spi_tx_buf_for_tx_skbs(struct oa_tc6 *tc6) 1196 { 1197 u16 used_tx_credits; 1198 1199 /* Get tx skbs and convert them into tx chunks based on the tx credits 1200 * available. 1201 */ 1202 for (used_tx_credits = 0; used_tx_credits < tc6->tx_credits; 1203 used_tx_credits++) { 1204 if (!tc6->ongoing_tx_skb) { 1205 spin_lock_bh(&tc6->tx_skb_lock); 1206 tc6->ongoing_tx_skb = tc6->waiting_tx_skb; 1207 tc6->waiting_tx_skb = NULL; 1208 spin_unlock_bh(&tc6->tx_skb_lock); 1209 } 1210 if (!tc6->ongoing_tx_skb) 1211 break; 1212 oa_tc6_add_tx_skb_to_spi_buf(tc6); 1213 } 1214 1215 return used_tx_credits * OA_TC6_CHUNK_SIZE; 1216 } 1217 1218 static void oa_tc6_add_empty_chunks_to_spi_buf(struct oa_tc6 *tc6, 1219 u16 needed_empty_chunks) 1220 { 1221 __be32 header; 1222 1223 header = oa_tc6_prepare_data_header(OA_TC6_DATA_INVALID, 1224 OA_TC6_DATA_START_INVALID, 1225 OA_TC6_DATA_END_INVALID, 0); 1226 1227 while (needed_empty_chunks--) { 1228 __be32 *tx_buf = tc6->spi_data_tx_buf + 1229 tc6->spi_data_tx_buf_offset; 1230 1231 *tx_buf = header; 1232 tc6->spi_data_tx_buf_offset += OA_TC6_CHUNK_SIZE; 1233 } 1234 } 1235 1236 static u16 oa_tc6_prepare_spi_tx_buf_for_rx_chunks(struct oa_tc6 *tc6, u16 len) 1237 { 1238 u16 tx_chunks = len / OA_TC6_CHUNK_SIZE; 1239 u16 needed_empty_chunks; 1240 1241 /* If there are more chunks to receive than to transmit, we need to add 1242 * enough empty tx chunks to allow the reception of the excess rx 1243 * chunks. 1244 */ 1245 if (tx_chunks >= tc6->rx_chunks_available) 1246 return len; 1247 1248 needed_empty_chunks = tc6->rx_chunks_available - tx_chunks; 1249 1250 oa_tc6_add_empty_chunks_to_spi_buf(tc6, needed_empty_chunks); 1251 1252 return needed_empty_chunks * OA_TC6_CHUNK_SIZE + len; 1253 } 1254 1255 static int oa_tc6_try_spi_transfer(struct oa_tc6 *tc6) 1256 { 1257 int ret; 1258 1259 while (true) { 1260 u16 spi_len = 0; 1261 1262 tc6->spi_data_tx_buf_offset = 0; 1263 1264 if (tc6->ongoing_tx_skb || tc6->waiting_tx_skb) 1265 spi_len = oa_tc6_prepare_spi_tx_buf_for_tx_skbs(tc6); 1266 1267 spi_len = oa_tc6_prepare_spi_tx_buf_for_rx_chunks(tc6, spi_len); 1268 1269 if (tc6->int_flag) { 1270 tc6->int_flag = false; 1271 if (spi_len == 0) { 1272 oa_tc6_add_empty_chunks_to_spi_buf(tc6, 1); 1273 spi_len = OA_TC6_CHUNK_SIZE; 1274 } 1275 } 1276 1277 if (spi_len == 0) 1278 break; 1279 1280 ret = oa_tc6_spi_transfer(tc6, OA_TC6_DATA_HEADER, spi_len); 1281 if (ret) { 1282 netdev_err(tc6->netdev, "SPI data transfer failed: %d\n", 1283 ret); 1284 return ret; 1285 } 1286 1287 ret = oa_tc6_process_spi_data_rx_buf(tc6, spi_len); 1288 1289 if (ret && ret != -EAGAIN) { 1290 oa_tc6_free_ongoing_skbs(tc6); 1291 netdev_err(tc6->netdev, "Device error: %d\n", ret); 1292 return ret; 1293 } 1294 1295 if (!tc6->waiting_tx_skb && netif_queue_stopped(tc6->netdev)) 1296 netif_wake_queue(tc6->netdev); 1297 } 1298 1299 return 0; 1300 } 1301 1302 static irqreturn_t oa_tc6_macphy_threaded_irq(int irq, void *data) 1303 { 1304 struct oa_tc6 *tc6 = data; 1305 int ret = 0; 1306 1307 /* It is possible that interrupt woke the thread before it is 1308 * disabled. Until we come up with good recovery mechanism, 1309 * no need to attempt spi transfer, once it fails. Pending skbs 1310 * are already freed. 1311 */ 1312 spin_lock_bh(&tc6->tx_skb_lock); 1313 if (tc6->disable_traffic) { 1314 spin_unlock_bh(&tc6->tx_skb_lock); 1315 return IRQ_HANDLED; 1316 } 1317 spin_unlock_bh(&tc6->tx_skb_lock); 1318 1319 while (tc6->int_flag || 1320 (tc6->waiting_tx_skb && tc6->tx_credits)) { 1321 ret = oa_tc6_try_spi_transfer(tc6); 1322 if (ret) { 1323 disable_irq_nosync(tc6->spi->irq); 1324 oa_tc6_disable_traffic(tc6); 1325 break; 1326 } 1327 } 1328 1329 return IRQ_HANDLED; 1330 } 1331 1332 static int oa_tc6_update_buffer_status_from_register(struct oa_tc6 *tc6) 1333 { 1334 u32 value; 1335 int ret; 1336 1337 /* Initially tx credits and rx chunks available to be updated from the 1338 * register as there is no data transfer performed yet. Later they will 1339 * be updated from the rx footer. 1340 */ 1341 ret = oa_tc6_read_register(tc6, OA_TC6_REG_BUFFER_STATUS, &value); 1342 if (ret) 1343 return ret; 1344 1345 tc6->tx_credits = FIELD_GET(OA_TC6_BUFFER_STATUS_TX_CREDITS_AVAILABLE, 1346 value); 1347 tc6->rx_chunks_available = 1348 FIELD_GET(OA_TC6_BUFFER_STATUS_RX_CHUNKS_AVAILABLE, value); 1349 1350 return 0; 1351 } 1352 1353 static irqreturn_t oa_tc6_macphy_isr(int irq, void *data) 1354 { 1355 struct oa_tc6 *tc6 = data; 1356 1357 /* MAC-PHY interrupt can occur for the following reasons. 1358 * - availability of tx credits if it was 0 before and not reported in 1359 * the previous rx footer. 1360 * - availability of rx chunks if it was 0 before and not reported in 1361 * the previous rx footer. 1362 * - extended status event not reported in the previous rx footer. 1363 */ 1364 if (tc6->disable_traffic) 1365 disable_irq_nosync(tc6->spi->irq); 1366 else 1367 tc6->int_flag = true; 1368 /* Wake IRQ thread to perform spi transfer . In case 1369 * disable_traffic is set, threaded irq may run again 1370 * one more time. 1371 */ 1372 return IRQ_WAKE_THREAD; 1373 } 1374 1375 /** 1376 * oa_tc6_zero_align_receive_frame_enable - function to enable zero align 1377 * receive frame feature. 1378 * @tc6: oa_tc6 struct. 1379 * 1380 * Return: 0 on success otherwise failed. 1381 */ 1382 int oa_tc6_zero_align_receive_frame_enable(struct oa_tc6 *tc6) 1383 { 1384 u32 regval; 1385 int ret; 1386 1387 ret = oa_tc6_read_register(tc6, OA_TC6_REG_CONFIG0, ®val); 1388 if (ret) 1389 return ret; 1390 1391 /* Set Zero-Align Receive Frame Enable */ 1392 regval |= OA_TC6_CONFIG0_ZARFE_ENABLE; 1393 1394 return oa_tc6_write_register(tc6, OA_TC6_REG_CONFIG0, regval); 1395 } 1396 EXPORT_SYMBOL_GPL(oa_tc6_zero_align_receive_frame_enable); 1397 1398 /** 1399 * oa_tc6_start_xmit - function for sending the tx skb which consists ethernet 1400 * frame. 1401 * @tc6: oa_tc6 struct. 1402 * @skb: socket buffer in which the ethernet frame is stored. 1403 * 1404 * Return: NETDEV_TX_OK either on successful queueing of the packet for 1405 * transmission, or on packet getting dropped. Packet can be dropped due to 1406 * failure in linearizing the buffer or disable_traffic is set due to 1407 * earlier fatal error. Returns NETDEV_TX_BUSY when there is no room 1408 * to queue the packet. 1409 */ 1410 netdev_tx_t oa_tc6_start_xmit(struct oa_tc6 *tc6, struct sk_buff *skb) 1411 { 1412 if (skb_linearize(skb)) { 1413 oa_tc6_drop_tx_skb(tc6, skb); 1414 return NETDEV_TX_OK; 1415 } 1416 1417 spin_lock_bh(&tc6->tx_skb_lock); 1418 if (tc6->waiting_tx_skb) { 1419 netif_stop_queue(tc6->netdev); 1420 spin_unlock_bh(&tc6->tx_skb_lock); 1421 return NETDEV_TX_BUSY; 1422 } 1423 if (tc6->disable_traffic) { 1424 spin_unlock_bh(&tc6->tx_skb_lock); 1425 oa_tc6_drop_tx_skb(tc6, skb); 1426 return NETDEV_TX_OK; 1427 } 1428 tc6->waiting_tx_skb = skb; 1429 spin_unlock_bh(&tc6->tx_skb_lock); 1430 1431 /* Wake the threaded IRQ to perform spi transfer. */ 1432 irq_wake_thread(tc6->spi->irq, tc6); 1433 1434 return NETDEV_TX_OK; 1435 } 1436 EXPORT_SYMBOL_GPL(oa_tc6_start_xmit); 1437 1438 static int oa_tc6_check_ctrl_protection(struct oa_tc6 *tc6) 1439 { 1440 u32 regval; 1441 int ret; 1442 1443 ret = oa_tc6_read_register(tc6, OA_TC6_REG_CONFIG0, ®val); 1444 if (ret) 1445 return ret; 1446 1447 tc6->prot_ctrl = FIELD_GET(OA_TC6_CONFIG0_PROTE, regval); 1448 1449 return 0; 1450 } 1451 1452 /** 1453 * oa_tc6_init - allocates and initializes oa_tc6 structure. 1454 * @spi: device with which data will be exchanged. 1455 * @netdev: network device interface structure. 1456 * @quirks: device specific modifiers for the OA TC6 protocol. 1457 * 1458 * Return: pointer reference to the oa_tc6 structure if the MAC-PHY 1459 * initialization is successful otherwise an ERR_PTR. 1460 */ 1461 struct oa_tc6 *oa_tc6_init(struct spi_device *spi, struct net_device *netdev, 1462 struct oa_tc6_quirks *quirks) 1463 { 1464 struct oa_tc6 *tc6; 1465 int ret; 1466 1467 tc6 = devm_kzalloc(&spi->dev, sizeof(*tc6), GFP_KERNEL); 1468 if (!tc6) 1469 return ERR_PTR(-ENOMEM); 1470 1471 tc6->spi = spi; 1472 tc6->netdev = netdev; 1473 SET_NETDEV_DEV(netdev, &spi->dev); 1474 mutex_init(&tc6->spi_ctrl_lock); 1475 spin_lock_init(&tc6->tx_skb_lock); 1476 1477 if (quirks) 1478 tc6->quirk_flags = quirks->quirk_flags; 1479 1480 /* Set the SPI controller to pump at realtime priority */ 1481 tc6->spi->rt = true; 1482 ret = spi_setup(tc6->spi); 1483 if (ret < 0) 1484 return ERR_PTR(ret); 1485 1486 tc6->spi_ctrl_tx_buf = devm_kzalloc(&tc6->spi->dev, 1487 OA_TC6_CTRL_SPI_BUF_SIZE, 1488 GFP_KERNEL); 1489 if (!tc6->spi_ctrl_tx_buf) 1490 return ERR_PTR(-ENOMEM); 1491 1492 tc6->spi_ctrl_rx_buf = devm_kzalloc(&tc6->spi->dev, 1493 OA_TC6_CTRL_SPI_BUF_SIZE, 1494 GFP_KERNEL); 1495 if (!tc6->spi_ctrl_rx_buf) 1496 return ERR_PTR(-ENOMEM); 1497 1498 tc6->spi_data_tx_buf = devm_kzalloc(&tc6->spi->dev, 1499 OA_TC6_SPI_DATA_BUF_SIZE, 1500 GFP_KERNEL); 1501 if (!tc6->spi_data_tx_buf) 1502 return ERR_PTR(-ENOMEM); 1503 1504 tc6->spi_data_rx_buf = devm_kzalloc(&tc6->spi->dev, 1505 OA_TC6_SPI_DATA_BUF_SIZE, 1506 GFP_KERNEL); 1507 if (!tc6->spi_data_rx_buf) 1508 return ERR_PTR(-ENOMEM); 1509 1510 tc6->reset_gpio = devm_gpiod_get_optional(&spi->dev, "reset", 1511 GPIOD_OUT_HIGH); 1512 if (IS_ERR(tc6->reset_gpio)) 1513 return ERR_PTR(dev_err_probe(&spi->dev, 1514 PTR_ERR(tc6->reset_gpio), 1515 "failed to get reset gpio\n")); 1516 1517 if (tc6->reset_gpio) { 1518 /* Keep the reset asserted for 10 us and then allow 1 ms of 1519 * settle time for the crystal oscillator startup. 1520 */ 1521 fsleep(10); 1522 gpiod_set_value_cansleep(tc6->reset_gpio, 0); 1523 fsleep(1000); 1524 } 1525 1526 /* Check the PROTE bit status so that we can reset the device */ 1527 ret = oa_tc6_check_ctrl_protection(tc6); 1528 if (ret) { 1529 dev_err(&tc6->spi->dev, 1530 "Failed to check the protection mode: %d\n", ret); 1531 return ERR_PTR(ret); 1532 } 1533 1534 ret = oa_tc6_sw_reset_macphy(tc6); 1535 if (ret) { 1536 dev_err(&tc6->spi->dev, 1537 "MAC-PHY software reset failed: %d\n", ret); 1538 return ERR_PTR(ret); 1539 } 1540 1541 ret = oa_tc6_unmask_macphy_error_interrupts(tc6); 1542 if (ret) { 1543 dev_err(&tc6->spi->dev, 1544 "MAC-PHY error interrupts unmask failed: %d\n", ret); 1545 return ERR_PTR(ret); 1546 } 1547 1548 ret = oa_tc6_phy_init(tc6); 1549 if (ret) { 1550 dev_err(&tc6->spi->dev, 1551 "MAC internal PHY initialization failed: %d\n", ret); 1552 return ERR_PTR(ret); 1553 } 1554 1555 ret = oa_tc6_enable_data_transfer(tc6); 1556 if (ret) { 1557 dev_err(&tc6->spi->dev, "Failed to enable data transfer: %d\n", 1558 ret); 1559 goto phy_exit; 1560 } 1561 1562 ret = oa_tc6_update_buffer_status_from_register(tc6); 1563 if (ret) { 1564 dev_err(&tc6->spi->dev, 1565 "Failed to update buffer status: %d\n", ret); 1566 goto phy_exit; 1567 } 1568 1569 ret = devm_request_threaded_irq(&tc6->spi->dev, tc6->spi->irq, 1570 oa_tc6_macphy_isr, 1571 oa_tc6_macphy_threaded_irq, 1572 IRQF_TRIGGER_LOW | IRQF_ONESHOT, 1573 dev_name(&tc6->spi->dev), tc6); 1574 if (ret) { 1575 dev_err(&tc6->spi->dev, "Failed to request macphy isr %d\n", 1576 ret); 1577 goto phy_exit; 1578 } 1579 1580 /* oa_tc6_sw_reset_macphy() function resets and clears the MAC-PHY reset 1581 * complete status. IRQ is also asserted on reset completion and it is 1582 * remain asserted until MAC-PHY receives a data chunk. So performing an 1583 * empty data chunk transmission will deassert the IRQ. Refer section 1584 * 7.7 and 9.2.8.8 in the OPEN Alliance specification for more details. 1585 */ 1586 tc6->int_flag = true; 1587 irq_wake_thread(tc6->spi->irq, tc6); 1588 1589 return tc6; 1590 1591 phy_exit: 1592 oa_tc6_phy_exit(tc6); 1593 return ERR_PTR(ret); 1594 } 1595 EXPORT_SYMBOL_GPL(oa_tc6_init); 1596 1597 /** 1598 * oa_tc6_exit - exit function. 1599 * @tc6: oa_tc6 struct. 1600 */ 1601 void oa_tc6_exit(struct oa_tc6 *tc6) 1602 { 1603 disable_irq(tc6->spi->irq); 1604 spin_lock_bh(&tc6->tx_skb_lock); 1605 tc6->disable_traffic = true; 1606 spin_unlock_bh(&tc6->tx_skb_lock); 1607 oa_tc6_phy_exit(tc6); 1608 oa_tc6_free_pending_skbs(tc6); 1609 } 1610 EXPORT_SYMBOL_GPL(oa_tc6_exit); 1611 1612 MODULE_DESCRIPTION("OPEN Alliance 10BASE‑T1x MAC‑PHY Serial Interface Lib"); 1613 MODULE_AUTHOR("Parthiban Veerasooran <parthiban.veerasooran@microchip.com>"); 1614 MODULE_LICENSE("GPL"); 1615