1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 10G controller driver for Samsung SoCs
3 *
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Author: Siva Reddy Kallam <siva.kallam@samsung.com>
8 */
9
10 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11
12 #include <linux/clk.h>
13 #include <linux/crc32.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/etherdevice.h>
16 #include <linux/ethtool.h>
17 #include <linux/if.h>
18 #include <linux/if_ether.h>
19 #include <linux/if_vlan.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/ip.h>
23 #include <linux/kernel.h>
24 #include <linux/mii.h>
25 #include <linux/module.h>
26 #include <linux/net_tstamp.h>
27 #include <linux/netdevice.h>
28 #include <linux/phy.h>
29 #include <linux/platform_device.h>
30 #include <linux/prefetch.h>
31 #include <linux/skbuff.h>
32 #include <linux/slab.h>
33 #include <linux/tcp.h>
34 #include <linux/sxgbe_platform.h>
35
36 #include "sxgbe_common.h"
37 #include "sxgbe_desc.h"
38 #include "sxgbe_dma.h"
39 #include "sxgbe_mtl.h"
40 #include "sxgbe_reg.h"
41
42 #define SXGBE_ALIGN(x) L1_CACHE_ALIGN(x)
43 #define JUMBO_LEN 9000
44
45 /* Module parameters */
46 #define TX_TIMEO 5000
47 #define DMA_TX_SIZE 512
48 #define DMA_RX_SIZE 1024
49 #define TC_DEFAULT 64
50 #define DMA_BUFFER_SIZE BUF_SIZE_2KiB
51 /* The default timer value as per the sxgbe specification 1 sec(1000 ms) */
52 #define SXGBE_DEFAULT_LPI_TIMER 1000
53
54 static int debug = -1;
55 static int eee_timer = SXGBE_DEFAULT_LPI_TIMER;
56
57 module_param(eee_timer, int, 0644);
58
59 module_param(debug, int, 0644);
60 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
61 NETIF_MSG_LINK | NETIF_MSG_IFUP |
62 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
63
64 static irqreturn_t sxgbe_common_interrupt(int irq, void *dev_id);
65 static irqreturn_t sxgbe_tx_interrupt(int irq, void *dev_id);
66 static irqreturn_t sxgbe_rx_interrupt(int irq, void *dev_id);
67
68 #define SXGBE_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
69
70 #define SXGBE_LPI_TIMER(x) (jiffies + msecs_to_jiffies(x))
71
72 /**
73 * sxgbe_verify_args - verify the driver parameters.
74 * Description: it verifies if some wrong parameter is passed to the driver.
75 * Note that wrong parameters are replaced with the default values.
76 */
sxgbe_verify_args(void)77 static void sxgbe_verify_args(void)
78 {
79 if (unlikely(eee_timer < 0))
80 eee_timer = SXGBE_DEFAULT_LPI_TIMER;
81 }
82
sxgbe_enable_eee_mode(const struct sxgbe_priv_data * priv)83 static void sxgbe_enable_eee_mode(const struct sxgbe_priv_data *priv)
84 {
85 /* Check and enter in LPI mode */
86 if (!priv->tx_path_in_lpi_mode)
87 priv->hw->mac->set_eee_mode(priv->ioaddr);
88 }
89
sxgbe_disable_eee_mode(struct sxgbe_priv_data * const priv)90 void sxgbe_disable_eee_mode(struct sxgbe_priv_data * const priv)
91 {
92 /* Exit and disable EEE in case of we are in LPI state. */
93 priv->hw->mac->reset_eee_mode(priv->ioaddr);
94 timer_delete_sync(&priv->eee_ctrl_timer);
95 priv->tx_path_in_lpi_mode = false;
96 }
97
98 /**
99 * sxgbe_eee_ctrl_timer
100 * @t: timer list containing a data
101 * Description:
102 * If there is no data transfer and if we are not in LPI state,
103 * then MAC Transmitter can be moved to LPI state.
104 */
sxgbe_eee_ctrl_timer(struct timer_list * t)105 static void sxgbe_eee_ctrl_timer(struct timer_list *t)
106 {
107 struct sxgbe_priv_data *priv = timer_container_of(priv, t,
108 eee_ctrl_timer);
109
110 sxgbe_enable_eee_mode(priv);
111 mod_timer(&priv->eee_ctrl_timer, SXGBE_LPI_TIMER(eee_timer));
112 }
113
114 /**
115 * sxgbe_eee_init
116 * @priv: private device pointer
117 * Description:
118 * If the EEE support has been enabled while configuring the driver,
119 * if the GMAC actually supports the EEE (from the HW cap reg) and the
120 * phy can also manage EEE, so enable the LPI state and start the timer
121 * to verify if the tx path can enter in LPI state.
122 */
sxgbe_eee_init(struct sxgbe_priv_data * const priv)123 bool sxgbe_eee_init(struct sxgbe_priv_data * const priv)
124 {
125 struct net_device *ndev = priv->dev;
126 bool ret = false;
127
128 /* MAC core supports the EEE feature. */
129 if (priv->hw_cap.eee) {
130 /* Check if the PHY supports EEE */
131 if (phy_init_eee(ndev->phydev, true))
132 return false;
133
134 timer_setup(&priv->eee_ctrl_timer, sxgbe_eee_ctrl_timer, 0);
135 priv->eee_ctrl_timer.expires = SXGBE_LPI_TIMER(eee_timer);
136 add_timer(&priv->eee_ctrl_timer);
137
138 priv->hw->mac->set_eee_timer(priv->ioaddr,
139 SXGBE_DEFAULT_LPI_TIMER,
140 priv->tx_lpi_timer);
141
142 pr_info("Energy-Efficient Ethernet initialized\n");
143
144 ret = true;
145 }
146
147 return ret;
148 }
149
sxgbe_eee_adjust(const struct sxgbe_priv_data * priv)150 static void sxgbe_eee_adjust(const struct sxgbe_priv_data *priv)
151 {
152 struct net_device *ndev = priv->dev;
153
154 /* When the EEE has been already initialised we have to
155 * modify the PLS bit in the LPI ctrl & status reg according
156 * to the PHY link status. For this reason.
157 */
158 if (priv->eee_enabled)
159 priv->hw->mac->set_eee_pls(priv->ioaddr, ndev->phydev->link);
160 }
161
162 /**
163 * sxgbe_clk_csr_set - dynamically set the MDC clock
164 * @priv: driver private structure
165 * Description: this is to dynamically set the MDC clock according to the csr
166 * clock input.
167 */
sxgbe_clk_csr_set(struct sxgbe_priv_data * priv)168 static void sxgbe_clk_csr_set(struct sxgbe_priv_data *priv)
169 {
170 u32 clk_rate = clk_get_rate(priv->sxgbe_clk);
171
172 /* assign the proper divider, this will be used during
173 * mdio communication
174 */
175 if (clk_rate < SXGBE_CSR_F_150M)
176 priv->clk_csr = SXGBE_CSR_100_150M;
177 else if (clk_rate <= SXGBE_CSR_F_250M)
178 priv->clk_csr = SXGBE_CSR_150_250M;
179 else if (clk_rate <= SXGBE_CSR_F_300M)
180 priv->clk_csr = SXGBE_CSR_250_300M;
181 else if (clk_rate <= SXGBE_CSR_F_350M)
182 priv->clk_csr = SXGBE_CSR_300_350M;
183 else if (clk_rate <= SXGBE_CSR_F_400M)
184 priv->clk_csr = SXGBE_CSR_350_400M;
185 else if (clk_rate <= SXGBE_CSR_F_500M)
186 priv->clk_csr = SXGBE_CSR_400_500M;
187 }
188
189 /* minimum number of free TX descriptors required to wake up TX process */
190 #define SXGBE_TX_THRESH(x) (x->dma_tx_size/4)
191
sxgbe_tx_avail(struct sxgbe_tx_queue * queue,int tx_qsize)192 static inline u32 sxgbe_tx_avail(struct sxgbe_tx_queue *queue, int tx_qsize)
193 {
194 return queue->dirty_tx + tx_qsize - queue->cur_tx - 1;
195 }
196
197 /**
198 * sxgbe_adjust_link
199 * @dev: net device structure
200 * Description: it adjusts the link parameters.
201 */
sxgbe_adjust_link(struct net_device * dev)202 static void sxgbe_adjust_link(struct net_device *dev)
203 {
204 struct sxgbe_priv_data *priv = netdev_priv(dev);
205 struct phy_device *phydev = dev->phydev;
206 u8 new_state = 0;
207 u8 speed = 0xff;
208
209 if (!phydev)
210 return;
211
212 /* SXGBE is not supporting auto-negotiation and
213 * half duplex mode. so, not handling duplex change
214 * in this function. only handling speed and link status
215 */
216 if (phydev->link) {
217 if (phydev->speed != priv->speed) {
218 new_state = 1;
219 switch (phydev->speed) {
220 case SPEED_10000:
221 speed = SXGBE_SPEED_10G;
222 break;
223 case SPEED_2500:
224 speed = SXGBE_SPEED_2_5G;
225 break;
226 case SPEED_1000:
227 speed = SXGBE_SPEED_1G;
228 break;
229 default:
230 netif_err(priv, link, dev,
231 "Speed (%d) not supported\n",
232 phydev->speed);
233 }
234
235 priv->speed = phydev->speed;
236 priv->hw->mac->set_speed(priv->ioaddr, speed);
237 }
238
239 if (!priv->oldlink) {
240 new_state = 1;
241 priv->oldlink = 1;
242 }
243 } else if (priv->oldlink) {
244 new_state = 1;
245 priv->oldlink = 0;
246 priv->speed = SPEED_UNKNOWN;
247 }
248
249 if (new_state & netif_msg_link(priv))
250 phy_print_status(phydev);
251
252 /* Alter the MAC settings for EEE */
253 sxgbe_eee_adjust(priv);
254 }
255
256 /**
257 * sxgbe_init_phy - PHY initialization
258 * @ndev: net device structure
259 * Description: it initializes the driver's PHY state, and attaches the PHY
260 * to the mac driver.
261 * Return value:
262 * 0 on success
263 */
sxgbe_init_phy(struct net_device * ndev)264 static int sxgbe_init_phy(struct net_device *ndev)
265 {
266 char phy_id_fmt[MII_BUS_ID_SIZE + 3];
267 char bus_id[MII_BUS_ID_SIZE];
268 struct phy_device *phydev;
269 struct sxgbe_priv_data *priv = netdev_priv(ndev);
270 int phy_iface = priv->plat->interface;
271
272 /* assign default link status */
273 priv->oldlink = 0;
274 priv->speed = SPEED_UNKNOWN;
275 priv->oldduplex = DUPLEX_UNKNOWN;
276
277 if (priv->plat->phy_bus_name)
278 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
279 priv->plat->phy_bus_name, priv->plat->bus_id);
280 else
281 snprintf(bus_id, MII_BUS_ID_SIZE, "sxgbe-%x",
282 priv->plat->bus_id);
283
284 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
285 priv->plat->phy_addr);
286 netdev_dbg(ndev, "%s: trying to attach to %s\n", __func__, phy_id_fmt);
287
288 phydev = phy_connect(ndev, phy_id_fmt, &sxgbe_adjust_link, phy_iface);
289
290 if (IS_ERR(phydev)) {
291 netdev_err(ndev, "Could not attach to PHY\n");
292 return PTR_ERR(phydev);
293 }
294
295 /* Stop Advertising 1000BASE Capability if interface is not GMII */
296 if ((phy_iface == PHY_INTERFACE_MODE_MII) ||
297 (phy_iface == PHY_INTERFACE_MODE_RMII))
298 phy_set_max_speed(phydev, SPEED_1000);
299
300 if (phydev->phy_id == 0) {
301 phy_disconnect(phydev);
302 return -ENODEV;
303 }
304
305 netdev_dbg(ndev, "%s: attached to PHY (UID 0x%x) Link = %d\n",
306 __func__, phydev->phy_id, phydev->link);
307
308 return 0;
309 }
310
311 /**
312 * sxgbe_clear_descriptors: clear descriptors
313 * @priv: driver private structure
314 * Description: this function is called to clear the tx and rx descriptors
315 * in case of both basic and extended descriptors are used.
316 */
sxgbe_clear_descriptors(struct sxgbe_priv_data * priv)317 static void sxgbe_clear_descriptors(struct sxgbe_priv_data *priv)
318 {
319 int i, j;
320 unsigned int txsize = priv->dma_tx_size;
321 unsigned int rxsize = priv->dma_rx_size;
322
323 /* Clear the Rx/Tx descriptors */
324 for (j = 0; j < SXGBE_RX_QUEUES; j++) {
325 for (i = 0; i < rxsize; i++)
326 priv->hw->desc->init_rx_desc(&priv->rxq[j]->dma_rx[i],
327 priv->use_riwt, priv->mode,
328 (i == rxsize - 1));
329 }
330
331 for (j = 0; j < SXGBE_TX_QUEUES; j++) {
332 for (i = 0; i < txsize; i++)
333 priv->hw->desc->init_tx_desc(&priv->txq[j]->dma_tx[i]);
334 }
335 }
336
sxgbe_init_rx_buffers(struct net_device * dev,struct sxgbe_rx_norm_desc * p,int i,unsigned int dma_buf_sz,struct sxgbe_rx_queue * rx_ring)337 static int sxgbe_init_rx_buffers(struct net_device *dev,
338 struct sxgbe_rx_norm_desc *p, int i,
339 unsigned int dma_buf_sz,
340 struct sxgbe_rx_queue *rx_ring)
341 {
342 struct sxgbe_priv_data *priv = netdev_priv(dev);
343 struct sk_buff *skb;
344
345 skb = __netdev_alloc_skb_ip_align(dev, dma_buf_sz, GFP_KERNEL);
346 if (!skb)
347 return -ENOMEM;
348
349 rx_ring->rx_skbuff[i] = skb;
350 rx_ring->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
351 dma_buf_sz, DMA_FROM_DEVICE);
352
353 if (dma_mapping_error(priv->device, rx_ring->rx_skbuff_dma[i])) {
354 netdev_err(dev, "%s: DMA mapping error\n", __func__);
355 dev_kfree_skb_any(skb);
356 return -EINVAL;
357 }
358
359 p->rdes23.rx_rd_des23.buf2_addr = rx_ring->rx_skbuff_dma[i];
360
361 return 0;
362 }
363
364 /**
365 * sxgbe_free_rx_buffers - free what sxgbe_init_rx_buffers() allocated
366 * @dev: net device structure
367 * @p: dec pointer
368 * @i: index
369 * @dma_buf_sz: size
370 * @rx_ring: ring to be freed
371 *
372 * Description: this function initializes the DMA RX descriptor
373 */
sxgbe_free_rx_buffers(struct net_device * dev,struct sxgbe_rx_norm_desc * p,int i,unsigned int dma_buf_sz,struct sxgbe_rx_queue * rx_ring)374 static void sxgbe_free_rx_buffers(struct net_device *dev,
375 struct sxgbe_rx_norm_desc *p, int i,
376 unsigned int dma_buf_sz,
377 struct sxgbe_rx_queue *rx_ring)
378 {
379 struct sxgbe_priv_data *priv = netdev_priv(dev);
380
381 kfree_skb(rx_ring->rx_skbuff[i]);
382 dma_unmap_single(priv->device, rx_ring->rx_skbuff_dma[i],
383 dma_buf_sz, DMA_FROM_DEVICE);
384 }
385
386 /**
387 * init_tx_ring - init the TX descriptor ring
388 * @dev: net device structure
389 * @queue_no: queue
390 * @tx_ring: ring to be initialised
391 * @tx_rsize: ring size
392 * Description: this function initializes the DMA TX descriptor
393 */
init_tx_ring(struct device * dev,u8 queue_no,struct sxgbe_tx_queue * tx_ring,int tx_rsize)394 static int init_tx_ring(struct device *dev, u8 queue_no,
395 struct sxgbe_tx_queue *tx_ring, int tx_rsize)
396 {
397 /* TX ring is not allcoated */
398 if (!tx_ring) {
399 dev_err(dev, "No memory for TX queue of SXGBE\n");
400 return -ENOMEM;
401 }
402
403 /* allocate memory for TX descriptors */
404 tx_ring->dma_tx = dma_alloc_coherent(dev,
405 tx_rsize * sizeof(struct sxgbe_tx_norm_desc),
406 &tx_ring->dma_tx_phy, GFP_KERNEL);
407 if (!tx_ring->dma_tx)
408 return -ENOMEM;
409
410 /* allocate memory for TX skbuff array */
411 tx_ring->tx_skbuff_dma = devm_kcalloc(dev, tx_rsize,
412 sizeof(dma_addr_t), GFP_KERNEL);
413 if (!tx_ring->tx_skbuff_dma)
414 goto dmamem_err;
415
416 tx_ring->tx_skbuff = devm_kcalloc(dev, tx_rsize,
417 sizeof(struct sk_buff *), GFP_KERNEL);
418
419 if (!tx_ring->tx_skbuff)
420 goto dmamem_err;
421
422 /* assign queue number */
423 tx_ring->queue_no = queue_no;
424
425 /* initialise counters */
426 tx_ring->dirty_tx = 0;
427 tx_ring->cur_tx = 0;
428
429 return 0;
430
431 dmamem_err:
432 dma_free_coherent(dev, tx_rsize * sizeof(struct sxgbe_tx_norm_desc),
433 tx_ring->dma_tx, tx_ring->dma_tx_phy);
434 return -ENOMEM;
435 }
436
437 /**
438 * free_rx_ring - free the RX descriptor ring
439 * @dev: net device structure
440 * @rx_ring: ring to be initialised
441 * @rx_rsize: ring size
442 * Description: this function initializes the DMA RX descriptor
443 */
free_rx_ring(struct device * dev,struct sxgbe_rx_queue * rx_ring,int rx_rsize)444 static void free_rx_ring(struct device *dev, struct sxgbe_rx_queue *rx_ring,
445 int rx_rsize)
446 {
447 dma_free_coherent(dev, rx_rsize * sizeof(struct sxgbe_rx_norm_desc),
448 rx_ring->dma_rx, rx_ring->dma_rx_phy);
449 kfree(rx_ring->rx_skbuff_dma);
450 kfree(rx_ring->rx_skbuff);
451 }
452
453 /**
454 * init_rx_ring - init the RX descriptor ring
455 * @dev: net device structure
456 * @queue_no: queue
457 * @rx_ring: ring to be initialised
458 * @rx_rsize: ring size
459 * Description: this function initializes the DMA RX descriptor
460 */
init_rx_ring(struct net_device * dev,u8 queue_no,struct sxgbe_rx_queue * rx_ring,int rx_rsize)461 static int init_rx_ring(struct net_device *dev, u8 queue_no,
462 struct sxgbe_rx_queue *rx_ring, int rx_rsize)
463 {
464 struct sxgbe_priv_data *priv = netdev_priv(dev);
465 int desc_index;
466 unsigned int bfsize = 0;
467 unsigned int ret = 0;
468
469 /* Set the max buffer size according to the MTU. */
470 bfsize = ALIGN(dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN, 8);
471
472 netif_dbg(priv, probe, dev, "%s: bfsize %d\n", __func__, bfsize);
473
474 /* RX ring is not allcoated */
475 if (rx_ring == NULL) {
476 netdev_err(dev, "No memory for RX queue\n");
477 return -ENOMEM;
478 }
479
480 /* assign queue number */
481 rx_ring->queue_no = queue_no;
482
483 /* allocate memory for RX descriptors */
484 rx_ring->dma_rx = dma_alloc_coherent(priv->device,
485 rx_rsize * sizeof(struct sxgbe_rx_norm_desc),
486 &rx_ring->dma_rx_phy, GFP_KERNEL);
487
488 if (rx_ring->dma_rx == NULL)
489 return -ENOMEM;
490
491 /* allocate memory for RX skbuff array */
492 rx_ring->rx_skbuff_dma = kmalloc_objs(dma_addr_t, rx_rsize);
493 if (!rx_ring->rx_skbuff_dma) {
494 ret = -ENOMEM;
495 goto err_free_dma_rx;
496 }
497
498 rx_ring->rx_skbuff = kmalloc_objs(struct sk_buff *, rx_rsize);
499 if (!rx_ring->rx_skbuff) {
500 ret = -ENOMEM;
501 goto err_free_skbuff_dma;
502 }
503
504 /* initialise the buffers */
505 for (desc_index = 0; desc_index < rx_rsize; desc_index++) {
506 struct sxgbe_rx_norm_desc *p;
507 p = rx_ring->dma_rx + desc_index;
508 ret = sxgbe_init_rx_buffers(dev, p, desc_index,
509 bfsize, rx_ring);
510 if (ret)
511 goto err_free_rx_buffers;
512 }
513
514 /* initialise counters */
515 rx_ring->cur_rx = 0;
516 rx_ring->dirty_rx = (unsigned int)(desc_index - rx_rsize);
517 priv->dma_buf_sz = bfsize;
518
519 return 0;
520
521 err_free_rx_buffers:
522 while (--desc_index >= 0) {
523 struct sxgbe_rx_norm_desc *p;
524
525 p = rx_ring->dma_rx + desc_index;
526 sxgbe_free_rx_buffers(dev, p, desc_index, bfsize, rx_ring);
527 }
528 kfree(rx_ring->rx_skbuff);
529 err_free_skbuff_dma:
530 kfree(rx_ring->rx_skbuff_dma);
531 err_free_dma_rx:
532 dma_free_coherent(priv->device,
533 rx_rsize * sizeof(struct sxgbe_rx_norm_desc),
534 rx_ring->dma_rx, rx_ring->dma_rx_phy);
535
536 return ret;
537 }
538 /**
539 * free_tx_ring - free the TX descriptor ring
540 * @dev: net device structure
541 * @tx_ring: ring to be initialised
542 * @tx_rsize: ring size
543 * Description: this function initializes the DMA TX descriptor
544 */
free_tx_ring(struct device * dev,struct sxgbe_tx_queue * tx_ring,int tx_rsize)545 static void free_tx_ring(struct device *dev, struct sxgbe_tx_queue *tx_ring,
546 int tx_rsize)
547 {
548 dma_free_coherent(dev, tx_rsize * sizeof(struct sxgbe_tx_norm_desc),
549 tx_ring->dma_tx, tx_ring->dma_tx_phy);
550 }
551
552 /**
553 * init_dma_desc_rings - init the RX/TX descriptor rings
554 * @netd: net device structure
555 * Description: this function initializes the DMA RX/TX descriptors
556 * and allocates the socket buffers. It suppors the chained and ring
557 * modes.
558 */
init_dma_desc_rings(struct net_device * netd)559 static int init_dma_desc_rings(struct net_device *netd)
560 {
561 int queue_num, ret;
562 struct sxgbe_priv_data *priv = netdev_priv(netd);
563 int tx_rsize = priv->dma_tx_size;
564 int rx_rsize = priv->dma_rx_size;
565
566 /* Allocate memory for queue structures and TX descs */
567 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
568 ret = init_tx_ring(priv->device, queue_num,
569 priv->txq[queue_num], tx_rsize);
570 if (ret) {
571 dev_err(&netd->dev, "TX DMA ring allocation failed!\n");
572 goto txalloc_err;
573 }
574
575 /* save private pointer in each ring this
576 * pointer is needed during cleaing TX queue
577 */
578 priv->txq[queue_num]->priv_ptr = priv;
579 }
580
581 /* Allocate memory for queue structures and RX descs */
582 SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) {
583 ret = init_rx_ring(netd, queue_num,
584 priv->rxq[queue_num], rx_rsize);
585 if (ret) {
586 netdev_err(netd, "RX DMA ring allocation failed!!\n");
587 goto rxalloc_err;
588 }
589
590 /* save private pointer in each ring this
591 * pointer is needed during cleaing TX queue
592 */
593 priv->rxq[queue_num]->priv_ptr = priv;
594 }
595
596 sxgbe_clear_descriptors(priv);
597
598 return 0;
599
600 txalloc_err:
601 while (queue_num--)
602 free_tx_ring(priv->device, priv->txq[queue_num], tx_rsize);
603 return ret;
604
605 rxalloc_err:
606 while (queue_num--)
607 free_rx_ring(priv->device, priv->rxq[queue_num], rx_rsize);
608 return ret;
609 }
610
tx_free_ring_skbufs(struct sxgbe_tx_queue * txqueue)611 static void tx_free_ring_skbufs(struct sxgbe_tx_queue *txqueue)
612 {
613 int dma_desc;
614 struct sxgbe_priv_data *priv = txqueue->priv_ptr;
615 int tx_rsize = priv->dma_tx_size;
616
617 for (dma_desc = 0; dma_desc < tx_rsize; dma_desc++) {
618 struct sxgbe_tx_norm_desc *tdesc = txqueue->dma_tx + dma_desc;
619
620 if (txqueue->tx_skbuff_dma[dma_desc])
621 dma_unmap_single(priv->device,
622 txqueue->tx_skbuff_dma[dma_desc],
623 priv->hw->desc->get_tx_len(tdesc),
624 DMA_TO_DEVICE);
625
626 dev_kfree_skb_any(txqueue->tx_skbuff[dma_desc]);
627 txqueue->tx_skbuff[dma_desc] = NULL;
628 txqueue->tx_skbuff_dma[dma_desc] = 0;
629 }
630 }
631
632
dma_free_tx_skbufs(struct sxgbe_priv_data * priv)633 static void dma_free_tx_skbufs(struct sxgbe_priv_data *priv)
634 {
635 int queue_num;
636
637 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
638 struct sxgbe_tx_queue *tqueue = priv->txq[queue_num];
639 tx_free_ring_skbufs(tqueue);
640 }
641 }
642
free_dma_desc_resources(struct sxgbe_priv_data * priv)643 static void free_dma_desc_resources(struct sxgbe_priv_data *priv)
644 {
645 int queue_num;
646 int tx_rsize = priv->dma_tx_size;
647 int rx_rsize = priv->dma_rx_size;
648
649 /* Release the DMA TX buffers */
650 dma_free_tx_skbufs(priv);
651
652 /* Release the TX ring memory also */
653 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
654 free_tx_ring(priv->device, priv->txq[queue_num], tx_rsize);
655 }
656
657 /* Release the RX ring memory also */
658 SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) {
659 free_rx_ring(priv->device, priv->rxq[queue_num], rx_rsize);
660 }
661 }
662
txring_mem_alloc(struct sxgbe_priv_data * priv)663 static int txring_mem_alloc(struct sxgbe_priv_data *priv)
664 {
665 int queue_num;
666
667 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
668 priv->txq[queue_num] = devm_kmalloc(priv->device,
669 sizeof(struct sxgbe_tx_queue), GFP_KERNEL);
670 if (!priv->txq[queue_num])
671 return -ENOMEM;
672 }
673
674 return 0;
675 }
676
rxring_mem_alloc(struct sxgbe_priv_data * priv)677 static int rxring_mem_alloc(struct sxgbe_priv_data *priv)
678 {
679 int queue_num;
680
681 SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) {
682 priv->rxq[queue_num] = devm_kmalloc(priv->device,
683 sizeof(struct sxgbe_rx_queue), GFP_KERNEL);
684 if (!priv->rxq[queue_num])
685 return -ENOMEM;
686 }
687
688 return 0;
689 }
690
691 /**
692 * sxgbe_mtl_operation_mode - HW MTL operation mode
693 * @priv: driver private structure
694 * Description: it sets the MTL operation mode: tx/rx MTL thresholds
695 * or Store-And-Forward capability.
696 */
sxgbe_mtl_operation_mode(struct sxgbe_priv_data * priv)697 static void sxgbe_mtl_operation_mode(struct sxgbe_priv_data *priv)
698 {
699 int queue_num;
700
701 /* TX/RX threshold control */
702 if (likely(priv->plat->force_sf_dma_mode)) {
703 /* set TC mode for TX QUEUES */
704 SXGBE_FOR_EACH_QUEUE(priv->hw_cap.tx_mtl_queues, queue_num)
705 priv->hw->mtl->set_tx_mtl_mode(priv->ioaddr, queue_num,
706 SXGBE_MTL_SFMODE);
707 priv->tx_tc = SXGBE_MTL_SFMODE;
708
709 /* set TC mode for RX QUEUES */
710 SXGBE_FOR_EACH_QUEUE(priv->hw_cap.rx_mtl_queues, queue_num)
711 priv->hw->mtl->set_rx_mtl_mode(priv->ioaddr, queue_num,
712 SXGBE_MTL_SFMODE);
713 priv->rx_tc = SXGBE_MTL_SFMODE;
714 } else if (unlikely(priv->plat->force_thresh_dma_mode)) {
715 /* set TC mode for TX QUEUES */
716 SXGBE_FOR_EACH_QUEUE(priv->hw_cap.tx_mtl_queues, queue_num)
717 priv->hw->mtl->set_tx_mtl_mode(priv->ioaddr, queue_num,
718 priv->tx_tc);
719 /* set TC mode for RX QUEUES */
720 SXGBE_FOR_EACH_QUEUE(priv->hw_cap.rx_mtl_queues, queue_num)
721 priv->hw->mtl->set_rx_mtl_mode(priv->ioaddr, queue_num,
722 priv->rx_tc);
723 } else {
724 pr_err("ERROR: %s: Invalid TX threshold mode\n", __func__);
725 }
726 }
727
728 /**
729 * sxgbe_tx_queue_clean:
730 * @tqueue: queue pointer
731 * Description: it reclaims resources after transmission completes.
732 */
sxgbe_tx_queue_clean(struct sxgbe_tx_queue * tqueue)733 static void sxgbe_tx_queue_clean(struct sxgbe_tx_queue *tqueue)
734 {
735 struct sxgbe_priv_data *priv = tqueue->priv_ptr;
736 unsigned int tx_rsize = priv->dma_tx_size;
737 struct netdev_queue *dev_txq;
738 u8 queue_no = tqueue->queue_no;
739
740 dev_txq = netdev_get_tx_queue(priv->dev, queue_no);
741
742 __netif_tx_lock(dev_txq, smp_processor_id());
743
744 priv->xstats.tx_clean++;
745 while (tqueue->dirty_tx != tqueue->cur_tx) {
746 unsigned int entry = tqueue->dirty_tx % tx_rsize;
747 struct sk_buff *skb = tqueue->tx_skbuff[entry];
748 struct sxgbe_tx_norm_desc *p;
749
750 p = tqueue->dma_tx + entry;
751
752 /* Check if the descriptor is owned by the DMA. */
753 if (priv->hw->desc->get_tx_owner(p))
754 break;
755
756 if (netif_msg_tx_done(priv))
757 pr_debug("%s: curr %d, dirty %d\n",
758 __func__, tqueue->cur_tx, tqueue->dirty_tx);
759
760 if (likely(tqueue->tx_skbuff_dma[entry])) {
761 dma_unmap_single(priv->device,
762 tqueue->tx_skbuff_dma[entry],
763 priv->hw->desc->get_tx_len(p),
764 DMA_TO_DEVICE);
765 tqueue->tx_skbuff_dma[entry] = 0;
766 }
767
768 if (likely(skb)) {
769 dev_kfree_skb(skb);
770 tqueue->tx_skbuff[entry] = NULL;
771 }
772
773 priv->hw->desc->release_tx_desc(p);
774
775 tqueue->dirty_tx++;
776 }
777
778 /* wake up queue */
779 if (unlikely(netif_tx_queue_stopped(dev_txq) &&
780 sxgbe_tx_avail(tqueue, tx_rsize) > SXGBE_TX_THRESH(priv))) {
781 if (netif_msg_tx_done(priv))
782 pr_debug("%s: restart transmit\n", __func__);
783 netif_tx_wake_queue(dev_txq);
784 }
785
786 __netif_tx_unlock(dev_txq);
787 }
788
789 /**
790 * sxgbe_tx_all_clean:
791 * @priv: driver private structure
792 * Description: it reclaims resources after transmission completes.
793 */
sxgbe_tx_all_clean(struct sxgbe_priv_data * const priv)794 static void sxgbe_tx_all_clean(struct sxgbe_priv_data * const priv)
795 {
796 u8 queue_num;
797
798 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
799 struct sxgbe_tx_queue *tqueue = priv->txq[queue_num];
800
801 sxgbe_tx_queue_clean(tqueue);
802 }
803
804 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
805 sxgbe_enable_eee_mode(priv);
806 mod_timer(&priv->eee_ctrl_timer, SXGBE_LPI_TIMER(eee_timer));
807 }
808 }
809
810 /**
811 * sxgbe_restart_tx_queue: irq tx error mng function
812 * @priv: driver private structure
813 * @queue_num: queue number
814 * Description: it cleans the descriptors and restarts the transmission
815 * in case of errors.
816 */
sxgbe_restart_tx_queue(struct sxgbe_priv_data * priv,int queue_num)817 static void sxgbe_restart_tx_queue(struct sxgbe_priv_data *priv, int queue_num)
818 {
819 struct sxgbe_tx_queue *tx_ring = priv->txq[queue_num];
820 struct netdev_queue *dev_txq = netdev_get_tx_queue(priv->dev,
821 queue_num);
822
823 /* stop the queue */
824 netif_tx_stop_queue(dev_txq);
825
826 /* stop the tx dma */
827 priv->hw->dma->stop_tx_queue(priv->ioaddr, queue_num);
828
829 /* free the skbuffs of the ring */
830 tx_free_ring_skbufs(tx_ring);
831
832 /* initialise counters */
833 tx_ring->cur_tx = 0;
834 tx_ring->dirty_tx = 0;
835
836 /* start the tx dma */
837 priv->hw->dma->start_tx_queue(priv->ioaddr, queue_num);
838
839 priv->dev->stats.tx_errors++;
840
841 /* wakeup the queue */
842 netif_tx_wake_queue(dev_txq);
843 }
844
845 /**
846 * sxgbe_reset_all_tx_queues: irq tx error mng function
847 * @priv: driver private structure
848 * Description: it cleans all the descriptors and
849 * restarts the transmission on all queues in case of errors.
850 */
sxgbe_reset_all_tx_queues(struct sxgbe_priv_data * priv)851 static void sxgbe_reset_all_tx_queues(struct sxgbe_priv_data *priv)
852 {
853 int queue_num;
854
855 /* On TX timeout of net device, resetting of all queues
856 * may not be proper way, revisit this later if needed
857 */
858 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num)
859 sxgbe_restart_tx_queue(priv, queue_num);
860 }
861
862 /**
863 * sxgbe_get_hw_features: get XMAC capabilities from the HW cap. register.
864 * @priv: driver private structure
865 * Description:
866 * new GMAC chip generations have a new register to indicate the
867 * presence of the optional feature/functions.
868 * This can be also used to override the value passed through the
869 * platform and necessary for old MAC10/100 and GMAC chips.
870 */
sxgbe_get_hw_features(struct sxgbe_priv_data * const priv)871 static int sxgbe_get_hw_features(struct sxgbe_priv_data * const priv)
872 {
873 int rval = 0;
874 struct sxgbe_hw_features *features = &priv->hw_cap;
875
876 /* Read First Capability Register CAP[0] */
877 rval = priv->hw->mac->get_hw_feature(priv->ioaddr, 0);
878 if (rval) {
879 features->pmt_remote_wake_up =
880 SXGBE_HW_FEAT_PMT_TEMOTE_WOP(rval);
881 features->pmt_magic_frame = SXGBE_HW_FEAT_PMT_MAGIC_PKT(rval);
882 features->atime_stamp = SXGBE_HW_FEAT_IEEE1500_2008(rval);
883 features->tx_csum_offload =
884 SXGBE_HW_FEAT_TX_CSUM_OFFLOAD(rval);
885 features->rx_csum_offload =
886 SXGBE_HW_FEAT_RX_CSUM_OFFLOAD(rval);
887 features->multi_macaddr = SXGBE_HW_FEAT_MACADDR_COUNT(rval);
888 features->tstamp_srcselect = SXGBE_HW_FEAT_TSTMAP_SRC(rval);
889 features->sa_vlan_insert = SXGBE_HW_FEAT_SRCADDR_VLAN(rval);
890 features->eee = SXGBE_HW_FEAT_EEE(rval);
891 }
892
893 /* Read First Capability Register CAP[1] */
894 rval = priv->hw->mac->get_hw_feature(priv->ioaddr, 1);
895 if (rval) {
896 features->rxfifo_size = SXGBE_HW_FEAT_RX_FIFO_SIZE(rval);
897 features->txfifo_size = SXGBE_HW_FEAT_TX_FIFO_SIZE(rval);
898 features->atstmap_hword = SXGBE_HW_FEAT_TX_FIFO_SIZE(rval);
899 features->dcb_enable = SXGBE_HW_FEAT_DCB(rval);
900 features->splithead_enable = SXGBE_HW_FEAT_SPLIT_HDR(rval);
901 features->tcpseg_offload = SXGBE_HW_FEAT_TSO(rval);
902 features->debug_mem = SXGBE_HW_FEAT_DEBUG_MEM_IFACE(rval);
903 features->rss_enable = SXGBE_HW_FEAT_RSS(rval);
904 features->hash_tsize = SXGBE_HW_FEAT_HASH_TABLE_SIZE(rval);
905 features->l3l4_filer_size = SXGBE_HW_FEAT_L3L4_FILTER_NUM(rval);
906 }
907
908 /* Read First Capability Register CAP[2] */
909 rval = priv->hw->mac->get_hw_feature(priv->ioaddr, 2);
910 if (rval) {
911 features->rx_mtl_queues = SXGBE_HW_FEAT_RX_MTL_QUEUES(rval);
912 features->tx_mtl_queues = SXGBE_HW_FEAT_TX_MTL_QUEUES(rval);
913 features->rx_dma_channels = SXGBE_HW_FEAT_RX_DMA_CHANNELS(rval);
914 features->tx_dma_channels = SXGBE_HW_FEAT_TX_DMA_CHANNELS(rval);
915 features->pps_output_count = SXGBE_HW_FEAT_PPS_OUTPUTS(rval);
916 features->aux_input_count = SXGBE_HW_FEAT_AUX_SNAPSHOTS(rval);
917 }
918
919 return rval;
920 }
921
922 /**
923 * sxgbe_check_ether_addr: check if the MAC addr is valid
924 * @priv: driver private structure
925 * Description:
926 * it is to verify if the MAC address is valid, in case of failures it
927 * generates a random MAC address
928 */
sxgbe_check_ether_addr(struct sxgbe_priv_data * priv)929 static void sxgbe_check_ether_addr(struct sxgbe_priv_data *priv)
930 {
931 if (!is_valid_ether_addr(priv->dev->dev_addr)) {
932 u8 addr[ETH_ALEN];
933
934 priv->hw->mac->get_umac_addr((void __iomem *)
935 priv->ioaddr, addr, 0);
936 if (is_valid_ether_addr(addr))
937 eth_hw_addr_set(priv->dev, addr);
938 else
939 eth_hw_addr_random(priv->dev);
940 }
941 dev_info(priv->device, "device MAC address %pM\n",
942 priv->dev->dev_addr);
943 }
944
945 /**
946 * sxgbe_init_dma_engine: DMA init.
947 * @priv: driver private structure
948 * Description:
949 * It inits the DMA invoking the specific SXGBE callback.
950 * Some DMA parameters can be passed from the platform;
951 * in case of these are not passed a default is kept for the MAC or GMAC.
952 */
sxgbe_init_dma_engine(struct sxgbe_priv_data * priv)953 static int sxgbe_init_dma_engine(struct sxgbe_priv_data *priv)
954 {
955 int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_map = 0;
956 int queue_num;
957
958 if (priv->plat->dma_cfg) {
959 pbl = priv->plat->dma_cfg->pbl;
960 fixed_burst = priv->plat->dma_cfg->fixed_burst;
961 burst_map = priv->plat->dma_cfg->burst_map;
962 }
963
964 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num)
965 priv->hw->dma->cha_init(priv->ioaddr, queue_num,
966 fixed_burst, pbl,
967 (priv->txq[queue_num])->dma_tx_phy,
968 (priv->rxq[queue_num])->dma_rx_phy,
969 priv->dma_tx_size, priv->dma_rx_size);
970
971 return priv->hw->dma->init(priv->ioaddr, fixed_burst, burst_map);
972 }
973
974 /**
975 * sxgbe_init_mtl_engine: MTL init.
976 * @priv: driver private structure
977 * Description:
978 * It inits the MTL invoking the specific SXGBE callback.
979 */
sxgbe_init_mtl_engine(struct sxgbe_priv_data * priv)980 static void sxgbe_init_mtl_engine(struct sxgbe_priv_data *priv)
981 {
982 int queue_num;
983
984 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
985 priv->hw->mtl->mtl_set_txfifosize(priv->ioaddr, queue_num,
986 priv->hw_cap.tx_mtl_qsize);
987 priv->hw->mtl->mtl_enable_txqueue(priv->ioaddr, queue_num);
988 }
989 }
990
991 /**
992 * sxgbe_disable_mtl_engine: MTL disable.
993 * @priv: driver private structure
994 * Description:
995 * It disables the MTL queues by invoking the specific SXGBE callback.
996 */
sxgbe_disable_mtl_engine(struct sxgbe_priv_data * priv)997 static void sxgbe_disable_mtl_engine(struct sxgbe_priv_data *priv)
998 {
999 int queue_num;
1000
1001 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num)
1002 priv->hw->mtl->mtl_disable_txqueue(priv->ioaddr, queue_num);
1003 }
1004
1005
1006 /**
1007 * sxgbe_tx_timer: mitigation sw timer for tx.
1008 * @t: timer pointer
1009 * Description:
1010 * This is the timer handler to directly invoke the sxgbe_tx_clean.
1011 */
sxgbe_tx_timer(struct timer_list * t)1012 static void sxgbe_tx_timer(struct timer_list *t)
1013 {
1014 struct sxgbe_tx_queue *p = timer_container_of(p, t, txtimer);
1015 sxgbe_tx_queue_clean(p);
1016 }
1017
1018 /**
1019 * sxgbe_tx_init_coalesce: init tx mitigation options.
1020 * @priv: driver private structure
1021 * Description:
1022 * This inits the transmit coalesce parameters: i.e. timer rate,
1023 * timer handler and default threshold used for enabling the
1024 * interrupt on completion bit.
1025 */
sxgbe_tx_init_coalesce(struct sxgbe_priv_data * priv)1026 static void sxgbe_tx_init_coalesce(struct sxgbe_priv_data *priv)
1027 {
1028 u8 queue_num;
1029
1030 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
1031 struct sxgbe_tx_queue *p = priv->txq[queue_num];
1032 p->tx_coal_frames = SXGBE_TX_FRAMES;
1033 p->tx_coal_timer = SXGBE_COAL_TX_TIMER;
1034 timer_setup(&p->txtimer, sxgbe_tx_timer, 0);
1035 p->txtimer.expires = SXGBE_COAL_TIMER(p->tx_coal_timer);
1036 add_timer(&p->txtimer);
1037 }
1038 }
1039
sxgbe_tx_del_timer(struct sxgbe_priv_data * priv)1040 static void sxgbe_tx_del_timer(struct sxgbe_priv_data *priv)
1041 {
1042 u8 queue_num;
1043
1044 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
1045 struct sxgbe_tx_queue *p = priv->txq[queue_num];
1046 timer_delete_sync(&p->txtimer);
1047 }
1048 }
1049
1050 /**
1051 * sxgbe_open - open entry point of the driver
1052 * @dev : pointer to the device structure.
1053 * Description:
1054 * This function is the open entry point of the driver.
1055 * Return value:
1056 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1057 * file on failure.
1058 */
sxgbe_open(struct net_device * dev)1059 static int sxgbe_open(struct net_device *dev)
1060 {
1061 struct sxgbe_priv_data *priv = netdev_priv(dev);
1062 int ret, queue_num;
1063
1064 clk_prepare_enable(priv->sxgbe_clk);
1065
1066 sxgbe_check_ether_addr(priv);
1067
1068 /* Init the phy */
1069 ret = sxgbe_init_phy(dev);
1070 if (ret) {
1071 netdev_err(dev, "%s: Cannot attach to PHY (error: %d)\n",
1072 __func__, ret);
1073 goto phy_error;
1074 }
1075
1076 /* Create and initialize the TX/RX descriptors chains. */
1077 priv->dma_tx_size = SXGBE_ALIGN(DMA_TX_SIZE);
1078 priv->dma_rx_size = SXGBE_ALIGN(DMA_RX_SIZE);
1079 priv->dma_buf_sz = SXGBE_ALIGN(DMA_BUFFER_SIZE);
1080 priv->tx_tc = TC_DEFAULT;
1081 priv->rx_tc = TC_DEFAULT;
1082 init_dma_desc_rings(dev);
1083
1084 /* DMA initialization and SW reset */
1085 ret = sxgbe_init_dma_engine(priv);
1086 if (ret < 0) {
1087 netdev_err(dev, "%s: DMA initialization failed\n", __func__);
1088 goto init_error;
1089 }
1090
1091 /* MTL initialization */
1092 sxgbe_init_mtl_engine(priv);
1093
1094 /* Copy the MAC addr into the HW */
1095 priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
1096
1097 /* Initialize the MAC Core */
1098 priv->hw->mac->core_init(priv->ioaddr);
1099 SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) {
1100 priv->hw->mac->enable_rxqueue(priv->ioaddr, queue_num);
1101 }
1102
1103 /* Request the IRQ lines */
1104 ret = devm_request_irq(priv->device, priv->irq, sxgbe_common_interrupt,
1105 IRQF_SHARED, dev->name, dev);
1106 if (unlikely(ret < 0)) {
1107 netdev_err(dev, "%s: ERROR: allocating the IRQ %d (error: %d)\n",
1108 __func__, priv->irq, ret);
1109 goto init_error;
1110 }
1111
1112 /* If the LPI irq is different from the mac irq
1113 * register a dedicated handler
1114 */
1115 if (priv->lpi_irq != dev->irq) {
1116 ret = devm_request_irq(priv->device, priv->lpi_irq,
1117 sxgbe_common_interrupt,
1118 IRQF_SHARED, dev->name, dev);
1119 if (unlikely(ret < 0)) {
1120 netdev_err(dev, "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1121 __func__, priv->lpi_irq, ret);
1122 goto init_error;
1123 }
1124 }
1125
1126 /* Request TX DMA irq lines */
1127 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
1128 ret = devm_request_irq(priv->device,
1129 (priv->txq[queue_num])->irq_no,
1130 sxgbe_tx_interrupt, 0,
1131 dev->name, priv->txq[queue_num]);
1132 if (unlikely(ret < 0)) {
1133 netdev_err(dev, "%s: ERROR: allocating TX IRQ %d (error: %d)\n",
1134 __func__, priv->irq, ret);
1135 goto init_error;
1136 }
1137 }
1138
1139 /* Request RX DMA irq lines */
1140 SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) {
1141 ret = devm_request_irq(priv->device,
1142 (priv->rxq[queue_num])->irq_no,
1143 sxgbe_rx_interrupt, 0,
1144 dev->name, priv->rxq[queue_num]);
1145 if (unlikely(ret < 0)) {
1146 netdev_err(dev, "%s: ERROR: allocating TX IRQ %d (error: %d)\n",
1147 __func__, priv->irq, ret);
1148 goto init_error;
1149 }
1150 }
1151
1152 /* Enable the MAC Rx/Tx */
1153 priv->hw->mac->enable_tx(priv->ioaddr, true);
1154 priv->hw->mac->enable_rx(priv->ioaddr, true);
1155
1156 /* Set the HW DMA mode and the COE */
1157 sxgbe_mtl_operation_mode(priv);
1158
1159 /* Extra statistics */
1160 memset(&priv->xstats, 0, sizeof(struct sxgbe_extra_stats));
1161
1162 priv->xstats.tx_threshold = priv->tx_tc;
1163 priv->xstats.rx_threshold = priv->rx_tc;
1164
1165 /* Start the ball rolling... */
1166 netdev_dbg(dev, "DMA RX/TX processes started...\n");
1167 priv->hw->dma->start_tx(priv->ioaddr, SXGBE_TX_QUEUES);
1168 priv->hw->dma->start_rx(priv->ioaddr, SXGBE_RX_QUEUES);
1169
1170 if (dev->phydev)
1171 phy_start(dev->phydev);
1172
1173 /* initialise TX coalesce parameters */
1174 sxgbe_tx_init_coalesce(priv);
1175
1176 if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1177 priv->rx_riwt = SXGBE_MAX_DMA_RIWT;
1178 priv->hw->dma->rx_watchdog(priv->ioaddr, SXGBE_MAX_DMA_RIWT);
1179 }
1180
1181 priv->tx_lpi_timer = SXGBE_DEFAULT_LPI_TIMER;
1182 priv->eee_enabled = sxgbe_eee_init(priv);
1183
1184 napi_enable(&priv->napi);
1185 netif_start_queue(dev);
1186
1187 return 0;
1188
1189 init_error:
1190 free_dma_desc_resources(priv);
1191 if (dev->phydev)
1192 phy_disconnect(dev->phydev);
1193 phy_error:
1194 clk_disable_unprepare(priv->sxgbe_clk);
1195
1196 return ret;
1197 }
1198
1199 /**
1200 * sxgbe_release - close entry point of the driver
1201 * @dev : device pointer.
1202 * Description:
1203 * This is the stop entry point of the driver.
1204 */
sxgbe_release(struct net_device * dev)1205 static int sxgbe_release(struct net_device *dev)
1206 {
1207 struct sxgbe_priv_data *priv = netdev_priv(dev);
1208
1209 if (priv->eee_enabled)
1210 timer_delete_sync(&priv->eee_ctrl_timer);
1211
1212 /* Stop and disconnect the PHY */
1213 if (dev->phydev) {
1214 phy_stop(dev->phydev);
1215 phy_disconnect(dev->phydev);
1216 }
1217
1218 netif_tx_stop_all_queues(dev);
1219
1220 napi_disable(&priv->napi);
1221
1222 /* delete TX timers */
1223 sxgbe_tx_del_timer(priv);
1224
1225 /* Stop TX/RX DMA and clear the descriptors */
1226 priv->hw->dma->stop_tx(priv->ioaddr, SXGBE_TX_QUEUES);
1227 priv->hw->dma->stop_rx(priv->ioaddr, SXGBE_RX_QUEUES);
1228
1229 /* disable MTL queue */
1230 sxgbe_disable_mtl_engine(priv);
1231
1232 /* Release and free the Rx/Tx resources */
1233 free_dma_desc_resources(priv);
1234
1235 /* Disable the MAC Rx/Tx */
1236 priv->hw->mac->enable_tx(priv->ioaddr, false);
1237 priv->hw->mac->enable_rx(priv->ioaddr, false);
1238
1239 clk_disable_unprepare(priv->sxgbe_clk);
1240
1241 return 0;
1242 }
1243 /* Prepare first Tx descriptor for doing TSO operation */
sxgbe_tso_prepare(struct sxgbe_priv_data * priv,struct sxgbe_tx_norm_desc * first_desc,struct sk_buff * skb)1244 static void sxgbe_tso_prepare(struct sxgbe_priv_data *priv,
1245 struct sxgbe_tx_norm_desc *first_desc,
1246 struct sk_buff *skb)
1247 {
1248 unsigned int total_hdr_len, tcp_hdr_len;
1249
1250 /* Write first Tx descriptor with appropriate value */
1251 tcp_hdr_len = tcp_hdrlen(skb);
1252 total_hdr_len = skb_transport_offset(skb) + tcp_hdr_len;
1253
1254 first_desc->tdes01 = dma_map_single(priv->device, skb->data,
1255 total_hdr_len, DMA_TO_DEVICE);
1256 if (dma_mapping_error(priv->device, first_desc->tdes01))
1257 pr_err("%s: TX dma mapping failed!!\n", __func__);
1258
1259 first_desc->tdes23.tx_rd_des23.first_desc = 1;
1260 priv->hw->desc->tx_desc_enable_tse(first_desc, 1, total_hdr_len,
1261 tcp_hdr_len,
1262 skb->len - total_hdr_len);
1263 }
1264
1265 /**
1266 * sxgbe_xmit: Tx entry point of the driver
1267 * @skb : the socket buffer
1268 * @dev : device pointer
1269 * Description : this is the tx entry point of the driver.
1270 * It programs the chain or the ring and supports oversized frames
1271 * and SG feature.
1272 */
sxgbe_xmit(struct sk_buff * skb,struct net_device * dev)1273 static netdev_tx_t sxgbe_xmit(struct sk_buff *skb, struct net_device *dev)
1274 {
1275 unsigned int entry, frag_num;
1276 int cksum_flag = 0;
1277 struct netdev_queue *dev_txq;
1278 unsigned txq_index = skb_get_queue_mapping(skb);
1279 struct sxgbe_priv_data *priv = netdev_priv(dev);
1280 unsigned int tx_rsize = priv->dma_tx_size;
1281 struct sxgbe_tx_queue *tqueue = priv->txq[txq_index];
1282 struct sxgbe_tx_norm_desc *tx_desc, *first_desc;
1283 struct sxgbe_tx_ctxt_desc *ctxt_desc = NULL;
1284 int nr_frags = skb_shinfo(skb)->nr_frags;
1285 int no_pagedlen = skb_headlen(skb);
1286 int is_jumbo = 0;
1287 u16 cur_mss = skb_shinfo(skb)->gso_size;
1288 u32 ctxt_desc_req = 0;
1289
1290 /* get the TX queue handle */
1291 dev_txq = netdev_get_tx_queue(dev, txq_index);
1292
1293 if (unlikely(skb_is_gso(skb) && tqueue->prev_mss != cur_mss))
1294 ctxt_desc_req = 1;
1295
1296 if (unlikely(skb_vlan_tag_present(skb) ||
1297 ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1298 tqueue->hwts_tx_en)))
1299 ctxt_desc_req = 1;
1300
1301 if (priv->tx_path_in_lpi_mode)
1302 sxgbe_disable_eee_mode(priv);
1303
1304 if (unlikely(sxgbe_tx_avail(tqueue, tx_rsize) < nr_frags + 1)) {
1305 if (!netif_tx_queue_stopped(dev_txq)) {
1306 netif_tx_stop_queue(dev_txq);
1307 netdev_err(dev, "%s: Tx Ring is full when %d queue is awake\n",
1308 __func__, txq_index);
1309 }
1310 return NETDEV_TX_BUSY;
1311 }
1312
1313 entry = tqueue->cur_tx % tx_rsize;
1314 tx_desc = tqueue->dma_tx + entry;
1315
1316 first_desc = tx_desc;
1317 if (ctxt_desc_req)
1318 ctxt_desc = (struct sxgbe_tx_ctxt_desc *)first_desc;
1319
1320 /* save the skb address */
1321 tqueue->tx_skbuff[entry] = skb;
1322
1323 if (!is_jumbo) {
1324 if (likely(skb_is_gso(skb))) {
1325 /* TSO support */
1326 if (unlikely(tqueue->prev_mss != cur_mss)) {
1327 priv->hw->desc->tx_ctxt_desc_set_mss(
1328 ctxt_desc, cur_mss);
1329 priv->hw->desc->tx_ctxt_desc_set_tcmssv(
1330 ctxt_desc);
1331 priv->hw->desc->tx_ctxt_desc_reset_ostc(
1332 ctxt_desc);
1333 priv->hw->desc->tx_ctxt_desc_set_ctxt(
1334 ctxt_desc);
1335 priv->hw->desc->tx_ctxt_desc_set_owner(
1336 ctxt_desc);
1337
1338 entry = (++tqueue->cur_tx) % tx_rsize;
1339 first_desc = tqueue->dma_tx + entry;
1340
1341 tqueue->prev_mss = cur_mss;
1342 }
1343 sxgbe_tso_prepare(priv, first_desc, skb);
1344 } else {
1345 tx_desc->tdes01 = dma_map_single(priv->device,
1346 skb->data, no_pagedlen, DMA_TO_DEVICE);
1347 if (dma_mapping_error(priv->device, tx_desc->tdes01))
1348 netdev_err(dev, "%s: TX dma mapping failed!!\n",
1349 __func__);
1350
1351 priv->hw->desc->prepare_tx_desc(tx_desc, 1, no_pagedlen,
1352 no_pagedlen, cksum_flag);
1353 }
1354 }
1355
1356 for (frag_num = 0; frag_num < nr_frags; frag_num++) {
1357 const skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_num];
1358 int len = skb_frag_size(frag);
1359
1360 entry = (++tqueue->cur_tx) % tx_rsize;
1361 tx_desc = tqueue->dma_tx + entry;
1362 tx_desc->tdes01 = skb_frag_dma_map(priv->device, frag, 0, len,
1363 DMA_TO_DEVICE);
1364
1365 tqueue->tx_skbuff_dma[entry] = tx_desc->tdes01;
1366 tqueue->tx_skbuff[entry] = NULL;
1367
1368 /* prepare the descriptor */
1369 priv->hw->desc->prepare_tx_desc(tx_desc, 0, len,
1370 len, cksum_flag);
1371 /* memory barrier to flush descriptor */
1372 wmb();
1373
1374 /* set the owner */
1375 priv->hw->desc->set_tx_owner(tx_desc);
1376 }
1377
1378 /* close the descriptors */
1379 priv->hw->desc->close_tx_desc(tx_desc);
1380
1381 /* memory barrier to flush descriptor */
1382 wmb();
1383
1384 tqueue->tx_count_frames += nr_frags + 1;
1385 if (tqueue->tx_count_frames > tqueue->tx_coal_frames) {
1386 priv->hw->desc->clear_tx_ic(tx_desc);
1387 priv->xstats.tx_reset_ic_bit++;
1388 mod_timer(&tqueue->txtimer,
1389 SXGBE_COAL_TIMER(tqueue->tx_coal_timer));
1390 } else {
1391 tqueue->tx_count_frames = 0;
1392 }
1393
1394 /* set owner for first desc */
1395 priv->hw->desc->set_tx_owner(first_desc);
1396
1397 /* memory barrier to flush descriptor */
1398 wmb();
1399
1400 tqueue->cur_tx++;
1401
1402 /* display current ring */
1403 netif_dbg(priv, pktdata, dev, "%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d\n",
1404 __func__, tqueue->cur_tx % tx_rsize,
1405 tqueue->dirty_tx % tx_rsize, entry,
1406 first_desc, nr_frags);
1407
1408 if (unlikely(sxgbe_tx_avail(tqueue, tx_rsize) <= (MAX_SKB_FRAGS + 1))) {
1409 netif_dbg(priv, hw, dev, "%s: stop transmitted packets\n",
1410 __func__);
1411 netif_tx_stop_queue(dev_txq);
1412 }
1413
1414 dev->stats.tx_bytes += skb->len;
1415
1416 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1417 tqueue->hwts_tx_en)) {
1418 /* declare that device is doing timestamping */
1419 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1420 priv->hw->desc->tx_enable_tstamp(first_desc);
1421 }
1422
1423 skb_tx_timestamp(skb);
1424
1425 priv->hw->dma->enable_dma_transmission(priv->ioaddr, txq_index);
1426
1427 return NETDEV_TX_OK;
1428 }
1429
1430 /**
1431 * sxgbe_rx_refill: refill used skb preallocated buffers
1432 * @priv: driver private structure
1433 * Description : this is to reallocate the skb for the reception process
1434 * that is based on zero-copy.
1435 */
sxgbe_rx_refill(struct sxgbe_priv_data * priv)1436 static void sxgbe_rx_refill(struct sxgbe_priv_data *priv)
1437 {
1438 unsigned int rxsize = priv->dma_rx_size;
1439 int bfsize = priv->dma_buf_sz;
1440 u8 qnum = priv->cur_rx_qnum;
1441
1442 for (; priv->rxq[qnum]->cur_rx - priv->rxq[qnum]->dirty_rx > 0;
1443 priv->rxq[qnum]->dirty_rx++) {
1444 unsigned int entry = priv->rxq[qnum]->dirty_rx % rxsize;
1445 struct sxgbe_rx_norm_desc *p;
1446
1447 p = priv->rxq[qnum]->dma_rx + entry;
1448
1449 if (likely(priv->rxq[qnum]->rx_skbuff[entry] == NULL)) {
1450 struct sk_buff *skb;
1451
1452 skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
1453
1454 if (unlikely(skb == NULL))
1455 break;
1456
1457 priv->rxq[qnum]->rx_skbuff[entry] = skb;
1458 priv->rxq[qnum]->rx_skbuff_dma[entry] =
1459 dma_map_single(priv->device, skb->data, bfsize,
1460 DMA_FROM_DEVICE);
1461
1462 p->rdes23.rx_rd_des23.buf2_addr =
1463 priv->rxq[qnum]->rx_skbuff_dma[entry];
1464 }
1465
1466 /* Added memory barrier for RX descriptor modification */
1467 wmb();
1468 priv->hw->desc->set_rx_owner(p);
1469 priv->hw->desc->set_rx_int_on_com(p);
1470 /* Added memory barrier for RX descriptor modification */
1471 wmb();
1472 }
1473 }
1474
1475 /**
1476 * sxgbe_rx: receive the frames from the remote host
1477 * @priv: driver private structure
1478 * @limit: napi bugget.
1479 * Description : this the function called by the napi poll method.
1480 * It gets all the frames inside the ring.
1481 */
sxgbe_rx(struct sxgbe_priv_data * priv,int limit)1482 static int sxgbe_rx(struct sxgbe_priv_data *priv, int limit)
1483 {
1484 u8 qnum = priv->cur_rx_qnum;
1485 unsigned int rxsize = priv->dma_rx_size;
1486 unsigned int entry = priv->rxq[qnum]->cur_rx;
1487 unsigned int next_entry = 0;
1488 unsigned int count = 0;
1489 int checksum;
1490 int status;
1491
1492 while (count < limit) {
1493 struct sxgbe_rx_norm_desc *p;
1494 struct sk_buff *skb;
1495 int frame_len;
1496
1497 p = priv->rxq[qnum]->dma_rx + entry;
1498
1499 if (priv->hw->desc->get_rx_owner(p))
1500 break;
1501
1502 count++;
1503
1504 next_entry = (++priv->rxq[qnum]->cur_rx) % rxsize;
1505 prefetch(priv->rxq[qnum]->dma_rx + next_entry);
1506
1507 /* Read the status of the incoming frame and also get checksum
1508 * value based on whether it is enabled in SXGBE hardware or
1509 * not.
1510 */
1511 status = priv->hw->desc->rx_wbstatus(p, &priv->xstats,
1512 &checksum);
1513 if (unlikely(status < 0)) {
1514 entry = next_entry;
1515 continue;
1516 }
1517 if (unlikely(!priv->rxcsum_insertion))
1518 checksum = CHECKSUM_NONE;
1519
1520 skb = priv->rxq[qnum]->rx_skbuff[entry];
1521
1522 if (unlikely(!skb)) {
1523 netdev_err(priv->dev, "rx descriptor is not consistent\n");
1524 break;
1525 }
1526
1527 prefetch(skb->data - NET_IP_ALIGN);
1528 priv->rxq[qnum]->rx_skbuff[entry] = NULL;
1529
1530 frame_len = priv->hw->desc->get_rx_frame_len(p);
1531
1532 skb_put(skb, frame_len);
1533
1534 skb->ip_summed = checksum;
1535 if (checksum == CHECKSUM_NONE)
1536 netif_receive_skb(skb);
1537 else
1538 napi_gro_receive(&priv->napi, skb);
1539
1540 entry = next_entry;
1541 }
1542
1543 sxgbe_rx_refill(priv);
1544
1545 return count;
1546 }
1547
1548 /**
1549 * sxgbe_poll - sxgbe poll method (NAPI)
1550 * @napi : pointer to the napi structure.
1551 * @budget : maximum number of packets that the current CPU can receive from
1552 * all interfaces.
1553 * Description :
1554 * To look at the incoming frames and clear the tx resources.
1555 */
sxgbe_poll(struct napi_struct * napi,int budget)1556 static int sxgbe_poll(struct napi_struct *napi, int budget)
1557 {
1558 struct sxgbe_priv_data *priv = container_of(napi,
1559 struct sxgbe_priv_data, napi);
1560 int work_done = 0;
1561 u8 qnum = priv->cur_rx_qnum;
1562
1563 priv->xstats.napi_poll++;
1564 /* first, clean the tx queues */
1565 sxgbe_tx_all_clean(priv);
1566
1567 work_done = sxgbe_rx(priv, budget);
1568 if (work_done < budget) {
1569 napi_complete_done(napi, work_done);
1570 priv->hw->dma->enable_dma_irq(priv->ioaddr, qnum);
1571 }
1572
1573 return work_done;
1574 }
1575
1576 /**
1577 * sxgbe_tx_timeout
1578 * @dev : Pointer to net device structure
1579 * @txqueue: index of the hanging queue
1580 * Description: this function is called when a packet transmission fails to
1581 * complete within a reasonable time. The driver will mark the error in the
1582 * netdev structure and arrange for the device to be reset to a sane state
1583 * in order to transmit a new packet.
1584 */
sxgbe_tx_timeout(struct net_device * dev,unsigned int txqueue)1585 static void sxgbe_tx_timeout(struct net_device *dev, unsigned int txqueue)
1586 {
1587 struct sxgbe_priv_data *priv = netdev_priv(dev);
1588
1589 sxgbe_reset_all_tx_queues(priv);
1590 }
1591
1592 /**
1593 * sxgbe_common_interrupt - main ISR
1594 * @irq: interrupt number.
1595 * @dev_id: to pass the net device pointer.
1596 * Description: this is the main driver interrupt service routine.
1597 * It calls the DMA ISR and also the core ISR to manage PMT, MMC, LPI
1598 * interrupts.
1599 */
sxgbe_common_interrupt(int irq,void * dev_id)1600 static irqreturn_t sxgbe_common_interrupt(int irq, void *dev_id)
1601 {
1602 struct net_device *netdev = (struct net_device *)dev_id;
1603 struct sxgbe_priv_data *priv = netdev_priv(netdev);
1604 int status;
1605
1606 status = priv->hw->mac->host_irq_status(priv->ioaddr, &priv->xstats);
1607 /* For LPI we need to save the tx status */
1608 if (status & TX_ENTRY_LPI_MODE) {
1609 priv->xstats.tx_lpi_entry_n++;
1610 priv->tx_path_in_lpi_mode = true;
1611 }
1612 if (status & TX_EXIT_LPI_MODE) {
1613 priv->xstats.tx_lpi_exit_n++;
1614 priv->tx_path_in_lpi_mode = false;
1615 }
1616 if (status & RX_ENTRY_LPI_MODE)
1617 priv->xstats.rx_lpi_entry_n++;
1618 if (status & RX_EXIT_LPI_MODE)
1619 priv->xstats.rx_lpi_exit_n++;
1620
1621 return IRQ_HANDLED;
1622 }
1623
1624 /**
1625 * sxgbe_tx_interrupt - TX DMA ISR
1626 * @irq: interrupt number.
1627 * @dev_id: to pass the net device pointer.
1628 * Description: this is the tx dma interrupt service routine.
1629 */
sxgbe_tx_interrupt(int irq,void * dev_id)1630 static irqreturn_t sxgbe_tx_interrupt(int irq, void *dev_id)
1631 {
1632 int status;
1633 struct sxgbe_tx_queue *txq = (struct sxgbe_tx_queue *)dev_id;
1634 struct sxgbe_priv_data *priv = txq->priv_ptr;
1635
1636 /* get the channel status */
1637 status = priv->hw->dma->tx_dma_int_status(priv->ioaddr, txq->queue_no,
1638 &priv->xstats);
1639 /* check for normal path */
1640 if (likely((status & handle_tx)))
1641 napi_schedule(&priv->napi);
1642
1643 /* check for unrecoverable error */
1644 if (unlikely((status & tx_hard_error)))
1645 sxgbe_restart_tx_queue(priv, txq->queue_no);
1646
1647 /* check for TC configuration change */
1648 if (unlikely((status & tx_bump_tc) &&
1649 (priv->tx_tc != SXGBE_MTL_SFMODE) &&
1650 (priv->tx_tc < 512))) {
1651 /* step of TX TC is 32 till 128, otherwise 64 */
1652 priv->tx_tc += (priv->tx_tc < 128) ? 32 : 64;
1653 priv->hw->mtl->set_tx_mtl_mode(priv->ioaddr,
1654 txq->queue_no, priv->tx_tc);
1655 priv->xstats.tx_threshold = priv->tx_tc;
1656 }
1657
1658 return IRQ_HANDLED;
1659 }
1660
1661 /**
1662 * sxgbe_rx_interrupt - RX DMA ISR
1663 * @irq: interrupt number.
1664 * @dev_id: to pass the net device pointer.
1665 * Description: this is the rx dma interrupt service routine.
1666 */
sxgbe_rx_interrupt(int irq,void * dev_id)1667 static irqreturn_t sxgbe_rx_interrupt(int irq, void *dev_id)
1668 {
1669 int status;
1670 struct sxgbe_rx_queue *rxq = (struct sxgbe_rx_queue *)dev_id;
1671 struct sxgbe_priv_data *priv = rxq->priv_ptr;
1672
1673 /* get the channel status */
1674 status = priv->hw->dma->rx_dma_int_status(priv->ioaddr, rxq->queue_no,
1675 &priv->xstats);
1676
1677 if (likely((status & handle_rx) && (napi_schedule_prep(&priv->napi)))) {
1678 priv->hw->dma->disable_dma_irq(priv->ioaddr, rxq->queue_no);
1679 __napi_schedule(&priv->napi);
1680 }
1681
1682 /* check for TC configuration change */
1683 if (unlikely((status & rx_bump_tc) &&
1684 (priv->rx_tc != SXGBE_MTL_SFMODE) &&
1685 (priv->rx_tc < 128))) {
1686 /* step of TC is 32 */
1687 priv->rx_tc += 32;
1688 priv->hw->mtl->set_rx_mtl_mode(priv->ioaddr,
1689 rxq->queue_no, priv->rx_tc);
1690 priv->xstats.rx_threshold = priv->rx_tc;
1691 }
1692
1693 return IRQ_HANDLED;
1694 }
1695
sxgbe_get_stat64(void __iomem * ioaddr,int reg_lo,int reg_hi)1696 static inline u64 sxgbe_get_stat64(void __iomem *ioaddr, int reg_lo, int reg_hi)
1697 {
1698 u64 val = readl(ioaddr + reg_lo);
1699
1700 val |= ((u64)readl(ioaddr + reg_hi)) << 32;
1701
1702 return val;
1703 }
1704
1705
1706 /* sxgbe_get_stats64 - entry point to see statistical information of device
1707 * @dev : device pointer.
1708 * @stats : pointer to hold all the statistical information of device.
1709 * Description:
1710 * This function is a driver entry point whenever ifconfig command gets
1711 * executed to see device statistics. Statistics are number of
1712 * bytes sent or received, errors occurred etc.
1713 */
sxgbe_get_stats64(struct net_device * dev,struct rtnl_link_stats64 * stats)1714 static void sxgbe_get_stats64(struct net_device *dev,
1715 struct rtnl_link_stats64 *stats)
1716 {
1717 struct sxgbe_priv_data *priv = netdev_priv(dev);
1718 void __iomem *ioaddr = priv->ioaddr;
1719 u64 count;
1720
1721 spin_lock(&priv->stats_lock);
1722 /* Freeze the counter registers before reading value otherwise it may
1723 * get updated by hardware while we are reading them
1724 */
1725 writel(SXGBE_MMC_CTRL_CNT_FRZ, ioaddr + SXGBE_MMC_CTL_REG);
1726
1727 stats->rx_bytes = sxgbe_get_stat64(ioaddr,
1728 SXGBE_MMC_RXOCTETLO_GCNT_REG,
1729 SXGBE_MMC_RXOCTETHI_GCNT_REG);
1730
1731 stats->rx_packets = sxgbe_get_stat64(ioaddr,
1732 SXGBE_MMC_RXFRAMELO_GBCNT_REG,
1733 SXGBE_MMC_RXFRAMEHI_GBCNT_REG);
1734
1735 stats->multicast = sxgbe_get_stat64(ioaddr,
1736 SXGBE_MMC_RXMULTILO_GCNT_REG,
1737 SXGBE_MMC_RXMULTIHI_GCNT_REG);
1738
1739 stats->rx_crc_errors = sxgbe_get_stat64(ioaddr,
1740 SXGBE_MMC_RXCRCERRLO_REG,
1741 SXGBE_MMC_RXCRCERRHI_REG);
1742
1743 stats->rx_length_errors = sxgbe_get_stat64(ioaddr,
1744 SXGBE_MMC_RXLENERRLO_REG,
1745 SXGBE_MMC_RXLENERRHI_REG);
1746
1747 stats->rx_missed_errors = sxgbe_get_stat64(ioaddr,
1748 SXGBE_MMC_RXFIFOOVERFLOWLO_GBCNT_REG,
1749 SXGBE_MMC_RXFIFOOVERFLOWHI_GBCNT_REG);
1750
1751 stats->tx_bytes = sxgbe_get_stat64(ioaddr,
1752 SXGBE_MMC_TXOCTETLO_GCNT_REG,
1753 SXGBE_MMC_TXOCTETHI_GCNT_REG);
1754
1755 count = sxgbe_get_stat64(ioaddr, SXGBE_MMC_TXFRAMELO_GBCNT_REG,
1756 SXGBE_MMC_TXFRAMEHI_GBCNT_REG);
1757
1758 stats->tx_errors = sxgbe_get_stat64(ioaddr, SXGBE_MMC_TXFRAMELO_GCNT_REG,
1759 SXGBE_MMC_TXFRAMEHI_GCNT_REG);
1760 stats->tx_errors = count - stats->tx_errors;
1761 stats->tx_packets = count;
1762 stats->tx_fifo_errors = sxgbe_get_stat64(ioaddr, SXGBE_MMC_TXUFLWLO_GBCNT_REG,
1763 SXGBE_MMC_TXUFLWHI_GBCNT_REG);
1764 writel(0, ioaddr + SXGBE_MMC_CTL_REG);
1765 spin_unlock(&priv->stats_lock);
1766 }
1767
1768 /* sxgbe_set_features - entry point to set offload features of the device.
1769 * @dev : device pointer.
1770 * @features : features which are required to be set.
1771 * Description:
1772 * This function is a driver entry point and called by Linux kernel whenever
1773 * any device features are set or reset by user.
1774 * Return value:
1775 * This function returns 0 after setting or resetting device features.
1776 */
sxgbe_set_features(struct net_device * dev,netdev_features_t features)1777 static int sxgbe_set_features(struct net_device *dev,
1778 netdev_features_t features)
1779 {
1780 struct sxgbe_priv_data *priv = netdev_priv(dev);
1781 netdev_features_t changed = dev->features ^ features;
1782
1783 if (changed & NETIF_F_RXCSUM) {
1784 if (features & NETIF_F_RXCSUM) {
1785 priv->hw->mac->enable_rx_csum(priv->ioaddr);
1786 priv->rxcsum_insertion = true;
1787 } else {
1788 priv->hw->mac->disable_rx_csum(priv->ioaddr);
1789 priv->rxcsum_insertion = false;
1790 }
1791 }
1792
1793 return 0;
1794 }
1795
1796 /* sxgbe_change_mtu - entry point to change MTU size for the device.
1797 * @dev : device pointer.
1798 * @new_mtu : the new MTU size for the device.
1799 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
1800 * to drive packet transmission. Ethernet has an MTU of 1500 octets
1801 * (ETH_DATA_LEN). This value can be changed with ifconfig.
1802 * Return value:
1803 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1804 * file on failure.
1805 */
sxgbe_change_mtu(struct net_device * dev,int new_mtu)1806 static int sxgbe_change_mtu(struct net_device *dev, int new_mtu)
1807 {
1808 WRITE_ONCE(dev->mtu, new_mtu);
1809
1810 if (!netif_running(dev))
1811 return 0;
1812
1813 /* Recevice ring buffer size is needed to be set based on MTU. If MTU is
1814 * changed then reinitilisation of the receive ring buffers need to be
1815 * done. Hence bring interface down and bring interface back up
1816 */
1817 sxgbe_release(dev);
1818 return sxgbe_open(dev);
1819 }
1820
sxgbe_set_umac_addr(void __iomem * ioaddr,unsigned char * addr,unsigned int reg_n)1821 static void sxgbe_set_umac_addr(void __iomem *ioaddr, unsigned char *addr,
1822 unsigned int reg_n)
1823 {
1824 unsigned long data;
1825
1826 data = (addr[5] << 8) | addr[4];
1827 /* For MAC Addr registers se have to set the Address Enable (AE)
1828 * bit that has no effect on the High Reg 0 where the bit 31 (MO)
1829 * is RO.
1830 */
1831 writel(data | SXGBE_HI_REG_AE, ioaddr + SXGBE_ADDR_HIGH(reg_n));
1832 data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
1833 writel(data, ioaddr + SXGBE_ADDR_LOW(reg_n));
1834 }
1835
1836 /**
1837 * sxgbe_set_rx_mode - entry point for setting different receive mode of
1838 * a device. unicast, multicast addressing
1839 * @dev : pointer to the device structure
1840 * Description:
1841 * This function is a driver entry point which gets called by the kernel
1842 * whenever different receive mode like unicast, multicast and promiscuous
1843 * must be enabled/disabled.
1844 * Return value:
1845 * void.
1846 */
sxgbe_set_rx_mode(struct net_device * dev)1847 static void sxgbe_set_rx_mode(struct net_device *dev)
1848 {
1849 struct sxgbe_priv_data *priv = netdev_priv(dev);
1850 void __iomem *ioaddr = (void __iomem *)priv->ioaddr;
1851 unsigned int value = 0;
1852 u32 mc_filter[2];
1853 struct netdev_hw_addr *ha;
1854 int reg = 1;
1855
1856 netdev_dbg(dev, "%s: # mcasts %d, # unicast %d\n",
1857 __func__, netdev_mc_count(dev), netdev_uc_count(dev));
1858
1859 if (dev->flags & IFF_PROMISC) {
1860 value = SXGBE_FRAME_FILTER_PR;
1861
1862 } else if ((netdev_mc_count(dev) > SXGBE_HASH_TABLE_SIZE) ||
1863 (dev->flags & IFF_ALLMULTI)) {
1864 value = SXGBE_FRAME_FILTER_PM; /* pass all multi */
1865 writel(0xffffffff, ioaddr + SXGBE_HASH_HIGH);
1866 writel(0xffffffff, ioaddr + SXGBE_HASH_LOW);
1867
1868 } else if (!netdev_mc_empty(dev)) {
1869 /* Hash filter for multicast */
1870 value = SXGBE_FRAME_FILTER_HMC;
1871
1872 memset(mc_filter, 0, sizeof(mc_filter));
1873 netdev_for_each_mc_addr(ha, dev) {
1874 /* The upper 6 bits of the calculated CRC are used to
1875 * index the contens of the hash table
1876 */
1877 int bit_nr = bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26;
1878
1879 /* The most significant bit determines the register to
1880 * use (H/L) while the other 5 bits determine the bit
1881 * within the register.
1882 */
1883 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1884 }
1885 writel(mc_filter[0], ioaddr + SXGBE_HASH_LOW);
1886 writel(mc_filter[1], ioaddr + SXGBE_HASH_HIGH);
1887 }
1888
1889 /* Handle multiple unicast addresses (perfect filtering) */
1890 if (netdev_uc_count(dev) > SXGBE_MAX_PERFECT_ADDRESSES)
1891 /* Switch to promiscuous mode if more than 16 addrs
1892 * are required
1893 */
1894 value |= SXGBE_FRAME_FILTER_PR;
1895 else {
1896 netdev_for_each_uc_addr(ha, dev) {
1897 sxgbe_set_umac_addr(ioaddr, ha->addr, reg);
1898 reg++;
1899 }
1900 }
1901 #ifdef FRAME_FILTER_DEBUG
1902 /* Enable Receive all mode (to debug filtering_fail errors) */
1903 value |= SXGBE_FRAME_FILTER_RA;
1904 #endif
1905 writel(value, ioaddr + SXGBE_FRAME_FILTER);
1906
1907 netdev_dbg(dev, "Filter: 0x%08x\n\tHash: HI 0x%08x, LO 0x%08x\n",
1908 readl(ioaddr + SXGBE_FRAME_FILTER),
1909 readl(ioaddr + SXGBE_HASH_HIGH),
1910 readl(ioaddr + SXGBE_HASH_LOW));
1911 }
1912
1913 #ifdef CONFIG_NET_POLL_CONTROLLER
1914 /**
1915 * sxgbe_poll_controller - entry point for polling receive by device
1916 * @dev : pointer to the device structure
1917 * Description:
1918 * This function is used by NETCONSOLE and other diagnostic tools
1919 * to allow network I/O with interrupts disabled.
1920 * Return value:
1921 * Void.
1922 */
sxgbe_poll_controller(struct net_device * dev)1923 static void sxgbe_poll_controller(struct net_device *dev)
1924 {
1925 struct sxgbe_priv_data *priv = netdev_priv(dev);
1926
1927 disable_irq(priv->irq);
1928 sxgbe_rx_interrupt(priv->irq, dev);
1929 enable_irq(priv->irq);
1930 }
1931 #endif
1932
1933 /* sxgbe_ioctl - Entry point for the Ioctl
1934 * @dev: Device pointer.
1935 * @rq: An IOCTL specefic structure, that can contain a pointer to
1936 * a proprietary structure used to pass information to the driver.
1937 * @cmd: IOCTL command
1938 * Description:
1939 * Currently it supports the phy_mii_ioctl(...) and HW time stamping.
1940 */
sxgbe_ioctl(struct net_device * dev,struct ifreq * rq,int cmd)1941 static int sxgbe_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1942 {
1943 int ret = -EOPNOTSUPP;
1944
1945 if (!netif_running(dev))
1946 return -EINVAL;
1947
1948 switch (cmd) {
1949 case SIOCGMIIPHY:
1950 case SIOCGMIIREG:
1951 case SIOCSMIIREG:
1952 ret = phy_do_ioctl(dev, rq, cmd);
1953 break;
1954 default:
1955 break;
1956 }
1957
1958 return ret;
1959 }
1960
1961 static const struct net_device_ops sxgbe_netdev_ops = {
1962 .ndo_open = sxgbe_open,
1963 .ndo_start_xmit = sxgbe_xmit,
1964 .ndo_stop = sxgbe_release,
1965 .ndo_get_stats64 = sxgbe_get_stats64,
1966 .ndo_change_mtu = sxgbe_change_mtu,
1967 .ndo_set_features = sxgbe_set_features,
1968 .ndo_set_rx_mode = sxgbe_set_rx_mode,
1969 .ndo_tx_timeout = sxgbe_tx_timeout,
1970 .ndo_eth_ioctl = sxgbe_ioctl,
1971 #ifdef CONFIG_NET_POLL_CONTROLLER
1972 .ndo_poll_controller = sxgbe_poll_controller,
1973 #endif
1974 .ndo_set_mac_address = eth_mac_addr,
1975 };
1976
1977 /* Get the hardware ops */
sxgbe_get_ops(struct sxgbe_ops * const ops_ptr)1978 static void sxgbe_get_ops(struct sxgbe_ops * const ops_ptr)
1979 {
1980 ops_ptr->mac = sxgbe_get_core_ops();
1981 ops_ptr->desc = sxgbe_get_desc_ops();
1982 ops_ptr->dma = sxgbe_get_dma_ops();
1983 ops_ptr->mtl = sxgbe_get_mtl_ops();
1984
1985 /* set the MDIO communication Address/Data regisers */
1986 ops_ptr->mii.addr = SXGBE_MDIO_SCMD_ADD_REG;
1987 ops_ptr->mii.data = SXGBE_MDIO_SCMD_DATA_REG;
1988
1989 /* Assigning the default link settings
1990 * no SXGBE defined default values to be set in registers,
1991 * so assigning as 0 for port and duplex
1992 */
1993 ops_ptr->link.port = 0;
1994 ops_ptr->link.duplex = 0;
1995 ops_ptr->link.speed = SXGBE_SPEED_10G;
1996 }
1997
1998 /**
1999 * sxgbe_hw_init - Init the GMAC device
2000 * @priv: driver private structure
2001 * Description: this function checks the HW capability
2002 * (if supported) and sets the driver's features.
2003 */
sxgbe_hw_init(struct sxgbe_priv_data * const priv)2004 static int sxgbe_hw_init(struct sxgbe_priv_data * const priv)
2005 {
2006 u32 ctrl_ids;
2007
2008 priv->hw = kmalloc_obj(*priv->hw);
2009 if(!priv->hw)
2010 return -ENOMEM;
2011
2012 /* get the hardware ops */
2013 sxgbe_get_ops(priv->hw);
2014
2015 /* get the controller id */
2016 ctrl_ids = priv->hw->mac->get_controller_version(priv->ioaddr);
2017 priv->hw->ctrl_uid = (ctrl_ids & 0x00ff0000) >> 16;
2018 priv->hw->ctrl_id = (ctrl_ids & 0x000000ff);
2019 pr_info("user ID: 0x%x, Controller ID: 0x%x\n",
2020 priv->hw->ctrl_uid, priv->hw->ctrl_id);
2021
2022 /* get the H/W features */
2023 if (!sxgbe_get_hw_features(priv))
2024 pr_info("Hardware features not found\n");
2025
2026 if (priv->hw_cap.tx_csum_offload)
2027 pr_info("TX Checksum offload supported\n");
2028
2029 if (priv->hw_cap.rx_csum_offload)
2030 pr_info("RX Checksum offload supported\n");
2031
2032 return 0;
2033 }
2034
sxgbe_sw_reset(void __iomem * addr)2035 static int sxgbe_sw_reset(void __iomem *addr)
2036 {
2037 int retry_count = 10;
2038
2039 writel(SXGBE_DMA_SOFT_RESET, addr + SXGBE_DMA_MODE_REG);
2040 while (retry_count--) {
2041 if (!(readl(addr + SXGBE_DMA_MODE_REG) &
2042 SXGBE_DMA_SOFT_RESET))
2043 break;
2044 mdelay(10);
2045 }
2046
2047 if (retry_count < 0)
2048 return -EBUSY;
2049
2050 return 0;
2051 }
2052
2053 /**
2054 * sxgbe_drv_probe
2055 * @device: device pointer
2056 * @plat_dat: platform data pointer
2057 * @addr: iobase memory address
2058 * Description: this is the main probe function used to
2059 * call the alloc_etherdev, allocate the priv structure.
2060 */
sxgbe_drv_probe(struct device * device,struct sxgbe_plat_data * plat_dat,void __iomem * addr)2061 struct sxgbe_priv_data *sxgbe_drv_probe(struct device *device,
2062 struct sxgbe_plat_data *plat_dat,
2063 void __iomem *addr)
2064 {
2065 struct sxgbe_priv_data *priv;
2066 struct net_device *ndev;
2067 int ret;
2068 u8 queue_num;
2069
2070 ndev = alloc_etherdev_mqs(sizeof(struct sxgbe_priv_data),
2071 SXGBE_TX_QUEUES, SXGBE_RX_QUEUES);
2072 if (!ndev)
2073 return NULL;
2074
2075 SET_NETDEV_DEV(ndev, device);
2076
2077 priv = netdev_priv(ndev);
2078 priv->device = device;
2079 priv->dev = ndev;
2080
2081 sxgbe_set_ethtool_ops(ndev);
2082 priv->plat = plat_dat;
2083 priv->ioaddr = addr;
2084
2085 ret = sxgbe_sw_reset(priv->ioaddr);
2086 if (ret)
2087 goto error_free_netdev;
2088
2089 /* Verify driver arguments */
2090 sxgbe_verify_args();
2091
2092 /* Init MAC and get the capabilities */
2093 ret = sxgbe_hw_init(priv);
2094 if (ret)
2095 goto error_free_netdev;
2096
2097 /* allocate memory resources for Descriptor rings */
2098 ret = txring_mem_alloc(priv);
2099 if (ret)
2100 goto error_free_hw;
2101
2102 ret = rxring_mem_alloc(priv);
2103 if (ret)
2104 goto error_free_hw;
2105
2106 ndev->netdev_ops = &sxgbe_netdev_ops;
2107
2108 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2109 NETIF_F_RXCSUM | NETIF_F_TSO | NETIF_F_TSO6 |
2110 NETIF_F_GRO;
2111 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
2112 ndev->watchdog_timeo = msecs_to_jiffies(TX_TIMEO);
2113
2114 /* assign filtering support */
2115 ndev->priv_flags |= IFF_UNICAST_FLT;
2116
2117 /* MTU range: 68 - 9000 */
2118 ndev->min_mtu = MIN_MTU;
2119 ndev->max_mtu = MAX_MTU;
2120
2121 priv->msg_enable = netif_msg_init(debug, default_msg_level);
2122
2123 /* Enable TCP segmentation offload for all DMA channels */
2124 if (priv->hw_cap.tcpseg_offload) {
2125 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
2126 priv->hw->dma->enable_tso(priv->ioaddr, queue_num);
2127 }
2128 }
2129
2130 /* Enable Rx checksum offload */
2131 if (priv->hw_cap.rx_csum_offload) {
2132 priv->hw->mac->enable_rx_csum(priv->ioaddr);
2133 priv->rxcsum_insertion = true;
2134 }
2135
2136 /* Initialise pause frame settings */
2137 priv->rx_pause = 1;
2138 priv->tx_pause = 1;
2139
2140 /* Rx Watchdog is available, enable depend on platform data */
2141 if (!priv->plat->riwt_off) {
2142 priv->use_riwt = 1;
2143 pr_info("Enable RX Mitigation via HW Watchdog Timer\n");
2144 }
2145
2146 netif_napi_add(ndev, &priv->napi, sxgbe_poll);
2147
2148 spin_lock_init(&priv->stats_lock);
2149
2150 priv->sxgbe_clk = clk_get(priv->device, SXGBE_RESOURCE_NAME);
2151 if (IS_ERR(priv->sxgbe_clk)) {
2152 netdev_warn(ndev, "%s: warning: cannot get CSR clock\n",
2153 __func__);
2154 goto error_napi_del;
2155 }
2156
2157 /* If a specific clk_csr value is passed from the platform
2158 * this means that the CSR Clock Range selection cannot be
2159 * changed at run-time and it is fixed. Viceversa the driver'll try to
2160 * set the MDC clock dynamically according to the csr actual
2161 * clock input.
2162 */
2163 if (!priv->plat->clk_csr)
2164 sxgbe_clk_csr_set(priv);
2165 else
2166 priv->clk_csr = priv->plat->clk_csr;
2167
2168 /* MDIO bus Registration */
2169 ret = sxgbe_mdio_register(ndev);
2170 if (ret < 0) {
2171 netdev_dbg(ndev, "%s: MDIO bus (id: %d) registration failed\n",
2172 __func__, priv->plat->bus_id);
2173 goto error_clk_put;
2174 }
2175
2176 ret = register_netdev(ndev);
2177 if (ret) {
2178 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
2179 goto error_mdio_unregister;
2180 }
2181
2182 sxgbe_check_ether_addr(priv);
2183
2184 return priv;
2185
2186 error_mdio_unregister:
2187 sxgbe_mdio_unregister(ndev);
2188 error_clk_put:
2189 clk_put(priv->sxgbe_clk);
2190 error_napi_del:
2191 netif_napi_del(&priv->napi);
2192 error_free_hw:
2193 kfree(priv->hw);
2194 error_free_netdev:
2195 free_netdev(ndev);
2196
2197 return NULL;
2198 }
2199
2200 /**
2201 * sxgbe_drv_remove
2202 * @ndev: net device pointer
2203 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
2204 * changes the link status, releases the DMA descriptor rings.
2205 */
sxgbe_drv_remove(struct net_device * ndev)2206 void sxgbe_drv_remove(struct net_device *ndev)
2207 {
2208 struct sxgbe_priv_data *priv = netdev_priv(ndev);
2209 u8 queue_num;
2210
2211 netdev_info(ndev, "%s: removing driver\n", __func__);
2212
2213 SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) {
2214 priv->hw->mac->disable_rxqueue(priv->ioaddr, queue_num);
2215 }
2216
2217 priv->hw->dma->stop_rx(priv->ioaddr, SXGBE_RX_QUEUES);
2218 priv->hw->dma->stop_tx(priv->ioaddr, SXGBE_TX_QUEUES);
2219
2220 priv->hw->mac->enable_tx(priv->ioaddr, false);
2221 priv->hw->mac->enable_rx(priv->ioaddr, false);
2222
2223 unregister_netdev(ndev);
2224
2225 sxgbe_mdio_unregister(ndev);
2226
2227 clk_put(priv->sxgbe_clk);
2228
2229 netif_napi_del(&priv->napi);
2230
2231 kfree(priv->hw);
2232
2233 free_netdev(ndev);
2234 }
2235
2236 #ifdef CONFIG_PM
sxgbe_suspend(struct net_device * ndev)2237 int sxgbe_suspend(struct net_device *ndev)
2238 {
2239 return 0;
2240 }
2241
sxgbe_resume(struct net_device * ndev)2242 int sxgbe_resume(struct net_device *ndev)
2243 {
2244 return 0;
2245 }
2246
sxgbe_freeze(struct net_device * ndev)2247 int sxgbe_freeze(struct net_device *ndev)
2248 {
2249 return -ENOSYS;
2250 }
2251
sxgbe_restore(struct net_device * ndev)2252 int sxgbe_restore(struct net_device *ndev)
2253 {
2254 return -ENOSYS;
2255 }
2256 #endif /* CONFIG_PM */
2257
2258 /* Driver is configured as Platform driver */
sxgbe_init(void)2259 static int __init sxgbe_init(void)
2260 {
2261 int ret;
2262
2263 ret = sxgbe_register_platform();
2264 if (ret)
2265 goto err;
2266 return 0;
2267 err:
2268 pr_err("driver registration failed\n");
2269 return ret;
2270 }
2271
sxgbe_exit(void)2272 static void __exit sxgbe_exit(void)
2273 {
2274 sxgbe_unregister_platform();
2275 }
2276
2277 module_init(sxgbe_init);
2278 module_exit(sxgbe_exit);
2279
2280 #ifndef MODULE
sxgbe_cmdline_opt(char * str)2281 static int __init sxgbe_cmdline_opt(char *str)
2282 {
2283 char *opt;
2284
2285 if (!str || !*str)
2286 return 1;
2287 while ((opt = strsep(&str, ",")) != NULL) {
2288 if (!strncmp(opt, "eee_timer:", 10)) {
2289 if (kstrtoint(opt + 10, 0, &eee_timer))
2290 goto err;
2291 }
2292 }
2293 return 1;
2294
2295 err:
2296 pr_err("%s: ERROR broken module parameter conversion\n", __func__);
2297 return 1;
2298 }
2299
2300 __setup("sxgbeeth=", sxgbe_cmdline_opt);
2301 #endif /* MODULE */
2302
2303
2304
2305 MODULE_DESCRIPTION("Samsung 10G/2.5G/1G Ethernet PLATFORM driver");
2306
2307 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
2308 MODULE_PARM_DESC(eee_timer, "EEE-LPI Default LS timer value");
2309
2310 MODULE_AUTHOR("Siva Reddy Kallam <siva.kallam@samsung.com>");
2311 MODULE_AUTHOR("ByungHo An <bh74.an@samsung.com>");
2312 MODULE_AUTHOR("Girish K S <ks.giri@samsung.com>");
2313 MODULE_AUTHOR("Vipul Pandya <vipul.pandya@samsung.com>");
2314
2315 MODULE_LICENSE("GPL");
2316