1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU specific errata definitions 4 * 5 * Copyright (C) 2014 ARM Ltd. 6 */ 7 8 #include <linux/arm-smccc.h> 9 #include <linux/types.h> 10 #include <linux/cpu.h> 11 #include <asm/cpu.h> 12 #include <asm/cputype.h> 13 #include <asm/cpufeature.h> 14 #include <asm/fpsimd.h> 15 #include <asm/kvm_asm.h> 16 #include <asm/smp_plat.h> 17 18 static u64 target_impl_cpu_num; 19 static struct target_impl_cpu *target_impl_cpus; 20 21 bool cpu_errata_set_target_impl(u64 num, void *impl_cpus) 22 { 23 if (target_impl_cpu_num || !num || !impl_cpus) 24 return false; 25 26 target_impl_cpu_num = num; 27 target_impl_cpus = impl_cpus; 28 return true; 29 } 30 31 static inline bool __is_midr_in_range(u32 midr, struct midr_range const *range) 32 { 33 return midr_is_cpu_model_range(midr, range->model, 34 range->rv_min, range->rv_max); 35 } 36 37 static inline bool is_midr_in_range(struct midr_range const *range) 38 { 39 int i; 40 41 if (!target_impl_cpu_num) 42 return __is_midr_in_range(read_cpuid_id(), range); 43 44 for (i = 0; i < target_impl_cpu_num; i++) { 45 if (__is_midr_in_range(target_impl_cpus[i].midr, range)) 46 return true; 47 } 48 return false; 49 } 50 51 bool is_midr_in_range_list(struct midr_range const *ranges) 52 { 53 while (ranges->model) 54 if (is_midr_in_range(ranges++)) 55 return true; 56 return false; 57 } 58 EXPORT_SYMBOL_GPL(is_midr_in_range_list); 59 60 static bool __maybe_unused 61 __is_affected_midr_range(const struct arm64_cpu_capabilities *entry, 62 u32 midr, u32 revidr) 63 { 64 const struct arm64_midr_revidr *fix; 65 if (!__is_midr_in_range(midr, &entry->midr_range)) 66 return false; 67 68 midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK; 69 for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++) 70 if (midr == fix->midr_rv && (revidr & fix->revidr_mask)) 71 return false; 72 return true; 73 } 74 75 static bool __maybe_unused 76 is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope) 77 { 78 int i; 79 80 if (!target_impl_cpu_num) { 81 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 82 return __is_affected_midr_range(entry, read_cpuid_id(), 83 read_cpuid(REVIDR_EL1)); 84 } 85 86 for (i = 0; i < target_impl_cpu_num; i++) { 87 if (__is_affected_midr_range(entry, target_impl_cpus[i].midr, 88 target_impl_cpus[i].revidr)) 89 return true; 90 } 91 return false; 92 } 93 94 static bool __maybe_unused 95 is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry, 96 int scope) 97 { 98 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 99 return is_midr_in_range_list(entry->midr_range_list); 100 } 101 102 static bool __maybe_unused 103 is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope) 104 { 105 u32 model; 106 107 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 108 109 model = read_cpuid_id(); 110 model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) | 111 MIDR_ARCHITECTURE_MASK; 112 113 return model == entry->midr_range.model; 114 } 115 116 static bool 117 has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry, 118 int scope) 119 { 120 u64 mask = arm64_ftr_reg_ctrel0.strict_mask; 121 u64 sys = arm64_ftr_reg_ctrel0.sys_val & mask; 122 u64 ctr_raw, ctr_real; 123 124 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 125 126 /* 127 * We want to make sure that all the CPUs in the system expose 128 * a consistent CTR_EL0 to make sure that applications behaves 129 * correctly with migration. 130 * 131 * If a CPU has CTR_EL0.IDC but does not advertise it via CTR_EL0 : 132 * 133 * 1) It is safe if the system doesn't support IDC, as CPU anyway 134 * reports IDC = 0, consistent with the rest. 135 * 136 * 2) If the system has IDC, it is still safe as we trap CTR_EL0 137 * access on this CPU via the ARM64_HAS_CACHE_IDC capability. 138 * 139 * So, we need to make sure either the raw CTR_EL0 or the effective 140 * CTR_EL0 matches the system's copy to allow a secondary CPU to boot. 141 */ 142 ctr_raw = read_cpuid_cachetype() & mask; 143 ctr_real = read_cpuid_effective_cachetype() & mask; 144 145 return (ctr_real != sys) && (ctr_raw != sys); 146 } 147 148 #ifdef CONFIG_ARM64_ERRATUM_4311569 149 static DEFINE_STATIC_KEY_FALSE(arm_si_l1_workaround_4311569); 150 static int __init early_arm_si_l1_workaround_4311569_cfg(char *arg) 151 { 152 static_branch_enable(&arm_si_l1_workaround_4311569); 153 pr_info("Enabling cache maintenance workaround for ARM SI-L1 erratum 4311569\n"); 154 155 return 0; 156 } 157 early_param("arm_si_l1_workaround_4311569", early_arm_si_l1_workaround_4311569_cfg); 158 159 /* 160 * We have some earlier use cases to call cache maintenance operation functions, for example, 161 * dcache_inval_poc() and dcache_clean_poc() in head.S, before making decision to turn on this 162 * workaround. Since the scope of this workaround is limited to non-coherent DMA agents, its 163 * safe to have the workaround off by default. 164 */ 165 static bool 166 need_arm_si_l1_workaround_4311569(const struct arm64_cpu_capabilities *entry, int scope) 167 { 168 return static_branch_unlikely(&arm_si_l1_workaround_4311569); 169 } 170 #endif 171 172 static void 173 cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *cap) 174 { 175 u64 mask = arm64_ftr_reg_ctrel0.strict_mask; 176 bool enable_uct_trap = false; 177 178 /* Trap CTR_EL0 access on this CPU, only if it has a mismatch */ 179 if ((read_cpuid_cachetype() & mask) != 180 (arm64_ftr_reg_ctrel0.sys_val & mask)) 181 enable_uct_trap = true; 182 183 /* ... or if the system is affected by an erratum */ 184 if (cap->capability == ARM64_WORKAROUND_1542419) 185 enable_uct_trap = true; 186 187 if (enable_uct_trap) 188 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 189 } 190 191 #ifdef CONFIG_ARM64_ERRATUM_1463225 192 static bool 193 has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities *entry, 194 int scope) 195 { 196 return is_affected_midr_range_list(entry, scope) && is_kernel_in_hyp_mode(); 197 } 198 #endif 199 200 static void __maybe_unused 201 cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused) 202 { 203 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0); 204 } 205 206 #define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \ 207 .matches = is_affected_midr_range, \ 208 .midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max) 209 210 #define CAP_MIDR_ALL_VERSIONS(model) \ 211 .matches = is_affected_midr_range, \ 212 .midr_range = MIDR_ALL_VERSIONS(model) 213 214 #define MIDR_FIXED(rev, revidr_mask) \ 215 .fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}} 216 217 #define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \ 218 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ 219 CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) 220 221 #define CAP_MIDR_RANGE_LIST(list) \ 222 .matches = is_affected_midr_range_list, \ 223 .midr_range_list = list 224 225 /* Errata affecting a range of revisions of given model variant */ 226 #define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max) \ 227 ERRATA_MIDR_RANGE(m, var, r_min, var, r_max) 228 229 /* Errata affecting a single variant/revision of a model */ 230 #define ERRATA_MIDR_REV(model, var, rev) \ 231 ERRATA_MIDR_RANGE(model, var, rev, var, rev) 232 233 /* Errata affecting all variants/revisions of a given a model */ 234 #define ERRATA_MIDR_ALL_VERSIONS(model) \ 235 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ 236 CAP_MIDR_ALL_VERSIONS(model) 237 238 /* Errata affecting a list of midr ranges, with same work around */ 239 #define ERRATA_MIDR_RANGE_LIST(midr_list) \ 240 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ 241 CAP_MIDR_RANGE_LIST(midr_list) 242 243 static const __maybe_unused struct midr_range tx2_family_cpus[] = { 244 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 245 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 246 {}, 247 }; 248 249 static bool __maybe_unused 250 needs_tx2_tvm_workaround(const struct arm64_cpu_capabilities *entry, 251 int scope) 252 { 253 int i; 254 255 if (!is_affected_midr_range_list(entry, scope) || 256 !is_hyp_mode_available()) 257 return false; 258 259 for_each_possible_cpu(i) { 260 if (MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 0) != 0) 261 return true; 262 } 263 264 return false; 265 } 266 267 static bool __maybe_unused 268 has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry, 269 int scope) 270 { 271 bool has_dic = read_cpuid_cachetype() & BIT(CTR_EL0_DIC_SHIFT); 272 const struct midr_range range = MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1); 273 274 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 275 return is_midr_in_range(&range) && has_dic; 276 } 277 278 static const struct midr_range apple_cpus[] = { 279 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM), 280 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM), 281 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_PRO), 282 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_PRO), 283 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_MAX), 284 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_MAX), 285 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD), 286 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE), 287 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO), 288 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO), 289 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX), 290 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX), 291 {}, 292 }; 293 294 static bool has_impdef_pmuv3(const struct arm64_cpu_capabilities *entry, int scope) 295 { 296 u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); 297 unsigned int pmuver; 298 299 if (!is_kernel_in_hyp_mode()) 300 return false; 301 302 pmuver = cpuid_feature_extract_unsigned_field(dfr0, 303 ID_AA64DFR0_EL1_PMUVer_SHIFT); 304 if (pmuver != ID_AA64DFR0_EL1_PMUVer_IMP_DEF) 305 return false; 306 307 return is_midr_in_range_list(apple_cpus); 308 } 309 310 static bool has_broken_gic_v3_seis(const struct arm64_cpu_capabilities *entry, int scope) 311 { 312 return (is_kernel_in_hyp_mode() && 313 is_midr_in_range_list(apple_cpus) && 314 (read_sysreg_s(SYS_ICH_VTR_EL2) & ICH_VTR_EL2_SEIS)); 315 } 316 317 static void cpu_enable_impdef_pmuv3_traps(const struct arm64_cpu_capabilities *__unused) 318 { 319 sysreg_clear_set_s(SYS_HACR_EL2, 0, BIT(56)); 320 } 321 322 #ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI_SYNC 323 static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = { 324 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009 325 { 326 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0) 327 }, 328 { 329 .midr_range.model = MIDR_QCOM_KRYO, 330 .matches = is_kryo_midr, 331 }, 332 #endif 333 #ifdef CONFIG_ARM64_ERRATUM_1286807 334 { 335 ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0), 336 }, 337 { 338 /* Kryo4xx Gold (rcpe to rfpe) => (r0p0 to r3p0) */ 339 ERRATA_MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xe), 340 }, 341 #endif 342 #ifdef CONFIG_ARM64_ERRATUM_2441007 343 { 344 ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 345 }, 346 #endif 347 #ifdef CONFIG_ARM64_ERRATUM_2441009 348 { 349 /* Cortex-A510 r0p0 -> r1p1. Fixed in r1p2 */ 350 ERRATA_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1), 351 }, 352 #endif 353 #ifdef CONFIG_ARM64_ERRATUM_4118414 354 { 355 ERRATA_MIDR_RANGE_LIST(((const struct midr_range[]) { 356 MIDR_ALL_VERSIONS(MIDR_C1_PREMIUM), 357 MIDR_ALL_VERSIONS(MIDR_C1_ULTRA), 358 MIDR_ALL_VERSIONS(MIDR_CORTEX_A76), 359 MIDR_ALL_VERSIONS(MIDR_CORTEX_A76AE), 360 MIDR_ALL_VERSIONS(MIDR_CORTEX_A77), 361 MIDR_ALL_VERSIONS(MIDR_CORTEX_A78), 362 MIDR_ALL_VERSIONS(MIDR_CORTEX_A78AE), 363 MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C), 364 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), 365 MIDR_ALL_VERSIONS(MIDR_CORTEX_X1), 366 MIDR_ALL_VERSIONS(MIDR_CORTEX_X1C), 367 MIDR_ALL_VERSIONS(MIDR_CORTEX_X2), 368 MIDR_ALL_VERSIONS(MIDR_CORTEX_X3), 369 MIDR_ALL_VERSIONS(MIDR_CORTEX_X4), 370 MIDR_ALL_VERSIONS(MIDR_CORTEX_X925), 371 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1), 372 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), 373 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1), 374 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2), 375 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3), 376 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3AE), 377 MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS), 378 MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100), 379 {} 380 })), 381 }, 382 #endif 383 {} 384 }; 385 #endif 386 387 #ifdef CONFIG_CAVIUM_ERRATUM_23154 388 static const struct midr_range cavium_erratum_23154_cpus[] = { 389 MIDR_ALL_VERSIONS(MIDR_THUNDERX), 390 MIDR_ALL_VERSIONS(MIDR_THUNDERX_81XX), 391 MIDR_ALL_VERSIONS(MIDR_THUNDERX_83XX), 392 MIDR_ALL_VERSIONS(MIDR_OCTX2_98XX), 393 MIDR_ALL_VERSIONS(MIDR_OCTX2_96XX), 394 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XX), 395 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXN), 396 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXMM), 397 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXO), 398 {}, 399 }; 400 #endif 401 402 #ifdef CONFIG_CAVIUM_ERRATUM_27456 403 static const struct midr_range cavium_erratum_27456_cpus[] = { 404 /* Cavium ThunderX, T88 pass 1.x - 2.1 */ 405 MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 1), 406 /* Cavium ThunderX, T81 pass 1.0 */ 407 MIDR_REV(MIDR_THUNDERX_81XX, 0, 0), 408 {}, 409 }; 410 #endif 411 412 #ifdef CONFIG_CAVIUM_ERRATUM_30115 413 static const struct midr_range cavium_erratum_30115_cpus[] = { 414 /* Cavium ThunderX, T88 pass 1.x - 2.2 */ 415 MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 2), 416 /* Cavium ThunderX, T81 pass 1.0 - 1.2 */ 417 MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2), 418 /* Cavium ThunderX, T83 pass 1.0 */ 419 MIDR_REV(MIDR_THUNDERX_83XX, 0, 0), 420 {}, 421 }; 422 #endif 423 424 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 425 static const struct arm64_cpu_capabilities qcom_erratum_1003_list[] = { 426 { 427 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0), 428 }, 429 { 430 .midr_range.model = MIDR_QCOM_KRYO, 431 .matches = is_kryo_midr, 432 }, 433 {}, 434 }; 435 #endif 436 437 #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE 438 static const struct midr_range workaround_clean_cache[] = { 439 #if defined(CONFIG_ARM64_ERRATUM_826319) || \ 440 defined(CONFIG_ARM64_ERRATUM_827319) || \ 441 defined(CONFIG_ARM64_ERRATUM_824069) 442 /* Cortex-A53 r0p[012]: ARM errata 826319, 827319, 824069 */ 443 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2), 444 #endif 445 #ifdef CONFIG_ARM64_ERRATUM_819472 446 /* Cortex-A53 r0p[01] : ARM errata 819472 */ 447 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1), 448 #endif 449 {}, 450 }; 451 #endif 452 453 #ifdef CONFIG_ARM64_ERRATUM_1418040 454 /* 455 * - 1188873 affects r0p0 to r2p0 456 * - 1418040 affects r0p0 to r3p1 457 */ 458 static const struct midr_range erratum_1418040_list[] = { 459 /* Cortex-A76 r0p0 to r3p1 */ 460 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1), 461 /* Neoverse-N1 r0p0 to r3p1 */ 462 MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 3, 1), 463 /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */ 464 MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf), 465 {}, 466 }; 467 #endif 468 469 #ifdef CONFIG_ARM64_ERRATUM_845719 470 static const struct midr_range erratum_845719_list[] = { 471 /* Cortex-A53 r0p[01234] */ 472 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4), 473 /* Brahma-B53 r0p[0] */ 474 MIDR_REV(MIDR_BRAHMA_B53, 0, 0), 475 /* Kryo2XX Silver rAp4 */ 476 MIDR_REV(MIDR_QCOM_KRYO_2XX_SILVER, 0xa, 0x4), 477 {}, 478 }; 479 #endif 480 481 #ifdef CONFIG_ARM64_ERRATUM_843419 482 static const struct arm64_cpu_capabilities erratum_843419_list[] = { 483 { 484 /* Cortex-A53 r0p[01234] */ 485 .matches = is_affected_midr_range, 486 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4), 487 MIDR_FIXED(0x4, BIT(8)), 488 }, 489 { 490 /* Brahma-B53 r0p[0] */ 491 .matches = is_affected_midr_range, 492 ERRATA_MIDR_REV(MIDR_BRAHMA_B53, 0, 0), 493 }, 494 {}, 495 }; 496 #endif 497 498 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT 499 static const struct midr_range erratum_speculative_at_list[] = { 500 #ifdef CONFIG_ARM64_ERRATUM_1165522 501 /* Cortex A76 r0p0 to r2p0 */ 502 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0), 503 #endif 504 #ifdef CONFIG_ARM64_ERRATUM_1319367 505 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 506 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 507 #endif 508 #ifdef CONFIG_ARM64_ERRATUM_1530923 509 /* Cortex A55 r0p0 to r2p0 */ 510 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 2, 0), 511 /* Kryo4xx Silver (rdpe => r1p0) */ 512 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 513 #endif 514 {}, 515 }; 516 #endif 517 518 #ifdef CONFIG_ARM64_ERRATUM_1463225 519 static const struct midr_range erratum_1463225[] = { 520 /* Cortex-A76 r0p0 - r3p1 */ 521 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1), 522 /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */ 523 MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf), 524 {}, 525 }; 526 #endif 527 528 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 529 static const struct midr_range trbe_overwrite_fill_mode_cpus[] = { 530 #ifdef CONFIG_ARM64_ERRATUM_2139208 531 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), 532 MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100), 533 #endif 534 #ifdef CONFIG_ARM64_ERRATUM_2119858 535 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), 536 MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0), 537 #endif 538 {}, 539 }; 540 #endif /* CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE */ 541 542 #ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE 543 static const struct midr_range tsb_flush_fail_cpus[] = { 544 #ifdef CONFIG_ARM64_ERRATUM_2067961 545 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), 546 MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100), 547 #endif 548 #ifdef CONFIG_ARM64_ERRATUM_2054223 549 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), 550 #endif 551 {}, 552 }; 553 #endif /* CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE */ 554 555 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 556 static struct midr_range trbe_write_out_of_range_cpus[] = { 557 #ifdef CONFIG_ARM64_ERRATUM_2253138 558 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), 559 MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100), 560 #endif 561 #ifdef CONFIG_ARM64_ERRATUM_2224489 562 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), 563 MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0), 564 #endif 565 {}, 566 }; 567 #endif /* CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE */ 568 569 #ifdef CONFIG_ARM64_ERRATUM_1742098 570 static struct midr_range broken_aarch32_aes[] = { 571 MIDR_RANGE(MIDR_CORTEX_A57, 0, 1, 0xf, 0xf), 572 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 573 {}, 574 }; 575 #endif /* CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE */ 576 577 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 578 static const struct midr_range erratum_spec_unpriv_load_list[] = { 579 #ifdef CONFIG_ARM64_ERRATUM_3117295 580 MIDR_ALL_VERSIONS(MIDR_CORTEX_A510), 581 #endif 582 #ifdef CONFIG_ARM64_ERRATUM_2966298 583 /* Cortex-A520 r0p0 to r0p1 */ 584 MIDR_REV_RANGE(MIDR_CORTEX_A520, 0, 0, 1), 585 #endif 586 {}, 587 }; 588 #endif 589 590 #ifdef CONFIG_ARM64_ERRATUM_3194386 591 static const struct midr_range erratum_spec_ssbs_list[] = { 592 MIDR_ALL_VERSIONS(MIDR_CORTEX_A76), 593 MIDR_ALL_VERSIONS(MIDR_CORTEX_A77), 594 MIDR_ALL_VERSIONS(MIDR_CORTEX_A78), 595 MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C), 596 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), 597 MIDR_ALL_VERSIONS(MIDR_CORTEX_A715), 598 MIDR_ALL_VERSIONS(MIDR_CORTEX_A720), 599 MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE), 600 MIDR_ALL_VERSIONS(MIDR_CORTEX_A725), 601 MIDR_ALL_VERSIONS(MIDR_CORTEX_X1), 602 MIDR_ALL_VERSIONS(MIDR_CORTEX_X1C), 603 MIDR_ALL_VERSIONS(MIDR_CORTEX_X2), 604 MIDR_ALL_VERSIONS(MIDR_CORTEX_X3), 605 MIDR_ALL_VERSIONS(MIDR_CORTEX_X4), 606 MIDR_ALL_VERSIONS(MIDR_CORTEX_X925), 607 MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100), 608 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1), 609 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), 610 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N3), 611 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1), 612 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2), 613 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3), 614 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3AE), 615 {} 616 }; 617 #endif 618 619 #ifdef CONFIG_ARM64_ERRATUM_4193714 620 static bool has_sme_dvmsync_erratum(const struct arm64_cpu_capabilities *entry, 621 int scope) 622 { 623 if (!id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) 624 return false; 625 626 return is_affected_midr_range(entry, scope); 627 } 628 629 static void cpu_enable_sme_dvmsync(const struct arm64_cpu_capabilities *__unused) 630 { 631 if (this_cpu_has_cap(ARM64_WORKAROUND_4193714)) 632 sme_enable_dvmsync(); 633 } 634 #endif 635 636 #ifdef CONFIG_AMPERE_ERRATUM_AC03_CPU_38 637 static const struct midr_range erratum_ac03_cpu_38_list[] = { 638 MIDR_ALL_VERSIONS(MIDR_AMPERE1), 639 MIDR_ALL_VERSIONS(MIDR_AMPERE1A), 640 {}, 641 }; 642 #endif 643 644 #ifdef CONFIG_AMPERE_ERRATUM_AC04_CPU_23 645 static const struct midr_range erratum_ac04_cpu_23_list[] = { 646 MIDR_ALL_VERSIONS(MIDR_AMPERE1A), 647 {}, 648 }; 649 #endif 650 651 #ifdef CONFIG_ARM64_WORKAROUND_DISABLE_CNP 652 static const struct midr_range cnp_erratum_cpus[] = { 653 #ifdef CONFIG_NVIDIA_CARMEL_CNP_ERRATUM 654 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 655 #endif 656 #ifdef CONFIG_HISILICON_ERRATUM_162100125 657 MIDR_ALL_VERSIONS(MIDR_HISI_HIP09), 658 #endif 659 {}, 660 }; 661 #endif 662 663 const struct arm64_cpu_capabilities arm64_errata[] = { 664 #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE 665 { 666 .desc = "ARM errata 826319, 827319, 824069, or 819472", 667 .capability = ARM64_WORKAROUND_CLEAN_CACHE, 668 ERRATA_MIDR_RANGE_LIST(workaround_clean_cache), 669 .cpu_enable = cpu_enable_cache_maint_trap, 670 }, 671 #endif 672 #ifdef CONFIG_ARM64_ERRATUM_832075 673 { 674 /* Cortex-A57 r0p0 - r1p2 */ 675 .desc = "ARM erratum 832075", 676 .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE, 677 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57, 678 0, 0, 679 1, 2), 680 }, 681 #endif 682 #ifdef CONFIG_ARM64_ERRATUM_834220 683 { 684 /* Cortex-A57 r0p0 - r1p2 */ 685 .desc = "ARM erratum 834220", 686 .capability = ARM64_WORKAROUND_834220, 687 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57, 688 0, 0, 689 1, 2), 690 }, 691 #endif 692 #ifdef CONFIG_ARM64_ERRATUM_843419 693 { 694 .desc = "ARM erratum 843419", 695 .capability = ARM64_WORKAROUND_843419, 696 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 697 .matches = cpucap_multi_entry_cap_matches, 698 .match_list = erratum_843419_list, 699 }, 700 #endif 701 #ifdef CONFIG_ARM64_ERRATUM_845719 702 { 703 .desc = "ARM erratum 845719", 704 .capability = ARM64_WORKAROUND_845719, 705 ERRATA_MIDR_RANGE_LIST(erratum_845719_list), 706 }, 707 #endif 708 #ifdef CONFIG_CAVIUM_ERRATUM_23154 709 { 710 .desc = "Cavium errata 23154 and 38545", 711 .capability = ARM64_WORKAROUND_CAVIUM_23154, 712 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 713 ERRATA_MIDR_RANGE_LIST(cavium_erratum_23154_cpus), 714 }, 715 #endif 716 #ifdef CONFIG_CAVIUM_ERRATUM_27456 717 { 718 .desc = "Cavium erratum 27456", 719 .capability = ARM64_WORKAROUND_CAVIUM_27456, 720 ERRATA_MIDR_RANGE_LIST(cavium_erratum_27456_cpus), 721 }, 722 #endif 723 #ifdef CONFIG_CAVIUM_ERRATUM_30115 724 { 725 .desc = "Cavium erratum 30115", 726 .capability = ARM64_WORKAROUND_CAVIUM_30115, 727 ERRATA_MIDR_RANGE_LIST(cavium_erratum_30115_cpus), 728 }, 729 #endif 730 { 731 .desc = "Mismatched cache type (CTR_EL0)", 732 .capability = ARM64_MISMATCHED_CACHE_TYPE, 733 .matches = has_mismatched_cache_type, 734 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 735 .cpu_enable = cpu_enable_trap_ctr_access, 736 }, 737 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 738 { 739 .desc = "Qualcomm Technologies Falkor/Kryo erratum 1003", 740 .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003, 741 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 742 .matches = cpucap_multi_entry_cap_matches, 743 .match_list = qcom_erratum_1003_list, 744 }, 745 #endif 746 #ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI_SYNC 747 { 748 .desc = "Broken broadcast TLBI completion", 749 .capability = ARM64_WORKAROUND_REPEAT_TLBI_SYNC, 750 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 751 .matches = cpucap_multi_entry_cap_matches, 752 .match_list = arm64_repeat_tlbi_list, 753 }, 754 #endif 755 #ifdef CONFIG_ARM64_ERRATUM_858921 756 { 757 /* Cortex-A73 all versions */ 758 .desc = "ARM erratum 858921", 759 .capability = ARM64_WORKAROUND_858921, 760 ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 761 }, 762 #endif 763 { 764 .desc = "Spectre-v2", 765 .capability = ARM64_SPECTRE_V2, 766 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 767 .matches = has_spectre_v2, 768 .cpu_enable = spectre_v2_enable_mitigation, 769 }, 770 #ifdef CONFIG_RANDOMIZE_BASE 771 { 772 /* Must come after the Spectre-v2 entry */ 773 .desc = "Spectre-v3a", 774 .capability = ARM64_SPECTRE_V3A, 775 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 776 .matches = has_spectre_v3a, 777 .cpu_enable = spectre_v3a_enable_mitigation, 778 }, 779 #endif 780 { 781 .desc = "Spectre-v4", 782 .capability = ARM64_SPECTRE_V4, 783 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 784 .matches = has_spectre_v4, 785 .cpu_enable = spectre_v4_enable_mitigation, 786 }, 787 { 788 .desc = "Spectre-BHB", 789 .capability = ARM64_SPECTRE_BHB, 790 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 791 .matches = is_spectre_bhb_affected, 792 .cpu_enable = spectre_bhb_enable_mitigation, 793 }, 794 #ifdef CONFIG_ARM64_ERRATUM_1418040 795 { 796 .desc = "ARM erratum 1418040", 797 .capability = ARM64_WORKAROUND_1418040, 798 ERRATA_MIDR_RANGE_LIST(erratum_1418040_list), 799 /* 800 * We need to allow affected CPUs to come in late, but 801 * also need the non-affected CPUs to be able to come 802 * in at any point in time. Wonderful. 803 */ 804 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 805 }, 806 #endif 807 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT 808 { 809 .desc = "ARM errata 1165522, 1319367, or 1530923", 810 .capability = ARM64_WORKAROUND_SPECULATIVE_AT, 811 ERRATA_MIDR_RANGE_LIST(erratum_speculative_at_list), 812 }, 813 #endif 814 #ifdef CONFIG_ARM64_ERRATUM_1463225 815 { 816 .desc = "ARM erratum 1463225", 817 .capability = ARM64_WORKAROUND_1463225, 818 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 819 .matches = has_cortex_a76_erratum_1463225, 820 .midr_range_list = erratum_1463225, 821 }, 822 #endif 823 #ifdef CONFIG_CAVIUM_TX2_ERRATUM_219 824 { 825 .desc = "Cavium ThunderX2 erratum 219 (KVM guest sysreg trapping)", 826 .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_TVM, 827 ERRATA_MIDR_RANGE_LIST(tx2_family_cpus), 828 .matches = needs_tx2_tvm_workaround, 829 }, 830 { 831 .desc = "Cavium ThunderX2 erratum 219 (PRFM removal)", 832 .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM, 833 ERRATA_MIDR_RANGE_LIST(tx2_family_cpus), 834 }, 835 #endif 836 #ifdef CONFIG_ARM64_ERRATUM_1542419 837 { 838 /* we depend on the firmware portion for correctness */ 839 .desc = "ARM erratum 1542419 (kernel portion)", 840 .capability = ARM64_WORKAROUND_1542419, 841 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 842 .matches = has_neoverse_n1_erratum_1542419, 843 .cpu_enable = cpu_enable_trap_ctr_access, 844 }, 845 #endif 846 #ifdef CONFIG_ARM64_ERRATUM_1508412 847 { 848 /* we depend on the firmware portion for correctness */ 849 .desc = "ARM erratum 1508412 (kernel portion)", 850 .capability = ARM64_WORKAROUND_1508412, 851 ERRATA_MIDR_RANGE(MIDR_CORTEX_A77, 852 0, 0, 853 1, 0), 854 }, 855 #endif 856 #ifdef CONFIG_ARM64_WORKAROUND_DISABLE_CNP 857 { 858 .desc = "NVIDIA Carmel CNP erratum, or Hisilicon erratum 162100125", 859 .capability = ARM64_WORKAROUND_DISABLE_CNP, 860 ERRATA_MIDR_RANGE_LIST(cnp_erratum_cpus), 861 }, 862 #endif 863 #ifdef CONFIG_NVIDIA_OLYMPUS_1027_ERRATUM 864 { 865 /* NVIDIA Olympus core */ 866 .desc = "NVIDIA Olympus device store/load ordering erratum", 867 .capability = ARM64_WORKAROUND_NVIDIA_OLYMPUS_1027, 868 ERRATA_MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS), 869 }, 870 #endif 871 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 872 { 873 /* 874 * The erratum work around is handled within the TRBE 875 * driver and can be applied per-cpu. So, we can allow 876 * a late CPU to come online with this erratum. 877 */ 878 .desc = "ARM erratum 2119858 or 2139208", 879 .capability = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE, 880 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 881 CAP_MIDR_RANGE_LIST(trbe_overwrite_fill_mode_cpus), 882 }, 883 #endif 884 #ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE 885 { 886 .desc = "ARM erratum 2067961 or 2054223", 887 .capability = ARM64_WORKAROUND_TSB_FLUSH_FAILURE, 888 ERRATA_MIDR_RANGE_LIST(tsb_flush_fail_cpus), 889 }, 890 #endif 891 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 892 { 893 .desc = "ARM erratum 2253138 or 2224489", 894 .capability = ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE, 895 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 896 CAP_MIDR_RANGE_LIST(trbe_write_out_of_range_cpus), 897 }, 898 #endif 899 #ifdef CONFIG_ARM64_ERRATUM_2645198 900 { 901 .desc = "ARM erratum 2645198", 902 .capability = ARM64_WORKAROUND_2645198, 903 ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A715) 904 }, 905 #endif 906 #ifdef CONFIG_ARM64_ERRATUM_2077057 907 { 908 .desc = "ARM erratum 2077057", 909 .capability = ARM64_WORKAROUND_2077057, 910 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 911 }, 912 #endif 913 #ifdef CONFIG_ARM64_ERRATUM_2064142 914 { 915 .desc = "ARM erratum 2064142", 916 .capability = ARM64_WORKAROUND_2064142, 917 918 /* Cortex-A510 r0p0 - r0p2 */ 919 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) 920 }, 921 #endif 922 #ifdef CONFIG_ARM64_ERRATUM_2457168 923 { 924 .desc = "ARM erratum 2457168", 925 .capability = ARM64_WORKAROUND_2457168, 926 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 927 928 /* Cortex-A510 r0p0-r1p1 */ 929 CAP_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1) 930 }, 931 #endif 932 #ifdef CONFIG_ARM64_ERRATUM_2038923 933 { 934 .desc = "ARM erratum 2038923", 935 .capability = ARM64_WORKAROUND_2038923, 936 937 /* Cortex-A510 r0p0 - r0p2 */ 938 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) 939 }, 940 #endif 941 #ifdef CONFIG_ARM64_ERRATUM_1902691 942 { 943 .desc = "ARM erratum 1902691", 944 .capability = ARM64_WORKAROUND_1902691, 945 946 /* Cortex-A510 r0p0 - r0p1 */ 947 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 1) 948 }, 949 #endif 950 #ifdef CONFIG_ARM64_ERRATUM_1742098 951 { 952 .desc = "ARM erratum 1742098", 953 .capability = ARM64_WORKAROUND_1742098, 954 CAP_MIDR_RANGE_LIST(broken_aarch32_aes), 955 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 956 }, 957 #endif 958 #ifdef CONFIG_ARM64_ERRATUM_2658417 959 { 960 .desc = "ARM erratum 2658417", 961 .capability = ARM64_WORKAROUND_2658417, 962 /* Cortex-A510 r0p0 - r1p1 */ 963 ERRATA_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1), 964 MIDR_FIXED(MIDR_CPU_VAR_REV(1,1), BIT(25)), 965 }, 966 #endif 967 #ifdef CONFIG_ARM64_ERRATUM_3194386 968 { 969 .desc = "SSBS not fully self-synchronizing", 970 .capability = ARM64_WORKAROUND_SPECULATIVE_SSBS, 971 ERRATA_MIDR_RANGE_LIST(erratum_spec_ssbs_list), 972 }, 973 #endif 974 #ifdef CONFIG_ARM64_ERRATUM_4311569 975 { 976 .capability = ARM64_WORKAROUND_4311569, 977 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 978 .matches = need_arm_si_l1_workaround_4311569, 979 }, 980 #endif 981 #ifdef CONFIG_ARM64_ERRATUM_4193714 982 { 983 .desc = "C1-Pro SME DVMSync early acknowledgement", 984 .capability = ARM64_WORKAROUND_4193714, 985 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 986 .matches = has_sme_dvmsync_erratum, 987 .cpu_enable = cpu_enable_sme_dvmsync, 988 /* C1-Pro r0p0 - r1p2 (the latter only when REVIDR_EL1[0]==0) */ 989 .midr_range = MIDR_RANGE(MIDR_C1_PRO, 0, 0, 1, 2), 990 MIDR_FIXED(MIDR_CPU_VAR_REV(1, 2), BIT(0)), 991 }, 992 #endif 993 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 994 { 995 .desc = "ARM errata 2966298, 3117295", 996 .capability = ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD, 997 /* Cortex-A520 r0p0 - r0p1 */ 998 ERRATA_MIDR_RANGE_LIST(erratum_spec_unpriv_load_list), 999 }, 1000 #endif 1001 #ifdef CONFIG_AMPERE_ERRATUM_AC03_CPU_38 1002 { 1003 .desc = "AmpereOne erratum AC03_CPU_38", 1004 .capability = ARM64_WORKAROUND_AMPERE_AC03_CPU_38, 1005 ERRATA_MIDR_RANGE_LIST(erratum_ac03_cpu_38_list), 1006 }, 1007 #endif 1008 #ifdef CONFIG_AMPERE_ERRATUM_AC04_CPU_23 1009 { 1010 .desc = "AmpereOne erratum AC04_CPU_23", 1011 .capability = ARM64_WORKAROUND_AMPERE_AC04_CPU_23, 1012 ERRATA_MIDR_RANGE_LIST(erratum_ac04_cpu_23_list), 1013 }, 1014 #endif 1015 { 1016 .desc = "Broken CNTVOFF_EL2", 1017 .capability = ARM64_WORKAROUND_QCOM_ORYON_CNTVOFF, 1018 ERRATA_MIDR_RANGE_LIST(((const struct midr_range[]) { 1019 MIDR_ALL_VERSIONS(MIDR_QCOM_ORYON_X1), 1020 {} 1021 })), 1022 }, 1023 { 1024 .desc = "Apple IMPDEF PMUv3 Traps", 1025 .capability = ARM64_WORKAROUND_PMUV3_IMPDEF_TRAPS, 1026 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 1027 .matches = has_impdef_pmuv3, 1028 .cpu_enable = cpu_enable_impdef_pmuv3_traps, 1029 }, 1030 { 1031 .desc = "Known broken GICv3 SEIS implementation", 1032 .capability = ARM64_WORKAROUND_GICv3_BROKEN_SEIS, 1033 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1034 .matches = has_broken_gic_v3_seis, 1035 }, 1036 { 1037 } 1038 }; 1039