1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
4 */
5
6 #ifndef __MT76_H
7 #define __MT76_H
8
9 #include <linux/kernel.h>
10 #include <linux/io.h>
11 #include <linux/spinlock.h>
12 #include <linux/skbuff.h>
13 #include <linux/leds.h>
14 #include <linux/usb.h>
15 #include <linux/average.h>
16 #include <linux/soc/airoha/airoha_offload.h>
17 #include <linux/soc/mediatek/mtk_wed.h>
18 #include <net/mac80211.h>
19 #include <net/page_pool/helpers.h>
20 #include "util.h"
21 #include "testmode.h"
22
23 #define MT_MCU_RING_SIZE 32
24 #define MT_RX_BUF_SIZE 2048
25 #define MT_SKB_HEAD_LEN 256
26
27 #define MT_MAX_NON_AQL_PKT 16
28 #define MT_TXQ_FREE_THR 32
29
30 #define MT76_TOKEN_FREE_THR 64
31
32 #define MT_QFLAG_WED_RING GENMASK(1, 0)
33 #define MT_QFLAG_WED_TYPE GENMASK(4, 2)
34 #define MT_QFLAG_WED BIT(5)
35 #define MT_QFLAG_WED_RRO BIT(6)
36 #define MT_QFLAG_WED_RRO_EN BIT(7)
37 #define MT_QFLAG_EMI_EN BIT(8)
38 #define MT_QFLAG_NPU BIT(9)
39
40 #define __MT_WED_Q(_type, _n) (MT_QFLAG_WED | \
41 FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \
42 FIELD_PREP(MT_QFLAG_WED_RING, _n))
43 #define __MT_WED_RRO_Q(_type, _n) (MT_QFLAG_WED_RRO | __MT_WED_Q(_type, _n))
44
45 #define MT_WED_Q_TX(_n) __MT_WED_Q(MT76_WED_Q_TX, _n)
46 #define MT_WED_Q_RX(_n) __MT_WED_Q(MT76_WED_Q_RX, _n)
47 #define MT_WED_Q_TXFREE __MT_WED_Q(MT76_WED_Q_TXFREE, 0)
48 #define MT_WED_RRO_Q_DATA(_n) __MT_WED_RRO_Q(MT76_WED_RRO_Q_DATA, _n)
49 #define MT_WED_RRO_Q_MSDU_PG(_n) __MT_WED_RRO_Q(MT76_WED_RRO_Q_MSDU_PG, _n)
50 #define MT_WED_RRO_Q_IND __MT_WED_RRO_Q(MT76_WED_RRO_Q_IND, 0)
51 #define MT_WED_RRO_Q_RXDMAD_C __MT_WED_RRO_Q(MT76_WED_RRO_Q_RXDMAD_C, 0)
52
53 #define __MT_NPU_Q(_type, _n) (MT_QFLAG_NPU | \
54 FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \
55 FIELD_PREP(MT_QFLAG_WED_RING, _n))
56 #define MT_NPU_Q_TX(_n) __MT_NPU_Q(MT76_WED_Q_TX, _n)
57 #define MT_NPU_Q_RX(_n) __MT_NPU_Q(MT76_WED_Q_RX, _n)
58 #define MT_NPU_Q_TXFREE(_n) (FIELD_PREP(MT_QFLAG_WED_TYPE, MT76_WED_Q_TXFREE) | \
59 FIELD_PREP(MT_QFLAG_WED_RING, _n))
60
61 struct mt76_dev;
62 struct mt76_phy;
63 struct mt76_wcid;
64 struct mt76s_intr;
65 struct mt76_chanctx;
66 struct mt76_vif_link;
67
68 struct mt76_reg_pair {
69 u32 reg;
70 u32 value;
71 };
72
73 enum mt76_bus_type {
74 MT76_BUS_MMIO,
75 MT76_BUS_USB,
76 MT76_BUS_SDIO,
77 };
78
79 enum mt76_wed_type {
80 MT76_WED_Q_TX,
81 MT76_WED_Q_TXFREE,
82 MT76_WED_Q_RX,
83 MT76_WED_RRO_Q_DATA,
84 MT76_WED_RRO_Q_MSDU_PG,
85 MT76_WED_RRO_Q_IND,
86 MT76_WED_RRO_Q_RXDMAD_C,
87 };
88
89 enum mt76_hwrro_mode {
90 MT76_HWRRO_OFF,
91 MT76_HWRRO_V3,
92 MT76_HWRRO_V3_1,
93 };
94
95 struct mt76_bus_ops {
96 u32 (*rr)(struct mt76_dev *dev, u32 offset);
97 void (*wr)(struct mt76_dev *dev, u32 offset, u32 val);
98 u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val);
99 void (*write_copy)(struct mt76_dev *dev, u32 offset, const void *data,
100 int len);
101 void (*read_copy)(struct mt76_dev *dev, u32 offset, void *data,
102 int len);
103 int (*wr_rp)(struct mt76_dev *dev, u32 base,
104 const struct mt76_reg_pair *rp, int len);
105 int (*rd_rp)(struct mt76_dev *dev, u32 base,
106 struct mt76_reg_pair *rp, int len);
107 enum mt76_bus_type type;
108 };
109
110 #define mt76_is_usb(dev) ((dev)->bus->type == MT76_BUS_USB)
111 #define mt76_is_mmio(dev) ((dev)->bus->type == MT76_BUS_MMIO)
112 #define mt76_is_sdio(dev) ((dev)->bus->type == MT76_BUS_SDIO)
113
114 enum mt76_txq_id {
115 MT_TXQ_VO = IEEE80211_AC_VO,
116 MT_TXQ_VI = IEEE80211_AC_VI,
117 MT_TXQ_BE = IEEE80211_AC_BE,
118 MT_TXQ_BK = IEEE80211_AC_BK,
119 MT_TXQ_PSD,
120 MT_TXQ_BEACON,
121 MT_TXQ_CAB,
122 __MT_TXQ_MAX
123 };
124
125 enum mt76_mcuq_id {
126 MT_MCUQ_WM,
127 MT_MCUQ_WA,
128 MT_MCUQ_FWDL,
129 __MT_MCUQ_MAX
130 };
131
132 enum mt76_rxq_id {
133 MT_RXQ_MAIN,
134 MT_RXQ_MCU,
135 MT_RXQ_MCU_WA,
136 MT_RXQ_BAND1,
137 MT_RXQ_BAND1_WA,
138 MT_RXQ_MAIN_WA,
139 MT_RXQ_BAND2,
140 MT_RXQ_BAND2_WA,
141 MT_RXQ_RRO_BAND0,
142 MT_RXQ_RRO_BAND1,
143 MT_RXQ_RRO_BAND2,
144 MT_RXQ_MSDU_PAGE_BAND0,
145 MT_RXQ_MSDU_PAGE_BAND1,
146 MT_RXQ_MSDU_PAGE_BAND2,
147 MT_RXQ_TXFREE_BAND0,
148 MT_RXQ_TXFREE_BAND1,
149 MT_RXQ_TXFREE_BAND2,
150 MT_RXQ_RRO_IND,
151 MT_RXQ_RRO_RXDMAD_C,
152 MT_RXQ_NPU0,
153 MT_RXQ_NPU1,
154 __MT_RXQ_MAX
155 };
156
157 enum mt76_band_id {
158 MT_BAND0,
159 MT_BAND1,
160 MT_BAND2,
161 __MT_MAX_BAND
162 };
163
164 enum mt76_cipher_type {
165 MT_CIPHER_NONE,
166 MT_CIPHER_WEP40,
167 MT_CIPHER_TKIP,
168 MT_CIPHER_TKIP_NO_MIC,
169 MT_CIPHER_AES_CCMP,
170 MT_CIPHER_WEP104,
171 MT_CIPHER_BIP_CMAC_128,
172 MT_CIPHER_WEP128,
173 MT_CIPHER_WAPI,
174 MT_CIPHER_CCMP_CCX,
175 MT_CIPHER_CCMP_256,
176 MT_CIPHER_GCMP,
177 MT_CIPHER_GCMP_256,
178 };
179
180 enum mt76_dfs_state {
181 MT_DFS_STATE_UNKNOWN,
182 MT_DFS_STATE_DISABLED,
183 MT_DFS_STATE_CAC,
184 MT_DFS_STATE_ACTIVE,
185 };
186
187 #define MT76_RNR_SCAN_MAX_BSSIDS 16
188 struct mt76_scan_rnr_param {
189 u8 bssid[MT76_RNR_SCAN_MAX_BSSIDS][ETH_ALEN];
190 u8 channel[MT76_RNR_SCAN_MAX_BSSIDS];
191 u8 random_mac[ETH_ALEN];
192 u8 seq_num;
193 u8 bssid_num;
194 u32 sreq_flag;
195 };
196
197 struct mt76_queue_buf {
198 dma_addr_t addr;
199 u16 len:15,
200 skip_unmap:1;
201 };
202
203 struct mt76_tx_info {
204 struct mt76_queue_buf buf[32];
205 struct sk_buff *skb;
206 int nbuf;
207 u32 info;
208 };
209
210 struct mt76_queue_entry {
211 union {
212 void *buf;
213 struct sk_buff *skb;
214 };
215 union {
216 struct mt76_txwi_cache *txwi;
217 struct urb *urb;
218 int buf_sz;
219 };
220 dma_addr_t dma_addr[2];
221 u16 dma_len[2];
222 u16 wcid;
223 bool skip_buf0:1;
224 bool skip_buf1:1;
225 bool done:1;
226 };
227
228 struct mt76_queue_regs {
229 u32 desc_base;
230 u32 ring_size;
231 u32 cpu_idx;
232 u32 dma_idx;
233 } __packed __aligned(4);
234
235 struct mt76_queue {
236 struct mt76_queue_regs __iomem *regs;
237
238 spinlock_t lock;
239 spinlock_t cleanup_lock;
240 struct mt76_queue_entry *entry;
241 struct mt76_rro_desc *rro_desc;
242 struct mt76_desc *desc;
243
244 u16 first;
245 u16 head;
246 u16 tail;
247 u8 hw_idx;
248 u8 ep;
249 int ndesc;
250 int queued;
251 int buf_size;
252 bool stopped;
253 bool blocked;
254
255 u8 buf_offset;
256 u16 flags;
257 u8 magic_cnt;
258
259 __le16 *emi_cpu_idx;
260
261 struct mtk_wed_device *wed;
262 struct mt76_dev *dev;
263 u32 wed_regs;
264
265 dma_addr_t desc_dma;
266 struct sk_buff *rx_head;
267 struct page_pool *page_pool;
268 };
269
270 struct mt76_mcu_ops {
271 unsigned int max_retry;
272 u32 headroom;
273 u32 tailroom;
274
275 int (*mcu_send_msg)(struct mt76_dev *dev, int cmd, const void *data,
276 int len, bool wait_resp);
277 int (*mcu_skb_prepare_msg)(struct mt76_dev *dev, struct sk_buff *skb,
278 int cmd, int *seq);
279 int (*mcu_skb_send_msg)(struct mt76_dev *dev, struct sk_buff *skb,
280 int cmd, int *seq);
281 int (*mcu_parse_response)(struct mt76_dev *dev, int cmd,
282 struct sk_buff *skb, int seq);
283 u32 (*mcu_rr)(struct mt76_dev *dev, u32 offset);
284 void (*mcu_wr)(struct mt76_dev *dev, u32 offset, u32 val);
285 int (*mcu_wr_rp)(struct mt76_dev *dev, u32 base,
286 const struct mt76_reg_pair *rp, int len);
287 int (*mcu_rd_rp)(struct mt76_dev *dev, u32 base,
288 struct mt76_reg_pair *rp, int len);
289 int (*mcu_restart)(struct mt76_dev *dev);
290 };
291
292 struct mt76_queue_ops {
293 int (*init)(struct mt76_dev *dev,
294 int (*poll)(struct napi_struct *napi, int budget));
295
296 int (*alloc)(struct mt76_dev *dev, struct mt76_queue *q,
297 int idx, int n_desc, int bufsize,
298 u32 ring_base);
299
300 int (*tx_queue_skb)(struct mt76_phy *phy, struct mt76_queue *q,
301 enum mt76_txq_id qid, struct sk_buff *skb,
302 struct mt76_wcid *wcid, struct ieee80211_sta *sta);
303
304 int (*tx_queue_skb_raw)(struct mt76_dev *dev, struct mt76_queue *q,
305 struct sk_buff *skb, u32 tx_info);
306
307 void *(*dequeue)(struct mt76_dev *dev, struct mt76_queue *q, bool flush,
308 int *len, u32 *info, bool *more);
309
310 void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid);
311
312 void (*tx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q,
313 bool flush);
314
315 void (*rx_queue_init)(struct mt76_dev *dev, enum mt76_rxq_id qid,
316 int (*poll)(struct napi_struct *napi, int budget));
317
318 void (*rx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q);
319
320 void (*kick)(struct mt76_dev *dev, struct mt76_queue *q);
321
322 void (*reset_q)(struct mt76_dev *dev, struct mt76_queue *q,
323 bool reset_idx);
324 };
325
326 enum mt76_phy_type {
327 MT_PHY_TYPE_CCK,
328 MT_PHY_TYPE_OFDM,
329 MT_PHY_TYPE_HT,
330 MT_PHY_TYPE_HT_GF,
331 MT_PHY_TYPE_VHT,
332 MT_PHY_TYPE_HE_SU = 8,
333 MT_PHY_TYPE_HE_EXT_SU,
334 MT_PHY_TYPE_HE_TB,
335 MT_PHY_TYPE_HE_MU,
336 MT_PHY_TYPE_EHT_SU = 13,
337 MT_PHY_TYPE_EHT_TRIG,
338 MT_PHY_TYPE_EHT_MU,
339 __MT_PHY_TYPE_MAX,
340 };
341
342 struct mt76_sta_stats {
343 u64 tx_mode[__MT_PHY_TYPE_MAX];
344 u64 tx_bw[5]; /* 20, 40, 80, 160, 320 */
345 u64 tx_nss[4]; /* 1, 2, 3, 4 */
346 u64 tx_mcs[16]; /* mcs idx */
347 u64 tx_bytes;
348 /* WED TX */
349 u32 tx_packets; /* unit: MSDU */
350 u32 tx_retries;
351 u32 tx_failed;
352 /* WED RX */
353 u64 rx_bytes;
354 u32 rx_packets;
355 u32 rx_errors;
356 u32 rx_drops;
357 };
358
359 enum mt76_wcid_flags {
360 MT_WCID_FLAG_CHECK_PS,
361 MT_WCID_FLAG_PS,
362 MT_WCID_FLAG_4ADDR,
363 MT_WCID_FLAG_HDR_TRANS,
364 MT_WCID_FLAG_TDLS_PEER,
365 };
366
367 #define MT76_N_WCIDS 1088
368 #define MT76_BEACON_MON_MAX_MISS 7
369
370 /* stored in ieee80211_tx_info::hw_queue */
371 #define MT_TX_HW_QUEUE_PHY GENMASK(3, 2)
372
373 DECLARE_EWMA(signal, 10, 8);
374
375 #define MT_WCID_TX_INFO_RATE GENMASK(15, 0)
376 #define MT_WCID_TX_INFO_NSS GENMASK(17, 16)
377 #define MT_WCID_TX_INFO_TXPWR_ADJ GENMASK(25, 18)
378 #define MT_WCID_TX_INFO_SET BIT(31)
379
380 struct mt76_wcid {
381 struct mt76_rx_tid __rcu *aggr[IEEE80211_NUM_TIDS];
382
383 atomic_t non_aql_packets;
384 unsigned long flags;
385
386 struct ewma_signal rssi;
387 int inactive_count;
388
389 struct rate_info rate;
390 unsigned long ampdu_state;
391
392 u16 idx;
393 u8 hw_key_idx;
394 u8 hw_key_idx2;
395
396 u8 offchannel:1;
397 u8 sta:1;
398 u8 sta_disabled:1;
399 u8 amsdu:1;
400 u8 phy_idx:2;
401 u8 link_id:4;
402 bool link_valid;
403
404 u8 rx_check_pn;
405 u8 rx_key_pn[IEEE80211_NUM_TIDS + 1][6];
406 u16 cipher;
407
408 u32 tx_info;
409 bool sw_iv;
410
411 struct list_head tx_list;
412 struct sk_buff_head tx_pending;
413 struct sk_buff_head tx_offchannel;
414
415 struct list_head list;
416 struct idr pktid;
417
418 struct mt76_sta_stats stats;
419
420 struct list_head poll_list;
421
422 struct mt76_wcid *def_wcid;
423 };
424
425 struct mt76_txq {
426 u16 wcid;
427
428 u16 agg_ssn;
429 bool send_bar;
430 bool aggr;
431 };
432
433 /* data0 */
434 #define RRO_IND_DATA0_IND_REASON_MASK GENMASK(31, 28)
435 #define RRO_IND_DATA0_START_SEQ_MASK GENMASK(27, 16)
436 #define RRO_IND_DATA0_SEQ_ID_MASK GENMASK(11, 0)
437 /* data1 */
438 #define RRO_IND_DATA1_MAGIC_CNT_MASK GENMASK(31, 29)
439 #define RRO_IND_DATA1_IND_COUNT_MASK GENMASK(12, 0)
440 struct mt76_wed_rro_ind {
441 __le32 data0;
442 __le32 data1;
443 };
444
445 struct mt76_txwi_cache {
446 struct list_head list;
447 dma_addr_t dma_addr;
448
449 union {
450 struct sk_buff *skb;
451 void *ptr;
452 };
453
454 u8 qid;
455 u8 phy_idx;
456 };
457
458 struct mt76_rx_tid {
459 struct rcu_head rcu_head;
460
461 struct mt76_dev *dev;
462
463 spinlock_t lock;
464 struct delayed_work reorder_work;
465
466 u16 id;
467 u16 head;
468 u16 size;
469 u16 nframes;
470
471 u8 num;
472
473 u8 started:1, stopped:1, timer_pending:1;
474
475 struct sk_buff *reorder_buf[] __counted_by(size);
476 };
477
478 #define MT_TX_CB_DMA_DONE BIT(0)
479 #define MT_TX_CB_TXS_DONE BIT(1)
480 #define MT_TX_CB_TXS_FAILED BIT(2)
481
482 #define MT_PACKET_ID_MASK GENMASK(6, 0)
483 #define MT_PACKET_ID_NO_ACK 0
484 #define MT_PACKET_ID_NO_SKB 1
485 #define MT_PACKET_ID_WED 2
486 #define MT_PACKET_ID_FIRST 3
487 #define MT_PACKET_ID_HAS_RATE BIT(7)
488 /* This is timer for when to give up when waiting for TXS callback,
489 * with starting time being the time at which the DMA_DONE callback
490 * was seen (so, we know packet was processed then, it should not take
491 * long after that for firmware to send the TXS callback if it is going
492 * to do so.)
493 */
494 #define MT_TX_STATUS_SKB_TIMEOUT (HZ / 4)
495
496 struct mt76_tx_cb {
497 unsigned long jiffies;
498 u16 wcid;
499 u8 pktid;
500 u8 flags;
501 };
502
503 enum {
504 MT76_STATE_INITIALIZED,
505 MT76_STATE_REGISTERED,
506 MT76_STATE_RUNNING,
507 MT76_STATE_MCU_RUNNING,
508 MT76_SCANNING,
509 MT76_HW_SCANNING,
510 MT76_HW_SCHED_SCANNING,
511 MT76_RESTART,
512 MT76_RESET,
513 MT76_MCU_RESET,
514 MT76_REMOVED,
515 MT76_READING_STATS,
516 MT76_STATE_POWER_OFF,
517 MT76_STATE_SUSPEND,
518 MT76_STATE_ROC,
519 MT76_STATE_PM,
520 MT76_STATE_WED_RESET,
521 };
522
523 enum mt76_sta_event {
524 MT76_STA_EVENT_ASSOC,
525 MT76_STA_EVENT_AUTHORIZE,
526 MT76_STA_EVENT_DISASSOC,
527 };
528
529 struct mt76_hw_cap {
530 bool has_2ghz;
531 bool has_5ghz;
532 bool has_6ghz;
533 };
534
535 #define MT_DRV_TXWI_NO_FREE BIT(0)
536 #define MT_DRV_TX_ALIGNED4_SKBS BIT(1)
537 #define MT_DRV_SW_RX_AIRTIME BIT(2)
538 #define MT_DRV_RX_DMA_HDR BIT(3)
539 #define MT_DRV_HW_MGMT_TXQ BIT(4)
540 #define MT_DRV_AMSDU_OFFLOAD BIT(5)
541 #define MT_DRV_IGNORE_TXS_FAILED BIT(6)
542 #define MT_DRV_HW_PS_BUFFERING BIT(7)
543
544 struct mt76_driver_ops {
545 u32 drv_flags;
546 u32 survey_flags;
547 u16 txwi_size;
548 u16 token_size;
549
550 unsigned int link_data_size;
551
552 void (*update_survey)(struct mt76_phy *phy);
553 int (*set_channel)(struct mt76_phy *phy);
554
555 int (*tx_prepare_skb)(struct mt76_dev *dev, void *txwi_ptr,
556 enum mt76_txq_id qid, struct mt76_wcid *wcid,
557 struct ieee80211_sta *sta,
558 struct mt76_tx_info *tx_info);
559
560 void (*tx_complete_skb)(struct mt76_dev *dev,
561 struct mt76_queue_entry *e);
562
563 bool (*tx_status_data)(struct mt76_dev *dev, u8 *update);
564
565 bool (*rx_check)(struct mt76_dev *dev, void *data, int len);
566
567 void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q,
568 struct sk_buff *skb, u32 *info);
569
570 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q);
571
572 void (*rx_rro_ind_process)(struct mt76_dev *dev, void *data);
573 int (*rx_rro_add_msdu_page)(struct mt76_dev *dev, struct mt76_queue *q,
574 dma_addr_t p, void *data);
575
576 void (*sta_ps)(struct mt76_dev *dev, struct ieee80211_sta *sta,
577 bool ps);
578
579 int (*sta_add)(struct mt76_dev *dev, struct ieee80211_vif *vif,
580 struct ieee80211_sta *sta);
581
582 int (*sta_event)(struct mt76_dev *dev, struct ieee80211_vif *vif,
583 struct ieee80211_sta *sta, enum mt76_sta_event ev);
584
585 void (*sta_remove)(struct mt76_dev *dev, struct ieee80211_vif *vif,
586 struct ieee80211_sta *sta);
587
588 int (*vif_link_add)(struct mt76_phy *phy, struct ieee80211_vif *vif,
589 struct ieee80211_bss_conf *link_conf,
590 struct mt76_vif_link *mlink);
591
592 void (*vif_link_remove)(struct mt76_phy *phy,
593 struct ieee80211_vif *vif,
594 struct ieee80211_bss_conf *link_conf,
595 struct mt76_vif_link *mlink);
596 };
597
598 struct mt76_channel_state {
599 u64 cc_active;
600 u64 cc_busy;
601 u64 cc_rx;
602 u64 cc_bss_rx;
603 u64 cc_tx;
604
605 s8 noise;
606 };
607
608 struct mt76_sband {
609 struct ieee80211_supported_band sband;
610 struct mt76_channel_state *chan;
611 };
612
613 /* addr req mask */
614 #define MT_VEND_TYPE_EEPROM BIT(31)
615 #define MT_VEND_TYPE_CFG BIT(30)
616 #define MT_VEND_TYPE_MASK (MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG)
617
618 #define MT_VEND_ADDR(type, n) (MT_VEND_TYPE_##type | (n))
619 enum mt_vendor_req {
620 MT_VEND_DEV_MODE = 0x1,
621 MT_VEND_WRITE = 0x2,
622 MT_VEND_POWER_ON = 0x4,
623 MT_VEND_MULTI_WRITE = 0x6,
624 MT_VEND_MULTI_READ = 0x7,
625 MT_VEND_READ_EEPROM = 0x9,
626 MT_VEND_WRITE_FCE = 0x42,
627 MT_VEND_WRITE_CFG = 0x46,
628 MT_VEND_READ_CFG = 0x47,
629 MT_VEND_READ_EXT = 0x63,
630 MT_VEND_WRITE_EXT = 0x66,
631 MT_VEND_FEATURE_SET = 0x91,
632 };
633
634 enum mt76u_in_ep {
635 MT_EP_IN_PKT_RX,
636 MT_EP_IN_CMD_RESP,
637 __MT_EP_IN_MAX,
638 };
639
640 enum mt76u_out_ep {
641 MT_EP_OUT_INBAND_CMD,
642 MT_EP_OUT_AC_BE,
643 MT_EP_OUT_AC_BK,
644 MT_EP_OUT_AC_VI,
645 MT_EP_OUT_AC_VO,
646 MT_EP_OUT_HCCA,
647 __MT_EP_OUT_MAX,
648 };
649
650 struct mt76_mcu {
651 struct mutex mutex;
652 u32 msg_seq;
653 int timeout;
654
655 struct sk_buff_head res_q;
656 wait_queue_head_t wait;
657 };
658
659 #define MT_TX_SG_MAX_SIZE 8
660 #define MT_RX_SG_MAX_SIZE 4
661 #define MT_NUM_TX_ENTRIES 256
662 #define MT_NUM_RX_ENTRIES 128
663 #define MCU_RESP_URB_SIZE 1024
664 struct mt76_usb {
665 struct mutex usb_ctrl_mtx;
666 u8 *data;
667 u16 data_len;
668
669 struct mt76_worker status_worker;
670 struct mt76_worker rx_worker;
671
672 struct work_struct stat_work;
673
674 u8 out_ep[__MT_EP_OUT_MAX];
675 u8 in_ep[__MT_EP_IN_MAX];
676 void (*ctrl_timeout)(struct mt76_dev *dev, int err);
677 bool sg_en;
678
679 struct mt76u_mcu {
680 u8 *data;
681 /* multiple reads */
682 struct mt76_reg_pair *rp;
683 int rp_len;
684 u32 base;
685 } mcu;
686 };
687
688 #define MT76S_XMIT_BUF_SZ 0x3fe00
689 #define MT76S_NUM_TX_ENTRIES 256
690 #define MT76S_NUM_RX_ENTRIES 512
691 struct mt76_sdio {
692 struct mt76_worker txrx_worker;
693 struct mt76_worker status_worker;
694 struct mt76_worker net_worker;
695 struct mt76_worker stat_worker;
696
697 u8 *xmit_buf;
698 u32 xmit_buf_sz;
699
700 struct sdio_func *func;
701 void *intr_data;
702 u8 hw_ver;
703 wait_queue_head_t wait;
704
705 int pse_mcu_quota_max;
706 struct {
707 int pse_data_quota;
708 int ple_data_quota;
709 int pse_mcu_quota;
710 int pse_page_size;
711 int deficit;
712 } sched;
713
714 int (*parse_irq)(struct mt76_dev *dev, struct mt76s_intr *intr);
715 };
716
717 struct mt76_mmio {
718 void __iomem *regs;
719 spinlock_t irq_lock;
720 u32 irqmask;
721
722 struct mtk_wed_device wed;
723 struct mtk_wed_device wed_hif2;
724 struct completion wed_reset;
725 struct completion wed_reset_complete;
726
727 struct airoha_ppe_dev __rcu *ppe_dev;
728 struct airoha_npu __rcu *npu;
729 phys_addr_t phy_addr;
730 int npu_type;
731 };
732
733 struct mt76_rx_status {
734 union {
735 struct mt76_wcid *wcid;
736 u16 wcid_idx;
737 };
738
739 u32 reorder_time;
740
741 u32 ampdu_ref;
742 u32 timestamp;
743
744 u8 iv[6];
745
746 u8 phy_idx:2;
747 u8 aggr:1;
748 u8 qos_ctl;
749 u16 seqno;
750
751 u16 freq;
752 u32 flag;
753 u8 enc_flags;
754 u8 encoding:3, bw:4;
755 union {
756 struct {
757 u8 he_ru:3;
758 u8 he_gi:2;
759 u8 he_dcm:1;
760 };
761 struct {
762 u8 ru:4;
763 u8 gi:2;
764 } eht;
765 };
766
767 u8 amsdu:1, first_amsdu:1, last_amsdu:1;
768 u8 rate_idx;
769 u8 nss:5, band:3;
770 s8 signal;
771 u8 chains;
772 s8 chain_signal[IEEE80211_MAX_CHAINS];
773 };
774
775 struct mt76_freq_range_power {
776 const struct cfg80211_sar_freq_ranges *range;
777 s8 power;
778 };
779
780 struct mt76_testmode_ops {
781 int (*set_state)(struct mt76_phy *phy, enum mt76_testmode_state state);
782 int (*set_params)(struct mt76_phy *phy, struct nlattr **tb,
783 enum mt76_testmode_state new_state);
784 int (*dump_stats)(struct mt76_phy *phy, struct sk_buff *msg);
785 };
786
787 struct mt76_testmode_data {
788 enum mt76_testmode_state state;
789
790 u32 param_set[DIV_ROUND_UP(NUM_MT76_TM_ATTRS, 32)];
791 struct sk_buff *tx_skb;
792
793 u32 tx_count;
794 u16 tx_mpdu_len;
795
796 u8 tx_rate_mode;
797 u8 tx_rate_idx;
798 u8 tx_rate_nss;
799 u8 tx_rate_sgi;
800 u8 tx_rate_ldpc;
801 u8 tx_rate_stbc;
802 u8 tx_ltf;
803
804 u8 tx_antenna_mask;
805 u8 tx_spe_idx;
806
807 u8 tx_duty_cycle;
808 u32 tx_time;
809 u32 tx_ipg;
810
811 u32 freq_offset;
812
813 u8 tx_power[4];
814 u8 tx_power_control;
815
816 u8 addr[3][ETH_ALEN];
817
818 u32 tx_pending;
819 u32 tx_queued;
820 u16 tx_queued_limit;
821 u32 tx_done;
822 struct {
823 u64 packets[__MT_RXQ_MAX];
824 u64 fcs_error[__MT_RXQ_MAX];
825 } rx_stats;
826 };
827
828 struct mt76_vif_link {
829 u8 idx;
830 u8 link_idx;
831 u8 omac_idx;
832 u8 band_idx;
833 u8 wmm_idx;
834 u8 scan_seq_num;
835 u8 cipher;
836 u8 basic_rates_idx;
837 u8 mcast_rates_idx;
838 u8 beacon_rates_idx;
839 bool offchannel;
840 unsigned long beacon_mon_last;
841 u16 beacon_mon_interval;
842 struct ieee80211_chanctx_conf *ctx;
843 struct mt76_wcid *wcid;
844 struct mt76_vif_data *mvif;
845 struct rcu_head rcu_head;
846 };
847
848 struct mt76_vif_data {
849 struct mt76_vif_link __rcu *link[IEEE80211_MLD_MAX_NUM_LINKS];
850 struct mt76_vif_link __rcu *offchannel_link;
851
852 struct mt76_phy *roc_phy;
853 u16 valid_links;
854 u8 deflink_id;
855 };
856
857 struct mt76_phy {
858 struct ieee80211_hw *hw;
859 struct mt76_dev *dev;
860 void *priv;
861
862 unsigned long state;
863 unsigned int num_sta;
864 u8 band_idx;
865
866 spinlock_t tx_lock;
867 struct list_head tx_list;
868 struct mt76_queue *q_tx[__MT_TXQ_MAX];
869
870 atomic_t mgmt_tx_pending;
871
872 struct cfg80211_chan_def chandef;
873 struct cfg80211_chan_def main_chandef;
874 bool offchannel;
875 bool radar_enabled;
876 bool no_active_monitor;
877
878 struct delayed_work roc_work;
879 struct ieee80211_vif *roc_vif;
880 struct mt76_vif_link *roc_link;
881
882 struct mt76_chanctx *chanctx;
883
884 struct mt76_channel_state *chan_state;
885 enum mt76_dfs_state dfs_state;
886 ktime_t survey_time;
887
888 u32 aggr_stats[32];
889
890 struct mt76_hw_cap cap;
891 struct mt76_sband sband_2g;
892 struct mt76_sband sband_5g;
893 struct mt76_sband sband_6g;
894
895 u8 macaddr[ETH_ALEN];
896
897 int txpower_cur;
898 u8 antenna_mask;
899 u16 chainmask;
900
901 #ifdef CONFIG_NL80211_TESTMODE
902 struct mt76_testmode_data test;
903 #endif
904
905 struct delayed_work mac_work;
906 u8 mac_work_count;
907
908 struct {
909 struct sk_buff *head;
910 struct sk_buff **tail;
911 u16 seqno;
912 } rx_amsdu[__MT_RXQ_MAX];
913
914 struct mt76_freq_range_power *frp;
915
916 struct {
917 struct led_classdev cdev;
918 char name[32];
919 bool al;
920 u8 pin;
921 } leds;
922 };
923
924 struct mt76_dev {
925 struct mt76_phy phy; /* must be first */
926 struct mt76_phy *phys[__MT_MAX_BAND];
927 struct mt76_phy *band_phys[NUM_NL80211_BANDS];
928
929 struct ieee80211_hw *hw;
930
931 spinlock_t wed_lock;
932 spinlock_t lock;
933 spinlock_t cc_lock;
934
935 u32 cur_cc_bss_rx;
936
937 struct mt76_rx_status rx_ampdu_status;
938 u32 rx_ampdu_len;
939 u32 rx_ampdu_ref;
940
941 struct mutex mutex;
942
943 const struct mt76_bus_ops *bus;
944 const struct mt76_driver_ops *drv;
945 const struct mt76_mcu_ops *mcu_ops;
946
947 /* Optional callback to finalize wiphy state before registration. */
948 int (*init_wiphy)(struct mt76_dev *dev);
949 struct device *dev;
950 struct device *dma_dev;
951
952 struct mt76_mcu mcu;
953
954 struct net_device *napi_dev;
955 struct net_device *tx_napi_dev;
956 spinlock_t rx_lock;
957 struct napi_struct napi[__MT_RXQ_MAX];
958 struct sk_buff_head rx_skb[__MT_RXQ_MAX];
959 struct tasklet_struct irq_tasklet;
960
961 struct list_head txwi_cache;
962 struct list_head rxwi_cache;
963 struct mt76_queue *q_mcu[__MT_MCUQ_MAX];
964 struct mt76_queue q_rx[__MT_RXQ_MAX];
965 const struct mt76_queue_ops *queue_ops;
966 int tx_dma_idx[4];
967 enum mt76_hwrro_mode hwrro_mode;
968
969 struct mt76_worker tx_worker;
970 struct napi_struct tx_napi;
971
972 spinlock_t token_lock;
973 struct idr token;
974 u16 wed_token_count;
975 u16 token_count;
976 u16 token_start;
977 u16 token_size;
978
979 spinlock_t rx_token_lock;
980 struct idr rx_token;
981 u16 rx_token_size;
982
983 wait_queue_head_t tx_wait;
984 /* spinclock used to protect wcid pktid linked list */
985 spinlock_t status_lock;
986
987 u32 wcid_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)];
988
989 u64 vif_mask;
990
991 struct mt76_wcid global_wcid;
992 struct mt76_wcid __rcu *wcid[MT76_N_WCIDS];
993 struct list_head wcid_list;
994
995 struct list_head sta_poll_list;
996 spinlock_t sta_poll_lock;
997
998 u32 rev;
999
1000 struct tasklet_struct pre_tbtt_tasklet;
1001 int beacon_int;
1002 u8 beacon_mask;
1003
1004 struct debugfs_blob_wrapper eeprom;
1005 struct debugfs_blob_wrapper otp;
1006
1007 char alpha2[3];
1008 enum nl80211_dfs_regions region;
1009
1010 struct mt76_scan_rnr_param rnr;
1011
1012 u32 debugfs_reg;
1013
1014 u8 csa_complete;
1015
1016 u32 rxfilter;
1017
1018 struct delayed_work scan_work;
1019 spinlock_t scan_lock;
1020 struct {
1021 struct cfg80211_scan_request *req;
1022 struct ieee80211_channel *chan;
1023 struct ieee80211_vif *vif;
1024 struct mt76_vif_link *mlink;
1025 struct mt76_phy *phy;
1026 int chan_idx;
1027 bool beacon_wait;
1028 bool beacon_received;
1029 } scan;
1030
1031 #ifdef CONFIG_NL80211_TESTMODE
1032 const struct mt76_testmode_ops *test_ops;
1033 struct {
1034 const char *name;
1035 u32 offset;
1036 } test_mtd;
1037 #endif
1038 struct workqueue_struct *wq;
1039
1040 union {
1041 struct mt76_mmio mmio;
1042 struct mt76_usb usb;
1043 struct mt76_sdio sdio;
1044 };
1045
1046 atomic_t bus_hung;
1047 };
1048
1049 /* per-phy stats. */
1050 struct mt76_mib_stats {
1051 u32 ack_fail_cnt;
1052 u32 fcs_err_cnt;
1053 u32 rts_cnt;
1054 u32 rts_retries_cnt;
1055 u32 ba_miss_cnt;
1056 u32 tx_bf_cnt;
1057 u32 tx_mu_bf_cnt;
1058 u32 tx_mu_mpdu_cnt;
1059 u32 tx_mu_acked_mpdu_cnt;
1060 u32 tx_su_acked_mpdu_cnt;
1061 u32 tx_bf_ibf_ppdu_cnt;
1062 u32 tx_bf_ebf_ppdu_cnt;
1063
1064 u32 tx_bf_rx_fb_all_cnt;
1065 u32 tx_bf_rx_fb_eht_cnt;
1066 u32 tx_bf_rx_fb_he_cnt;
1067 u32 tx_bf_rx_fb_vht_cnt;
1068 u32 tx_bf_rx_fb_ht_cnt;
1069
1070 u32 tx_bf_rx_fb_bw; /* value of last sample, not cumulative */
1071 u32 tx_bf_rx_fb_nc_cnt;
1072 u32 tx_bf_rx_fb_nr_cnt;
1073 u32 tx_bf_fb_cpl_cnt;
1074 u32 tx_bf_fb_trig_cnt;
1075
1076 u32 tx_ampdu_cnt;
1077 u32 tx_stop_q_empty_cnt;
1078 u32 tx_mpdu_attempts_cnt;
1079 u32 tx_mpdu_success_cnt;
1080 u32 tx_pkt_ebf_cnt;
1081 u32 tx_pkt_ibf_cnt;
1082
1083 u32 tx_rwp_fail_cnt;
1084 u32 tx_rwp_need_cnt;
1085
1086 /* rx stats */
1087 u32 rx_fifo_full_cnt;
1088 u32 channel_idle_cnt;
1089 u32 primary_cca_busy_time;
1090 u32 secondary_cca_busy_time;
1091 u32 primary_energy_detect_time;
1092 u32 cck_mdrdy_time;
1093 u32 ofdm_mdrdy_time;
1094 u32 green_mdrdy_time;
1095 u32 rx_vector_mismatch_cnt;
1096 u32 rx_delimiter_fail_cnt;
1097 u32 rx_mrdy_cnt;
1098 u32 rx_len_mismatch_cnt;
1099 u32 rx_mpdu_cnt;
1100 u32 rx_ampdu_cnt;
1101 u32 rx_ampdu_bytes_cnt;
1102 u32 rx_ampdu_valid_subframe_cnt;
1103 u32 rx_ampdu_valid_subframe_bytes_cnt;
1104 u32 rx_pfdrop_cnt;
1105 u32 rx_vec_queue_overflow_drop_cnt;
1106 u32 rx_ba_cnt;
1107
1108 u32 tx_amsdu[8];
1109 u32 tx_amsdu_cnt;
1110
1111 /* mcu_muru_stats */
1112 u32 dl_cck_cnt;
1113 u32 dl_ofdm_cnt;
1114 u32 dl_htmix_cnt;
1115 u32 dl_htgf_cnt;
1116 u32 dl_vht_su_cnt;
1117 u32 dl_vht_2mu_cnt;
1118 u32 dl_vht_3mu_cnt;
1119 u32 dl_vht_4mu_cnt;
1120 u32 dl_he_su_cnt;
1121 u32 dl_he_ext_su_cnt;
1122 u32 dl_he_2ru_cnt;
1123 u32 dl_he_2mu_cnt;
1124 u32 dl_he_3ru_cnt;
1125 u32 dl_he_3mu_cnt;
1126 u32 dl_he_4ru_cnt;
1127 u32 dl_he_4mu_cnt;
1128 u32 dl_he_5to8ru_cnt;
1129 u32 dl_he_9to16ru_cnt;
1130 u32 dl_he_gtr16ru_cnt;
1131
1132 u32 ul_hetrig_su_cnt;
1133 u32 ul_hetrig_2ru_cnt;
1134 u32 ul_hetrig_3ru_cnt;
1135 u32 ul_hetrig_4ru_cnt;
1136 u32 ul_hetrig_5to8ru_cnt;
1137 u32 ul_hetrig_9to16ru_cnt;
1138 u32 ul_hetrig_gtr16ru_cnt;
1139 u32 ul_hetrig_2mu_cnt;
1140 u32 ul_hetrig_3mu_cnt;
1141 u32 ul_hetrig_4mu_cnt;
1142 };
1143
1144 struct mt76_power_limits {
1145 s8 cck[4];
1146 s8 ofdm[8];
1147 s8 mcs[4][10];
1148 s8 ru[7][12];
1149 s8 eht[16][16];
1150
1151 struct {
1152 s8 cck[4];
1153 s8 ofdm[4];
1154 s8 ofdm_bf[4];
1155 s8 ru[7][10];
1156 s8 ru_bf[7][10];
1157 } path;
1158 };
1159
1160 struct mt76_ethtool_worker_info {
1161 u64 *data;
1162 int idx;
1163 int initial_stat_idx;
1164 int worker_stat_count;
1165 int sta_count;
1166 };
1167
1168 struct mt76_chanctx {
1169 struct mt76_phy *phy;
1170 };
1171
1172 #define CCK_RATE(_idx, _rate) { \
1173 .bitrate = _rate, \
1174 .flags = IEEE80211_RATE_SHORT_PREAMBLE, \
1175 .hw_value = (MT_PHY_TYPE_CCK << 8) | (_idx), \
1176 .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (4 + _idx), \
1177 }
1178
1179 #define OFDM_RATE(_idx, _rate) { \
1180 .bitrate = _rate, \
1181 .hw_value = (MT_PHY_TYPE_OFDM << 8) | (_idx), \
1182 .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | (_idx), \
1183 }
1184
1185 extern struct ieee80211_rate mt76_rates[12];
1186
1187 #define __mt76_rr(dev, ...) (dev)->bus->rr((dev), __VA_ARGS__)
1188 #define __mt76_wr(dev, ...) (dev)->bus->wr((dev), __VA_ARGS__)
1189 #define __mt76_rmw(dev, ...) (dev)->bus->rmw((dev), __VA_ARGS__)
1190 #define __mt76_wr_copy(dev, ...) (dev)->bus->write_copy((dev), __VA_ARGS__)
1191 #define __mt76_rr_copy(dev, ...) (dev)->bus->read_copy((dev), __VA_ARGS__)
1192
1193 #define __mt76_set(dev, offset, val) __mt76_rmw(dev, offset, 0, val)
1194 #define __mt76_clear(dev, offset, val) __mt76_rmw(dev, offset, val, 0)
1195
1196 #define mt76_rr(dev, ...) (dev)->mt76.bus->rr(&((dev)->mt76), __VA_ARGS__)
1197 #define mt76_wr(dev, ...) (dev)->mt76.bus->wr(&((dev)->mt76), __VA_ARGS__)
1198 #define mt76_rmw(dev, ...) (dev)->mt76.bus->rmw(&((dev)->mt76), __VA_ARGS__)
1199 #define mt76_wr_copy(dev, ...) (dev)->mt76.bus->write_copy(&((dev)->mt76), __VA_ARGS__)
1200 #define mt76_rr_copy(dev, ...) (dev)->mt76.bus->read_copy(&((dev)->mt76), __VA_ARGS__)
1201 #define mt76_wr_rp(dev, ...) (dev)->mt76.bus->wr_rp(&((dev)->mt76), __VA_ARGS__)
1202 #define mt76_rd_rp(dev, ...) (dev)->mt76.bus->rd_rp(&((dev)->mt76), __VA_ARGS__)
1203
1204
1205 #define mt76_mcu_restart(dev, ...) (dev)->mt76.mcu_ops->mcu_restart(&((dev)->mt76))
1206
1207 #define mt76_set(dev, offset, val) mt76_rmw(dev, offset, 0, val)
1208 #define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0)
1209
1210 #define mt76_get_field(_dev, _reg, _field) \
1211 FIELD_GET(_field, mt76_rr(dev, _reg))
1212
1213 #define mt76_rmw_field(_dev, _reg, _field, _val) \
1214 mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val))
1215
1216 #define __mt76_rmw_field(_dev, _reg, _field, _val) \
1217 __mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val))
1218
1219 #define mt76_hw(dev) (dev)->mphy.hw
1220
1221 bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val,
1222 int timeout);
1223
1224 #define mt76_poll(dev, ...) __mt76_poll(&((dev)->mt76), __VA_ARGS__)
1225
1226 bool ____mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val,
1227 int timeout, int kick);
1228 #define __mt76_poll_msec(...) ____mt76_poll_msec(__VA_ARGS__, 10)
1229 #define mt76_poll_msec(dev, ...) ____mt76_poll_msec(&((dev)->mt76), __VA_ARGS__, 10)
1230 #define mt76_poll_msec_tick(dev, ...) ____mt76_poll_msec(&((dev)->mt76), __VA_ARGS__)
1231
1232 void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs);
1233 void mt76_pci_disable_aspm(struct pci_dev *pdev);
1234 bool mt76_pci_aspm_supported(struct pci_dev *pdev);
1235
mt76_chip(struct mt76_dev * dev)1236 static inline u16 mt76_chip(struct mt76_dev *dev)
1237 {
1238 return dev->rev >> 16;
1239 }
1240
mt76_rev(struct mt76_dev * dev)1241 static inline u16 mt76_rev(struct mt76_dev *dev)
1242 {
1243 return dev->rev & 0xffff;
1244 }
1245
1246 void mt76_wed_release_rx_buf(struct mtk_wed_device *wed);
1247 void mt76_wed_offload_disable(struct mtk_wed_device *wed);
1248 void mt76_wed_reset_complete(struct mtk_wed_device *wed);
1249 void mt76_wed_dma_reset(struct mt76_dev *dev);
1250 int mt76_wed_net_setup_tc(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1251 struct net_device *netdev, enum tc_setup_type type,
1252 void *type_data);
1253 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
1254 u32 mt76_wed_init_rx_buf(struct mtk_wed_device *wed, int size);
1255 int mt76_wed_offload_enable(struct mtk_wed_device *wed);
1256 int mt76_wed_dma_setup(struct mt76_dev *dev, struct mt76_queue *q, bool reset);
1257 #else
mt76_wed_init_rx_buf(struct mtk_wed_device * wed,int size)1258 static inline u32 mt76_wed_init_rx_buf(struct mtk_wed_device *wed, int size)
1259 {
1260 return 0;
1261 }
1262
mt76_wed_offload_enable(struct mtk_wed_device * wed)1263 static inline int mt76_wed_offload_enable(struct mtk_wed_device *wed)
1264 {
1265 return 0;
1266 }
1267
mt76_wed_dma_setup(struct mt76_dev * dev,struct mt76_queue * q,bool reset)1268 static inline int mt76_wed_dma_setup(struct mt76_dev *dev, struct mt76_queue *q,
1269 bool reset)
1270 {
1271 return 0;
1272 }
1273 #endif /* CONFIG_NET_MEDIATEK_SOC_WED */
1274
1275 #define mt76xx_chip(dev) mt76_chip(&((dev)->mt76))
1276 #define mt76xx_rev(dev) mt76_rev(&((dev)->mt76))
1277
1278 #define mt76_init_queues(dev, ...) (dev)->mt76.queue_ops->init(&((dev)->mt76), __VA_ARGS__)
1279 #define mt76_queue_alloc(dev, ...) (dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__)
1280 #define mt76_tx_queue_skb_raw(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb_raw(&((dev)->mt76), __VA_ARGS__)
1281 #define mt76_tx_queue_skb(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb(&((dev)->mphy), __VA_ARGS__)
1282 #define mt76_queue_rx_reset(dev, ...) (dev)->mt76.queue_ops->rx_reset(&((dev)->mt76), __VA_ARGS__)
1283 #define mt76_queue_tx_cleanup(dev, ...) (dev)->mt76.queue_ops->tx_cleanup(&((dev)->mt76), __VA_ARGS__)
1284 #define mt76_queue_rx_init(dev, ...) (dev)->mt76.queue_ops->rx_queue_init(&((dev)->mt76), __VA_ARGS__)
1285 #define mt76_queue_rx_cleanup(dev, ...) (dev)->mt76.queue_ops->rx_cleanup(&((dev)->mt76), __VA_ARGS__)
1286 #define mt76_queue_kick(dev, ...) (dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__)
1287 #define mt76_queue_reset(dev, ...) (dev)->mt76.queue_ops->reset_q(&((dev)->mt76), __VA_ARGS__)
1288
1289 #define mt76_for_each_q_rx(dev, i) \
1290 for (i = 0; i < ARRAY_SIZE((dev)->q_rx); i++) \
1291 if ((dev)->q_rx[i].ndesc)
1292
1293
1294 #define mt76_dereference(p, dev) \
1295 rcu_dereference_protected(p, lockdep_is_held(&(dev)->mutex))
1296
mt76_wed_to_dev(struct mtk_wed_device * wed)1297 static inline struct mt76_dev *mt76_wed_to_dev(struct mtk_wed_device *wed)
1298 {
1299 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
1300 if (wed->wlan.hif2)
1301 return container_of(wed, struct mt76_dev, mmio.wed_hif2);
1302 #endif /* CONFIG_NET_MEDIATEK_SOC_WED */
1303 return container_of(wed, struct mt76_dev, mmio.wed);
1304 }
1305
1306 static inline struct mt76_wcid *
__mt76_wcid_ptr(struct mt76_dev * dev,u16 idx)1307 __mt76_wcid_ptr(struct mt76_dev *dev, u16 idx)
1308 {
1309 if (idx >= ARRAY_SIZE(dev->wcid))
1310 return NULL;
1311 return rcu_dereference(dev->wcid[idx]);
1312 }
1313
1314 #define mt76_wcid_ptr(dev, idx) __mt76_wcid_ptr(&(dev)->mt76, idx)
1315
1316 struct mt76_dev *mt76_alloc_device(struct device *pdev, unsigned int size,
1317 const struct ieee80211_ops *ops,
1318 const struct mt76_driver_ops *drv_ops);
1319 int mt76_register_device(struct mt76_dev *dev, bool vht,
1320 struct ieee80211_rate *rates, int n_rates);
1321 void mt76_unregister_device(struct mt76_dev *dev);
1322 void mt76_free_device(struct mt76_dev *dev);
1323 void mt76_reset_device(struct mt76_dev *dev);
1324 void mt76_unregister_phy(struct mt76_phy *phy);
1325
1326 struct mt76_phy *mt76_alloc_radio_phy(struct mt76_dev *dev, unsigned int size,
1327 u8 band_idx);
1328 struct mt76_phy *mt76_alloc_phy(struct mt76_dev *dev, unsigned int size,
1329 const struct ieee80211_ops *ops,
1330 u8 band_idx);
1331 int mt76_register_phy(struct mt76_phy *phy, bool vht,
1332 struct ieee80211_rate *rates, int n_rates);
1333 struct mt76_phy *mt76_vif_phy(struct ieee80211_hw *hw,
1334 struct ieee80211_vif *vif);
1335
1336 struct dentry *mt76_register_debugfs_fops(struct mt76_phy *phy,
1337 const struct file_operations *ops);
mt76_register_debugfs(struct mt76_dev * dev)1338 static inline struct dentry *mt76_register_debugfs(struct mt76_dev *dev)
1339 {
1340 return mt76_register_debugfs_fops(&dev->phy, NULL);
1341 }
1342
1343 int mt76_queues_read(struct seq_file *s, void *data);
1344 void mt76_seq_puts_array(struct seq_file *file, const char *str,
1345 s8 *val, int len);
1346
1347 int mt76_eeprom_init(struct mt76_dev *dev, int len);
1348 int mt76_eeprom_override(struct mt76_phy *phy);
1349 int mt76_get_of_data_from_mtd(struct mt76_dev *dev, void *eep, int offset, int len);
1350 int mt76_get_of_data_from_nvmem(struct mt76_dev *dev, void *eep,
1351 const char *cell_name, int len);
1352
1353 struct mt76_queue *
1354 mt76_init_queue(struct mt76_dev *dev, int qid, int idx, int n_desc,
1355 int ring_base, void *wed, u32 flags);
mt76_init_tx_queue(struct mt76_phy * phy,int qid,int idx,int n_desc,int ring_base,void * wed,u32 flags)1356 static inline int mt76_init_tx_queue(struct mt76_phy *phy, int qid, int idx,
1357 int n_desc, int ring_base, void *wed,
1358 u32 flags)
1359 {
1360 struct mt76_queue *q;
1361
1362 q = mt76_init_queue(phy->dev, qid, idx, n_desc, ring_base, wed, flags);
1363 if (IS_ERR(q))
1364 return PTR_ERR(q);
1365
1366 phy->q_tx[qid] = q;
1367
1368 return 0;
1369 }
1370
mt76_init_mcu_queue(struct mt76_dev * dev,int qid,int idx,int n_desc,int ring_base)1371 static inline int mt76_init_mcu_queue(struct mt76_dev *dev, int qid, int idx,
1372 int n_desc, int ring_base)
1373 {
1374 struct mt76_queue *q;
1375
1376 q = mt76_init_queue(dev, qid, idx, n_desc, ring_base, NULL, 0);
1377 if (IS_ERR(q))
1378 return PTR_ERR(q);
1379
1380 dev->q_mcu[qid] = q;
1381
1382 return 0;
1383 }
1384
1385 static inline struct mt76_phy *
mt76_dev_phy(struct mt76_dev * dev,u8 phy_idx)1386 mt76_dev_phy(struct mt76_dev *dev, u8 phy_idx)
1387 {
1388 if ((phy_idx == MT_BAND1 && dev->phys[phy_idx]) ||
1389 (phy_idx == MT_BAND2 && dev->phys[phy_idx]))
1390 return dev->phys[phy_idx];
1391
1392 return &dev->phy;
1393 }
1394
1395 static inline struct ieee80211_hw *
mt76_phy_hw(struct mt76_dev * dev,u8 phy_idx)1396 mt76_phy_hw(struct mt76_dev *dev, u8 phy_idx)
1397 {
1398 return mt76_dev_phy(dev, phy_idx)->hw;
1399 }
1400
1401 static inline u8 *
mt76_get_txwi_ptr(struct mt76_dev * dev,struct mt76_txwi_cache * t)1402 mt76_get_txwi_ptr(struct mt76_dev *dev, struct mt76_txwi_cache *t)
1403 {
1404 return (u8 *)t - dev->drv->txwi_size;
1405 }
1406
1407 /* increment with wrap-around */
mt76_incr(int val,int size)1408 static inline int mt76_incr(int val, int size)
1409 {
1410 return (val + 1) & (size - 1);
1411 }
1412
1413 /* decrement with wrap-around */
mt76_decr(int val,int size)1414 static inline int mt76_decr(int val, int size)
1415 {
1416 return (val - 1) & (size - 1);
1417 }
1418
1419 u8 mt76_ac_to_hwq(u8 ac);
1420
1421 static inline struct ieee80211_txq *
mtxq_to_txq(struct mt76_txq * mtxq)1422 mtxq_to_txq(struct mt76_txq *mtxq)
1423 {
1424 void *ptr = mtxq;
1425
1426 return container_of(ptr, struct ieee80211_txq, drv_priv);
1427 }
1428
1429 /* peer-wide state uses the wcid of the primary link */
1430 static inline struct mt76_wcid *
mt76_wcid_primary(struct mt76_wcid * wcid)1431 mt76_wcid_primary(struct mt76_wcid *wcid)
1432 {
1433 return wcid->def_wcid ? wcid->def_wcid : wcid;
1434 }
1435
1436 static inline struct ieee80211_sta *
wcid_to_sta(struct mt76_wcid * wcid)1437 wcid_to_sta(struct mt76_wcid *wcid)
1438 {
1439 void *ptr = wcid;
1440
1441 if (!wcid || !wcid->sta)
1442 return NULL;
1443
1444 if (wcid->def_wcid)
1445 ptr = wcid->def_wcid;
1446
1447 return container_of(ptr, struct ieee80211_sta, drv_priv);
1448 }
1449
mt76_tx_skb_cb(struct sk_buff * skb)1450 static inline struct mt76_tx_cb *mt76_tx_skb_cb(struct sk_buff *skb)
1451 {
1452 BUILD_BUG_ON(sizeof(struct mt76_tx_cb) >
1453 sizeof(IEEE80211_SKB_CB(skb)->status.status_driver_data));
1454 return ((void *)IEEE80211_SKB_CB(skb)->status.status_driver_data);
1455 }
1456
mt76_skb_get_hdr(struct sk_buff * skb)1457 static inline void *mt76_skb_get_hdr(struct sk_buff *skb)
1458 {
1459 struct mt76_rx_status mstat;
1460 u8 *data = skb->data;
1461
1462 /* Alignment concerns */
1463 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he) % 4);
1464 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he_mu) % 4);
1465
1466 mstat = *((struct mt76_rx_status *)skb->cb);
1467
1468 if (mstat.flag & RX_FLAG_RADIOTAP_HE)
1469 data += sizeof(struct ieee80211_radiotap_he);
1470 if (mstat.flag & RX_FLAG_RADIOTAP_HE_MU)
1471 data += sizeof(struct ieee80211_radiotap_he_mu);
1472
1473 return data;
1474 }
1475
mt76_insert_hdr_pad(struct sk_buff * skb)1476 static inline void mt76_insert_hdr_pad(struct sk_buff *skb)
1477 {
1478 int len = ieee80211_get_hdrlen_from_skb(skb);
1479
1480 if (len % 4 == 0)
1481 return;
1482
1483 skb_push(skb, 2);
1484 memmove(skb->data, skb->data + 2, len);
1485
1486 skb->data[len] = 0;
1487 skb->data[len + 1] = 0;
1488 }
1489
mt76_is_skb_pktid(u8 pktid)1490 static inline bool mt76_is_skb_pktid(u8 pktid)
1491 {
1492 if (pktid & MT_PACKET_ID_HAS_RATE)
1493 return false;
1494
1495 return pktid >= MT_PACKET_ID_FIRST;
1496 }
1497
mt76_tx_power_path_delta(u8 path)1498 static inline u8 mt76_tx_power_path_delta(u8 path)
1499 {
1500 static const u8 path_delta[5] = { 0, 6, 9, 12, 14 };
1501 u8 idx = path - 1;
1502
1503 return (idx < ARRAY_SIZE(path_delta)) ? path_delta[idx] : 0;
1504 }
1505
mt76_testmode_enabled(struct mt76_phy * phy)1506 static inline bool mt76_testmode_enabled(struct mt76_phy *phy)
1507 {
1508 #ifdef CONFIG_NL80211_TESTMODE
1509 return phy->test.state != MT76_TM_STATE_OFF;
1510 #else
1511 return false;
1512 #endif
1513 }
1514
mt76_is_testmode_skb(struct mt76_dev * dev,struct sk_buff * skb,struct ieee80211_hw ** hw)1515 static inline bool mt76_is_testmode_skb(struct mt76_dev *dev,
1516 struct sk_buff *skb,
1517 struct ieee80211_hw **hw)
1518 {
1519 #ifdef CONFIG_NL80211_TESTMODE
1520 int i;
1521
1522 for (i = 0; i < ARRAY_SIZE(dev->phys); i++) {
1523 struct mt76_phy *phy = dev->phys[i];
1524
1525 if (phy && skb == phy->test.tx_skb) {
1526 *hw = dev->phys[i]->hw;
1527 return true;
1528 }
1529 }
1530 return false;
1531 #else
1532 return false;
1533 #endif
1534 }
1535
1536 void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb);
1537 void mt76_tx(struct mt76_phy *dev, struct ieee80211_sta *sta,
1538 struct mt76_wcid *wcid, struct sk_buff *skb);
1539 void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq);
1540 void mt76_stop_tx_queues(struct mt76_phy *phy, struct ieee80211_sta *sta,
1541 bool send_bar);
1542 void mt76_tx_check_agg_ssn(struct ieee80211_sta *sta, struct sk_buff *skb);
1543 void mt76_txq_schedule(struct mt76_phy *phy, enum mt76_txq_id qid);
1544 void mt76_txq_schedule_all(struct mt76_phy *phy);
1545 void mt76_txq_schedule_pending(struct mt76_phy *phy);
1546 void mt76_tx_worker_run(struct mt76_dev *dev);
1547 void mt76_tx_worker(struct mt76_worker *w);
1548 void mt76_release_buffered_frames(struct ieee80211_hw *hw,
1549 struct ieee80211_sta *sta,
1550 u16 tids, int nframes,
1551 enum ieee80211_frame_release_type reason,
1552 bool more_data);
1553 void mt76_sta_ps_transition(struct mt76_dev *dev, struct mt76_wcid *wcid,
1554 bool ps);
1555 bool mt76_has_tx_pending(struct mt76_phy *phy);
1556 int mt76_update_channel(struct mt76_phy *phy);
1557 void mt76_update_survey(struct mt76_phy *phy);
1558 void mt76_update_survey_active_time(struct mt76_phy *phy, ktime_t time);
1559 int mt76_get_survey(struct ieee80211_hw *hw, int idx,
1560 struct survey_info *survey);
1561 int mt76_rx_signal(u8 chain_mask, s8 *chain_signal);
1562 void mt76_set_stream_caps(struct mt76_phy *phy, bool vht);
1563
1564 int mt76_rx_aggr_start(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid,
1565 u16 ssn, u16 size);
1566 void mt76_rx_aggr_stop(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid);
1567
1568 void mt76_wcid_key_setup(struct mt76_dev *dev, struct mt76_wcid *wcid,
1569 struct ieee80211_key_conf *key);
1570
1571 void mt76_tx_status_lock(struct mt76_dev *dev, struct sk_buff_head *list)
1572 __acquires(&dev->status_lock);
1573 void mt76_tx_status_unlock(struct mt76_dev *dev, struct sk_buff_head *list)
1574 __releases(&dev->status_lock);
1575
1576 int mt76_tx_status_skb_add(struct mt76_dev *dev, struct mt76_wcid *wcid,
1577 struct sk_buff *skb);
1578 struct sk_buff *mt76_tx_status_skb_get(struct mt76_dev *dev,
1579 struct mt76_wcid *wcid, int pktid,
1580 struct sk_buff_head *list);
1581 void mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb,
1582 struct sk_buff_head *list);
1583 void __mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb,
1584 struct list_head *free_list);
1585 static inline void
mt76_tx_complete_skb(struct mt76_dev * dev,u16 wcid,struct sk_buff * skb)1586 mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb)
1587 {
1588 __mt76_tx_complete_skb(dev, wcid, skb, NULL);
1589 }
1590
1591 void mt76_tx_status_check(struct mt76_dev *dev, bool flush);
1592 int mt76_sta_state(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1593 struct ieee80211_sta *sta,
1594 enum ieee80211_sta_state old_state,
1595 enum ieee80211_sta_state new_state);
1596 void __mt76_sta_remove(struct mt76_phy *phy, struct ieee80211_vif *vif,
1597 struct ieee80211_sta *sta);
1598 void mt76_sta_pre_rcu_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1599 struct ieee80211_sta *sta);
1600
1601 int mt76_get_min_avg_rssi(struct mt76_dev *dev, u8 phy_idx);
1602
1603 s8 mt76_get_power_bound(struct mt76_phy *phy, s8 txpower);
1604
1605 int mt76_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1606 unsigned int link_id, int *dbm);
1607 int mt76_init_sar_power(struct ieee80211_hw *hw,
1608 const struct cfg80211_sar_specs *sar);
1609 int mt76_get_sar_power(struct mt76_phy *phy,
1610 struct ieee80211_channel *chan,
1611 int power);
1612
1613 void mt76_csa_check(struct mt76_dev *dev);
1614 void mt76_csa_finish(struct mt76_dev *dev);
1615
1616 int mt76_get_antenna(struct ieee80211_hw *hw, int radio_idx, u32 *tx_ant,
1617 u32 *rx_ant);
1618 int mt76_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set);
1619 void mt76_insert_ccmp_hdr(struct sk_buff *skb, u8 key_id);
1620 int mt76_get_rate(struct mt76_dev *dev,
1621 struct ieee80211_supported_band *sband,
1622 int idx, bool cck);
1623 int mt76_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1624 struct ieee80211_scan_request *hw_req);
1625 void mt76_cancel_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
1626 void mt76_scan_rx_beacon(struct mt76_dev *dev, struct ieee80211_channel *chan);
1627 void mt76_rx_beacon(struct mt76_phy *phy, struct sk_buff *skb);
1628 void mt76_beacon_mon_check(struct mt76_phy *phy);
1629 void mt76_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1630 const u8 *mac);
1631 void mt76_sw_scan_complete(struct ieee80211_hw *hw,
1632 struct ieee80211_vif *vif);
1633 enum mt76_dfs_state mt76_phy_dfs_state(struct mt76_phy *phy);
1634 int mt76_add_chanctx(struct ieee80211_hw *hw,
1635 struct ieee80211_chanctx_conf *conf);
1636 void mt76_remove_chanctx(struct ieee80211_hw *hw,
1637 struct ieee80211_chanctx_conf *conf);
1638 void mt76_change_chanctx(struct ieee80211_hw *hw,
1639 struct ieee80211_chanctx_conf *conf,
1640 u32 changed);
1641 int mt76_assign_vif_chanctx(struct ieee80211_hw *hw,
1642 struct ieee80211_vif *vif,
1643 struct ieee80211_bss_conf *link_conf,
1644 struct ieee80211_chanctx_conf *conf);
1645 void mt76_unassign_vif_chanctx(struct ieee80211_hw *hw,
1646 struct ieee80211_vif *vif,
1647 struct ieee80211_bss_conf *link_conf,
1648 struct ieee80211_chanctx_conf *conf);
1649 int mt76_switch_vif_chanctx(struct ieee80211_hw *hw,
1650 struct ieee80211_vif_chanctx_switch *vifs,
1651 int n_vifs,
1652 enum ieee80211_chanctx_switch_mode mode);
1653 int mt76_remain_on_channel(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1654 struct ieee80211_channel *chan, int duration,
1655 enum ieee80211_roc_type type);
1656 int mt76_cancel_remain_on_channel(struct ieee80211_hw *hw,
1657 struct ieee80211_vif *vif);
1658 int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1659 void *data, int len);
1660 int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *skb,
1661 struct netlink_callback *cb, void *data, int len);
1662 int mt76_testmode_set_state(struct mt76_phy *phy, enum mt76_testmode_state state);
1663 int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len);
1664
1665 #if IS_ENABLED(CONFIG_MT76_NPU)
1666 void mt76_npu_check_ppe(struct mt76_dev *dev, struct sk_buff *skb,
1667 u32 info);
1668 int mt76_npu_dma_add_buf(struct mt76_phy *phy, struct mt76_queue *q,
1669 struct sk_buff *skb, struct mt76_queue_buf *buf,
1670 void *txwi_ptr);
1671 int mt76_npu_rx_queue_init(struct mt76_dev *dev, struct mt76_queue *q);
1672 int mt76_npu_fill_rx_queue(struct mt76_dev *dev, struct mt76_queue *q);
1673 void mt76_npu_queue_cleanup(struct mt76_dev *dev, struct mt76_queue *q);
1674 void mt76_npu_disable_irqs(struct mt76_dev *dev);
1675 int mt76_npu_init(struct mt76_dev *dev, phys_addr_t phy_addr, int type);
1676 void mt76_npu_deinit(struct mt76_dev *dev);
1677 void mt76_npu_queue_setup(struct mt76_dev *dev, struct mt76_queue *q);
1678 void mt76_npu_txdesc_cleanup(struct mt76_queue *q, int index);
1679 int mt76_npu_net_setup_tc(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1680 struct net_device *dev, enum tc_setup_type type,
1681 void *type_data);
1682 int mt76_npu_send_txrx_addr(struct mt76_dev *dev, int ifindex,
1683 u32 direction, u32 i_count_addr,
1684 u32 o_status_addr, u32 o_count_addr);
1685 #else
mt76_npu_check_ppe(struct mt76_dev * dev,struct sk_buff * skb,u32 info)1686 static inline void mt76_npu_check_ppe(struct mt76_dev *dev,
1687 struct sk_buff *skb, u32 info)
1688 {
1689 }
1690
mt76_npu_dma_add_buf(struct mt76_phy * phy,struct mt76_queue * q,struct sk_buff * skb,struct mt76_queue_buf * buf,void * txwi_ptr)1691 static inline int mt76_npu_dma_add_buf(struct mt76_phy *phy,
1692 struct mt76_queue *q,
1693 struct sk_buff *skb,
1694 struct mt76_queue_buf *buf,
1695 void *txwi_ptr)
1696 {
1697 return -EOPNOTSUPP;
1698 }
1699
mt76_npu_fill_rx_queue(struct mt76_dev * dev,struct mt76_queue * q)1700 static inline int mt76_npu_fill_rx_queue(struct mt76_dev *dev,
1701 struct mt76_queue *q)
1702 {
1703 return 0;
1704 }
1705
mt76_npu_queue_cleanup(struct mt76_dev * dev,struct mt76_queue * q)1706 static inline void mt76_npu_queue_cleanup(struct mt76_dev *dev,
1707 struct mt76_queue *q)
1708 {
1709 }
1710
mt76_npu_disable_irqs(struct mt76_dev * dev)1711 static inline void mt76_npu_disable_irqs(struct mt76_dev *dev)
1712 {
1713 }
1714
mt76_npu_init(struct mt76_dev * dev,phys_addr_t phy_addr,int type)1715 static inline int mt76_npu_init(struct mt76_dev *dev, phys_addr_t phy_addr,
1716 int type)
1717 {
1718 return 0;
1719 }
1720
mt76_npu_deinit(struct mt76_dev * dev)1721 static inline void mt76_npu_deinit(struct mt76_dev *dev)
1722 {
1723 }
1724
mt76_npu_queue_setup(struct mt76_dev * dev,struct mt76_queue * q)1725 static inline void mt76_npu_queue_setup(struct mt76_dev *dev,
1726 struct mt76_queue *q)
1727 {
1728 }
1729
mt76_npu_txdesc_cleanup(struct mt76_queue * q,int index)1730 static inline void mt76_npu_txdesc_cleanup(struct mt76_queue *q,
1731 int index)
1732 {
1733 }
1734
mt76_npu_net_setup_tc(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct net_device * dev,enum tc_setup_type type,void * type_data)1735 static inline int mt76_npu_net_setup_tc(struct ieee80211_hw *hw,
1736 struct ieee80211_vif *vif,
1737 struct net_device *dev,
1738 enum tc_setup_type type,
1739 void *type_data)
1740 {
1741 return -EOPNOTSUPP;
1742 }
1743
mt76_npu_send_txrx_addr(struct mt76_dev * dev,int ifindex,u32 direction,u32 i_count_addr,u32 o_status_addr,u32 o_count_addr)1744 static inline int mt76_npu_send_txrx_addr(struct mt76_dev *dev, int ifindex,
1745 u32 direction, u32 i_count_addr,
1746 u32 o_status_addr, u32 o_count_addr)
1747 {
1748 return -EOPNOTSUPP;
1749 }
1750 #endif /* CONFIG_MT76_NPU */
1751
mt76_npu_device_active(struct mt76_dev * dev)1752 static inline bool mt76_npu_device_active(struct mt76_dev *dev)
1753 {
1754 return mt76_is_mmio(dev) && !!rcu_access_pointer(dev->mmio.npu);
1755 }
1756
mt76_ppe_device_active(struct mt76_dev * dev)1757 static inline bool mt76_ppe_device_active(struct mt76_dev *dev)
1758 {
1759 return mt76_is_mmio(dev) && !!rcu_access_pointer(dev->mmio.ppe_dev);
1760 }
1761
mt76_npu_send_msg(struct airoha_npu * npu,int ifindex,enum airoha_npu_wlan_set_cmd cmd,u32 val,gfp_t gfp)1762 static inline int mt76_npu_send_msg(struct airoha_npu *npu, int ifindex,
1763 enum airoha_npu_wlan_set_cmd cmd,
1764 u32 val, gfp_t gfp)
1765 {
1766 return airoha_npu_wlan_send_msg(npu, ifindex, cmd, &val, sizeof(val),
1767 gfp);
1768 }
1769
mt76_npu_get_msg(struct airoha_npu * npu,int ifindex,enum airoha_npu_wlan_get_cmd cmd,u32 * val,gfp_t gfp)1770 static inline int mt76_npu_get_msg(struct airoha_npu *npu, int ifindex,
1771 enum airoha_npu_wlan_get_cmd cmd,
1772 u32 *val, gfp_t gfp)
1773 {
1774 return airoha_npu_wlan_get_msg(npu, ifindex, cmd, val, sizeof(*val),
1775 gfp);
1776 }
1777
mt76_testmode_reset(struct mt76_phy * phy,bool disable)1778 static inline void mt76_testmode_reset(struct mt76_phy *phy, bool disable)
1779 {
1780 #ifdef CONFIG_NL80211_TESTMODE
1781 enum mt76_testmode_state state = MT76_TM_STATE_IDLE;
1782
1783 if (disable || phy->test.state == MT76_TM_STATE_OFF)
1784 state = MT76_TM_STATE_OFF;
1785
1786 mt76_testmode_set_state(phy, state);
1787 #endif
1788 }
1789
1790
1791 /* internal */
1792 static inline struct ieee80211_hw *
mt76_tx_status_get_hw(struct mt76_dev * dev,struct sk_buff * skb)1793 mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb)
1794 {
1795 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1796 u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2;
1797 struct ieee80211_hw *hw = mt76_phy_hw(dev, phy_idx);
1798
1799 info->hw_queue &= ~MT_TX_HW_QUEUE_PHY;
1800
1801 return hw;
1802 }
1803
1804 void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t);
1805 void mt76_put_rxwi(struct mt76_dev *dev, struct mt76_txwi_cache *t);
1806 struct mt76_txwi_cache *mt76_get_rxwi(struct mt76_dev *dev);
1807 void mt76_free_pending_rxwi(struct mt76_dev *dev);
1808 void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames,
1809 struct napi_struct *napi);
1810 void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q,
1811 struct napi_struct *napi);
1812 void mt76_rx_aggr_reorder(struct sk_buff *skb, struct sk_buff_head *frames);
1813 void mt76_testmode_tx_pending(struct mt76_phy *phy);
1814 void mt76_queue_tx_complete(struct mt76_dev *dev, struct mt76_queue *q,
1815 struct mt76_queue_entry *e);
1816 int __mt76_set_channel(struct mt76_phy *phy, struct cfg80211_chan_def *chandef,
1817 bool offchannel);
1818
1819 static inline bool
mt76_offchannel_chandef(struct mt76_phy * phy,struct ieee80211_channel * chan,struct cfg80211_chan_def * chandef)1820 mt76_offchannel_chandef(struct mt76_phy *phy, struct ieee80211_channel *chan,
1821 struct cfg80211_chan_def *chandef)
1822 {
1823 cfg80211_chandef_create(chandef, chan, NL80211_CHAN_HT20);
1824 if (phy->main_chandef.chan != chan)
1825 return true;
1826
1827 *chandef = phy->main_chandef;
1828 return false;
1829 }
1830 int mt76_set_channel(struct mt76_phy *phy, struct cfg80211_chan_def *chandef,
1831 bool offchannel);
1832 void mt76_scan_work(struct work_struct *work);
1833 void mt76_abort_scan(struct mt76_dev *dev);
1834 void mt76_roc_complete_work(struct work_struct *work);
1835 void mt76_roc_complete(struct mt76_phy *phy);
1836 void mt76_abort_roc(struct mt76_phy *phy);
1837 struct mt76_vif_link *mt76_get_vif_phy_link(struct mt76_phy *phy,
1838 struct ieee80211_vif *vif);
1839 void mt76_put_vif_phy_link(struct mt76_phy *phy, struct ieee80211_vif *vif,
1840 struct mt76_vif_link *mlink);
1841 void mt76_offchannel_notify(struct mt76_phy *phy, bool offchannel);
1842
1843 /* usb */
mt76u_urb_error(struct urb * urb)1844 static inline bool mt76u_urb_error(struct urb *urb)
1845 {
1846 return urb->status &&
1847 urb->status != -ECONNRESET &&
1848 urb->status != -ESHUTDOWN &&
1849 urb->status != -ENOENT;
1850 }
1851
1852 static inline int
mt76u_bulk_msg(struct mt76_dev * dev,void * data,int len,int * actual_len,int timeout,int ep)1853 mt76u_bulk_msg(struct mt76_dev *dev, void *data, int len, int *actual_len,
1854 int timeout, int ep)
1855 {
1856 struct usb_interface *uintf = to_usb_interface(dev->dev);
1857 struct usb_device *udev = interface_to_usbdev(uintf);
1858 struct mt76_usb *usb = &dev->usb;
1859 unsigned int pipe;
1860
1861 if (actual_len)
1862 pipe = usb_rcvbulkpipe(udev, usb->in_ep[ep]);
1863 else
1864 pipe = usb_sndbulkpipe(udev, usb->out_ep[ep]);
1865
1866 return usb_bulk_msg(udev, pipe, data, len, actual_len, timeout);
1867 }
1868
1869 void mt76_ethtool_page_pool_stats(struct mt76_dev *dev, u64 *data, int *index);
1870 void mt76_ethtool_worker(struct mt76_ethtool_worker_info *wi,
1871 struct mt76_sta_stats *stats, bool eht);
1872 int mt76_skb_adjust_pad(struct sk_buff *skb, int pad);
1873 int __mt76u_vendor_request(struct mt76_dev *dev, u8 req, u8 req_type,
1874 u16 val, u16 offset, void *buf, size_t len);
1875 int mt76u_vendor_request(struct mt76_dev *dev, u8 req,
1876 u8 req_type, u16 val, u16 offset,
1877 void *buf, size_t len);
1878 void mt76u_single_wr(struct mt76_dev *dev, const u8 req,
1879 const u16 offset, const u32 val);
1880 void mt76u_read_copy(struct mt76_dev *dev, u32 offset,
1881 void *data, int len);
1882 u32 ___mt76u_rr(struct mt76_dev *dev, u8 req, u8 req_type, u32 addr);
1883 void ___mt76u_wr(struct mt76_dev *dev, u8 req, u8 req_type,
1884 u32 addr, u32 val);
1885 int __mt76u_init(struct mt76_dev *dev, struct usb_interface *intf,
1886 struct mt76_bus_ops *ops);
1887 int mt76u_init(struct mt76_dev *dev, struct usb_interface *intf);
1888 int mt76u_alloc_mcu_queue(struct mt76_dev *dev);
1889 int mt76u_alloc_queues(struct mt76_dev *dev);
1890 void mt76u_stop_tx(struct mt76_dev *dev);
1891 void mt76u_stop_rx(struct mt76_dev *dev);
1892 int mt76u_resume_rx(struct mt76_dev *dev);
1893 void mt76u_queues_deinit(struct mt76_dev *dev);
1894
1895 int mt76s_init(struct mt76_dev *dev, struct sdio_func *func,
1896 const struct mt76_bus_ops *bus_ops);
1897 int mt76s_alloc_rx_queue(struct mt76_dev *dev, enum mt76_rxq_id qid);
1898 int mt76s_alloc_tx(struct mt76_dev *dev);
1899 void mt76s_deinit(struct mt76_dev *dev);
1900 void mt76s_sdio_irq(struct sdio_func *func);
1901 void mt76s_txrx_worker(struct mt76_sdio *sdio);
1902 bool mt76s_txqs_empty(struct mt76_dev *dev);
1903 int mt76s_hw_init(struct mt76_dev *dev, struct sdio_func *func,
1904 int hw_ver);
1905 u32 mt76s_rr(struct mt76_dev *dev, u32 offset);
1906 void mt76s_wr(struct mt76_dev *dev, u32 offset, u32 val);
1907 u32 mt76s_rmw(struct mt76_dev *dev, u32 offset, u32 mask, u32 val);
1908 u32 mt76s_read_pcr(struct mt76_dev *dev);
1909 void mt76s_write_copy(struct mt76_dev *dev, u32 offset,
1910 const void *data, int len);
1911 void mt76s_read_copy(struct mt76_dev *dev, u32 offset,
1912 void *data, int len);
1913 int mt76s_wr_rp(struct mt76_dev *dev, u32 base,
1914 const struct mt76_reg_pair *data,
1915 int len);
1916 int mt76s_rd_rp(struct mt76_dev *dev, u32 base,
1917 struct mt76_reg_pair *data, int len);
1918
1919 struct sk_buff *
1920 __mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data,
1921 int len, int data_len, gfp_t gfp);
1922 static inline struct sk_buff *
mt76_mcu_msg_alloc(struct mt76_dev * dev,const void * data,int data_len)1923 mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data,
1924 int data_len)
1925 {
1926 return __mt76_mcu_msg_alloc(dev, data, data_len, data_len, GFP_KERNEL);
1927 }
1928
1929 void mt76_mcu_rx_event(struct mt76_dev *dev, struct sk_buff *skb);
1930 struct sk_buff *mt76_mcu_get_response(struct mt76_dev *dev,
1931 unsigned long expires);
1932 int mt76_mcu_send_and_get_msg(struct mt76_dev *dev, int cmd, const void *data,
1933 int len, bool wait_resp, struct sk_buff **ret);
1934 int mt76_mcu_skb_send_and_get_msg(struct mt76_dev *dev, struct sk_buff *skb,
1935 int cmd, bool wait_resp, struct sk_buff **ret);
1936 int __mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data,
1937 int len, int max_len);
1938 static inline int
mt76_mcu_send_firmware(struct mt76_dev * dev,int cmd,const void * data,int len)1939 mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data,
1940 int len)
1941 {
1942 int max_len = 4096 - dev->mcu_ops->headroom;
1943
1944 return __mt76_mcu_send_firmware(dev, cmd, data, len, max_len);
1945 }
1946
1947 static inline int
mt76_mcu_send_msg(struct mt76_dev * dev,int cmd,const void * data,int len,bool wait_resp)1948 mt76_mcu_send_msg(struct mt76_dev *dev, int cmd, const void *data, int len,
1949 bool wait_resp)
1950 {
1951 return mt76_mcu_send_and_get_msg(dev, cmd, data, len, wait_resp, NULL);
1952 }
1953
1954 static inline int
mt76_mcu_skb_send_msg(struct mt76_dev * dev,struct sk_buff * skb,int cmd,bool wait_resp)1955 mt76_mcu_skb_send_msg(struct mt76_dev *dev, struct sk_buff *skb, int cmd,
1956 bool wait_resp)
1957 {
1958 return mt76_mcu_skb_send_and_get_msg(dev, skb, cmd, wait_resp, NULL);
1959 }
1960
1961 void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr, u32 clear, u32 set);
1962
1963 struct device_node *
1964 mt76_find_power_limits_node(struct mt76_dev *dev);
1965 struct device_node *
1966 mt76_find_channel_node(struct device_node *np, struct ieee80211_channel *chan);
1967
1968 s8 mt76_get_rate_power_limits(struct mt76_phy *phy,
1969 struct ieee80211_channel *chan,
1970 struct mt76_power_limits *dest,
1971 s8 target_power);
1972
mt76_queue_is_rx(struct mt76_dev * dev,struct mt76_queue * q)1973 static inline bool mt76_queue_is_rx(struct mt76_dev *dev, struct mt76_queue *q)
1974 {
1975 int i;
1976
1977 for (i = 0; i < ARRAY_SIZE(dev->q_rx); i++) {
1978 if (q == &dev->q_rx[i])
1979 return true;
1980 }
1981
1982 return false;
1983 }
1984
mt76_queue_is_wed_tx_free(struct mt76_queue * q)1985 static inline bool mt76_queue_is_wed_tx_free(struct mt76_queue *q)
1986 {
1987 return (q->flags & MT_QFLAG_WED) &&
1988 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_TXFREE;
1989 }
1990
mt76_queue_is_wed_rro(struct mt76_queue * q)1991 static inline bool mt76_queue_is_wed_rro(struct mt76_queue *q)
1992 {
1993 return q->flags & MT_QFLAG_WED_RRO;
1994 }
1995
mt76_queue_is_wed_rro_ind(struct mt76_queue * q)1996 static inline bool mt76_queue_is_wed_rro_ind(struct mt76_queue *q)
1997 {
1998 return mt76_queue_is_wed_rro(q) &&
1999 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_RRO_Q_IND;
2000 }
2001
mt76_queue_is_wed_rro_rxdmad_c(struct mt76_queue * q)2002 static inline bool mt76_queue_is_wed_rro_rxdmad_c(struct mt76_queue *q)
2003 {
2004 return mt76_queue_is_wed_rro(q) &&
2005 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_RRO_Q_RXDMAD_C;
2006 }
2007
mt76_queue_is_wed_rro_data(struct mt76_queue * q)2008 static inline bool mt76_queue_is_wed_rro_data(struct mt76_queue *q)
2009 {
2010 return mt76_queue_is_wed_rro(q) &&
2011 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_RRO_Q_DATA;
2012 }
2013
mt76_queue_is_wed_rro_msdu_pg(struct mt76_queue * q)2014 static inline bool mt76_queue_is_wed_rro_msdu_pg(struct mt76_queue *q)
2015 {
2016 return mt76_queue_is_wed_rro(q) &&
2017 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) ==
2018 MT76_WED_RRO_Q_MSDU_PG;
2019 }
2020
mt76_queue_is_wed_rx(struct mt76_queue * q)2021 static inline bool mt76_queue_is_wed_rx(struct mt76_queue *q)
2022 {
2023 return (q->flags & MT_QFLAG_WED) &&
2024 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_RX;
2025 }
2026
mt76_queue_is_emi(struct mt76_queue * q)2027 static inline bool mt76_queue_is_emi(struct mt76_queue *q)
2028 {
2029 return q->flags & MT_QFLAG_EMI_EN;
2030 }
2031
mt76_queue_is_npu(struct mt76_queue * q)2032 static inline bool mt76_queue_is_npu(struct mt76_queue *q)
2033 {
2034 return q->flags & MT_QFLAG_NPU;
2035 }
2036
mt76_queue_is_npu_tx(struct mt76_queue * q)2037 static inline bool mt76_queue_is_npu_tx(struct mt76_queue *q)
2038 {
2039 return mt76_queue_is_npu(q) &&
2040 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_TX;
2041 }
2042
mt76_queue_is_npu_rx(struct mt76_queue * q)2043 static inline bool mt76_queue_is_npu_rx(struct mt76_queue *q)
2044 {
2045 return mt76_queue_is_npu(q) &&
2046 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_RX;
2047 }
2048
mt76_queue_is_npu_txfree(struct mt76_queue * q)2049 static inline bool mt76_queue_is_npu_txfree(struct mt76_queue *q)
2050 {
2051 if (q->flags & MT_QFLAG_WED)
2052 return false;
2053
2054 return FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_TXFREE;
2055 }
2056
2057 struct mt76_txwi_cache *
2058 mt76_token_release(struct mt76_dev *dev, int token, bool *wake);
2059 int mt76_token_consume(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi);
2060 void __mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked);
2061 struct mt76_txwi_cache *mt76_rx_token_release(struct mt76_dev *dev, int token);
2062 int mt76_rx_token_consume(struct mt76_dev *dev, void *ptr,
2063 struct mt76_txwi_cache *r, dma_addr_t phys);
2064 int mt76_create_page_pool(struct mt76_dev *dev, struct mt76_queue *q);
mt76_put_page_pool_buf(void * buf,bool allow_direct)2065 static inline void mt76_put_page_pool_buf(void *buf, bool allow_direct)
2066 {
2067 struct page *page = virt_to_head_page(buf);
2068
2069 page_pool_put_full_page(pp_page_to_nmdesc(page)->pp, page,
2070 allow_direct);
2071 }
2072
2073 static inline void *
mt76_get_page_pool_buf(struct mt76_queue * q,u32 * offset,u32 size)2074 mt76_get_page_pool_buf(struct mt76_queue *q, u32 *offset, u32 size)
2075 {
2076 struct page *page;
2077
2078 page = page_pool_alloc_frag(q->page_pool, offset, size,
2079 GFP_ATOMIC | __GFP_NOWARN | GFP_DMA32);
2080 if (!page)
2081 return NULL;
2082
2083 return page_address(page) + *offset;
2084 }
2085
mt76_set_tx_blocked(struct mt76_dev * dev,bool blocked)2086 static inline void mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked)
2087 {
2088 spin_lock_bh(&dev->token_lock);
2089 __mt76_set_tx_blocked(dev, blocked);
2090 spin_unlock_bh(&dev->token_lock);
2091 }
2092
2093 static inline int
mt76_token_get(struct mt76_dev * dev,struct mt76_txwi_cache ** ptxwi)2094 mt76_token_get(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi)
2095 {
2096 int token;
2097
2098 spin_lock_bh(&dev->token_lock);
2099 token = idr_alloc(&dev->token, *ptxwi, 0, dev->token_size, GFP_ATOMIC);
2100 spin_unlock_bh(&dev->token_lock);
2101
2102 return token;
2103 }
2104
2105 static inline struct mt76_txwi_cache *
mt76_token_put(struct mt76_dev * dev,int token)2106 mt76_token_put(struct mt76_dev *dev, int token)
2107 {
2108 struct mt76_txwi_cache *txwi;
2109
2110 spin_lock_bh(&dev->token_lock);
2111 txwi = idr_remove(&dev->token, token);
2112 spin_unlock_bh(&dev->token_lock);
2113
2114 return txwi;
2115 }
2116
2117 void mt76_wcid_init(struct mt76_wcid *wcid, u8 band_idx);
2118 void mt76_wcid_cleanup(struct mt76_dev *dev, struct mt76_wcid *wcid);
2119 void mt76_wcid_add_poll(struct mt76_dev *dev, struct mt76_wcid *wcid);
2120
2121 static inline void
mt76_vif_init(struct ieee80211_vif * vif,struct mt76_vif_data * mvif)2122 mt76_vif_init(struct ieee80211_vif *vif, struct mt76_vif_data *mvif)
2123 {
2124 struct mt76_vif_link *mlink = (struct mt76_vif_link *)vif->drv_priv;
2125
2126 mlink->mvif = mvif;
2127 rcu_assign_pointer(mvif->link[0], mlink);
2128 }
2129
2130 void mt76_vif_cleanup(struct mt76_dev *dev, struct ieee80211_vif *vif);
2131 u16 mt76_select_links(struct ieee80211_vif *vif, int max_active_links);
2132
2133 static inline struct mt76_vif_link *
mt76_vif_link(struct mt76_dev * dev,struct ieee80211_vif * vif,int link_id)2134 mt76_vif_link(struct mt76_dev *dev, struct ieee80211_vif *vif, int link_id)
2135 {
2136 struct mt76_vif_link *mlink = (struct mt76_vif_link *)vif->drv_priv;
2137 struct mt76_vif_data *mvif = mlink->mvif;
2138
2139 if (!link_id)
2140 return mlink;
2141
2142 if (link_id >= IEEE80211_MLD_MAX_NUM_LINKS)
2143 return NULL;
2144
2145 return mt76_dereference(mvif->link[link_id], dev);
2146 }
2147
2148 static inline struct mt76_vif_link *
mt76_vif_conf_link(struct mt76_dev * dev,struct ieee80211_vif * vif,struct ieee80211_bss_conf * link_conf)2149 mt76_vif_conf_link(struct mt76_dev *dev, struct ieee80211_vif *vif,
2150 struct ieee80211_bss_conf *link_conf)
2151 {
2152 struct mt76_vif_link *mlink = (struct mt76_vif_link *)vif->drv_priv;
2153 struct mt76_vif_data *mvif = mlink->mvif;
2154
2155 if (link_conf == &vif->bss_conf || !link_conf->link_id)
2156 return mlink;
2157
2158 return mt76_dereference(mvif->link[link_conf->link_id], dev);
2159 }
2160
2161 static inline struct mt76_phy *
mt76_vif_link_phy(struct mt76_vif_link * mlink)2162 mt76_vif_link_phy(struct mt76_vif_link *mlink)
2163 {
2164 struct mt76_chanctx *ctx;
2165
2166 if (!mlink->ctx)
2167 return NULL;
2168
2169 ctx = (struct mt76_chanctx *)mlink->ctx->drv_priv;
2170
2171 return ctx->phy;
2172 }
2173
2174 #endif
2175