1 /*-
2 * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
3 *
4 * Copyright (c) 2015 - 2026 Intel Corporation
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenFabrics.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include "irdma_main.h"
36
37 /**
38 * irdma_query_device - get device attributes
39 * @ibdev: device pointer from stack
40 * @props: returning device attributes
41 * @udata: user data
42 */
43 static int
irdma_query_device(struct ib_device * ibdev,struct ib_device_attr * props,struct ib_udata * udata)44 irdma_query_device(struct ib_device *ibdev,
45 struct ib_device_attr *props,
46 struct ib_udata *udata)
47 {
48 struct irdma_device *iwdev = to_iwdev(ibdev);
49 struct irdma_pci_f *rf = iwdev->rf;
50 struct pci_dev *pcidev = iwdev->rf->pcidev;
51 struct irdma_hw_attrs *hw_attrs = &rf->sc_dev.hw_attrs;
52
53 if (udata->inlen || udata->outlen)
54 return -EINVAL;
55
56 memset(props, 0, sizeof(*props));
57 addrconf_addr_eui48((u8 *)&props->sys_image_guid,
58 if_getlladdr(iwdev->netdev));
59 props->fw_ver = (u64)irdma_fw_major_ver(&rf->sc_dev) << 32 |
60 irdma_fw_minor_ver(&rf->sc_dev);
61 props->device_cap_flags = IB_DEVICE_MEM_WINDOW |
62 IB_DEVICE_MEM_MGT_EXTENSIONS;
63 props->vendor_id = pcidev->vendor;
64 props->vendor_part_id = pcidev->device;
65 props->hw_ver = pcidev->revision;
66 props->page_size_cap = hw_attrs->page_size_cap;
67 props->max_mr_size = hw_attrs->max_mr_size;
68 props->max_qp = rf->max_qp - rf->used_qps;
69 props->max_qp_wr = hw_attrs->max_qp_wr;
70 set_max_sge(props, rf);
71 props->max_cq = rf->max_cq - rf->used_cqs;
72 props->max_cqe = rf->max_cqe - 1;
73 props->max_mr = rf->max_mr - rf->used_mrs;
74 props->max_pd = rf->max_pd - rf->used_pds;
75 props->max_sge_rd = hw_attrs->uk_attrs.max_hw_read_sges;
76 props->max_qp_rd_atom = hw_attrs->max_hw_ird;
77 props->max_qp_init_rd_atom = hw_attrs->max_hw_ord;
78 if (rdma_protocol_roce(ibdev, 1)) {
79 props->device_cap_flags |= IB_DEVICE_RC_RNR_NAK_GEN;
80 props->max_pkeys = IRDMA_PKEY_TBL_SZ;
81 props->max_ah = rf->max_ah;
82 if (hw_attrs->uk_attrs.hw_rev == IRDMA_GEN_2) {
83 props->max_mcast_grp = rf->max_mcg;
84 props->max_mcast_qp_attach = IRDMA_MAX_MGS_PER_CTX;
85 props->max_total_mcast_qp_attach = rf->max_qp * IRDMA_MAX_MGS_PER_CTX;
86 }
87 }
88 props->max_fast_reg_page_list_len = IRDMA_MAX_PAGES_PER_FMR;
89 if (hw_attrs->uk_attrs.hw_rev >= IRDMA_GEN_2)
90 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2B;
91
92 return 0;
93 }
94
95 static int
irdma_mmap_legacy(struct irdma_ucontext * ucontext,struct vm_area_struct * vma)96 irdma_mmap_legacy(struct irdma_ucontext *ucontext,
97 struct vm_area_struct *vma)
98 {
99 u64 pfn;
100
101 if (vma->vm_pgoff || vma->vm_end - vma->vm_start != PAGE_SIZE)
102 return -EINVAL;
103
104 vma->vm_private_data = ucontext;
105 pfn = ((uintptr_t)ucontext->iwdev->rf->sc_dev.hw_regs[IRDMA_DB_ADDR_OFFSET] +
106 pci_resource_start(ucontext->iwdev->rf->pcidev, 0)) >> PAGE_SHIFT;
107
108 return rdma_user_mmap_io(&ucontext->ibucontext, vma, pfn, PAGE_SIZE,
109 pgprot_noncached(vma->vm_page_prot), NULL);
110 }
111
112 static void
irdma_mmap_free(struct rdma_user_mmap_entry * rdma_entry)113 irdma_mmap_free(struct rdma_user_mmap_entry *rdma_entry)
114 {
115 struct irdma_user_mmap_entry *entry = to_irdma_mmap_entry(rdma_entry);
116
117 kfree(entry);
118 }
119
120 struct rdma_user_mmap_entry *
irdma_user_mmap_entry_insert(struct irdma_ucontext * ucontext,u64 bar_offset,enum irdma_mmap_flag mmap_flag,u64 * mmap_offset)121 irdma_user_mmap_entry_insert(struct irdma_ucontext *ucontext, u64 bar_offset,
122 enum irdma_mmap_flag mmap_flag, u64 *mmap_offset)
123 {
124 struct irdma_user_mmap_entry *entry = kzalloc(sizeof(*entry), GFP_KERNEL);
125 int ret;
126
127 if (!entry)
128 return NULL;
129
130 entry->bar_offset = bar_offset;
131 entry->mmap_flag = mmap_flag;
132
133 ret = rdma_user_mmap_entry_insert(&ucontext->ibucontext,
134 &entry->rdma_entry, PAGE_SIZE);
135 if (ret) {
136 kfree(entry);
137 return NULL;
138 }
139 *mmap_offset = rdma_user_mmap_get_offset(&entry->rdma_entry);
140
141 return &entry->rdma_entry;
142 }
143
144 /**
145 * irdma_mmap - user memory map
146 * @context: context created during alloc
147 * @vma: kernel info for user memory map
148 */
149 static int
irdma_mmap(struct ib_ucontext * context,struct vm_area_struct * vma)150 irdma_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
151 {
152 struct rdma_user_mmap_entry *rdma_entry;
153 struct irdma_user_mmap_entry *entry;
154 struct irdma_ucontext *ucontext;
155 u64 pfn;
156 int ret;
157
158 ucontext = to_ucontext(context);
159
160 /* Legacy support for libi40iw with hard-coded mmap key */
161 if (ucontext->legacy_mode)
162 return irdma_mmap_legacy(ucontext, vma);
163
164 rdma_entry = rdma_user_mmap_entry_get(&ucontext->ibucontext, vma);
165 if (!rdma_entry) {
166 irdma_debug(&ucontext->iwdev->rf->sc_dev, IRDMA_DEBUG_VERBS,
167 "pgoff[0x%lx] does not have valid entry\n",
168 vma->vm_pgoff);
169 return -EINVAL;
170 }
171
172 entry = to_irdma_mmap_entry(rdma_entry);
173 irdma_debug(&ucontext->iwdev->rf->sc_dev, IRDMA_DEBUG_VERBS,
174 "bar_offset [0x%lx] mmap_flag [%d]\n", entry->bar_offset,
175 entry->mmap_flag);
176
177 pfn = (entry->bar_offset +
178 pci_resource_start(ucontext->iwdev->rf->pcidev, 0)) >> PAGE_SHIFT;
179
180 switch (entry->mmap_flag) {
181 case IRDMA_MMAP_IO_NC:
182 ret = rdma_user_mmap_io(context, vma, pfn, PAGE_SIZE,
183 pgprot_noncached(vma->vm_page_prot),
184 rdma_entry);
185 break;
186 case IRDMA_MMAP_IO_WC:
187 ret = rdma_user_mmap_io(context, vma, pfn, PAGE_SIZE,
188 pgprot_writecombine(vma->vm_page_prot),
189 rdma_entry);
190 break;
191 default:
192 ret = -EINVAL;
193 }
194
195 if (ret)
196 irdma_debug(&ucontext->iwdev->rf->sc_dev, IRDMA_DEBUG_VERBS,
197 "bar_offset [0x%lx] mmap_flag[%d] err[%d]\n",
198 entry->bar_offset, entry->mmap_flag, ret);
199 rdma_user_mmap_entry_put(rdma_entry);
200
201 return ret;
202 }
203
204 /**
205 * irdma_alloc_push_page - allocate a push page for qp
206 * @iwqp: qp pointer
207 */
208 static void
irdma_alloc_push_page(struct irdma_qp * iwqp)209 irdma_alloc_push_page(struct irdma_qp *iwqp)
210 {
211 struct irdma_cqp_request *cqp_request;
212 struct cqp_cmds_info *cqp_info;
213 struct irdma_device *iwdev = iwqp->iwdev;
214 struct irdma_sc_qp *qp = &iwqp->sc_qp;
215 int status;
216
217 cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true);
218 if (!cqp_request)
219 return;
220
221 cqp_info = &cqp_request->info;
222 cqp_info->cqp_cmd = IRDMA_OP_MANAGE_PUSH_PAGE;
223 cqp_info->post_sq = 1;
224 cqp_info->in.u.manage_push_page.info.push_idx = 0;
225 cqp_info->in.u.manage_push_page.info.qs_handle =
226 qp->vsi->qos[qp->user_pri].qs_handle;
227 cqp_info->in.u.manage_push_page.info.free_page = 0;
228 cqp_info->in.u.manage_push_page.info.push_page_type = 0;
229 cqp_info->in.u.manage_push_page.cqp = &iwdev->rf->cqp.sc_cqp;
230 cqp_info->in.u.manage_push_page.scratch = (uintptr_t)cqp_request;
231 cqp_info->create = true;
232
233 status = irdma_handle_cqp_op(iwdev->rf, cqp_request);
234 if (!status && cqp_request->compl_info.op_ret_val <
235 iwdev->rf->sc_dev.hw_attrs.max_hw_device_pages) {
236 qp->push_idx = cqp_request->compl_info.op_ret_val;
237 qp->push_offset = 0;
238 }
239
240 irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request);
241 }
242
243 /**
244 * irdma_get_pbl - Retrieve pbl from a list given a virtual
245 * address
246 * @va: user virtual address
247 * @pbl_list: pbl list to search in (QP's or CQ's)
248 */
249 struct irdma_pbl *
irdma_get_pbl(unsigned long va,struct list_head * pbl_list)250 irdma_get_pbl(unsigned long va,
251 struct list_head *pbl_list)
252 {
253 struct irdma_pbl *iwpbl;
254
255 list_for_each_entry(iwpbl, pbl_list, list) {
256 if (iwpbl->user_base == va) {
257 list_del(&iwpbl->list);
258 iwpbl->on_list = false;
259 return iwpbl;
260 }
261 }
262
263 return NULL;
264 }
265
266 /**
267 * irdma_clean_cqes - clean cq entries for qp
268 * @iwqp: qp ptr (user or kernel)
269 * @iwcq: cq ptr
270 */
271 void
irdma_clean_cqes(struct irdma_qp * iwqp,struct irdma_cq * iwcq)272 irdma_clean_cqes(struct irdma_qp *iwqp, struct irdma_cq *iwcq)
273 {
274 struct irdma_cq_uk *ukcq = &iwcq->sc_cq.cq_uk;
275 unsigned long flags;
276 struct irdma_cmpl_gen *cmpl_node;
277 struct list_head *tmp_node, *list_node;
278
279 spin_lock_irqsave(&iwcq->lock, flags);
280 irdma_uk_clean_cq(&iwqp->sc_qp.qp_uk, ukcq);
281
282 list_for_each_safe(list_node, tmp_node, &iwcq->cmpl_generated) {
283 cmpl_node = list_entry(list_node, struct irdma_cmpl_gen, list);
284 if (cmpl_node->cpi.qp_id == iwqp->ibqp.qp_num) {
285 list_del(&cmpl_node->list);
286 kfree(cmpl_node);
287 }
288 }
289
290 spin_unlock_irqrestore(&iwcq->lock, flags);
291 }
292
irdma_compute_push_wqe_offset(struct irdma_device * iwdev,u32 page_idx)293 static u64 irdma_compute_push_wqe_offset(struct irdma_device *iwdev, u32 page_idx){
294 u64 bar_off = (uintptr_t)iwdev->rf->sc_dev.hw_regs[IRDMA_DB_ADDR_OFFSET];
295
296 if (iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_2) {
297 /* skip over db page */
298 bar_off += IRDMA_HW_PAGE_SIZE;
299 /* skip over reserved space */
300 bar_off += IRDMA_PF_BAR_RSVD;
301 }
302
303 /* push wqe page */
304 bar_off += (u64)page_idx * IRDMA_HW_PAGE_SIZE;
305
306 return bar_off;
307 }
308
309 void
irdma_remove_push_mmap_entries(struct irdma_qp * iwqp)310 irdma_remove_push_mmap_entries(struct irdma_qp *iwqp)
311 {
312 if (iwqp->push_db_mmap_entry) {
313 rdma_user_mmap_entry_remove(iwqp->push_db_mmap_entry);
314 iwqp->push_db_mmap_entry = NULL;
315 }
316 if (iwqp->push_wqe_mmap_entry) {
317 rdma_user_mmap_entry_remove(iwqp->push_wqe_mmap_entry);
318 iwqp->push_wqe_mmap_entry = NULL;
319 }
320 }
321
322 static int
irdma_setup_push_mmap_entries(struct irdma_ucontext * ucontext,struct irdma_qp * iwqp,u64 * push_wqe_mmap_key,u64 * push_db_mmap_key)323 irdma_setup_push_mmap_entries(struct irdma_ucontext *ucontext,
324 struct irdma_qp *iwqp,
325 u64 *push_wqe_mmap_key,
326 u64 *push_db_mmap_key)
327 {
328 struct irdma_device *iwdev = ucontext->iwdev;
329 u64 bar_off;
330
331 WARN_ON_ONCE(iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev < IRDMA_GEN_2);
332
333 bar_off = irdma_compute_push_wqe_offset(iwdev, iwqp->sc_qp.push_idx);
334
335 iwqp->push_wqe_mmap_entry = irdma_user_mmap_entry_insert(ucontext,
336 bar_off, IRDMA_MMAP_IO_WC,
337 push_wqe_mmap_key);
338 if (!iwqp->push_wqe_mmap_entry)
339 return -ENOMEM;
340
341 /* push doorbell page */
342 bar_off += IRDMA_HW_PAGE_SIZE;
343 iwqp->push_db_mmap_entry = irdma_user_mmap_entry_insert(ucontext,
344 bar_off, IRDMA_MMAP_IO_NC,
345 push_db_mmap_key);
346 if (!iwqp->push_db_mmap_entry) {
347 rdma_user_mmap_entry_remove(iwqp->push_wqe_mmap_entry);
348 return -ENOMEM;
349 }
350
351 return 0;
352 }
353
354 /**
355 * irdma_setup_virt_qp - setup for allocation of virtual qp
356 * @iwdev: irdma device
357 * @iwqp: qp ptr
358 * @init_info: initialize info to return
359 */
360 void
irdma_setup_virt_qp(struct irdma_device * iwdev,struct irdma_qp * iwqp,struct irdma_qp_init_info * init_info)361 irdma_setup_virt_qp(struct irdma_device *iwdev,
362 struct irdma_qp *iwqp,
363 struct irdma_qp_init_info *init_info)
364 {
365 struct irdma_pbl *iwpbl = iwqp->iwpbl;
366 struct irdma_qp_mr *qpmr = &iwpbl->qp_mr;
367
368 iwqp->page = qpmr->sq_page;
369 init_info->shadow_area_pa = qpmr->shadow;
370 if (iwpbl->pbl_allocated) {
371 init_info->virtual_map = true;
372 init_info->sq_pa = qpmr->sq_pbl.idx;
373 init_info->rq_pa = qpmr->rq_pbl.idx;
374 } else {
375 init_info->sq_pa = qpmr->sq_pbl.addr;
376 init_info->rq_pa = qpmr->rq_pbl.addr;
377 }
378 }
379
380 /**
381 * irdma_setup_umode_qp - setup sq and rq size in user mode qp
382 * @udata: user data
383 * @iwdev: iwarp device
384 * @iwqp: qp ptr (user or kernel)
385 * @info: initialize info to return
386 * @init_attr: Initial QP create attributes
387 */
388 int
irdma_setup_umode_qp(struct ib_udata * udata,struct irdma_device * iwdev,struct irdma_qp * iwqp,struct irdma_qp_init_info * info,struct ib_qp_init_attr * init_attr)389 irdma_setup_umode_qp(struct ib_udata *udata,
390 struct irdma_device *iwdev,
391 struct irdma_qp *iwqp,
392 struct irdma_qp_init_info *info,
393 struct ib_qp_init_attr *init_attr)
394 {
395 struct irdma_ucontext *ucontext = rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext);
396 struct irdma_qp_uk_init_info *ukinfo = &info->qp_uk_init_info;
397 struct irdma_create_qp_req req = {0};
398 unsigned long flags;
399 int ret;
400
401 ret = ib_copy_from_udata(&req, udata,
402 min(sizeof(req), udata->inlen));
403 if (ret) {
404 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_VERBS, "ib_copy_from_data fail\n");
405 return ret;
406 }
407
408 iwqp->ctx_info.qp_compl_ctx = req.user_compl_ctx;
409 iwqp->user_mode = 1;
410 if (req.user_wqe_bufs) {
411 info->qp_uk_init_info.legacy_mode = ucontext->legacy_mode;
412 spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags);
413 iwqp->iwpbl = irdma_get_pbl((unsigned long)req.user_wqe_bufs,
414 &ucontext->qp_reg_mem_list);
415 spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
416
417 if (!iwqp->iwpbl) {
418 ret = -ENODATA;
419 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_VERBS, "no pbl info\n");
420 return ret;
421 }
422 }
423
424 if (!ucontext->use_raw_attrs) {
425 /**
426 * Maintain backward compat with older ABI which passes sq and
427 * rq depth in quanta in cap.max_send_wr and cap.max_recv_wr.
428 * There is no way to compute the correct value of
429 * iwqp->max_send_wr/max_recv_wr in the kernel.
430 */
431 iwqp->max_send_wr = init_attr->cap.max_send_wr;
432 iwqp->max_recv_wr = init_attr->cap.max_recv_wr;
433 ukinfo->sq_size = init_attr->cap.max_send_wr;
434 ukinfo->rq_size = init_attr->cap.max_recv_wr;
435 irdma_uk_calc_shift_wq(ukinfo, &ukinfo->sq_shift, &ukinfo->rq_shift);
436 } else {
437 ret = irdma_uk_calc_depth_shift_sq(ukinfo, &ukinfo->sq_depth,
438 &ukinfo->sq_shift);
439 if (ret)
440 return ret;
441
442 ret = irdma_uk_calc_depth_shift_rq(ukinfo, &ukinfo->rq_depth,
443 &ukinfo->rq_shift);
444 if (ret)
445 return ret;
446
447 iwqp->max_send_wr = (ukinfo->sq_depth - IRDMA_SQ_RSVD) >> ukinfo->sq_shift;
448 iwqp->max_recv_wr = (ukinfo->rq_depth - IRDMA_RQ_RSVD) >> ukinfo->rq_shift;
449 ukinfo->sq_size = ukinfo->sq_depth >> ukinfo->sq_shift;
450 ukinfo->rq_size = ukinfo->rq_depth >> ukinfo->rq_shift;
451 }
452 if (req.comp_mask & IRDMA_CREATE_QP_USE_START_WQE_IDX &&
453 iwdev->rf->sc_dev.hw_attrs.uk_attrs.feature_flags & IRDMA_FEATURE_RTS_AE)
454 ukinfo->start_wqe_idx = 4;
455 irdma_setup_virt_qp(iwdev, iwqp, info);
456
457 return 0;
458 }
459
460 /**
461 * irdma_setup_kmode_qp - setup initialization for kernel mode qp
462 * @iwdev: iwarp device
463 * @iwqp: qp ptr (user or kernel)
464 * @info: initialize info to return
465 * @init_attr: Initial QP create attributes
466 */
467 int
irdma_setup_kmode_qp(struct irdma_device * iwdev,struct irdma_qp * iwqp,struct irdma_qp_init_info * info,struct ib_qp_init_attr * init_attr)468 irdma_setup_kmode_qp(struct irdma_device *iwdev,
469 struct irdma_qp *iwqp,
470 struct irdma_qp_init_info *info,
471 struct ib_qp_init_attr *init_attr)
472 {
473 struct irdma_dma_mem *mem = &iwqp->kqp.dma_mem;
474 u32 size;
475 int status;
476 struct irdma_qp_uk_init_info *ukinfo = &info->qp_uk_init_info;
477
478 status = irdma_uk_calc_depth_shift_sq(ukinfo, &ukinfo->sq_depth,
479 &ukinfo->sq_shift);
480 if (status)
481 return status;
482
483 status = irdma_uk_calc_depth_shift_rq(ukinfo, &ukinfo->rq_depth,
484 &ukinfo->rq_shift);
485 if (status)
486 return status;
487
488 iwqp->kqp.sq_wrid_mem =
489 kcalloc(ukinfo->sq_depth, sizeof(*iwqp->kqp.sq_wrid_mem), GFP_KERNEL);
490 if (!iwqp->kqp.sq_wrid_mem)
491 return -ENOMEM;
492
493 iwqp->kqp.rq_wrid_mem =
494 kcalloc(ukinfo->rq_depth, sizeof(*iwqp->kqp.rq_wrid_mem), GFP_KERNEL);
495 if (!iwqp->kqp.rq_wrid_mem) {
496 kfree(iwqp->kqp.sq_wrid_mem);
497 iwqp->kqp.sq_wrid_mem = NULL;
498 return -ENOMEM;
499 }
500
501 iwqp->kqp.sig_trk_mem = kcalloc(ukinfo->sq_depth, sizeof(u32), GFP_KERNEL);
502 memset(iwqp->kqp.sig_trk_mem, 0, ukinfo->sq_depth * sizeof(u32));
503 if (!iwqp->kqp.sig_trk_mem) {
504 kfree(iwqp->kqp.sq_wrid_mem);
505 iwqp->kqp.sq_wrid_mem = NULL;
506 kfree(iwqp->kqp.rq_wrid_mem);
507 iwqp->kqp.rq_wrid_mem = NULL;
508 return -ENOMEM;
509 }
510 ukinfo->sq_sigwrtrk_array = (void *)iwqp->kqp.sig_trk_mem;
511 ukinfo->sq_wrtrk_array = iwqp->kqp.sq_wrid_mem;
512 ukinfo->rq_wrid_array = iwqp->kqp.rq_wrid_mem;
513
514 size = (ukinfo->sq_depth + ukinfo->rq_depth) * IRDMA_QP_WQE_MIN_SIZE;
515 size += (IRDMA_SHADOW_AREA_SIZE << 3);
516
517 mem->size = size;
518 mem->va = irdma_allocate_dma_mem(&iwdev->rf->hw, mem, mem->size,
519 256);
520 if (!mem->va) {
521 kfree(iwqp->kqp.sq_wrid_mem);
522 iwqp->kqp.sq_wrid_mem = NULL;
523 kfree(iwqp->kqp.rq_wrid_mem);
524 iwqp->kqp.rq_wrid_mem = NULL;
525 return -ENOMEM;
526 }
527
528 ukinfo->sq = mem->va;
529 info->sq_pa = mem->pa;
530 ukinfo->rq = &ukinfo->sq[ukinfo->sq_depth];
531 info->rq_pa = info->sq_pa + (ukinfo->sq_depth * IRDMA_QP_WQE_MIN_SIZE);
532 ukinfo->shadow_area = ukinfo->rq[ukinfo->rq_depth].elem;
533 info->shadow_area_pa = info->rq_pa + (ukinfo->rq_depth * IRDMA_QP_WQE_MIN_SIZE);
534 ukinfo->sq_size = ukinfo->sq_depth >> ukinfo->sq_shift;
535 ukinfo->rq_size = ukinfo->rq_depth >> ukinfo->rq_shift;
536
537 iwqp->max_send_wr = (ukinfo->sq_depth - IRDMA_SQ_RSVD) >> ukinfo->sq_shift;
538 iwqp->max_recv_wr = (ukinfo->rq_depth - IRDMA_RQ_RSVD) >> ukinfo->rq_shift;
539 init_attr->cap.max_send_wr = iwqp->max_send_wr;
540 init_attr->cap.max_recv_wr = iwqp->max_recv_wr;
541
542 return 0;
543 }
544
545 int
irdma_cqp_create_qp_cmd(struct irdma_qp * iwqp)546 irdma_cqp_create_qp_cmd(struct irdma_qp *iwqp)
547 {
548 struct irdma_pci_f *rf = iwqp->iwdev->rf;
549 struct irdma_cqp_request *cqp_request;
550 struct cqp_cmds_info *cqp_info;
551 struct irdma_create_qp_info *qp_info;
552 int status;
553
554 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true);
555 if (!cqp_request)
556 return -ENOMEM;
557
558 cqp_info = &cqp_request->info;
559 qp_info = &cqp_request->info.in.u.qp_create.info;
560 qp_info->mac_valid = true;
561 qp_info->cq_num_valid = true;
562 qp_info->next_iwarp_state = IRDMA_QP_STATE_IDLE;
563
564 cqp_info->cqp_cmd = IRDMA_OP_QP_CREATE;
565 cqp_info->post_sq = 1;
566 cqp_info->in.u.qp_create.qp = &iwqp->sc_qp;
567 cqp_info->in.u.qp_create.scratch = (uintptr_t)cqp_request;
568 cqp_info->create = true;
569 status = irdma_handle_cqp_op(rf, cqp_request);
570 irdma_put_cqp_request(&rf->cqp, cqp_request);
571
572 return status;
573 }
574
575 void
irdma_roce_fill_and_set_qpctx_info(struct irdma_qp * iwqp,struct irdma_qp_host_ctx_info * ctx_info)576 irdma_roce_fill_and_set_qpctx_info(struct irdma_qp *iwqp,
577 struct irdma_qp_host_ctx_info *ctx_info)
578 {
579 struct irdma_device *iwdev = iwqp->iwdev;
580 struct irdma_sc_dev *dev = &iwdev->rf->sc_dev;
581 struct irdma_roce_offload_info *roce_info;
582 struct irdma_udp_offload_info *udp_info;
583
584 udp_info = &iwqp->udp_info;
585 udp_info->snd_mss = ib_mtu_enum_to_int(iboe_get_mtu(iwdev->vsi.mtu));
586 udp_info->cwnd = iwdev->roce_cwnd;
587 udp_info->rexmit_thresh = 2;
588 udp_info->rnr_nak_thresh = 2;
589 udp_info->src_port = 0xc000;
590 udp_info->dst_port = ROCE_V2_UDP_DPORT;
591 roce_info = &iwqp->roce_info;
592 ether_addr_copy(roce_info->mac_addr, if_getlladdr(iwdev->netdev));
593
594 roce_info->rd_en = true;
595 roce_info->wr_rdresp_en = true;
596 roce_info->dcqcn_en = false;
597 roce_info->rtomin = iwdev->roce_rtomin;
598
599 roce_info->ack_credits = iwdev->roce_ackcreds;
600 roce_info->ird_size = dev->hw_attrs.max_hw_ird;
601 roce_info->ord_size = dev->hw_attrs.max_hw_ord;
602
603 if (!iwqp->user_mode) {
604 roce_info->priv_mode_en = true;
605 roce_info->fast_reg_en = true;
606 roce_info->udprivcq_en = true;
607 }
608 roce_info->roce_tver = 0;
609
610 ctx_info->roce_info = &iwqp->roce_info;
611 ctx_info->udp_info = &iwqp->udp_info;
612 irdma_sc_qp_setctx_roce(&iwqp->sc_qp, iwqp->host_ctx.va, ctx_info);
613 }
614
615 void
irdma_iw_fill_and_set_qpctx_info(struct irdma_qp * iwqp,struct irdma_qp_host_ctx_info * ctx_info)616 irdma_iw_fill_and_set_qpctx_info(struct irdma_qp *iwqp,
617 struct irdma_qp_host_ctx_info *ctx_info)
618 {
619 struct irdma_device *iwdev = iwqp->iwdev;
620 struct irdma_sc_dev *dev = &iwdev->rf->sc_dev;
621 struct irdma_iwarp_offload_info *iwarp_info;
622
623 iwarp_info = &iwqp->iwarp_info;
624 ether_addr_copy(iwarp_info->mac_addr, if_getlladdr(iwdev->netdev));
625 iwarp_info->rd_en = true;
626 iwarp_info->wr_rdresp_en = true;
627 iwarp_info->ecn_en = true;
628 iwarp_info->rtomin = 5;
629
630 if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2)
631 iwarp_info->ib_rd_en = true;
632 if (!iwqp->user_mode) {
633 iwarp_info->priv_mode_en = true;
634 iwarp_info->fast_reg_en = true;
635 }
636 iwarp_info->ddp_ver = 1;
637 iwarp_info->rdmap_ver = 1;
638
639 ctx_info->iwarp_info = &iwqp->iwarp_info;
640 ctx_info->iwarp_info_valid = true;
641 irdma_sc_qp_setctx(&iwqp->sc_qp, iwqp->host_ctx.va, ctx_info);
642 ctx_info->iwarp_info_valid = false;
643 }
644
645 int
irdma_validate_qp_attrs(struct ib_qp_init_attr * init_attr,struct irdma_device * iwdev)646 irdma_validate_qp_attrs(struct ib_qp_init_attr *init_attr,
647 struct irdma_device *iwdev)
648 {
649 struct irdma_sc_dev *dev = &iwdev->rf->sc_dev;
650 struct irdma_uk_attrs *uk_attrs = &dev->hw_attrs.uk_attrs;
651
652 if (init_attr->create_flags)
653 return -EOPNOTSUPP;
654
655 if (init_attr->cap.max_inline_data > uk_attrs->max_hw_inline ||
656 init_attr->cap.max_send_sge > uk_attrs->max_hw_wq_frags ||
657 init_attr->cap.max_send_wr > uk_attrs->max_hw_wq_quanta ||
658 init_attr->cap.max_recv_wr > uk_attrs->max_hw_rq_quanta ||
659 init_attr->cap.max_recv_sge > uk_attrs->max_hw_wq_frags)
660 return -EINVAL;
661
662 if (rdma_protocol_roce(&iwdev->ibdev, 1)) {
663 if (init_attr->qp_type != IB_QPT_RC &&
664 init_attr->qp_type != IB_QPT_UD &&
665 init_attr->qp_type != IB_QPT_GSI)
666 return -EOPNOTSUPP;
667 } else {
668 if (init_attr->qp_type != IB_QPT_RC)
669 return -EOPNOTSUPP;
670 }
671
672 return 0;
673 }
674
675 void
irdma_sched_qp_flush_work(struct irdma_qp * iwqp)676 irdma_sched_qp_flush_work(struct irdma_qp *iwqp)
677 {
678 unsigned long flags;
679
680 if (iwqp->sc_qp.qp_uk.destroy_pending)
681 return;
682 irdma_qp_add_ref(&iwqp->ibqp);
683 spin_lock_irqsave(&iwqp->dwork_flush_lock, flags);
684 if (mod_delayed_work(iwqp->iwdev->cleanup_wq, &iwqp->dwork_flush,
685 msecs_to_jiffies(IRDMA_FLUSH_DELAY_MS)))
686 irdma_qp_rem_ref(&iwqp->ibqp);
687 spin_unlock_irqrestore(&iwqp->dwork_flush_lock, flags);
688 }
689
690 void
irdma_user_flush_worker(struct work_struct * work)691 irdma_user_flush_worker(struct work_struct *work)
692 {
693 struct delayed_work *dwork = to_delayed_work(work);
694 struct irdma_qp *iwqp = container_of(dwork, struct irdma_qp,
695 dwork_flush);
696
697 /*
698 * Set the WAIT flag to prevent a massive buildup of flush commands in the extreme case of many QPs lingering
699 * in the ERROR state.
700 */
701 irdma_flush_wqes(iwqp, IRDMA_FLUSH_SQ | IRDMA_FLUSH_RQ | IRDMA_REFLUSH |
702 IRDMA_FLUSH_WAIT);
703
704 /* Re-arm continuously. Work is canceled when QP is deleted. */
705 mod_delayed_work(iwqp->iwdev->cleanup_wq, &iwqp->dwork_flush,
706 msecs_to_jiffies(IRDMA_PERIODIC_FLUSH_MS));
707 }
708
709 void
irdma_kern_flush_worker(struct work_struct * work)710 irdma_kern_flush_worker(struct work_struct *work)
711 {
712 struct delayed_work *dwork = to_delayed_work(work);
713 struct irdma_qp *iwqp = container_of(dwork, struct irdma_qp, dwork_flush);
714
715 irdma_generate_flush_completions(iwqp);
716 /* For the add in irdma_sched_qp_flush_work */
717 irdma_qp_rem_ref(&iwqp->ibqp);
718 }
719
720 static int
irdma_get_ib_acc_flags(struct irdma_qp * iwqp)721 irdma_get_ib_acc_flags(struct irdma_qp *iwqp)
722 {
723 int acc_flags = 0;
724
725 if (rdma_protocol_roce(iwqp->ibqp.device, 1)) {
726 if (iwqp->roce_info.wr_rdresp_en) {
727 acc_flags |= IB_ACCESS_LOCAL_WRITE;
728 acc_flags |= IB_ACCESS_REMOTE_WRITE;
729 }
730 if (iwqp->roce_info.rd_en)
731 acc_flags |= IB_ACCESS_REMOTE_READ;
732 } else {
733 if (iwqp->iwarp_info.wr_rdresp_en) {
734 acc_flags |= IB_ACCESS_LOCAL_WRITE;
735 acc_flags |= IB_ACCESS_REMOTE_WRITE;
736 }
737 if (iwqp->iwarp_info.rd_en)
738 acc_flags |= IB_ACCESS_REMOTE_READ;
739 }
740 return acc_flags;
741 }
742
743 /**
744 * irdma_query_qp - query qp attributes
745 * @ibqp: qp pointer
746 * @attr: attributes pointer
747 * @attr_mask: Not used
748 * @init_attr: qp attributes to return
749 */
750 static int
irdma_query_qp(struct ib_qp * ibqp,struct ib_qp_attr * attr,int attr_mask,struct ib_qp_init_attr * init_attr)751 irdma_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
752 int attr_mask, struct ib_qp_init_attr *init_attr)
753 {
754 struct irdma_qp *iwqp = to_iwqp(ibqp);
755 struct irdma_sc_qp *qp = &iwqp->sc_qp;
756
757 memset(attr, 0, sizeof(*attr));
758 memset(init_attr, 0, sizeof(*init_attr));
759
760 attr->qp_state = iwqp->ibqp_state;
761 attr->cur_qp_state = iwqp->ibqp_state;
762 attr->cap.max_send_wr = iwqp->max_send_wr;
763 attr->cap.max_recv_wr = iwqp->max_recv_wr;
764 attr->cap.max_inline_data = qp->qp_uk.max_inline_data;
765 attr->cap.max_send_sge = qp->qp_uk.max_sq_frag_cnt;
766 attr->cap.max_recv_sge = qp->qp_uk.max_rq_frag_cnt;
767 attr->qp_access_flags = irdma_get_ib_acc_flags(iwqp);
768 attr->port_num = 1;
769 if (rdma_protocol_roce(ibqp->device, 1)) {
770 attr->path_mtu = ib_mtu_int_to_enum(iwqp->udp_info.snd_mss);
771 attr->qkey = iwqp->roce_info.qkey;
772 attr->rq_psn = iwqp->udp_info.epsn;
773 attr->sq_psn = iwqp->udp_info.psn_nxt;
774 attr->dest_qp_num = iwqp->roce_info.dest_qp;
775 attr->pkey_index = iwqp->roce_info.p_key;
776 attr->retry_cnt = iwqp->udp_info.rexmit_thresh;
777 attr->rnr_retry = iwqp->udp_info.rnr_nak_thresh;
778 attr->max_rd_atomic = iwqp->roce_info.ord_size;
779 attr->max_dest_rd_atomic = iwqp->roce_info.ird_size;
780 }
781
782 init_attr->event_handler = iwqp->ibqp.event_handler;
783 init_attr->qp_context = iwqp->ibqp.qp_context;
784 init_attr->send_cq = iwqp->ibqp.send_cq;
785 init_attr->recv_cq = iwqp->ibqp.recv_cq;
786 init_attr->cap = attr->cap;
787
788 return 0;
789 }
790
791 static int
irdma_wait_for_suspend(struct irdma_qp * iwqp)792 irdma_wait_for_suspend(struct irdma_qp *iwqp)
793 {
794 if (!wait_event_timeout(iwqp->iwdev->suspend_wq,
795 !iwqp->suspend_pending,
796 msecs_to_jiffies(IRDMA_EVENT_TIMEOUT_MS))) {
797 iwqp->suspend_pending = false;
798 irdma_dev_warn(&iwqp->iwdev->ibdev,
799 "modify_qp timed out waiting for suspend. qp_id = %d, last_ae = 0x%x\n",
800 iwqp->ibqp.qp_num, iwqp->last_aeq);
801 return -EBUSY;
802 }
803
804 return 0;
805 }
806
807 /**
808 * irdma_modify_qp_roce - modify qp request
809 * @ibqp: qp's pointer for modify
810 * @attr: access attributes
811 * @attr_mask: state mask
812 * @udata: user data
813 */
814 int
irdma_modify_qp_roce(struct ib_qp * ibqp,struct ib_qp_attr * attr,int attr_mask,struct ib_udata * udata)815 irdma_modify_qp_roce(struct ib_qp *ibqp, struct ib_qp_attr *attr,
816 int attr_mask, struct ib_udata *udata)
817 {
818 #define IRDMA_MODIFY_QP_MIN_REQ_LEN offsetofend(struct irdma_modify_qp_req, rq_flush)
819 #define IRDMA_MODIFY_QP_MIN_RESP_LEN offsetofend(struct irdma_modify_qp_resp, push_valid)
820 struct irdma_pd *iwpd = to_iwpd(ibqp->pd);
821 struct irdma_qp *iwqp = to_iwqp(ibqp);
822 struct irdma_device *iwdev = iwqp->iwdev;
823 struct irdma_sc_dev *dev = &iwdev->rf->sc_dev;
824 struct irdma_qp_host_ctx_info *ctx_info;
825 struct irdma_roce_offload_info *roce_info;
826 struct irdma_udp_offload_info *udp_info;
827 struct irdma_modify_qp_info info = {0};
828 struct irdma_modify_qp_resp uresp = {};
829 struct irdma_modify_qp_req ureq;
830 unsigned long flags;
831 u8 issue_modify_qp = 0;
832 int ret = 0;
833
834 ctx_info = &iwqp->ctx_info;
835 roce_info = &iwqp->roce_info;
836 udp_info = &iwqp->udp_info;
837
838 if (udata) {
839 if ((udata->inlen && udata->inlen < IRDMA_MODIFY_QP_MIN_REQ_LEN) ||
840 (udata->outlen && udata->outlen < IRDMA_MODIFY_QP_MIN_RESP_LEN))
841 return -EINVAL;
842 }
843
844 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS)
845 return -EOPNOTSUPP;
846
847 if (attr_mask & IB_QP_DEST_QPN)
848 roce_info->dest_qp = attr->dest_qp_num;
849
850 if (attr_mask & IB_QP_PKEY_INDEX) {
851 ret = irdma_query_pkey(ibqp->device, 0, attr->pkey_index,
852 &roce_info->p_key);
853 if (ret)
854 return ret;
855 }
856
857 if (attr_mask & IB_QP_QKEY)
858 roce_info->qkey = attr->qkey;
859
860 if (attr_mask & IB_QP_PATH_MTU)
861 udp_info->snd_mss = ib_mtu_enum_to_int(attr->path_mtu);
862
863 if (attr_mask & IB_QP_SQ_PSN) {
864 udp_info->psn_nxt = attr->sq_psn;
865 udp_info->lsn = 0xffff;
866 udp_info->psn_una = attr->sq_psn;
867 udp_info->psn_max = attr->sq_psn;
868 }
869
870 if (attr_mask & IB_QP_RQ_PSN)
871 udp_info->epsn = attr->rq_psn;
872
873 if (attr_mask & IB_QP_RNR_RETRY)
874 udp_info->rnr_nak_thresh = attr->rnr_retry;
875
876 if (attr_mask & IB_QP_RETRY_CNT)
877 udp_info->rexmit_thresh = attr->retry_cnt;
878
879 ctx_info->roce_info->pd_id = iwpd->sc_pd.pd_id;
880
881 if (attr_mask & IB_QP_AV) {
882 const struct ib_global_route *grh =
883 rdma_ah_read_grh(&attr->ah_attr);
884 struct irdma_av *av = &iwqp->roce_ah.av;
885 u16 vlan_id = VLAN_N_VID;
886 u32 local_ip[4] = {};
887
888 memset(&iwqp->roce_ah, 0, sizeof(iwqp->roce_ah));
889 if (rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH) {
890
891 udp_info->ttl = grh->hop_limit;
892 udp_info->flow_label = grh->flow_label;
893 udp_info->tos = grh->traffic_class;
894
895 udp_info->src_port = kc_rdma_get_udp_sport(udp_info->flow_label,
896 ibqp->qp_num,
897 roce_info->dest_qp);
898
899 irdma_qp_rem_qos(&iwqp->sc_qp);
900 dev->ws_remove(iwqp->sc_qp.vsi, ctx_info->user_pri);
901 if (iwqp->sc_qp.vsi->dscp_mode)
902 ctx_info->user_pri =
903 iwqp->sc_qp.vsi->dscp_map[irdma_tos2dscp(udp_info->tos)];
904 else
905 ctx_info->user_pri = rt_tos2priority(udp_info->tos);
906 }
907 ret = kc_irdma_set_roce_cm_info(iwqp, attr, &vlan_id);
908 if (ret)
909 return ret;
910 if (dev->ws_add(iwqp->sc_qp.vsi, ctx_info->user_pri))
911 return -ENOMEM;
912 iwqp->sc_qp.user_pri = ctx_info->user_pri;
913 irdma_qp_add_qos(&iwqp->sc_qp);
914
915 if (vlan_id >= VLAN_N_VID && iwdev->dcb_vlan_mode)
916 vlan_id = 0;
917 if (vlan_id < VLAN_N_VID) {
918 udp_info->insert_vlan_tag = true;
919 udp_info->vlan_tag = vlan_id |
920 ctx_info->user_pri << VLAN_PRIO_SHIFT;
921 } else {
922 udp_info->insert_vlan_tag = false;
923 }
924
925 av->attrs = attr->ah_attr;
926 rdma_gid2ip((struct sockaddr *)&av->dgid_addr, &grh->dgid);
927 if (av->net_type == RDMA_NETWORK_IPV6) {
928 __be32 *daddr =
929 av->dgid_addr.saddr_in6.sin6_addr.__u6_addr.__u6_addr32;
930 __be32 *saddr =
931 av->sgid_addr.saddr_in6.sin6_addr.__u6_addr.__u6_addr32;
932
933 irdma_copy_ip_ntohl(&udp_info->dest_ip_addr[0], daddr);
934 irdma_copy_ip_ntohl(&udp_info->local_ipaddr[0], saddr);
935
936 udp_info->ipv4 = false;
937 irdma_copy_ip_ntohl(local_ip, daddr);
938 } else if (av->net_type == RDMA_NETWORK_IPV4) {
939 __be32 saddr = av->sgid_addr.saddr_in.sin_addr.s_addr;
940 __be32 daddr = av->dgid_addr.saddr_in.sin_addr.s_addr;
941
942 local_ip[0] = ntohl(daddr);
943
944 udp_info->ipv4 = true;
945 udp_info->dest_ip_addr[0] = 0;
946 udp_info->dest_ip_addr[1] = 0;
947 udp_info->dest_ip_addr[2] = 0;
948 udp_info->dest_ip_addr[3] = local_ip[0];
949
950 udp_info->local_ipaddr[0] = 0;
951 udp_info->local_ipaddr[1] = 0;
952 udp_info->local_ipaddr[2] = 0;
953 udp_info->local_ipaddr[3] = ntohl(saddr);
954 } else {
955 return -EINVAL;
956 }
957 udp_info->arp_idx =
958 irdma_add_arp(iwdev->rf, local_ip,
959 ah_attr_to_dmac(attr->ah_attr));
960 }
961
962 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
963 if (attr->max_rd_atomic > dev->hw_attrs.max_hw_ord) {
964 irdma_dev_err(&iwdev->ibdev,
965 "rd_atomic = %d, above max_hw_ord=%d\n",
966 attr->max_rd_atomic,
967 dev->hw_attrs.max_hw_ord);
968 return -EINVAL;
969 }
970 if (attr->max_rd_atomic)
971 roce_info->ord_size = attr->max_rd_atomic;
972 info.ord_valid = true;
973 }
974
975 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
976 if (attr->max_dest_rd_atomic > dev->hw_attrs.max_hw_ird) {
977 irdma_dev_err(&iwdev->ibdev,
978 "rd_atomic = %d, above max_hw_ird=%d\n",
979 attr->max_rd_atomic,
980 dev->hw_attrs.max_hw_ird);
981 return -EINVAL;
982 }
983 if (attr->max_dest_rd_atomic)
984 roce_info->ird_size = attr->max_dest_rd_atomic;
985 }
986
987 if (attr_mask & IB_QP_ACCESS_FLAGS) {
988 if (attr->qp_access_flags & IB_ACCESS_LOCAL_WRITE)
989 roce_info->wr_rdresp_en = true;
990 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
991 roce_info->wr_rdresp_en = true;
992 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
993 roce_info->rd_en = true;
994 }
995
996 wait_event(iwqp->mod_qp_waitq, !atomic_read(&iwqp->hw_mod_qp_pend));
997
998 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_VERBS,
999 "caller: %pS qp_id=%d to_ibqpstate=%d ibqpstate=%d irdma_qpstate=%d attr_mask=0x%x\n",
1000 __builtin_return_address(0), ibqp->qp_num, attr->qp_state,
1001 iwqp->ibqp_state, iwqp->iwarp_state, attr_mask);
1002
1003 spin_lock_irqsave(&iwqp->lock, flags);
1004 if (attr_mask & IB_QP_STATE) {
1005 if (!ib_modify_qp_is_ok(iwqp->ibqp_state, attr->qp_state,
1006 iwqp->ibqp.qp_type, attr_mask)) {
1007 irdma_dev_warn(&iwdev->ibdev, "modify_qp invalid for qp_id=%d, old_state=0x%x, new_state=0x%x\n",
1008 iwqp->ibqp.qp_num, iwqp->ibqp_state,
1009 attr->qp_state);
1010 ret = -EINVAL;
1011 goto exit;
1012 }
1013 info.curr_iwarp_state = iwqp->iwarp_state;
1014
1015 switch (attr->qp_state) {
1016 case IB_QPS_INIT:
1017 if (iwqp->iwarp_state > IRDMA_QP_STATE_IDLE) {
1018 ret = -EINVAL;
1019 goto exit;
1020 }
1021
1022 if (iwqp->iwarp_state == IRDMA_QP_STATE_INVALID) {
1023 info.next_iwarp_state = IRDMA_QP_STATE_IDLE;
1024 issue_modify_qp = 1;
1025 }
1026 break;
1027 case IB_QPS_RTR:
1028 if (iwqp->iwarp_state > IRDMA_QP_STATE_IDLE) {
1029 ret = -EINVAL;
1030 goto exit;
1031 }
1032 info.arp_cache_idx_valid = true;
1033 info.cq_num_valid = true;
1034 info.next_iwarp_state = IRDMA_QP_STATE_RTR;
1035 issue_modify_qp = 1;
1036 break;
1037 case IB_QPS_RTS:
1038 if (iwqp->ibqp_state < IB_QPS_RTR ||
1039 iwqp->ibqp_state == IB_QPS_ERR) {
1040 ret = -EINVAL;
1041 goto exit;
1042 }
1043
1044 info.arp_cache_idx_valid = true;
1045 info.cq_num_valid = true;
1046 info.ord_valid = true;
1047 info.next_iwarp_state = IRDMA_QP_STATE_RTS;
1048 issue_modify_qp = 1;
1049 if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_2)
1050 iwdev->rf->check_fc(&iwdev->vsi, &iwqp->sc_qp);
1051 udp_info->cwnd = iwdev->roce_cwnd;
1052 roce_info->ack_credits = iwdev->roce_ackcreds;
1053 if (iwdev->push_mode && udata &&
1054 iwqp->sc_qp.push_idx == IRDMA_INVALID_PUSH_PAGE_INDEX) {
1055 spin_unlock_irqrestore(&iwqp->lock, flags);
1056 irdma_alloc_push_page(iwqp);
1057 spin_lock_irqsave(&iwqp->lock, flags);
1058 }
1059 break;
1060 case IB_QPS_SQD:
1061 if (iwqp->iwarp_state == IRDMA_QP_STATE_SQD)
1062 goto exit;
1063
1064 if (iwqp->iwarp_state != IRDMA_QP_STATE_RTS) {
1065 ret = -EINVAL;
1066 goto exit;
1067 }
1068
1069 info.next_iwarp_state = IRDMA_QP_STATE_SQD;
1070 issue_modify_qp = 1;
1071 iwqp->suspend_pending = true;
1072 break;
1073 case IB_QPS_SQE:
1074 case IB_QPS_ERR:
1075 case IB_QPS_RESET:
1076 if (iwqp->iwarp_state == IRDMA_QP_STATE_ERROR) {
1077 spin_unlock_irqrestore(&iwqp->lock, flags);
1078 if (udata && udata->inlen) {
1079 if (ib_copy_from_udata(&ureq, udata,
1080 min(sizeof(ureq), udata->inlen)))
1081 return -EINVAL;
1082
1083 irdma_flush_wqes(iwqp,
1084 (ureq.sq_flush ? IRDMA_FLUSH_SQ : 0) |
1085 (ureq.rq_flush ? IRDMA_FLUSH_RQ : 0) |
1086 IRDMA_REFLUSH);
1087 }
1088 return 0;
1089 }
1090
1091 info.next_iwarp_state = IRDMA_QP_STATE_ERROR;
1092 issue_modify_qp = 1;
1093 break;
1094 default:
1095 ret = -EINVAL;
1096 goto exit;
1097 }
1098
1099 iwqp->ibqp_state = attr->qp_state;
1100 }
1101
1102 ctx_info->send_cq_num = iwqp->iwscq->sc_cq.cq_uk.cq_id;
1103 ctx_info->rcv_cq_num = iwqp->iwrcq->sc_cq.cq_uk.cq_id;
1104 irdma_sc_qp_setctx_roce(&iwqp->sc_qp, iwqp->host_ctx.va, ctx_info);
1105 spin_unlock_irqrestore(&iwqp->lock, flags);
1106
1107 if (attr_mask & IB_QP_STATE) {
1108 if (issue_modify_qp) {
1109 ctx_info->rem_endpoint_idx = udp_info->arp_idx;
1110 if (irdma_hw_modify_qp(iwdev, iwqp, &info, true))
1111 return -EINVAL;
1112 if (info.next_iwarp_state == IRDMA_QP_STATE_SQD) {
1113 ret = irdma_wait_for_suspend(iwqp);
1114 if (ret)
1115 return ret;
1116 }
1117 spin_lock_irqsave(&iwqp->lock, flags);
1118 if (iwqp->iwarp_state == info.curr_iwarp_state) {
1119 iwqp->iwarp_state = info.next_iwarp_state;
1120 iwqp->ibqp_state = attr->qp_state;
1121 iwqp->sc_qp.qp_state = iwqp->iwarp_state;
1122 }
1123 if (iwqp->ibqp_state > IB_QPS_RTS &&
1124 !atomic_read(&iwqp->flush_issued)) {
1125 spin_unlock_irqrestore(&iwqp->lock, flags);
1126 irdma_flush_wqes(iwqp, IRDMA_FLUSH_SQ |
1127 IRDMA_FLUSH_RQ |
1128 IRDMA_FLUSH_WAIT);
1129
1130 } else {
1131 spin_unlock_irqrestore(&iwqp->lock, flags);
1132 }
1133 } else {
1134 iwqp->ibqp_state = attr->qp_state;
1135 }
1136 if (udata && udata->outlen && dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) {
1137 struct irdma_ucontext *ucontext;
1138
1139 ucontext = rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext);
1140 if (iwqp->sc_qp.push_idx != IRDMA_INVALID_PUSH_PAGE_INDEX &&
1141 !iwqp->push_wqe_mmap_entry &&
1142 !irdma_setup_push_mmap_entries(ucontext, iwqp,
1143 &uresp.push_wqe_mmap_key, &uresp.push_db_mmap_key)) {
1144 uresp.push_valid = 1;
1145 uresp.push_offset = iwqp->sc_qp.push_offset;
1146 }
1147 uresp.rd_fence_rate = iwdev->rd_fence_rate;
1148 ret = ib_copy_to_udata(udata, &uresp, min(sizeof(uresp),
1149 udata->outlen));
1150 if (ret) {
1151 irdma_remove_push_mmap_entries(iwqp);
1152 irdma_debug(&iwdev->rf->sc_dev,
1153 IRDMA_DEBUG_VERBS,
1154 "copy_to_udata failed\n");
1155 return ret;
1156 }
1157 }
1158 }
1159
1160 return 0;
1161 exit:
1162 spin_unlock_irqrestore(&iwqp->lock, flags);
1163
1164 return ret;
1165 }
1166
1167 /**
1168 * irdma_modify_qp - modify qp request
1169 * @ibqp: qp's pointer for modify
1170 * @attr: access attributes
1171 * @attr_mask: state mask
1172 * @udata: user data
1173 */
1174 int
irdma_modify_qp(struct ib_qp * ibqp,struct ib_qp_attr * attr,int attr_mask,struct ib_udata * udata)1175 irdma_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask,
1176 struct ib_udata *udata)
1177 {
1178 #define IRDMA_MODIFY_QP_MIN_REQ_LEN offsetofend(struct irdma_modify_qp_req, rq_flush)
1179 #define IRDMA_MODIFY_QP_MIN_RESP_LEN offsetofend(struct irdma_modify_qp_resp, push_valid)
1180 struct irdma_qp *iwqp = to_iwqp(ibqp);
1181 struct irdma_device *iwdev = iwqp->iwdev;
1182 struct irdma_sc_dev *dev = &iwdev->rf->sc_dev;
1183 struct irdma_qp_host_ctx_info *ctx_info;
1184 struct irdma_tcp_offload_info *tcp_info;
1185 struct irdma_iwarp_offload_info *offload_info;
1186 struct irdma_modify_qp_info info = {0};
1187 struct irdma_modify_qp_resp uresp = {};
1188 struct irdma_modify_qp_req ureq = {};
1189 u8 issue_modify_qp = 0;
1190 u8 dont_wait = 0;
1191 int err;
1192 unsigned long flags;
1193
1194 if (udata) {
1195 if ((udata->inlen && udata->inlen < IRDMA_MODIFY_QP_MIN_REQ_LEN) ||
1196 (udata->outlen && udata->outlen < IRDMA_MODIFY_QP_MIN_RESP_LEN))
1197 return -EINVAL;
1198 }
1199
1200 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS)
1201 return -EOPNOTSUPP;
1202
1203 ctx_info = &iwqp->ctx_info;
1204 offload_info = &iwqp->iwarp_info;
1205 tcp_info = &iwqp->tcp_info;
1206 wait_event(iwqp->mod_qp_waitq, !atomic_read(&iwqp->hw_mod_qp_pend));
1207 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_VERBS,
1208 "caller: %pS qp_id=%d to_ibqpstate=%d ibqpstate=%d irdma_qpstate=%d last_aeq=%d hw_tcp_state=%d hw_iwarp_state=%d attr_mask=0x%x\n",
1209 __builtin_return_address(0), ibqp->qp_num, attr->qp_state,
1210 iwqp->ibqp_state, iwqp->iwarp_state, iwqp->last_aeq,
1211 iwqp->hw_tcp_state, iwqp->hw_iwarp_state, attr_mask);
1212
1213 spin_lock_irqsave(&iwqp->lock, flags);
1214 if (attr_mask & IB_QP_STATE) {
1215 info.curr_iwarp_state = iwqp->iwarp_state;
1216 switch (attr->qp_state) {
1217 case IB_QPS_INIT:
1218 case IB_QPS_RTR:
1219 if (iwqp->iwarp_state > IRDMA_QP_STATE_IDLE) {
1220 err = -EINVAL;
1221 goto exit;
1222 }
1223
1224 if (iwqp->iwarp_state == IRDMA_QP_STATE_INVALID) {
1225 info.next_iwarp_state = IRDMA_QP_STATE_IDLE;
1226 issue_modify_qp = 1;
1227 }
1228 if (iwdev->push_mode && udata &&
1229 iwqp->sc_qp.push_idx == IRDMA_INVALID_PUSH_PAGE_INDEX) {
1230 spin_unlock_irqrestore(&iwqp->lock, flags);
1231 irdma_alloc_push_page(iwqp);
1232 spin_lock_irqsave(&iwqp->lock, flags);
1233 }
1234 break;
1235 case IB_QPS_RTS:
1236 if (iwqp->iwarp_state > IRDMA_QP_STATE_RTS ||
1237 !iwqp->cm_id) {
1238 err = -EINVAL;
1239 goto exit;
1240 }
1241
1242 issue_modify_qp = 1;
1243 iwqp->hw_tcp_state = IRDMA_TCP_STATE_ESTABLISHED;
1244 iwqp->hte_added = 1;
1245 info.next_iwarp_state = IRDMA_QP_STATE_RTS;
1246 info.tcp_ctx_valid = true;
1247 info.ord_valid = true;
1248 info.arp_cache_idx_valid = true;
1249 info.cq_num_valid = true;
1250 break;
1251 case IB_QPS_SQD:
1252 if (iwqp->hw_iwarp_state > IRDMA_QP_STATE_RTS) {
1253 err = 0;
1254 goto exit;
1255 }
1256
1257 if (iwqp->iwarp_state == IRDMA_QP_STATE_CLOSING ||
1258 iwqp->iwarp_state < IRDMA_QP_STATE_RTS) {
1259 err = 0;
1260 goto exit;
1261 }
1262
1263 if (iwqp->iwarp_state > IRDMA_QP_STATE_CLOSING) {
1264 err = -EINVAL;
1265 goto exit;
1266 }
1267
1268 info.next_iwarp_state = IRDMA_QP_STATE_CLOSING;
1269 issue_modify_qp = 1;
1270 break;
1271 case IB_QPS_SQE:
1272 if (iwqp->iwarp_state >= IRDMA_QP_STATE_TERMINATE) {
1273 err = -EINVAL;
1274 goto exit;
1275 }
1276
1277 info.next_iwarp_state = IRDMA_QP_STATE_TERMINATE;
1278 issue_modify_qp = 1;
1279 break;
1280 case IB_QPS_ERR:
1281 case IB_QPS_RESET:
1282 if (iwqp->iwarp_state == IRDMA_QP_STATE_ERROR) {
1283 spin_unlock_irqrestore(&iwqp->lock, flags);
1284 if (udata && udata->inlen) {
1285 if (ib_copy_from_udata(&ureq, udata,
1286 min(sizeof(ureq), udata->inlen)))
1287 return -EINVAL;
1288
1289 irdma_flush_wqes(iwqp,
1290 (ureq.sq_flush ? IRDMA_FLUSH_SQ : 0) |
1291 (ureq.rq_flush ? IRDMA_FLUSH_RQ : 0) |
1292 IRDMA_REFLUSH);
1293 }
1294 return 0;
1295 }
1296
1297 if (iwqp->sc_qp.term_flags) {
1298 spin_unlock_irqrestore(&iwqp->lock, flags);
1299 irdma_terminate_del_timer(&iwqp->sc_qp);
1300 spin_lock_irqsave(&iwqp->lock, flags);
1301 }
1302 info.next_iwarp_state = IRDMA_QP_STATE_ERROR;
1303 if (iwqp->hw_tcp_state > IRDMA_TCP_STATE_CLOSED &&
1304 iwdev->iw_status &&
1305 iwqp->hw_tcp_state != IRDMA_TCP_STATE_TIME_WAIT)
1306 info.reset_tcp_conn = true;
1307 else
1308 dont_wait = 1;
1309
1310 issue_modify_qp = 1;
1311 info.next_iwarp_state = IRDMA_QP_STATE_ERROR;
1312 break;
1313 default:
1314 err = -EINVAL;
1315 goto exit;
1316 }
1317
1318 iwqp->ibqp_state = attr->qp_state;
1319 }
1320 if (attr_mask & IB_QP_ACCESS_FLAGS) {
1321 ctx_info->iwarp_info_valid = true;
1322 if (attr->qp_access_flags & IB_ACCESS_LOCAL_WRITE)
1323 offload_info->wr_rdresp_en = true;
1324 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
1325 offload_info->wr_rdresp_en = true;
1326 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
1327 offload_info->rd_en = true;
1328 }
1329
1330 if (ctx_info->iwarp_info_valid) {
1331 ctx_info->send_cq_num = iwqp->iwscq->sc_cq.cq_uk.cq_id;
1332 ctx_info->rcv_cq_num = iwqp->iwrcq->sc_cq.cq_uk.cq_id;
1333 irdma_sc_qp_setctx(&iwqp->sc_qp, iwqp->host_ctx.va, ctx_info);
1334 }
1335 spin_unlock_irqrestore(&iwqp->lock, flags);
1336
1337 if (attr_mask & IB_QP_STATE) {
1338 if (issue_modify_qp) {
1339 ctx_info->rem_endpoint_idx = tcp_info->arp_idx;
1340 if (irdma_hw_modify_qp(iwdev, iwqp, &info, true))
1341 return -EINVAL;
1342 }
1343
1344 spin_lock_irqsave(&iwqp->lock, flags);
1345 if (iwqp->iwarp_state == info.curr_iwarp_state) {
1346 iwqp->iwarp_state = info.next_iwarp_state;
1347 iwqp->ibqp_state = attr->qp_state;
1348 iwqp->sc_qp.qp_state = iwqp->iwarp_state;
1349 }
1350 spin_unlock_irqrestore(&iwqp->lock, flags);
1351 }
1352
1353 if (issue_modify_qp && iwqp->ibqp_state > IB_QPS_RTS) {
1354 if (dont_wait) {
1355 if (iwqp->hw_tcp_state) {
1356 spin_lock_irqsave(&iwqp->lock, flags);
1357 iwqp->hw_tcp_state = IRDMA_TCP_STATE_CLOSED;
1358 iwqp->last_aeq = IRDMA_AE_RESET_SENT;
1359 spin_unlock_irqrestore(&iwqp->lock, flags);
1360 }
1361 irdma_cm_disconn(iwqp);
1362 } else {
1363 int close_timer_started;
1364
1365 spin_lock_irqsave(&iwdev->cm_core.ht_lock, flags);
1366
1367 if (iwqp->cm_node) {
1368 irdma_add_ref_cmnode(iwqp->cm_node);
1369 spin_unlock_irqrestore(&iwdev->cm_core.ht_lock, flags);
1370 close_timer_started = atomic_inc_return(&iwqp->close_timer_started);
1371 if (iwqp->cm_id && close_timer_started == 1)
1372 irdma_schedule_cm_timer(iwqp->cm_node,
1373 (struct irdma_puda_buf *)iwqp,
1374 IRDMA_TIMER_TYPE_CLOSE, 1, 0);
1375
1376 irdma_rem_ref_cmnode(iwqp->cm_node);
1377 } else {
1378 spin_unlock_irqrestore(&iwdev->cm_core.ht_lock, flags);
1379 }
1380 }
1381 }
1382 if (attr_mask & IB_QP_STATE && udata && udata->outlen &&
1383 dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) {
1384 struct irdma_ucontext *ucontext;
1385
1386 ucontext = rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext);
1387 if (iwqp->sc_qp.push_idx != IRDMA_INVALID_PUSH_PAGE_INDEX &&
1388 !iwqp->push_wqe_mmap_entry &&
1389 !irdma_setup_push_mmap_entries(ucontext, iwqp,
1390 &uresp.push_wqe_mmap_key, &uresp.push_db_mmap_key)) {
1391 uresp.push_valid = 1;
1392 uresp.push_offset = iwqp->sc_qp.push_offset;
1393 }
1394 uresp.rd_fence_rate = iwdev->rd_fence_rate;
1395
1396 err = ib_copy_to_udata(udata, &uresp, min(sizeof(uresp),
1397 udata->outlen));
1398 if (err) {
1399 irdma_remove_push_mmap_entries(iwqp);
1400 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_VERBS,
1401 "copy_to_udata failed\n");
1402 return err;
1403 }
1404 }
1405
1406 return 0;
1407 exit:
1408 spin_unlock_irqrestore(&iwqp->lock, flags);
1409
1410 return err;
1411 }
1412
1413 /**
1414 * irdma_cq_free_rsrc - free up resources for cq
1415 * @rf: RDMA PCI function
1416 * @iwcq: cq ptr
1417 */
1418 void
irdma_cq_free_rsrc(struct irdma_pci_f * rf,struct irdma_cq * iwcq)1419 irdma_cq_free_rsrc(struct irdma_pci_f *rf, struct irdma_cq *iwcq)
1420 {
1421 struct irdma_sc_cq *cq = &iwcq->sc_cq;
1422
1423 if (!iwcq->user_mode) {
1424 irdma_free_dma_mem(rf->sc_dev.hw, &iwcq->kmem);
1425 irdma_free_dma_mem(rf->sc_dev.hw, &iwcq->kmem_shadow);
1426 }
1427
1428 irdma_free_rsrc(rf, rf->allocated_cqs, cq->cq_uk.cq_id);
1429 }
1430
1431 /**
1432 * irdma_free_cqbuf - worker to free a cq buffer
1433 * @work: provides access to the cq buffer to free
1434 */
1435 static void
irdma_free_cqbuf(struct work_struct * work)1436 irdma_free_cqbuf(struct work_struct *work)
1437 {
1438 struct irdma_cq_buf *cq_buf = container_of(work, struct irdma_cq_buf, work);
1439
1440 irdma_free_dma_mem(cq_buf->hw, &cq_buf->kmem_buf);
1441 kfree(cq_buf);
1442 }
1443
1444 /**
1445 * irdma_process_resize_list - remove resized cq buffers from the resize_list
1446 * @iwcq: cq which owns the resize_list
1447 * @iwdev: irdma device
1448 * @lcqe_buf: the buffer where the last cqe is received
1449 */
1450 int
irdma_process_resize_list(struct irdma_cq * iwcq,struct irdma_device * iwdev,struct irdma_cq_buf * lcqe_buf)1451 irdma_process_resize_list(struct irdma_cq *iwcq,
1452 struct irdma_device *iwdev,
1453 struct irdma_cq_buf *lcqe_buf)
1454 {
1455 struct list_head *tmp_node, *list_node;
1456 struct irdma_cq_buf *cq_buf;
1457 int cnt = 0;
1458
1459 list_for_each_safe(list_node, tmp_node, &iwcq->resize_list) {
1460 cq_buf = list_entry(list_node, struct irdma_cq_buf, list);
1461 if (cq_buf == lcqe_buf)
1462 return cnt;
1463
1464 list_del(&cq_buf->list);
1465 queue_work(iwdev->cleanup_wq, &cq_buf->work);
1466 cnt++;
1467 }
1468
1469 return cnt;
1470 }
1471
1472 /**
1473 * irdma_resize_cq - resize cq
1474 * @ibcq: cq to be resized
1475 * @entries: desired cq size
1476 * @udata: user data
1477 */
1478 static int
irdma_resize_cq(struct ib_cq * ibcq,int entries,struct ib_udata * udata)1479 irdma_resize_cq(struct ib_cq *ibcq, int entries,
1480 struct ib_udata *udata)
1481 {
1482 #define IRDMA_RESIZE_CQ_MIN_REQ_LEN offsetofend(struct irdma_resize_cq_req, user_cq_buffer)
1483 struct irdma_cq *iwcq = to_iwcq(ibcq);
1484 struct irdma_sc_dev *dev = iwcq->sc_cq.dev;
1485 struct irdma_cqp_request *cqp_request;
1486 struct cqp_cmds_info *cqp_info;
1487 struct irdma_modify_cq_info *m_info;
1488 struct irdma_modify_cq_info info = {0};
1489 struct irdma_dma_mem kmem_buf;
1490 struct irdma_cq_mr *cqmr_buf;
1491 struct irdma_pbl *iwpbl_buf;
1492 struct irdma_device *iwdev;
1493 struct irdma_pci_f *rf;
1494 struct irdma_cq_buf *cq_buf = NULL;
1495 unsigned long flags;
1496 int ret;
1497
1498 iwdev = to_iwdev(ibcq->device);
1499 rf = iwdev->rf;
1500
1501 if (!(rf->sc_dev.hw_attrs.uk_attrs.feature_flags &
1502 IRDMA_FEATURE_CQ_RESIZE))
1503 return -EOPNOTSUPP;
1504
1505 if (udata && udata->inlen < IRDMA_RESIZE_CQ_MIN_REQ_LEN)
1506 return -EINVAL;
1507
1508 if (entries > rf->max_cqe)
1509 return -EINVAL;
1510
1511 if (!iwcq->user_mode) {
1512 entries++;
1513 if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_2)
1514 entries *= 2;
1515 }
1516
1517 info.cq_size = max_t(int, entries, 4);
1518
1519 if (info.cq_size == iwcq->sc_cq.cq_uk.cq_size - 1)
1520 return 0;
1521
1522 if (udata) {
1523 struct irdma_resize_cq_req req = {};
1524 struct irdma_ucontext *ucontext =
1525 rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext);
1526
1527 /* CQ resize not supported with legacy GEN_1 libi40iw */
1528 if (ucontext->legacy_mode)
1529 return -EOPNOTSUPP;
1530
1531 if (ib_copy_from_udata(&req, udata,
1532 min(sizeof(req), udata->inlen)))
1533 return -EINVAL;
1534
1535 spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
1536 iwpbl_buf = irdma_get_pbl((unsigned long)req.user_cq_buffer,
1537 &ucontext->cq_reg_mem_list);
1538 spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
1539
1540 if (!iwpbl_buf)
1541 return -ENOMEM;
1542
1543 cqmr_buf = &iwpbl_buf->cq_mr;
1544 if (iwpbl_buf->pbl_allocated) {
1545 info.virtual_map = true;
1546 info.pbl_chunk_size = 1;
1547 info.first_pm_pbl_idx = cqmr_buf->cq_pbl.idx;
1548 } else {
1549 info.cq_pa = cqmr_buf->cq_pbl.addr;
1550 }
1551 } else {
1552 /* Kmode CQ resize */
1553 int rsize;
1554
1555 rsize = info.cq_size * sizeof(struct irdma_cqe);
1556 kmem_buf.size = round_up(rsize, 256);
1557 kmem_buf.va = irdma_allocate_dma_mem(dev->hw, &kmem_buf,
1558 kmem_buf.size, 256);
1559 if (!kmem_buf.va)
1560 return -ENOMEM;
1561
1562 info.cq_base = kmem_buf.va;
1563 info.cq_pa = kmem_buf.pa;
1564 cq_buf = kzalloc(sizeof(*cq_buf), GFP_KERNEL);
1565 if (!cq_buf) {
1566 ret = -ENOMEM;
1567 goto error;
1568 }
1569 }
1570
1571 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true);
1572 if (!cqp_request) {
1573 ret = -ENOMEM;
1574 goto error;
1575 }
1576
1577 info.shadow_read_threshold = iwcq->sc_cq.shadow_read_threshold;
1578 info.cq_resize = true;
1579
1580 cqp_info = &cqp_request->info;
1581 m_info = &cqp_info->in.u.cq_modify.info;
1582 memcpy(m_info, &info, sizeof(*m_info));
1583
1584 cqp_info->cqp_cmd = IRDMA_OP_CQ_MODIFY;
1585 cqp_info->in.u.cq_modify.cq = &iwcq->sc_cq;
1586 cqp_info->in.u.cq_modify.scratch = (uintptr_t)cqp_request;
1587 cqp_info->post_sq = 1;
1588 cqp_info->create = true;
1589 ret = irdma_handle_cqp_op(rf, cqp_request);
1590 irdma_put_cqp_request(&rf->cqp, cqp_request);
1591 if (ret)
1592 goto error;
1593
1594 spin_lock_irqsave(&iwcq->lock, flags);
1595 if (cq_buf) {
1596 cq_buf->kmem_buf = iwcq->kmem;
1597 cq_buf->hw = dev->hw;
1598 memcpy(&cq_buf->cq_uk, &iwcq->sc_cq.cq_uk, sizeof(cq_buf->cq_uk));
1599 INIT_WORK(&cq_buf->work, irdma_free_cqbuf);
1600 list_add_tail(&cq_buf->list, &iwcq->resize_list);
1601 iwcq->kmem = kmem_buf;
1602 }
1603
1604 irdma_sc_cq_resize(&iwcq->sc_cq, &info);
1605 ibcq->cqe = info.cq_size - 1;
1606 spin_unlock_irqrestore(&iwcq->lock, flags);
1607
1608 return 0;
1609 error:
1610 if (!udata)
1611 irdma_free_dma_mem(dev->hw, &kmem_buf);
1612 kfree(cq_buf);
1613
1614 return ret;
1615 }
1616
1617 /**
1618 * irdma_get_mr_access - get hw MR access permissions from IB access flags
1619 * @access: IB access flags
1620 * @hw_rev: Hardware version
1621 */
irdma_get_mr_access(int access,u8 hw_rev)1622 static inline u16 irdma_get_mr_access(int access, u8 hw_rev)
1623 {
1624 u16 hw_access = 0;
1625
1626 hw_access |= (access & IB_ACCESS_LOCAL_WRITE) ?
1627 IRDMA_ACCESS_FLAGS_LOCALWRITE : 0;
1628 hw_access |= (access & IB_ACCESS_REMOTE_WRITE) ?
1629 IRDMA_ACCESS_FLAGS_REMOTEWRITE : 0;
1630 hw_access |= (access & IB_ACCESS_REMOTE_READ) ?
1631 IRDMA_ACCESS_FLAGS_REMOTEREAD : 0;
1632 hw_access |= (access & IB_ZERO_BASED) ?
1633 IRDMA_ACCESS_FLAGS_ZERO_BASED : 0;
1634 hw_access |= IRDMA_ACCESS_FLAGS_LOCALREAD;
1635
1636 return hw_access;
1637 }
1638
1639 /**
1640 * irdma_free_stag - free stag resource
1641 * @iwdev: irdma device
1642 * @stag: stag to free
1643 */
1644 void
irdma_free_stag(struct irdma_device * iwdev,u32 stag)1645 irdma_free_stag(struct irdma_device *iwdev, u32 stag)
1646 {
1647 u32 stag_idx;
1648
1649 stag_idx = (stag & iwdev->rf->mr_stagmask) >> IRDMA_CQPSQ_STAG_IDX_S;
1650 irdma_free_rsrc(iwdev->rf, iwdev->rf->allocated_mrs, stag_idx);
1651 }
1652
1653 /**
1654 * irdma_create_stag - create random stag
1655 * @iwdev: irdma device
1656 */
1657 u32
irdma_create_stag(struct irdma_device * iwdev)1658 irdma_create_stag(struct irdma_device *iwdev)
1659 {
1660 u32 stag;
1661 u32 stag_index = 0;
1662 u32 next_stag_index;
1663 u32 driver_key;
1664 u32 random;
1665 u8 consumer_key;
1666 int ret;
1667
1668 get_random_bytes(&random, sizeof(random));
1669 consumer_key = (u8)random;
1670
1671 driver_key = random & ~iwdev->rf->mr_stagmask;
1672 next_stag_index = (random & iwdev->rf->mr_stagmask) >> 8;
1673 next_stag_index %= iwdev->rf->max_mr;
1674
1675 ret = irdma_alloc_rsrc(iwdev->rf, iwdev->rf->allocated_mrs,
1676 iwdev->rf->max_mr, &stag_index,
1677 &next_stag_index);
1678 if (ret)
1679 return 0;
1680 stag = stag_index << IRDMA_CQPSQ_STAG_IDX_S;
1681 stag |= driver_key;
1682 stag += (u32)consumer_key;
1683
1684 return stag;
1685 }
1686
1687 /**
1688 * irdma_check_mem_contiguous - check if pbls stored in arr are contiguous
1689 * @arr: lvl1 pbl array
1690 * @npages: page count
1691 * @pg_size: page size
1692 *
1693 */
1694 static bool
irdma_check_mem_contiguous(u64 * arr,u32 npages,u32 pg_size)1695 irdma_check_mem_contiguous(u64 *arr, u32 npages, u32 pg_size)
1696 {
1697 u32 pg_idx;
1698
1699 for (pg_idx = 0; pg_idx < npages; pg_idx++) {
1700 if ((*arr + ((u64)pg_size * pg_idx)) != arr[pg_idx])
1701 return false;
1702 }
1703
1704 return true;
1705 }
1706
1707 /**
1708 * irdma_check_mr_contiguous - check if MR is physically contiguous
1709 * @palloc: pbl allocation struct
1710 * @pg_size: page size
1711 */
1712 static bool
irdma_check_mr_contiguous(struct irdma_pble_alloc * palloc,u32 pg_size)1713 irdma_check_mr_contiguous(struct irdma_pble_alloc *palloc,
1714 u32 pg_size)
1715 {
1716 struct irdma_pble_level2 *lvl2 = &palloc->level2;
1717 struct irdma_pble_info *leaf = lvl2->leaf;
1718 u64 *arr = NULL;
1719 u64 *start_addr = NULL;
1720 int i;
1721 bool ret;
1722
1723 if (palloc->level == PBLE_LEVEL_1) {
1724 arr = palloc->level1.addr;
1725 ret = irdma_check_mem_contiguous(arr, palloc->total_cnt,
1726 pg_size);
1727 return ret;
1728 }
1729
1730 start_addr = leaf->addr;
1731
1732 for (i = 0; i < lvl2->leaf_cnt; i++, leaf++) {
1733 arr = leaf->addr;
1734 if ((*start_addr + (i * pg_size * PBLE_PER_PAGE)) != *arr)
1735 return false;
1736 ret = irdma_check_mem_contiguous(arr, leaf->cnt, pg_size);
1737 if (!ret)
1738 return false;
1739 }
1740
1741 return true;
1742 }
1743
1744 /**
1745 * irdma_setup_pbles - copy user pg address to pble's
1746 * @rf: RDMA PCI function
1747 * @iwmr: mr pointer for this memory registration
1748 * @lvl: requested pble levels
1749 */
1750 static int
irdma_setup_pbles(struct irdma_pci_f * rf,struct irdma_mr * iwmr,u8 lvl)1751 irdma_setup_pbles(struct irdma_pci_f *rf, struct irdma_mr *iwmr,
1752 u8 lvl)
1753 {
1754 struct irdma_pbl *iwpbl = &iwmr->iwpbl;
1755 struct irdma_pble_alloc *palloc = &iwpbl->pble_alloc;
1756 struct irdma_pble_info *pinfo;
1757 u64 *pbl;
1758 int status;
1759 enum irdma_pble_level level = PBLE_LEVEL_1;
1760
1761 if (lvl) {
1762 status = irdma_get_pble(rf->pble_rsrc, palloc, iwmr->page_cnt,
1763 lvl);
1764 if (status)
1765 return status;
1766
1767 iwpbl->pbl_allocated = true;
1768 level = palloc->level;
1769 pinfo = (level == PBLE_LEVEL_1) ? &palloc->level1 :
1770 palloc->level2.leaf;
1771 pbl = pinfo->addr;
1772 } else {
1773 pbl = iwmr->pgaddrmem;
1774 }
1775
1776 irdma_copy_user_pgaddrs(iwmr, pbl, level);
1777
1778 if (lvl)
1779 iwmr->pgaddrmem[0] = *pbl;
1780
1781 return 0;
1782 }
1783
1784 /**
1785 * irdma_handle_q_mem - handle memory for qp and cq
1786 * @iwdev: irdma device
1787 * @req: information for q memory management
1788 * @iwpbl: pble struct
1789 * @lvl: pble level mask
1790 */
1791 static int
irdma_handle_q_mem(struct irdma_device * iwdev,struct irdma_mem_reg_req * req,struct irdma_pbl * iwpbl,u8 lvl)1792 irdma_handle_q_mem(struct irdma_device *iwdev,
1793 struct irdma_mem_reg_req *req,
1794 struct irdma_pbl *iwpbl, u8 lvl)
1795 {
1796 struct irdma_pble_alloc *palloc = &iwpbl->pble_alloc;
1797 struct irdma_mr *iwmr = iwpbl->iwmr;
1798 struct irdma_qp_mr *qpmr = &iwpbl->qp_mr;
1799 struct irdma_cq_mr *cqmr = &iwpbl->cq_mr;
1800 struct irdma_hmc_pble *hmc_p;
1801 u64 *arr = iwmr->pgaddrmem;
1802 u32 pg_size, total;
1803 int err = 0;
1804 bool ret = true;
1805
1806 pg_size = iwmr->page_size;
1807 err = irdma_setup_pbles(iwdev->rf, iwmr, lvl);
1808 if (err)
1809 return err;
1810
1811 if (lvl)
1812 arr = palloc->level1.addr;
1813
1814 switch (iwmr->type) {
1815 case IRDMA_MEMREG_TYPE_QP:
1816 total = req->sq_pages + req->rq_pages;
1817 hmc_p = &qpmr->sq_pbl;
1818 qpmr->shadow = (dma_addr_t) arr[total];
1819 if (lvl) {
1820 ret = irdma_check_mem_contiguous(arr, req->sq_pages,
1821 pg_size);
1822 if (ret)
1823 ret = irdma_check_mem_contiguous(&arr[req->sq_pages],
1824 req->rq_pages,
1825 pg_size);
1826 }
1827
1828 if (!ret) {
1829 hmc_p->idx = palloc->level1.idx;
1830 hmc_p = &qpmr->rq_pbl;
1831 hmc_p->idx = palloc->level1.idx + req->sq_pages;
1832 } else {
1833 hmc_p->addr = arr[0];
1834 hmc_p = &qpmr->rq_pbl;
1835 hmc_p->addr = arr[req->sq_pages];
1836 }
1837 break;
1838 case IRDMA_MEMREG_TYPE_CQ:
1839 hmc_p = &cqmr->cq_pbl;
1840
1841 if (!cqmr->split)
1842 cqmr->shadow = (dma_addr_t) arr[req->cq_pages];
1843
1844 if (lvl)
1845 ret = irdma_check_mem_contiguous(arr, req->cq_pages,
1846 pg_size);
1847
1848 if (!ret)
1849 hmc_p->idx = palloc->level1.idx;
1850 else
1851 hmc_p->addr = arr[0];
1852 break;
1853 default:
1854 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_VERBS, "MR type error\n");
1855 err = -EINVAL;
1856 }
1857
1858 if (lvl && ret) {
1859 irdma_free_pble(iwdev->rf->pble_rsrc, palloc);
1860 iwpbl->pbl_allocated = false;
1861 }
1862
1863 return err;
1864 }
1865
1866 /**
1867 * irdma_hw_alloc_mw - create the hw memory window
1868 * @iwdev: irdma device
1869 * @iwmr: pointer to memory window info
1870 */
1871 int
irdma_hw_alloc_mw(struct irdma_device * iwdev,struct irdma_mr * iwmr)1872 irdma_hw_alloc_mw(struct irdma_device *iwdev, struct irdma_mr *iwmr)
1873 {
1874 struct irdma_mw_alloc_info *info;
1875 struct irdma_pd *iwpd = to_iwpd(iwmr->ibmr.pd);
1876 struct irdma_cqp_request *cqp_request;
1877 struct cqp_cmds_info *cqp_info;
1878 int status;
1879
1880 cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true);
1881 if (!cqp_request)
1882 return -ENOMEM;
1883
1884 cqp_info = &cqp_request->info;
1885 info = &cqp_info->in.u.mw_alloc.info;
1886 if (iwmr->ibmw.type == IB_MW_TYPE_1)
1887 info->mw_wide = true;
1888
1889 info->page_size = PAGE_SIZE;
1890 info->mw_stag_index = iwmr->stag >> IRDMA_CQPSQ_STAG_IDX_S;
1891 info->pd_id = iwpd->sc_pd.pd_id;
1892 info->remote_access = true;
1893 cqp_info->cqp_cmd = IRDMA_OP_MW_ALLOC;
1894 cqp_info->post_sq = 1;
1895 cqp_info->in.u.mw_alloc.dev = &iwdev->rf->sc_dev;
1896 cqp_info->in.u.mw_alloc.scratch = (uintptr_t)cqp_request;
1897 cqp_info->create = true;
1898 status = irdma_handle_cqp_op(iwdev->rf, cqp_request);
1899 irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request);
1900
1901 return status;
1902 }
1903
1904 /**
1905 * irdma_hw_alloc_stag - cqp command to allocate stag
1906 * @iwdev: irdma device
1907 * @iwmr: irdma mr pointer
1908 */
1909 int
irdma_hw_alloc_stag(struct irdma_device * iwdev,struct irdma_mr * iwmr)1910 irdma_hw_alloc_stag(struct irdma_device *iwdev,
1911 struct irdma_mr *iwmr)
1912 {
1913 struct irdma_allocate_stag_info *info;
1914 struct ib_pd *pd = iwmr->ibmr.pd;
1915 struct irdma_pd *iwpd = to_iwpd(pd);
1916 struct irdma_cqp_request *cqp_request;
1917 struct cqp_cmds_info *cqp_info;
1918 int status;
1919
1920 cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true);
1921 if (!cqp_request)
1922 return -ENOMEM;
1923
1924 cqp_info = &cqp_request->info;
1925 info = &cqp_info->in.u.alloc_stag.info;
1926 info->page_size = PAGE_SIZE;
1927 info->stag_idx = iwmr->stag >> IRDMA_CQPSQ_STAG_IDX_S;
1928 info->pd_id = iwpd->sc_pd.pd_id;
1929 info->total_len = iwmr->len;
1930 info->all_memory = (pd->flags & IB_PD_UNSAFE_GLOBAL_RKEY) ? true : false;
1931 info->remote_access = true;
1932 cqp_info->cqp_cmd = IRDMA_OP_ALLOC_STAG;
1933 cqp_info->post_sq = 1;
1934 cqp_info->in.u.alloc_stag.dev = &iwdev->rf->sc_dev;
1935 cqp_info->in.u.alloc_stag.scratch = (uintptr_t)cqp_request;
1936 cqp_info->create = true;
1937 status = irdma_handle_cqp_op(iwdev->rf, cqp_request);
1938 irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request);
1939 if (!status)
1940 iwmr->is_hwreg = 1;
1941
1942 return status;
1943 }
1944
1945 /**
1946 * irdma_set_page - populate pbl list for fmr
1947 * @ibmr: ib mem to access iwarp mr pointer
1948 * @addr: page dma address fro pbl list
1949 */
1950 static int
irdma_set_page(struct ib_mr * ibmr,u64 addr)1951 irdma_set_page(struct ib_mr *ibmr, u64 addr)
1952 {
1953 struct irdma_mr *iwmr = to_iwmr(ibmr);
1954 struct irdma_pbl *iwpbl = &iwmr->iwpbl;
1955 struct irdma_pble_alloc *palloc = &iwpbl->pble_alloc;
1956 u64 *pbl;
1957
1958 if (unlikely(iwmr->npages == iwmr->page_cnt))
1959 return -ENOMEM;
1960
1961 if (palloc->level == PBLE_LEVEL_2) {
1962 struct irdma_pble_info *palloc_info =
1963 palloc->level2.leaf + (iwmr->npages >> PBLE_512_SHIFT);
1964
1965 palloc_info->addr[iwmr->npages & (PBLE_PER_PAGE - 1)] = addr;
1966 } else {
1967 pbl = palloc->level1.addr;
1968 pbl[iwmr->npages] = addr;
1969 }
1970
1971 iwmr->npages++;
1972 return 0;
1973 }
1974
1975 /**
1976 * irdma_map_mr_sg - map of sg list for fmr
1977 * @ibmr: ib mem to access iwarp mr pointer
1978 * @sg: scatter gather list
1979 * @sg_nents: number of sg pages
1980 * @sg_offset: scatter gather list for fmr
1981 */
1982 static int
irdma_map_mr_sg(struct ib_mr * ibmr,struct scatterlist * sg,int sg_nents,unsigned int * sg_offset)1983 irdma_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg,
1984 int sg_nents, unsigned int *sg_offset)
1985 {
1986 struct irdma_mr *iwmr = to_iwmr(ibmr);
1987
1988 iwmr->npages = 0;
1989
1990 return ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, irdma_set_page);
1991 }
1992
1993 /**
1994 * irdma_hwreg_mr - send cqp command for memory registration
1995 * @iwdev: irdma device
1996 * @iwmr: irdma mr pointer
1997 * @access: access for MR
1998 */
1999 int
irdma_hwreg_mr(struct irdma_device * iwdev,struct irdma_mr * iwmr,u16 access)2000 irdma_hwreg_mr(struct irdma_device *iwdev, struct irdma_mr *iwmr,
2001 u16 access)
2002 {
2003 struct irdma_pbl *iwpbl = &iwmr->iwpbl;
2004 struct irdma_reg_ns_stag_info *stag_info;
2005 struct ib_pd *pd = iwmr->ibmr.pd;
2006 struct irdma_pd *iwpd = to_iwpd(pd);
2007 struct irdma_pble_alloc *palloc = &iwpbl->pble_alloc;
2008 struct irdma_cqp_request *cqp_request;
2009 struct cqp_cmds_info *cqp_info;
2010 int ret;
2011
2012 cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true);
2013 if (!cqp_request)
2014 return -ENOMEM;
2015
2016 cqp_info = &cqp_request->info;
2017 stag_info = &cqp_info->in.u.mr_reg_non_shared.info;
2018 stag_info->va = iwpbl->user_base;
2019 stag_info->stag_idx = iwmr->stag >> IRDMA_CQPSQ_STAG_IDX_S;
2020 stag_info->stag_key = (u8)iwmr->stag;
2021 stag_info->total_len = iwmr->len;
2022 if ((pd->flags & IB_PD_UNSAFE_GLOBAL_RKEY) || iwmr->dma_mr)
2023 stag_info->all_memory = true;
2024 else
2025 stag_info->all_memory = false;
2026 stag_info->access_rights = irdma_get_mr_access(access,
2027 iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev);
2028 stag_info->pd_id = iwpd->sc_pd.pd_id;
2029 if (stag_info->access_rights & IRDMA_ACCESS_FLAGS_ZERO_BASED)
2030 stag_info->addr_type = IRDMA_ADDR_TYPE_ZERO_BASED;
2031 else
2032 stag_info->addr_type = IRDMA_ADDR_TYPE_VA_BASED;
2033 stag_info->page_size = iwmr->page_size;
2034
2035 if (iwpbl->pbl_allocated) {
2036 if (palloc->level == PBLE_LEVEL_1) {
2037 stag_info->first_pm_pbl_index = palloc->level1.idx;
2038 stag_info->chunk_size = 1;
2039 } else {
2040 stag_info->first_pm_pbl_index = palloc->level2.root.idx;
2041 stag_info->chunk_size = 3;
2042 }
2043 } else {
2044 stag_info->reg_addr_pa = iwmr->pgaddrmem[0];
2045 }
2046
2047 cqp_info->cqp_cmd = IRDMA_OP_MR_REG_NON_SHARED;
2048 cqp_info->post_sq = 1;
2049 cqp_info->in.u.mr_reg_non_shared.dev = &iwdev->rf->sc_dev;
2050 cqp_info->in.u.mr_reg_non_shared.scratch = (uintptr_t)cqp_request;
2051 cqp_info->create = true;
2052 ret = irdma_handle_cqp_op(iwdev->rf, cqp_request);
2053 irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request);
2054
2055 if (!ret)
2056 iwmr->is_hwreg = 1;
2057
2058 return ret;
2059 }
2060
2061 /*
2062 * irdma_alloc_iwmr - Allocate iwmr @region - memory region @pd - protection domain @virt - virtual address @reg_type -
2063 * registration type
2064 */
2065 struct irdma_mr *
irdma_alloc_iwmr(struct ib_umem * region,struct ib_pd * pd,u64 virt,enum irdma_memreg_type reg_type)2066 irdma_alloc_iwmr(struct ib_umem *region,
2067 struct ib_pd *pd, u64 virt,
2068 enum irdma_memreg_type reg_type)
2069 {
2070 struct irdma_pbl *iwpbl;
2071 struct irdma_mr *iwmr;
2072
2073 iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL);
2074 if (!iwmr)
2075 return ERR_PTR(-ENOMEM);
2076
2077 iwpbl = &iwmr->iwpbl;
2078 iwpbl->iwmr = iwmr;
2079 iwmr->region = region;
2080 iwmr->ibmr.pd = pd;
2081 iwmr->ibmr.device = pd->device;
2082 iwmr->ibmr.iova = virt;
2083 iwmr->type = reg_type;
2084
2085 /* Some OOT versions of irdma_copy_user_pg_addr require the pg mask */
2086 iwmr->page_msk = ~(IRDMA_HW_PAGE_SIZE - 1);
2087 iwmr->page_size = IRDMA_HW_PAGE_SIZE;
2088 iwmr->len = region->length;
2089 iwpbl->user_base = virt;
2090 iwmr->page_cnt = irdma_ib_umem_num_dma_blocks(region, iwmr->page_size, virt);
2091
2092 return iwmr;
2093 }
2094
2095 void
irdma_free_iwmr(struct irdma_mr * iwmr)2096 irdma_free_iwmr(struct irdma_mr *iwmr)
2097 {
2098 kfree(iwmr);
2099 }
2100
2101 /*
2102 * irdma_reg_user_mr_type_mem - Handle memory registration @iwmr - irdma mr @access - access rights @create_stag - flag
2103 * to create stag or not
2104 */
2105 int
irdma_reg_user_mr_type_mem(struct irdma_mr * iwmr,int access,bool create_stag)2106 irdma_reg_user_mr_type_mem(struct irdma_mr *iwmr, int access,
2107 bool create_stag)
2108 {
2109 struct irdma_device *iwdev = to_iwdev(iwmr->ibmr.device);
2110 struct irdma_pbl *iwpbl = &iwmr->iwpbl;
2111 u32 stag = 0;
2112 int err;
2113 u8 lvl;
2114
2115 lvl = iwmr->page_cnt != 1 ? PBLE_LEVEL_1 | PBLE_LEVEL_2 : PBLE_LEVEL_0;
2116
2117 err = irdma_setup_pbles(iwdev->rf, iwmr, lvl);
2118 if (err)
2119 return err;
2120
2121 if (lvl) {
2122 err = irdma_check_mr_contiguous(&iwpbl->pble_alloc,
2123 iwmr->page_size);
2124 if (err) {
2125 irdma_free_pble(iwdev->rf->pble_rsrc, &iwpbl->pble_alloc);
2126 iwpbl->pbl_allocated = false;
2127 }
2128 }
2129
2130 if (create_stag) {
2131 stag = irdma_create_stag(iwdev);
2132 if (!stag) {
2133 err = -ENOMEM;
2134 goto free_pble;
2135 }
2136
2137 iwmr->stag = stag;
2138 iwmr->ibmr.rkey = stag;
2139 iwmr->ibmr.lkey = stag;
2140 }
2141 iwmr->access = access;
2142 err = irdma_hwreg_mr(iwdev, iwmr, access);
2143 if (err)
2144 goto err_hwreg;
2145
2146 return 0;
2147
2148 err_hwreg:
2149 if (stag)
2150 irdma_free_stag(iwdev, stag);
2151
2152 free_pble:
2153 if (iwpbl->pble_alloc.level != PBLE_LEVEL_0 && iwpbl->pbl_allocated)
2154 irdma_free_pble(iwdev->rf->pble_rsrc, &iwpbl->pble_alloc);
2155
2156 return err;
2157 }
2158
2159 /*
2160 * irdma_reg_user_mr_type_qp - Handle QP memory registration @req - memory reg req @udata - user info @iwmr - irdma mr
2161 */
2162 int
irdma_reg_user_mr_type_qp(struct irdma_mem_reg_req req,struct ib_udata * udata,struct irdma_mr * iwmr)2163 irdma_reg_user_mr_type_qp(struct irdma_mem_reg_req req,
2164 struct ib_udata *udata,
2165 struct irdma_mr *iwmr)
2166 {
2167 struct irdma_device *iwdev = to_iwdev(iwmr->ibmr.device);
2168 struct irdma_pbl *iwpbl = &iwmr->iwpbl;
2169 struct irdma_ucontext *ucontext;
2170 unsigned long flags;
2171 u32 total;
2172 int err;
2173 u8 lvl;
2174
2175 /* iWarp: Catch page not starting on OS page boundary */
2176 if (!rdma_protocol_roce(&iwdev->ibdev, 1) &&
2177 ib_umem_offset(iwmr->region))
2178 return -EINVAL;
2179
2180 total = req.sq_pages + req.rq_pages + IRDMA_SHADOW_PGCNT;
2181 if (total > iwmr->page_cnt)
2182 return -EINVAL;
2183
2184 total = req.sq_pages + req.rq_pages;
2185 lvl = total > 2 ? PBLE_LEVEL_1 : PBLE_LEVEL_0;
2186 err = irdma_handle_q_mem(iwdev, &req, iwpbl, lvl);
2187 if (err)
2188 return err;
2189
2190 ucontext = rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext);
2191 spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags);
2192 list_add_tail(&iwpbl->list, &ucontext->qp_reg_mem_list);
2193 iwpbl->on_list = true;
2194 spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
2195
2196 return 0;
2197 }
2198
2199 /*
2200 * irdma_reg_user_mr_type_cq - Handle CQ memory registration @req - memory reg req @udata - user info @iwmr - irdma mr
2201 */
2202 int
irdma_reg_user_mr_type_cq(struct irdma_mem_reg_req req,struct ib_udata * udata,struct irdma_mr * iwmr)2203 irdma_reg_user_mr_type_cq(struct irdma_mem_reg_req req,
2204 struct ib_udata *udata,
2205 struct irdma_mr *iwmr)
2206 {
2207 struct irdma_device *iwdev = to_iwdev(iwmr->ibmr.device);
2208 struct irdma_pbl *iwpbl = &iwmr->iwpbl;
2209 struct irdma_ucontext *ucontext;
2210 unsigned long flags;
2211 u32 total;
2212 int err;
2213 u8 lvl;
2214
2215 total = req.cq_pages +
2216 ((iwdev->rf->sc_dev.hw_attrs.uk_attrs.feature_flags & IRDMA_FEATURE_CQ_RESIZE) ? 0 : IRDMA_SHADOW_PGCNT);
2217 if (total > iwmr->page_cnt)
2218 return -EINVAL;
2219
2220 lvl = req.cq_pages > 1 ? PBLE_LEVEL_1 : PBLE_LEVEL_0;
2221 err = irdma_handle_q_mem(iwdev, &req, iwpbl, lvl);
2222 if (err)
2223 return err;
2224
2225 ucontext = rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext);
2226 spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
2227 list_add_tail(&iwpbl->list, &ucontext->cq_reg_mem_list);
2228 iwpbl->on_list = true;
2229 spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
2230
2231 return 0;
2232 }
2233
2234 int
irdma_hwdereg_mr(struct ib_mr * ib_mr)2235 irdma_hwdereg_mr(struct ib_mr *ib_mr)
2236 {
2237 struct irdma_device *iwdev = to_iwdev(ib_mr->device);
2238 struct irdma_mr *iwmr = to_iwmr(ib_mr);
2239 struct irdma_pd *iwpd = to_iwpd(ib_mr->pd);
2240 struct irdma_dealloc_stag_info *info;
2241 struct irdma_pbl *iwpbl = &iwmr->iwpbl;
2242 struct irdma_cqp_request *cqp_request;
2243 struct cqp_cmds_info *cqp_info;
2244 int status;
2245
2246 /*
2247 * Skip HW MR de-register when it is already de-registered during an MR re-reregister and the re-registration
2248 * fails
2249 */
2250 if (!iwmr->is_hwreg)
2251 return 0;
2252
2253 cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true);
2254 if (!cqp_request)
2255 return -ENOMEM;
2256
2257 cqp_info = &cqp_request->info;
2258 info = &cqp_info->in.u.dealloc_stag.info;
2259 info->pd_id = iwpd->sc_pd.pd_id;
2260 info->stag_idx = RS_64_1(ib_mr->rkey, IRDMA_CQPSQ_STAG_IDX_S);
2261 info->mr = true;
2262 if (iwmr->type != IRDMA_MEMREG_TYPE_MEM)
2263 info->skip_flush_markers = true;
2264 if (iwpbl->pbl_allocated)
2265 info->dealloc_pbl = true;
2266
2267 cqp_info->cqp_cmd = IRDMA_OP_DEALLOC_STAG;
2268 cqp_info->post_sq = 1;
2269 cqp_info->in.u.dealloc_stag.dev = &iwdev->rf->sc_dev;
2270 cqp_info->in.u.dealloc_stag.scratch = (uintptr_t)cqp_request;
2271 status = irdma_handle_cqp_op(iwdev->rf, cqp_request);
2272 irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request);
2273
2274 if (!status)
2275 iwmr->is_hwreg = 0;
2276
2277 return status;
2278 }
2279
2280 /*
2281 * irdma_rereg_mr_trans - Re-register a user MR for a change translation. @iwmr: ptr of iwmr @start: virtual start
2282 * address @len: length of mr @virt: virtual address
2283 *
2284 * Re-register a user memory region when a change translation is requested. Re-register a new region while reusing the
2285 * stag from the original registration.
2286 */
2287 struct ib_mr *
irdma_rereg_mr_trans(struct irdma_mr * iwmr,u64 start,u64 len,u64 virt,struct ib_udata * udata)2288 irdma_rereg_mr_trans(struct irdma_mr *iwmr, u64 start, u64 len,
2289 u64 virt, struct ib_udata *udata)
2290 {
2291 struct irdma_device *iwdev = to_iwdev(iwmr->ibmr.device);
2292 struct irdma_pbl *iwpbl = &iwmr->iwpbl;
2293 struct ib_pd *pd = iwmr->ibmr.pd;
2294 struct ib_umem *region;
2295 int err;
2296
2297 region = ib_umem_get(pd->uobject->context, start, len, iwmr->access, 0);
2298
2299 if (IS_ERR(region)) {
2300 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_VERBS,
2301 "Failed to create ib_umem region err=%ld\n",
2302 PTR_ERR(region));
2303 return (struct ib_mr *)region;
2304 }
2305
2306 iwmr->region = region;
2307 iwmr->ibmr.iova = virt;
2308 iwmr->ibmr.pd = pd;
2309 iwmr->page_size = PAGE_SIZE;
2310
2311 iwmr->len = region->length;
2312 iwpbl->user_base = virt;
2313 iwmr->page_cnt = irdma_ib_umem_num_dma_blocks(region, iwmr->page_size,
2314 virt);
2315
2316 err = irdma_reg_user_mr_type_mem(iwmr, iwmr->access, false);
2317 if (err)
2318 goto err;
2319
2320 return &iwmr->ibmr;
2321
2322 err:
2323 ib_umem_release(region);
2324 return ERR_PTR(err);
2325 }
2326
2327 /**
2328 * irdma_reg_phys_mr - register kernel physical memory
2329 * @pd: ibpd pointer
2330 * @addr: physical address of memory to register
2331 * @size: size of memory to register
2332 * @access: Access rights
2333 * @iova_start: start of virtual address for physical buffers
2334 * @dma_mr: Flag indicating DMA Mem region
2335 */
2336 struct ib_mr *
irdma_reg_phys_mr(struct ib_pd * pd,u64 addr,u64 size,int access,u64 * iova_start,bool dma_mr)2337 irdma_reg_phys_mr(struct ib_pd *pd, u64 addr, u64 size, int access,
2338 u64 *iova_start, bool dma_mr)
2339 {
2340 struct irdma_device *iwdev = to_iwdev(pd->device);
2341 struct irdma_pbl *iwpbl;
2342 struct irdma_mr *iwmr;
2343 u32 stag;
2344 int ret;
2345
2346 iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL);
2347 if (!iwmr)
2348 return ERR_PTR(-ENOMEM);
2349
2350 iwmr->ibmr.pd = pd;
2351 iwmr->ibmr.device = pd->device;
2352 iwpbl = &iwmr->iwpbl;
2353 iwpbl->iwmr = iwmr;
2354 iwmr->type = IRDMA_MEMREG_TYPE_MEM;
2355 iwmr->dma_mr = dma_mr;
2356 iwpbl->user_base = *iova_start;
2357 stag = irdma_create_stag(iwdev);
2358 if (!stag) {
2359 ret = -ENOMEM;
2360 goto err;
2361 }
2362
2363 iwmr->stag = stag;
2364 iwmr->ibmr.iova = *iova_start;
2365 iwmr->ibmr.rkey = stag;
2366 iwmr->ibmr.lkey = stag;
2367 iwmr->page_cnt = 1;
2368 iwmr->pgaddrmem[0] = addr;
2369 iwmr->len = size;
2370 iwmr->page_size = SZ_4K;
2371 ret = irdma_hwreg_mr(iwdev, iwmr, access);
2372 if (ret) {
2373 irdma_free_stag(iwdev, stag);
2374 goto err;
2375 }
2376
2377 return &iwmr->ibmr;
2378
2379 err:
2380 kfree(iwmr);
2381
2382 return ERR_PTR(ret);
2383 }
2384
2385 /**
2386 * irdma_get_dma_mr - register physical mem
2387 * @pd: ptr of pd
2388 * @acc: access for memory
2389 */
2390 static struct ib_mr *
irdma_get_dma_mr(struct ib_pd * pd,int acc)2391 irdma_get_dma_mr(struct ib_pd *pd, int acc)
2392 {
2393 u64 kva = 0;
2394
2395 return irdma_reg_phys_mr(pd, 0, 0, acc, &kva, true);
2396 }
2397
2398 /**
2399 * irdma_del_memlist - Deleting pbl list entries for CQ/QP
2400 * @iwmr: iwmr for IB's user page addresses
2401 * @ucontext: ptr to user context
2402 */
2403 void
irdma_del_memlist(struct irdma_mr * iwmr,struct irdma_ucontext * ucontext)2404 irdma_del_memlist(struct irdma_mr *iwmr,
2405 struct irdma_ucontext *ucontext)
2406 {
2407 struct irdma_pbl *iwpbl = &iwmr->iwpbl;
2408 unsigned long flags;
2409
2410 switch (iwmr->type) {
2411 case IRDMA_MEMREG_TYPE_CQ:
2412 spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
2413 if (iwpbl->on_list) {
2414 iwpbl->on_list = false;
2415 list_del(&iwpbl->list);
2416 }
2417 spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
2418 break;
2419 case IRDMA_MEMREG_TYPE_QP:
2420 spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags);
2421 if (iwpbl->on_list) {
2422 iwpbl->on_list = false;
2423 list_del(&iwpbl->list);
2424 }
2425 spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
2426 break;
2427 default:
2428 break;
2429 }
2430 }
2431
2432 /**
2433 * irdma_post_send - kernel application wr
2434 * @ibqp: qp ptr for wr
2435 * @ib_wr: work request ptr
2436 * @bad_wr: return of bad wr if err
2437 */
2438 static int
irdma_post_send(struct ib_qp * ibqp,const struct ib_send_wr * ib_wr,const struct ib_send_wr ** bad_wr)2439 irdma_post_send(struct ib_qp *ibqp,
2440 const struct ib_send_wr *ib_wr,
2441 const struct ib_send_wr **bad_wr)
2442 {
2443 struct irdma_qp *iwqp;
2444 struct irdma_qp_uk *ukqp;
2445 struct irdma_sc_dev *dev;
2446 struct irdma_post_sq_info info;
2447 int err = 0;
2448 unsigned long flags;
2449 bool inv_stag;
2450 struct irdma_ah *ah;
2451
2452 iwqp = to_iwqp(ibqp);
2453 ukqp = &iwqp->sc_qp.qp_uk;
2454 dev = &iwqp->iwdev->rf->sc_dev;
2455
2456 spin_lock_irqsave(&iwqp->lock, flags);
2457 while (ib_wr) {
2458 memset(&info, 0, sizeof(info));
2459 inv_stag = false;
2460 info.wr_id = (ib_wr->wr_id);
2461 if ((ib_wr->send_flags & IB_SEND_SIGNALED) || iwqp->sig_all)
2462 info.signaled = true;
2463 if (ib_wr->send_flags & IB_SEND_FENCE)
2464 info.read_fence = true;
2465 switch (ib_wr->opcode) {
2466 case IB_WR_SEND_WITH_IMM:
2467 if (ukqp->qp_caps & IRDMA_SEND_WITH_IMM) {
2468 info.imm_data_valid = true;
2469 info.imm_data = ntohl(ib_wr->ex.imm_data);
2470 } else {
2471 err = -EINVAL;
2472 break;
2473 }
2474 /* fallthrough */
2475 case IB_WR_SEND:
2476 case IB_WR_SEND_WITH_INV:
2477 if (ib_wr->opcode == IB_WR_SEND ||
2478 ib_wr->opcode == IB_WR_SEND_WITH_IMM) {
2479 if (ib_wr->send_flags & IB_SEND_SOLICITED)
2480 info.op_type = IRDMA_OP_TYPE_SEND_SOL;
2481 else
2482 info.op_type = IRDMA_OP_TYPE_SEND;
2483 } else {
2484 if (ib_wr->send_flags & IB_SEND_SOLICITED)
2485 info.op_type = IRDMA_OP_TYPE_SEND_SOL_INV;
2486 else
2487 info.op_type = IRDMA_OP_TYPE_SEND_INV;
2488 info.stag_to_inv = ib_wr->ex.invalidate_rkey;
2489 }
2490
2491 info.op.send.num_sges = ib_wr->num_sge;
2492 info.op.send.sg_list = ib_wr->sg_list;
2493 if (iwqp->ibqp.qp_type == IB_QPT_UD ||
2494 iwqp->ibqp.qp_type == IB_QPT_GSI) {
2495 ah = to_iwah(ud_wr(ib_wr)->ah);
2496 info.op.send.ah_id = ah->sc_ah.ah_info.ah_idx;
2497 info.op.send.qkey = ud_wr(ib_wr)->remote_qkey;
2498 info.op.send.dest_qp = ud_wr(ib_wr)->remote_qpn;
2499 }
2500
2501 if (ib_wr->send_flags & IB_SEND_INLINE)
2502 err = irdma_uk_inline_send(ukqp, &info, false);
2503 else
2504 err = irdma_uk_send(ukqp, &info, false);
2505 break;
2506 case IB_WR_RDMA_WRITE_WITH_IMM:
2507 if (ukqp->qp_caps & IRDMA_WRITE_WITH_IMM) {
2508 info.imm_data_valid = true;
2509 info.imm_data = ntohl(ib_wr->ex.imm_data);
2510 } else {
2511 err = -EINVAL;
2512 break;
2513 }
2514 /* fallthrough */
2515 case IB_WR_RDMA_WRITE:
2516 if (ib_wr->send_flags & IB_SEND_SOLICITED)
2517 info.op_type = IRDMA_OP_TYPE_RDMA_WRITE_SOL;
2518 else
2519 info.op_type = IRDMA_OP_TYPE_RDMA_WRITE;
2520
2521 info.op.rdma_write.num_lo_sges = ib_wr->num_sge;
2522 info.op.rdma_write.lo_sg_list = (void *)ib_wr->sg_list;
2523 info.op.rdma_write.rem_addr.addr = rdma_wr(ib_wr)->remote_addr;
2524 info.op.rdma_write.rem_addr.lkey = rdma_wr(ib_wr)->rkey;
2525 if (ib_wr->send_flags & IB_SEND_INLINE)
2526 err = irdma_uk_inline_rdma_write(ukqp, &info, false);
2527 else
2528 err = irdma_uk_rdma_write(ukqp, &info, false);
2529 break;
2530 case IB_WR_RDMA_READ_WITH_INV:
2531 inv_stag = true;
2532 /* fallthrough */
2533 case IB_WR_RDMA_READ:
2534 if (ib_wr->num_sge >
2535 dev->hw_attrs.uk_attrs.max_hw_read_sges) {
2536 err = -EINVAL;
2537 break;
2538 }
2539 info.op_type = IRDMA_OP_TYPE_RDMA_READ;
2540 info.op.rdma_read.rem_addr.addr = rdma_wr(ib_wr)->remote_addr;
2541 info.op.rdma_read.rem_addr.lkey = rdma_wr(ib_wr)->rkey;
2542 info.op.rdma_read.lo_sg_list = (void *)ib_wr->sg_list;
2543 info.op.rdma_read.num_lo_sges = ib_wr->num_sge;
2544 err = irdma_uk_rdma_read(ukqp, &info, inv_stag, false);
2545 break;
2546 case IB_WR_LOCAL_INV:
2547 info.op_type = IRDMA_OP_TYPE_INV_STAG;
2548 info.local_fence = true;
2549 info.op.inv_local_stag.target_stag = ib_wr->ex.invalidate_rkey;
2550 err = irdma_uk_stag_local_invalidate(ukqp, &info, true);
2551 break;
2552 case IB_WR_REG_MR:{
2553 struct irdma_mr *iwmr = to_iwmr(reg_wr(ib_wr)->mr);
2554 struct irdma_pble_alloc *palloc = &iwmr->iwpbl.pble_alloc;
2555 struct irdma_fast_reg_stag_info stag_info = {0};
2556
2557 stag_info.signaled = info.signaled;
2558 stag_info.read_fence = info.read_fence;
2559 stag_info.access_rights =
2560 irdma_get_mr_access(reg_wr(ib_wr)->access,
2561 dev->hw_attrs.uk_attrs.hw_rev);
2562 stag_info.stag_key = reg_wr(ib_wr)->key & 0xff;
2563 stag_info.stag_idx = reg_wr(ib_wr)->key >> 8;
2564 stag_info.page_size = reg_wr(ib_wr)->mr->page_size;
2565 stag_info.wr_id = ib_wr->wr_id;
2566 stag_info.addr_type = IRDMA_ADDR_TYPE_VA_BASED;
2567 stag_info.va = (void *)(uintptr_t)iwmr->ibmr.iova;
2568 stag_info.total_len = iwmr->ibmr.length;
2569 if (palloc->level == PBLE_LEVEL_2) {
2570 stag_info.chunk_size = 3;
2571 stag_info.first_pm_pbl_index = palloc->level2.root.idx;
2572 } else {
2573 stag_info.chunk_size = 1;
2574 stag_info.first_pm_pbl_index = palloc->level1.idx;
2575 }
2576 stag_info.local_fence = ib_wr->send_flags & IB_SEND_FENCE;
2577 err = irdma_sc_mr_fast_register(&iwqp->sc_qp, &stag_info,
2578 true);
2579 break;
2580 }
2581 default:
2582 err = -EINVAL;
2583 irdma_debug(&iwqp->iwdev->rf->sc_dev, IRDMA_DEBUG_VERBS,
2584 "upost_send bad opcode = 0x%x\n",
2585 ib_wr->opcode);
2586 break;
2587 }
2588
2589 if (err)
2590 break;
2591 ib_wr = ib_wr->next;
2592 }
2593
2594 if (!atomic_read(&iwqp->flush_issued)) {
2595 if (iwqp->hw_iwarp_state <= IRDMA_QP_STATE_RTS)
2596 irdma_uk_qp_post_wr(ukqp);
2597 spin_unlock_irqrestore(&iwqp->lock, flags);
2598 } else {
2599 spin_unlock_irqrestore(&iwqp->lock, flags);
2600 irdma_sched_qp_flush_work(iwqp);
2601 }
2602
2603 if (err)
2604 *bad_wr = ib_wr;
2605
2606 return err;
2607 }
2608
2609 /**
2610 * irdma_post_recv - post receive wr for kernel application
2611 * @ibqp: ib qp pointer
2612 * @ib_wr: work request for receive
2613 * @bad_wr: bad wr caused an error
2614 */
2615 static int
irdma_post_recv(struct ib_qp * ibqp,const struct ib_recv_wr * ib_wr,const struct ib_recv_wr ** bad_wr)2616 irdma_post_recv(struct ib_qp *ibqp,
2617 const struct ib_recv_wr *ib_wr,
2618 const struct ib_recv_wr **bad_wr)
2619 {
2620 struct irdma_qp *iwqp = to_iwqp(ibqp);
2621 struct irdma_qp_uk *ukqp = &iwqp->sc_qp.qp_uk;
2622 struct irdma_post_rq_info post_recv = {0};
2623 unsigned long flags;
2624 int err = 0;
2625
2626 spin_lock_irqsave(&iwqp->lock, flags);
2627
2628 while (ib_wr) {
2629 if (ib_wr->num_sge > ukqp->max_rq_frag_cnt) {
2630 err = -EINVAL;
2631 goto out;
2632 }
2633 post_recv.num_sges = ib_wr->num_sge;
2634 post_recv.wr_id = ib_wr->wr_id;
2635 post_recv.sg_list = ib_wr->sg_list;
2636 err = irdma_uk_post_receive(ukqp, &post_recv);
2637 if (err) {
2638 irdma_debug(&iwqp->iwdev->rf->sc_dev, IRDMA_DEBUG_VERBS,
2639 "post_recv err %d\n", err);
2640 goto out;
2641 }
2642 ib_wr = ib_wr->next;
2643 }
2644
2645 out:
2646 spin_unlock_irqrestore(&iwqp->lock, flags);
2647
2648 if (atomic_read(&iwqp->flush_issued))
2649 irdma_sched_qp_flush_work(iwqp);
2650
2651 if (err)
2652 *bad_wr = ib_wr;
2653
2654 return err;
2655 }
2656
2657 /**
2658 * irdma_flush_err_to_ib_wc_status - return change flush error code to IB status
2659 * @opcode: iwarp flush code
2660 */
2661 static enum ib_wc_status
irdma_flush_err_to_ib_wc_status(enum irdma_flush_opcode opcode)2662 irdma_flush_err_to_ib_wc_status(enum irdma_flush_opcode opcode)
2663 {
2664 switch (opcode) {
2665 case FLUSH_PROT_ERR:
2666 return IB_WC_LOC_PROT_ERR;
2667 case FLUSH_REM_ACCESS_ERR:
2668 return IB_WC_REM_ACCESS_ERR;
2669 case FLUSH_LOC_QP_OP_ERR:
2670 return IB_WC_LOC_QP_OP_ERR;
2671 case FLUSH_REM_OP_ERR:
2672 return IB_WC_REM_OP_ERR;
2673 case FLUSH_LOC_LEN_ERR:
2674 return IB_WC_LOC_LEN_ERR;
2675 case FLUSH_GENERAL_ERR:
2676 return IB_WC_WR_FLUSH_ERR;
2677 case FLUSH_MW_BIND_ERR:
2678 return IB_WC_MW_BIND_ERR;
2679 case FLUSH_REM_INV_REQ_ERR:
2680 return IB_WC_REM_INV_REQ_ERR;
2681 case FLUSH_RETRY_EXC_ERR:
2682 return IB_WC_RETRY_EXC_ERR;
2683 case FLUSH_FATAL_ERR:
2684 default:
2685 return IB_WC_FATAL_ERR;
2686 }
2687 }
2688
2689 /**
2690 * irdma_process_cqe - process cqe info
2691 * @entry: processed cqe
2692 * @cq_poll_info: cqe info
2693 */
2694 static void
irdma_process_cqe(struct ib_wc * entry,struct irdma_cq_poll_info * cq_poll_info)2695 irdma_process_cqe(struct ib_wc *entry,
2696 struct irdma_cq_poll_info *cq_poll_info)
2697 {
2698 struct irdma_sc_qp *qp;
2699
2700 entry->wc_flags = 0;
2701 entry->pkey_index = 0;
2702 entry->wr_id = cq_poll_info->wr_id;
2703
2704 qp = cq_poll_info->qp_handle;
2705 entry->qp = qp->qp_uk.back_qp;
2706
2707 if (cq_poll_info->error) {
2708 entry->status = (cq_poll_info->comp_status == IRDMA_COMPL_STATUS_FLUSHED) ?
2709 irdma_flush_err_to_ib_wc_status(cq_poll_info->minor_err) : IB_WC_GENERAL_ERR;
2710
2711 entry->vendor_err = cq_poll_info->major_err << 16 |
2712 cq_poll_info->minor_err;
2713 } else {
2714 entry->status = IB_WC_SUCCESS;
2715 if (cq_poll_info->imm_valid) {
2716 entry->ex.imm_data = htonl(cq_poll_info->imm_data);
2717 entry->wc_flags |= IB_WC_WITH_IMM;
2718 }
2719 if (cq_poll_info->ud_smac_valid) {
2720 ether_addr_copy(entry->smac, cq_poll_info->ud_smac);
2721 entry->wc_flags |= IB_WC_WITH_SMAC;
2722 }
2723
2724 if (cq_poll_info->ud_vlan_valid) {
2725 u16 vlan = cq_poll_info->ud_vlan & EVL_VLID_MASK;
2726
2727 entry->sl = cq_poll_info->ud_vlan >> VLAN_PRIO_SHIFT;
2728 if (vlan) {
2729 entry->vlan_id = vlan;
2730 entry->wc_flags |= IB_WC_WITH_VLAN;
2731 }
2732 } else {
2733 entry->sl = 0;
2734 }
2735 }
2736
2737 if (cq_poll_info->q_type == IRDMA_CQE_QTYPE_SQ) {
2738 set_ib_wc_op_sq(cq_poll_info, entry);
2739 } else {
2740 set_ib_wc_op_rq(cq_poll_info, entry,
2741 qp->qp_uk.qp_caps & IRDMA_SEND_WITH_IMM ?
2742 true : false);
2743 if (qp->qp_uk.qp_type != IRDMA_QP_TYPE_ROCE_UD &&
2744 cq_poll_info->stag_invalid_set) {
2745 entry->ex.invalidate_rkey = cq_poll_info->inv_stag;
2746 entry->wc_flags |= IB_WC_WITH_INVALIDATE;
2747 }
2748 }
2749
2750 if (qp->qp_uk.qp_type == IRDMA_QP_TYPE_ROCE_UD) {
2751 entry->src_qp = cq_poll_info->ud_src_qpn;
2752 entry->slid = 0;
2753 entry->wc_flags |=
2754 (IB_WC_GRH | IB_WC_WITH_NETWORK_HDR_TYPE);
2755 entry->network_hdr_type = cq_poll_info->ipv4 ?
2756 RDMA_NETWORK_IPV4 :
2757 RDMA_NETWORK_IPV6;
2758 } else {
2759 entry->src_qp = cq_poll_info->qp_id;
2760 }
2761
2762 entry->byte_len = cq_poll_info->bytes_xfered;
2763 }
2764
2765 /**
2766 * irdma_poll_one - poll one entry of the CQ
2767 * @ukcq: ukcq to poll
2768 * @cur_cqe: current CQE info to be filled in
2769 * @entry: ibv_wc object to be filled for non-extended CQ or NULL for extended CQ
2770 *
2771 * Returns the internal irdma device error code or 0 on success
2772 */
2773 static inline int
irdma_poll_one(struct irdma_cq_uk * ukcq,struct irdma_cq_poll_info * cur_cqe,struct ib_wc * entry)2774 irdma_poll_one(struct irdma_cq_uk *ukcq,
2775 struct irdma_cq_poll_info *cur_cqe,
2776 struct ib_wc *entry)
2777 {
2778 int ret = irdma_uk_cq_poll_cmpl(ukcq, cur_cqe);
2779
2780 if (ret)
2781 return ret;
2782
2783 irdma_process_cqe(entry, cur_cqe);
2784
2785 return 0;
2786 }
2787
2788 /**
2789 * __irdma_poll_cq - poll cq for completion (kernel apps)
2790 * @iwcq: cq to poll
2791 * @num_entries: number of entries to poll
2792 * @entry: wr of a completed entry
2793 */
2794 static int
__irdma_poll_cq(struct irdma_cq * iwcq,int num_entries,struct ib_wc * entry)2795 __irdma_poll_cq(struct irdma_cq *iwcq, int num_entries, struct ib_wc *entry)
2796 {
2797 struct list_head *tmp_node, *list_node;
2798 struct irdma_cq_buf *last_buf = NULL;
2799 struct irdma_cq_poll_info *cur_cqe = &iwcq->cur_cqe;
2800 struct irdma_cq_buf *cq_buf;
2801 int ret;
2802 struct irdma_device *iwdev;
2803 struct irdma_cq_uk *ukcq;
2804 bool cq_new_cqe = false;
2805 int resized_bufs = 0;
2806 int npolled = 0;
2807
2808 iwdev = to_iwdev(iwcq->ibcq.device);
2809 ukcq = &iwcq->sc_cq.cq_uk;
2810
2811 /* go through the list of previously resized CQ buffers */
2812 list_for_each_safe(list_node, tmp_node, &iwcq->resize_list) {
2813 cq_buf = container_of(list_node, struct irdma_cq_buf, list);
2814 while (npolled < num_entries) {
2815 ret = irdma_poll_one(&cq_buf->cq_uk, cur_cqe, entry + npolled);
2816 if (!ret) {
2817 ++npolled;
2818 cq_new_cqe = true;
2819 continue;
2820 }
2821 if (ret == -ENOENT)
2822 break;
2823 /* QP using the CQ is destroyed. Skip reporting this CQE */
2824 if (ret == -EFAULT) {
2825 cq_new_cqe = true;
2826 continue;
2827 }
2828 goto error;
2829 }
2830
2831 /* save the resized CQ buffer which received the last cqe */
2832 if (cq_new_cqe)
2833 last_buf = cq_buf;
2834 cq_new_cqe = false;
2835 }
2836
2837 /* check the current CQ for new cqes */
2838 while (npolled < num_entries) {
2839 ret = irdma_poll_one(ukcq, cur_cqe, entry + npolled);
2840 if (ret == -ENOENT) {
2841 ret = irdma_generated_cmpls(iwcq, cur_cqe);
2842 if (!ret)
2843 irdma_process_cqe(entry + npolled, cur_cqe);
2844 }
2845 if (!ret) {
2846 ++npolled;
2847 cq_new_cqe = true;
2848 continue;
2849 }
2850
2851 if (ret == -ENOENT)
2852 break;
2853 /* QP using the CQ is destroyed. Skip reporting this CQE */
2854 if (ret == -EFAULT) {
2855 cq_new_cqe = true;
2856 continue;
2857 }
2858 goto error;
2859 }
2860
2861 if (cq_new_cqe)
2862 /* all previous CQ resizes are complete */
2863 resized_bufs = irdma_process_resize_list(iwcq, iwdev, NULL);
2864 else if (last_buf)
2865 /* only CQ resizes up to the last_buf are complete */
2866 resized_bufs = irdma_process_resize_list(iwcq, iwdev, last_buf);
2867 if (resized_bufs)
2868 /* report to the HW the number of complete CQ resizes */
2869 irdma_uk_cq_set_resized_cnt(ukcq, resized_bufs);
2870
2871 return npolled;
2872 error:
2873 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_VERBS,
2874 "%s: Error polling CQ, irdma_err: %d\n", __func__, ret);
2875
2876 return ret;
2877 }
2878
2879 /**
2880 * irdma_poll_cq - poll cq for completion (kernel apps)
2881 * @ibcq: cq to poll
2882 * @num_entries: number of entries to poll
2883 * @entry: wr of a completed entry
2884 */
2885 static int
irdma_poll_cq(struct ib_cq * ibcq,int num_entries,struct ib_wc * entry)2886 irdma_poll_cq(struct ib_cq *ibcq, int num_entries,
2887 struct ib_wc *entry)
2888 {
2889 struct irdma_cq *iwcq;
2890 unsigned long flags;
2891 int ret;
2892
2893 iwcq = to_iwcq(ibcq);
2894
2895 spin_lock_irqsave(&iwcq->lock, flags);
2896 ret = __irdma_poll_cq(iwcq, num_entries, entry);
2897 spin_unlock_irqrestore(&iwcq->lock, flags);
2898
2899 return ret;
2900 }
2901
2902 /**
2903 * irdma_req_notify_cq - arm cq kernel application
2904 * @ibcq: cq to arm
2905 * @notify_flags: notofication flags
2906 */
2907 static int
irdma_req_notify_cq(struct ib_cq * ibcq,enum ib_cq_notify_flags notify_flags)2908 irdma_req_notify_cq(struct ib_cq *ibcq,
2909 enum ib_cq_notify_flags notify_flags)
2910 {
2911 struct irdma_cq *iwcq;
2912 struct irdma_cq_uk *ukcq;
2913 unsigned long flags;
2914 enum irdma_cmpl_notify cq_notify = IRDMA_CQ_COMPL_EVENT;
2915 bool promo_event = false;
2916 int ret = 0;
2917
2918 iwcq = to_iwcq(ibcq);
2919 ukcq = &iwcq->sc_cq.cq_uk;
2920
2921 spin_lock_irqsave(&iwcq->lock, flags);
2922 if (notify_flags == IB_CQ_SOLICITED) {
2923 cq_notify = IRDMA_CQ_COMPL_SOLICITED;
2924 } else {
2925 if (iwcq->last_notify == IRDMA_CQ_COMPL_SOLICITED)
2926 promo_event = true;
2927 }
2928
2929 if (!atomic_cmpxchg(&iwcq->armed, 0, 1) || promo_event) {
2930 iwcq->last_notify = cq_notify;
2931 irdma_uk_cq_request_notification(ukcq, cq_notify);
2932 }
2933
2934 if ((notify_flags & IB_CQ_REPORT_MISSED_EVENTS) &&
2935 (!irdma_uk_cq_empty(&iwcq->sc_cq.cq_uk) || !list_empty(&iwcq->cmpl_generated)))
2936 ret = 1;
2937 spin_unlock_irqrestore(&iwcq->lock, flags);
2938
2939 return ret;
2940 }
2941
2942 /**
2943 * mcast_list_add - Add a new mcast item to list
2944 * @rf: RDMA PCI function
2945 * @new_elem: pointer to element to add
2946 */
2947 static void
mcast_list_add(struct irdma_pci_f * rf,struct mc_table_list * new_elem)2948 mcast_list_add(struct irdma_pci_f *rf,
2949 struct mc_table_list *new_elem)
2950 {
2951 list_add(&new_elem->list, &rf->mc_qht_list.list);
2952 }
2953
2954 /**
2955 * mcast_list_del - Remove an mcast item from list
2956 * @mc_qht_elem: pointer to mcast table list element
2957 */
2958 static void
mcast_list_del(struct mc_table_list * mc_qht_elem)2959 mcast_list_del(struct mc_table_list *mc_qht_elem)
2960 {
2961 if (mc_qht_elem)
2962 list_del(&mc_qht_elem->list);
2963 }
2964
2965 /**
2966 * mcast_list_lookup_ip - Search mcast list for address
2967 * @rf: RDMA PCI function
2968 * @ip_mcast: pointer to mcast IP address
2969 */
2970 static struct mc_table_list *
mcast_list_lookup_ip(struct irdma_pci_f * rf,u32 * ip_mcast)2971 mcast_list_lookup_ip(struct irdma_pci_f *rf,
2972 u32 *ip_mcast)
2973 {
2974 struct mc_table_list *mc_qht_el;
2975 struct list_head *pos, *q;
2976
2977 list_for_each_safe(pos, q, &rf->mc_qht_list.list) {
2978 mc_qht_el = list_entry(pos, struct mc_table_list, list);
2979 if (!memcmp(mc_qht_el->mc_info.dest_ip, ip_mcast,
2980 sizeof(mc_qht_el->mc_info.dest_ip)))
2981 return mc_qht_el;
2982 }
2983
2984 return NULL;
2985 }
2986
2987 /**
2988 * irdma_mcast_cqp_op - perform a mcast cqp operation
2989 * @iwdev: irdma device
2990 * @mc_grp_ctx: mcast group info
2991 * @op: operation
2992 *
2993 * returns error status
2994 */
2995 static int
irdma_mcast_cqp_op(struct irdma_device * iwdev,struct irdma_mcast_grp_info * mc_grp_ctx,u8 op)2996 irdma_mcast_cqp_op(struct irdma_device *iwdev,
2997 struct irdma_mcast_grp_info *mc_grp_ctx, u8 op)
2998 {
2999 struct cqp_cmds_info *cqp_info;
3000 struct irdma_cqp_request *cqp_request;
3001 int status;
3002
3003 cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true);
3004 if (!cqp_request)
3005 return -ENOMEM;
3006
3007 cqp_request->info.in.u.mc_create.info = *mc_grp_ctx;
3008 cqp_info = &cqp_request->info;
3009 cqp_info->cqp_cmd = op;
3010 cqp_info->post_sq = 1;
3011 cqp_info->in.u.mc_create.scratch = (uintptr_t)cqp_request;
3012 cqp_info->in.u.mc_create.cqp = &iwdev->rf->cqp.sc_cqp;
3013
3014 if (op == IRDMA_OP_MC_CREATE)
3015 cqp_info->create = true;
3016
3017 status = irdma_handle_cqp_op(iwdev->rf, cqp_request);
3018 irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request);
3019
3020 return status;
3021 }
3022
3023 /**
3024 * irdma_attach_mcast - attach a qp to a multicast group
3025 * @ibqp: ptr to qp
3026 * @ibgid: pointer to global ID
3027 * @lid: local ID
3028 *
3029 * returns error status
3030 */
3031 static int
irdma_attach_mcast(struct ib_qp * ibqp,union ib_gid * ibgid,u16 lid)3032 irdma_attach_mcast(struct ib_qp *ibqp, union ib_gid *ibgid, u16 lid)
3033 {
3034 struct irdma_qp *iwqp = to_iwqp(ibqp);
3035 struct irdma_device *iwdev = iwqp->iwdev;
3036 struct irdma_pci_f *rf = iwdev->rf;
3037 struct mc_table_list *mc_qht_elem;
3038 struct irdma_mcast_grp_ctx_entry_info mcg_info = {0};
3039 unsigned long flags;
3040 u32 ip_addr[4] = {0};
3041 u32 mgn;
3042 u32 no_mgs;
3043 int ret = 0;
3044 bool ipv4;
3045 u16 vlan_id;
3046 union irdma_sockaddr sgid_addr;
3047 unsigned char dmac[ETHER_ADDR_LEN];
3048
3049 rdma_gid2ip((struct sockaddr *)&sgid_addr, ibgid);
3050
3051 if (!ipv6_addr_v4mapped((struct in6_addr *)ibgid)) {
3052 irdma_copy_ip_ntohl(ip_addr,
3053 sgid_addr.saddr_in6.sin6_addr.__u6_addr.__u6_addr32);
3054 irdma_get_vlan_mac_ipv6(iwqp->cm_id, ip_addr, &vlan_id, NULL);
3055 ipv4 = false;
3056 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_VERBS,
3057 "qp_id=%d, IP6address=%x:%x:%x:%x\n", ibqp->qp_num,
3058 IRDMA_PRINT_IP6(ip_addr));
3059 irdma_mcast_mac_v6(ip_addr, dmac);
3060 } else {
3061 ip_addr[0] = ntohl(sgid_addr.saddr_in.sin_addr.s_addr);
3062 ipv4 = true;
3063 vlan_id = irdma_get_vlan_ipv4(iwqp->cm_id, ip_addr);
3064 irdma_mcast_mac_v4(ip_addr, dmac);
3065 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_VERBS,
3066 "qp_id=%d, IP4address=%x, MAC=%x:%x:%x:%x:%x:%x\n",
3067 ibqp->qp_num, ip_addr[0], dmac[0], dmac[1], dmac[2],
3068 dmac[3], dmac[4], dmac[5]);
3069 }
3070
3071 spin_lock_irqsave(&rf->qh_list_lock, flags);
3072 mc_qht_elem = mcast_list_lookup_ip(rf, ip_addr);
3073 if (!mc_qht_elem) {
3074 struct irdma_dma_mem *dma_mem_mc;
3075
3076 spin_unlock_irqrestore(&rf->qh_list_lock, flags);
3077 mc_qht_elem = kzalloc(sizeof(*mc_qht_elem), GFP_KERNEL);
3078 if (!mc_qht_elem)
3079 return -ENOMEM;
3080
3081 mc_qht_elem->mc_info.ipv4_valid = ipv4;
3082 memcpy(mc_qht_elem->mc_info.dest_ip, ip_addr,
3083 sizeof(mc_qht_elem->mc_info.dest_ip));
3084 ret = irdma_alloc_rsrc(rf, rf->allocated_mcgs, rf->max_mcg,
3085 &mgn, &rf->next_mcg);
3086 if (ret) {
3087 kfree(mc_qht_elem);
3088 return -ENOMEM;
3089 }
3090
3091 mc_qht_elem->mc_info.mgn = mgn;
3092 dma_mem_mc = &mc_qht_elem->mc_grp_ctx.dma_mem_mc;
3093 dma_mem_mc->size = sizeof(u64)* IRDMA_MAX_MGS_PER_CTX;
3094 dma_mem_mc->va = irdma_allocate_dma_mem(&rf->hw, dma_mem_mc,
3095 dma_mem_mc->size,
3096 IRDMA_HW_PAGE_SIZE);
3097 if (!dma_mem_mc->va) {
3098 irdma_free_rsrc(rf, rf->allocated_mcgs, mgn);
3099 kfree(mc_qht_elem);
3100 return -ENOMEM;
3101 }
3102
3103 mc_qht_elem->mc_grp_ctx.mg_id = (u16)mgn;
3104 memcpy(mc_qht_elem->mc_grp_ctx.dest_ip_addr, ip_addr,
3105 sizeof(mc_qht_elem->mc_grp_ctx.dest_ip_addr));
3106 mc_qht_elem->mc_grp_ctx.ipv4_valid = ipv4;
3107 mc_qht_elem->mc_grp_ctx.vlan_id = vlan_id;
3108 if (vlan_id < VLAN_N_VID)
3109 mc_qht_elem->mc_grp_ctx.vlan_valid = true;
3110 mc_qht_elem->mc_grp_ctx.hmc_fcn_id = iwdev->rf->sc_dev.hmc_fn_id;
3111 mc_qht_elem->mc_grp_ctx.qs_handle =
3112 iwqp->sc_qp.vsi->qos[iwqp->sc_qp.user_pri].qs_handle;
3113 ether_addr_copy(mc_qht_elem->mc_grp_ctx.dest_mac_addr, dmac);
3114
3115 spin_lock_irqsave(&rf->qh_list_lock, flags);
3116 mcast_list_add(rf, mc_qht_elem);
3117 } else {
3118 if (mc_qht_elem->mc_grp_ctx.no_of_mgs ==
3119 IRDMA_MAX_MGS_PER_CTX) {
3120 spin_unlock_irqrestore(&rf->qh_list_lock, flags);
3121 return -ENOMEM;
3122 }
3123 }
3124
3125 mcg_info.qp_id = iwqp->ibqp.qp_num;
3126 no_mgs = mc_qht_elem->mc_grp_ctx.no_of_mgs;
3127 irdma_sc_add_mcast_grp(&mc_qht_elem->mc_grp_ctx, &mcg_info);
3128 spin_unlock_irqrestore(&rf->qh_list_lock, flags);
3129
3130 /* Only if there is a change do we need to modify or create */
3131 if (!no_mgs) {
3132 ret = irdma_mcast_cqp_op(iwdev, &mc_qht_elem->mc_grp_ctx,
3133 IRDMA_OP_MC_CREATE);
3134 } else if (no_mgs != mc_qht_elem->mc_grp_ctx.no_of_mgs) {
3135 ret = irdma_mcast_cqp_op(iwdev, &mc_qht_elem->mc_grp_ctx,
3136 IRDMA_OP_MC_MODIFY);
3137 } else {
3138 return 0;
3139 }
3140
3141 if (ret)
3142 goto error;
3143
3144 return 0;
3145
3146 error:
3147 irdma_sc_del_mcast_grp(&mc_qht_elem->mc_grp_ctx, &mcg_info);
3148 if (!mc_qht_elem->mc_grp_ctx.no_of_mgs) {
3149 mcast_list_del(mc_qht_elem);
3150 irdma_free_dma_mem(&rf->hw,
3151 &mc_qht_elem->mc_grp_ctx.dma_mem_mc);
3152 irdma_free_rsrc(rf, rf->allocated_mcgs,
3153 mc_qht_elem->mc_grp_ctx.mg_id);
3154 kfree(mc_qht_elem);
3155 }
3156
3157 return ret;
3158 }
3159
3160 /**
3161 * irdma_detach_mcast - detach a qp from a multicast group
3162 * @ibqp: ptr to qp
3163 * @ibgid: pointer to global ID
3164 * @lid: local ID
3165 *
3166 * returns error status
3167 */
3168 static int
irdma_detach_mcast(struct ib_qp * ibqp,union ib_gid * ibgid,u16 lid)3169 irdma_detach_mcast(struct ib_qp *ibqp, union ib_gid *ibgid, u16 lid)
3170 {
3171 struct irdma_qp *iwqp = to_iwqp(ibqp);
3172 struct irdma_device *iwdev = iwqp->iwdev;
3173 struct irdma_pci_f *rf = iwdev->rf;
3174 u32 ip_addr[4] = {0};
3175 struct mc_table_list *mc_qht_elem;
3176 struct irdma_mcast_grp_ctx_entry_info mcg_info = {0};
3177 int ret;
3178 unsigned long flags;
3179 union irdma_sockaddr sgid_addr;
3180
3181 rdma_gid2ip((struct sockaddr *)&sgid_addr, ibgid);
3182 if (!ipv6_addr_v4mapped((struct in6_addr *)ibgid))
3183 irdma_copy_ip_ntohl(ip_addr,
3184 sgid_addr.saddr_in6.sin6_addr.__u6_addr.__u6_addr32);
3185 else
3186 ip_addr[0] = ntohl(sgid_addr.saddr_in.sin_addr.s_addr);
3187
3188 spin_lock_irqsave(&rf->qh_list_lock, flags);
3189 mc_qht_elem = mcast_list_lookup_ip(rf, ip_addr);
3190 if (!mc_qht_elem) {
3191 spin_unlock_irqrestore(&rf->qh_list_lock, flags);
3192 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_VERBS,
3193 "address not found MCG\n");
3194 return 0;
3195 }
3196
3197 mcg_info.qp_id = iwqp->ibqp.qp_num;
3198 irdma_sc_del_mcast_grp(&mc_qht_elem->mc_grp_ctx, &mcg_info);
3199 if (!mc_qht_elem->mc_grp_ctx.no_of_mgs) {
3200 mcast_list_del(mc_qht_elem);
3201 spin_unlock_irqrestore(&rf->qh_list_lock, flags);
3202 ret = irdma_mcast_cqp_op(iwdev, &mc_qht_elem->mc_grp_ctx,
3203 IRDMA_OP_MC_DESTROY);
3204 if (ret) {
3205 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_VERBS,
3206 "failed MC_DESTROY MCG\n");
3207 spin_lock_irqsave(&rf->qh_list_lock, flags);
3208 mcast_list_add(rf, mc_qht_elem);
3209 spin_unlock_irqrestore(&rf->qh_list_lock, flags);
3210 return -EAGAIN;
3211 }
3212
3213 irdma_free_dma_mem(&rf->hw,
3214 &mc_qht_elem->mc_grp_ctx.dma_mem_mc);
3215 irdma_free_rsrc(rf, rf->allocated_mcgs,
3216 mc_qht_elem->mc_grp_ctx.mg_id);
3217 kfree(mc_qht_elem);
3218 } else {
3219 spin_unlock_irqrestore(&rf->qh_list_lock, flags);
3220 ret = irdma_mcast_cqp_op(iwdev, &mc_qht_elem->mc_grp_ctx,
3221 IRDMA_OP_MC_MODIFY);
3222 if (ret) {
3223 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_VERBS,
3224 "failed Modify MCG\n");
3225 return ret;
3226 }
3227 }
3228
3229 return 0;
3230 }
3231
3232 /**
3233 * irdma_query_ah - Query address handle
3234 * @ibah: pointer to address handle
3235 * @ah_attr: address handle attributes
3236 */
3237 static int
irdma_query_ah(struct ib_ah * ibah,struct rdma_ah_attr * ah_attr)3238 irdma_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr)
3239 {
3240 struct irdma_ah *ah = to_iwah(ibah);
3241
3242 memset(ah_attr, 0, sizeof(*ah_attr));
3243 ah_attr->type = ibah->type;
3244 if (rdma_ah_get_ah_flags(&ah->av.attrs) & IB_AH_GRH) {
3245 rdma_ah_set_grh(ah_attr, &ah->dgid,
3246 ah->sc_ah.ah_info.flow_label,
3247 ah->sgid_index,
3248 ah->sc_ah.ah_info.hop_ttl,
3249 ah->sc_ah.ah_info.tc_tos);
3250 }
3251
3252 return 0;
3253 }
3254
irdma_get_netdev(struct ib_device * ibdev,u8 port_num)3255 static if_t irdma_get_netdev(struct ib_device *ibdev, u8 port_num){
3256 struct irdma_device *iwdev = to_iwdev(ibdev);
3257
3258 if (iwdev->netdev) {
3259 dev_hold(iwdev->netdev);
3260 return iwdev->netdev;
3261 }
3262
3263 return NULL;
3264 }
3265
3266 static void
irdma_set_device_ops(struct ib_device * ibdev)3267 irdma_set_device_ops(struct ib_device *ibdev)
3268 {
3269 struct ib_device *dev_ops = ibdev;
3270
3271 dev_ops->ops.driver_id = RDMA_DRIVER_I40IW;
3272 dev_ops->ops.size_ib_ah = IRDMA_SET_RDMA_OBJ_SIZE(ib_ah, irdma_ah, ibah);
3273 dev_ops->ops.size_ib_cq = IRDMA_SET_RDMA_OBJ_SIZE(ib_cq, irdma_cq, ibcq);
3274 dev_ops->ops.size_ib_pd = IRDMA_SET_RDMA_OBJ_SIZE(ib_pd, irdma_pd, ibpd);
3275 dev_ops->ops.size_ib_ucontext = IRDMA_SET_RDMA_OBJ_SIZE(ib_ucontext,
3276 irdma_ucontext,
3277 ibucontext);
3278
3279 dev_ops->alloc_hw_stats = irdma_alloc_hw_stats;
3280 dev_ops->alloc_mr = irdma_alloc_mr;
3281 dev_ops->alloc_pd = irdma_alloc_pd;
3282 dev_ops->alloc_ucontext = irdma_alloc_ucontext;
3283 dev_ops->create_cq = irdma_create_cq;
3284 dev_ops->create_qp = irdma_create_qp;
3285 dev_ops->dealloc_pd = irdma_dealloc_pd;
3286 dev_ops->dealloc_ucontext = irdma_dealloc_ucontext;
3287 dev_ops->dereg_mr = irdma_dereg_mr;
3288 dev_ops->destroy_cq = irdma_destroy_cq;
3289 dev_ops->destroy_qp = irdma_destroy_qp;
3290 dev_ops->disassociate_ucontext = irdma_disassociate_ucontext;
3291 dev_ops->get_dev_fw_str = irdma_get_dev_fw_str;
3292 dev_ops->get_dma_mr = irdma_get_dma_mr;
3293 dev_ops->get_hw_stats = irdma_get_hw_stats;
3294 dev_ops->get_netdev = irdma_get_netdev;
3295 dev_ops->map_mr_sg = irdma_map_mr_sg;
3296 dev_ops->mmap = irdma_mmap;
3297 dev_ops->mmap_free = irdma_mmap_free;
3298 dev_ops->poll_cq = irdma_poll_cq;
3299 dev_ops->post_recv = irdma_post_recv;
3300 dev_ops->post_send = irdma_post_send;
3301 dev_ops->query_device = irdma_query_device;
3302 dev_ops->query_port = irdma_query_port;
3303 dev_ops->modify_port = irdma_modify_port;
3304 dev_ops->query_qp = irdma_query_qp;
3305 dev_ops->reg_user_mr = irdma_reg_user_mr;
3306 dev_ops->rereg_user_mr = irdma_rereg_user_mr;
3307 dev_ops->req_notify_cq = irdma_req_notify_cq;
3308 dev_ops->resize_cq = irdma_resize_cq;
3309 }
3310
3311 static void
irdma_set_device_mcast_ops(struct ib_device * ibdev)3312 irdma_set_device_mcast_ops(struct ib_device *ibdev)
3313 {
3314 struct ib_device *dev_ops = ibdev;
3315
3316 dev_ops->attach_mcast = irdma_attach_mcast;
3317 dev_ops->detach_mcast = irdma_detach_mcast;
3318 }
3319
3320 static void
irdma_set_device_roce_ops(struct ib_device * ibdev)3321 irdma_set_device_roce_ops(struct ib_device *ibdev)
3322 {
3323 struct ib_device *dev_ops = ibdev;
3324
3325 dev_ops->create_ah = irdma_create_ah;
3326 dev_ops->destroy_ah = irdma_destroy_ah;
3327 dev_ops->get_link_layer = irdma_get_link_layer;
3328 dev_ops->get_port_immutable = irdma_roce_port_immutable;
3329 dev_ops->modify_qp = irdma_modify_qp_roce;
3330 dev_ops->query_ah = irdma_query_ah;
3331 dev_ops->query_pkey = irdma_query_pkey;
3332 ibdev->add_gid = irdma_add_gid;
3333 ibdev->del_gid = irdma_del_gid;
3334 }
3335
3336 static void
irdma_set_device_iw_ops(struct ib_device * ibdev)3337 irdma_set_device_iw_ops(struct ib_device *ibdev)
3338 {
3339 struct ib_device *dev_ops = ibdev;
3340
3341 ibdev->uverbs_cmd_mask |=
3342 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
3343 (1ull << IB_USER_VERBS_CMD_DESTROY_AH);
3344
3345 dev_ops->create_ah = irdma_create_ah_stub;
3346 dev_ops->destroy_ah = irdma_destroy_ah_stub;
3347 dev_ops->get_port_immutable = irdma_iw_port_immutable;
3348 dev_ops->modify_qp = irdma_modify_qp;
3349 dev_ops->query_gid = irdma_query_gid;
3350 dev_ops->query_pkey = irdma_iw_query_pkey;
3351 }
3352
3353 static inline void
irdma_set_device_gen1_ops(struct ib_device * ibdev)3354 irdma_set_device_gen1_ops(struct ib_device *ibdev)
3355 {
3356 }
3357
3358 /**
3359 * irdma_init_roce_device - initialization of roce rdma device
3360 * @iwdev: irdma device
3361 */
3362 static void
irdma_init_roce_device(struct irdma_device * iwdev)3363 irdma_init_roce_device(struct irdma_device *iwdev)
3364 {
3365 kc_set_roce_uverbs_cmd_mask(iwdev);
3366 iwdev->ibdev.node_type = RDMA_NODE_IB_CA;
3367 addrconf_addr_eui48((u8 *)&iwdev->ibdev.node_guid,
3368 if_getlladdr(iwdev->netdev));
3369 irdma_set_device_roce_ops(&iwdev->ibdev);
3370 if (iwdev->rf->rdma_ver == IRDMA_GEN_2)
3371 irdma_set_device_mcast_ops(&iwdev->ibdev);
3372 }
3373
3374 /**
3375 * irdma_init_iw_device - initialization of iwarp rdma device
3376 * @iwdev: irdma device
3377 */
3378 static int
irdma_init_iw_device(struct irdma_device * iwdev)3379 irdma_init_iw_device(struct irdma_device *iwdev)
3380 {
3381 if_t netdev = iwdev->netdev;
3382
3383 iwdev->ibdev.node_type = RDMA_NODE_RNIC;
3384 addrconf_addr_eui48((u8 *)&iwdev->ibdev.node_guid,
3385 if_getlladdr(netdev));
3386 iwdev->ibdev.iwcm = kzalloc(sizeof(*iwdev->ibdev.iwcm), GFP_KERNEL);
3387 if (!iwdev->ibdev.iwcm)
3388 return -ENOMEM;
3389
3390 iwdev->ibdev.iwcm->add_ref = irdma_qp_add_ref;
3391 iwdev->ibdev.iwcm->rem_ref = irdma_qp_rem_ref;
3392 iwdev->ibdev.iwcm->get_qp = irdma_get_qp;
3393 iwdev->ibdev.iwcm->connect = irdma_connect;
3394 iwdev->ibdev.iwcm->accept = irdma_accept;
3395 iwdev->ibdev.iwcm->reject = irdma_reject;
3396 iwdev->ibdev.iwcm->create_listen = irdma_create_listen;
3397 iwdev->ibdev.iwcm->destroy_listen = irdma_destroy_listen;
3398 memcpy(iwdev->ibdev.iwcm->ifname, if_name(netdev),
3399 sizeof(iwdev->ibdev.iwcm->ifname));
3400 irdma_set_device_iw_ops(&iwdev->ibdev);
3401
3402 return 0;
3403 }
3404
3405 /**
3406 * irdma_init_rdma_device - initialization of rdma device
3407 * @iwdev: irdma device
3408 */
3409 static int
irdma_init_rdma_device(struct irdma_device * iwdev)3410 irdma_init_rdma_device(struct irdma_device *iwdev)
3411 {
3412 int ret;
3413
3414 iwdev->ibdev.owner = THIS_MODULE;
3415 iwdev->ibdev.uverbs_abi_ver = IRDMA_ABI_VER;
3416 kc_set_rdma_uverbs_cmd_mask(iwdev);
3417
3418 if (iwdev->roce_mode) {
3419 irdma_init_roce_device(iwdev);
3420 } else {
3421 ret = irdma_init_iw_device(iwdev);
3422 if (ret)
3423 return ret;
3424 }
3425
3426 iwdev->ibdev.phys_port_cnt = 1;
3427 iwdev->ibdev.num_comp_vectors = iwdev->rf->ceqs_count;
3428 iwdev->ibdev.dev.parent = iwdev->rf->dev_ctx.dev;
3429 set_ibdev_dma_device(iwdev->ibdev, &iwdev->rf->pcidev->dev);
3430 irdma_set_device_ops(&iwdev->ibdev);
3431 if (iwdev->rf->rdma_ver == IRDMA_GEN_1)
3432 irdma_set_device_gen1_ops(&iwdev->ibdev);
3433
3434 return 0;
3435 }
3436
3437 /**
3438 * irdma_port_ibevent - indicate port event
3439 * @iwdev: irdma device
3440 */
3441 void
irdma_port_ibevent(struct irdma_device * iwdev)3442 irdma_port_ibevent(struct irdma_device *iwdev)
3443 {
3444 struct ib_event event;
3445
3446 event.device = &iwdev->ibdev;
3447 event.element.port_num = 1;
3448 event.event =
3449 iwdev->iw_status ? IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
3450 ib_dispatch_event(&event);
3451 }
3452
3453 /**
3454 * irdma_ib_unregister_device - unregister rdma device from IB
3455 * core
3456 * @iwdev: irdma device
3457 */
3458 void
irdma_ib_unregister_device(struct irdma_device * iwdev)3459 irdma_ib_unregister_device(struct irdma_device *iwdev)
3460 {
3461 iwdev->iw_status = 0;
3462 irdma_port_ibevent(iwdev);
3463 ib_unregister_device(&iwdev->ibdev);
3464 dev_put(iwdev->netdev);
3465 kfree(iwdev->ibdev.iwcm);
3466 iwdev->ibdev.iwcm = NULL;
3467 }
3468
3469 /**
3470 * irdma_ib_register_device - register irdma device to IB core
3471 * @iwdev: irdma device
3472 */
3473 int
irdma_ib_register_device(struct irdma_device * iwdev)3474 irdma_ib_register_device(struct irdma_device *iwdev)
3475 {
3476 int ret;
3477
3478 ret = irdma_init_rdma_device(iwdev);
3479 if (ret)
3480 return ret;
3481
3482 dev_hold(iwdev->netdev);
3483 sprintf(iwdev->ibdev.name, "irdma-%s", if_name(iwdev->netdev));
3484 ret = ib_register_device(&iwdev->ibdev, NULL);
3485 if (ret)
3486 goto error;
3487
3488 iwdev->iw_status = 1;
3489 irdma_port_ibevent(iwdev);
3490
3491 return 0;
3492
3493 error:
3494 kfree(iwdev->ibdev.iwcm);
3495 iwdev->ibdev.iwcm = NULL;
3496 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_VERBS, "Register RDMA device fail\n");
3497
3498 return ret;
3499 }
3500