1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
4 * Copyright (C) 2023 Vivo Communication Technology Co. Ltd.
5 * Authors: Yangtao Li <frank.li@vivo.com>
6 */
7
8 #include <dt-bindings/clock/thead,th1520-clk-ap.h>
9 #include <linux/bitfield.h>
10 #include <linux/clk-provider.h>
11 #include <linux/device.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/regmap.h>
15
16 #define TH1520_PLL_POSTDIV2 GENMASK(26, 24)
17 #define TH1520_PLL_POSTDIV1 GENMASK(22, 20)
18 #define TH1520_PLL_FBDIV GENMASK(19, 8)
19 #define TH1520_PLL_REFDIV GENMASK(5, 0)
20 #define TH1520_PLL_BYPASS BIT(30)
21 #define TH1520_PLL_VCO_RST BIT(29)
22 #define TH1520_PLL_DSMPD BIT(24)
23 #define TH1520_PLL_FRAC GENMASK(23, 0)
24 #define TH1520_PLL_FRAC_BITS 24
25
26 struct ccu_internal {
27 u8 shift;
28 u8 width;
29 };
30
31 struct ccu_div_internal {
32 u8 shift;
33 u8 width;
34 u32 flags;
35 };
36
37 struct ccu_common {
38 int clkid;
39 struct regmap *map;
40 u16 cfg0;
41 u16 cfg1;
42 struct clk_hw hw;
43 };
44
45 struct ccu_mux {
46 int clkid;
47 u32 reg;
48 struct clk_mux mux;
49 };
50
51 struct ccu_gate {
52 int clkid;
53 u32 reg;
54 struct clk_gate gate;
55 };
56
57 struct ccu_div {
58 u32 enable;
59 u32 div_en;
60 struct ccu_div_internal div;
61 struct ccu_internal mux;
62 struct ccu_common common;
63 };
64
65 struct ccu_pll {
66 struct ccu_common common;
67 };
68
69 #define TH_CCU_ARG(_shift, _width) \
70 { \
71 .shift = _shift, \
72 .width = _width, \
73 }
74
75 #define TH_CCU_DIV_FLAGS(_shift, _width, _flags) \
76 { \
77 .shift = _shift, \
78 .width = _width, \
79 .flags = _flags, \
80 }
81
82 #define TH_CCU_MUX(_name, _parents, _shift, _width) \
83 { \
84 .mask = GENMASK(_width - 1, 0), \
85 .shift = _shift, \
86 .hw.init = CLK_HW_INIT_PARENTS_DATA( \
87 _name, \
88 _parents, \
89 &clk_mux_ops, \
90 0), \
91 }
92
93 #define CCU_GATE(_clkid, _struct, _name, _parent, _reg, _bit, _flags) \
94 struct ccu_gate _struct = { \
95 .clkid = _clkid, \
96 .reg = _reg, \
97 .gate = { \
98 .bit_idx = _bit, \
99 .hw.init = CLK_HW_INIT_PARENTS_DATA( \
100 _name, \
101 _parent, \
102 &clk_gate_ops, \
103 _flags), \
104 } \
105 }
106
hw_to_ccu_common(struct clk_hw * hw)107 static inline struct ccu_common *hw_to_ccu_common(struct clk_hw *hw)
108 {
109 return container_of(hw, struct ccu_common, hw);
110 }
111
hw_to_ccu_pll(struct clk_hw * hw)112 static inline struct ccu_pll *hw_to_ccu_pll(struct clk_hw *hw)
113 {
114 struct ccu_common *common = hw_to_ccu_common(hw);
115
116 return container_of(common, struct ccu_pll, common);
117 }
118
hw_to_ccu_div(struct clk_hw * hw)119 static inline struct ccu_div *hw_to_ccu_div(struct clk_hw *hw)
120 {
121 struct ccu_common *common = hw_to_ccu_common(hw);
122
123 return container_of(common, struct ccu_div, common);
124 }
125
ccu_get_parent_helper(struct ccu_common * common,struct ccu_internal * mux)126 static u8 ccu_get_parent_helper(struct ccu_common *common,
127 struct ccu_internal *mux)
128 {
129 unsigned int val;
130 u8 parent;
131
132 regmap_read(common->map, common->cfg0, &val);
133 parent = val >> mux->shift;
134 parent &= GENMASK(mux->width - 1, 0);
135
136 return parent;
137 }
138
ccu_set_parent_helper(struct ccu_common * common,struct ccu_internal * mux,u8 index)139 static int ccu_set_parent_helper(struct ccu_common *common,
140 struct ccu_internal *mux,
141 u8 index)
142 {
143 return regmap_update_bits(common->map, common->cfg0,
144 GENMASK(mux->width - 1, 0) << mux->shift,
145 index << mux->shift);
146 }
147
ccu_disable_helper(struct ccu_common * common,u32 gate)148 static void ccu_disable_helper(struct ccu_common *common, u32 gate)
149 {
150 if (!gate)
151 return;
152 regmap_update_bits(common->map, common->cfg0,
153 gate, ~gate);
154 }
155
ccu_enable_helper(struct ccu_common * common,u32 gate)156 static int ccu_enable_helper(struct ccu_common *common, u32 gate)
157 {
158 unsigned int val;
159 int ret;
160
161 if (!gate)
162 return 0;
163
164 ret = regmap_update_bits(common->map, common->cfg0, gate, gate);
165 regmap_read(common->map, common->cfg0, &val);
166 return ret;
167 }
168
ccu_is_enabled_helper(struct ccu_common * common,u32 gate)169 static int ccu_is_enabled_helper(struct ccu_common *common, u32 gate)
170 {
171 unsigned int val;
172
173 if (!gate)
174 return true;
175
176 regmap_read(common->map, common->cfg0, &val);
177 return val & gate;
178 }
179
ccu_div_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)180 static unsigned long ccu_div_recalc_rate(struct clk_hw *hw,
181 unsigned long parent_rate)
182 {
183 struct ccu_div *cd = hw_to_ccu_div(hw);
184 unsigned long rate;
185 unsigned int val;
186
187 regmap_read(cd->common.map, cd->common.cfg0, &val);
188 val = val >> cd->div.shift;
189 val &= GENMASK(cd->div.width - 1, 0);
190 rate = divider_recalc_rate(hw, parent_rate, val, NULL,
191 cd->div.flags, cd->div.width);
192
193 return rate;
194 }
195
ccu_div_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)196 static int ccu_div_determine_rate(struct clk_hw *hw,
197 struct clk_rate_request *req)
198 {
199 struct ccu_div *cd = hw_to_ccu_div(hw);
200 unsigned int val;
201
202 if (cd->div_en)
203 return divider_determine_rate(hw, req, NULL,
204 cd->div.width, cd->div.flags);
205
206 regmap_read(cd->common.map, cd->common.cfg0, &val);
207 val = val >> cd->div.shift;
208 val &= GENMASK(cd->div.width - 1, 0);
209 return divider_ro_determine_rate(hw, req, NULL, cd->div.width,
210 cd->div.flags, val);
211 }
212
ccu_div_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)213 static int ccu_div_set_rate(struct clk_hw *hw, unsigned long rate,
214 unsigned long parent_rate)
215 {
216 struct ccu_div *cd = hw_to_ccu_div(hw);
217 int val = divider_get_val(rate, parent_rate, NULL,
218 cd->div.width, cd->div.flags);
219 unsigned int curr_val, reg_val;
220
221 if (val < 0)
222 return val;
223
224 regmap_read(cd->common.map, cd->common.cfg0, ®_val);
225 curr_val = reg_val >> cd->div.shift;
226 curr_val &= GENMASK(cd->div.width - 1, 0);
227
228 if (!cd->div_en && curr_val != val)
229 return -EINVAL;
230
231 reg_val &= ~cd->div_en;
232 regmap_write(cd->common.map, cd->common.cfg0, reg_val);
233 udelay(1);
234
235 reg_val &= ~GENMASK(cd->div.width + cd->div.shift - 1, cd->div.shift);
236 reg_val |= val << cd->div.shift;
237 regmap_write(cd->common.map, cd->common.cfg0, reg_val);
238
239 reg_val |= cd->div_en;
240 regmap_write(cd->common.map, cd->common.cfg0, reg_val);
241
242 return 0;
243 }
244
ccu_div_get_parent(struct clk_hw * hw)245 static u8 ccu_div_get_parent(struct clk_hw *hw)
246 {
247 struct ccu_div *cd = hw_to_ccu_div(hw);
248
249 return ccu_get_parent_helper(&cd->common, &cd->mux);
250 }
251
ccu_div_set_parent(struct clk_hw * hw,u8 index)252 static int ccu_div_set_parent(struct clk_hw *hw, u8 index)
253 {
254 struct ccu_div *cd = hw_to_ccu_div(hw);
255
256 return ccu_set_parent_helper(&cd->common, &cd->mux, index);
257 }
258
ccu_div_disable(struct clk_hw * hw)259 static void ccu_div_disable(struct clk_hw *hw)
260 {
261 struct ccu_div *cd = hw_to_ccu_div(hw);
262
263 ccu_disable_helper(&cd->common, cd->enable);
264 }
265
ccu_div_enable(struct clk_hw * hw)266 static int ccu_div_enable(struct clk_hw *hw)
267 {
268 struct ccu_div *cd = hw_to_ccu_div(hw);
269
270 return ccu_enable_helper(&cd->common, cd->enable);
271 }
272
ccu_div_is_enabled(struct clk_hw * hw)273 static int ccu_div_is_enabled(struct clk_hw *hw)
274 {
275 struct ccu_div *cd = hw_to_ccu_div(hw);
276
277 return ccu_is_enabled_helper(&cd->common, cd->enable);
278 }
279
280 static const struct clk_ops ccu_div_ops = {
281 .disable = ccu_div_disable,
282 .enable = ccu_div_enable,
283 .is_enabled = ccu_div_is_enabled,
284 .get_parent = ccu_div_get_parent,
285 .set_parent = ccu_div_set_parent,
286 .recalc_rate = ccu_div_recalc_rate,
287 .set_rate = ccu_div_set_rate,
288 .determine_rate = ccu_div_determine_rate,
289 };
290
ccu_pll_disable(struct clk_hw * hw)291 static void ccu_pll_disable(struct clk_hw *hw)
292 {
293 struct ccu_pll *pll = hw_to_ccu_pll(hw);
294
295 regmap_set_bits(pll->common.map, pll->common.cfg1,
296 TH1520_PLL_VCO_RST);
297 }
298
ccu_pll_enable(struct clk_hw * hw)299 static int ccu_pll_enable(struct clk_hw *hw)
300 {
301 struct ccu_pll *pll = hw_to_ccu_pll(hw);
302
303 return regmap_clear_bits(pll->common.map, pll->common.cfg1,
304 TH1520_PLL_VCO_RST);
305 }
306
ccu_pll_is_enabled(struct clk_hw * hw)307 static int ccu_pll_is_enabled(struct clk_hw *hw)
308 {
309 struct ccu_pll *pll = hw_to_ccu_pll(hw);
310
311 return !regmap_test_bits(pll->common.map, pll->common.cfg1,
312 TH1520_PLL_VCO_RST);
313 }
314
th1520_pll_vco_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)315 static unsigned long th1520_pll_vco_recalc_rate(struct clk_hw *hw,
316 unsigned long parent_rate)
317 {
318 struct ccu_pll *pll = hw_to_ccu_pll(hw);
319 unsigned long div, mul, frac;
320 unsigned int cfg0, cfg1;
321 u64 rate = parent_rate;
322
323 regmap_read(pll->common.map, pll->common.cfg0, &cfg0);
324 regmap_read(pll->common.map, pll->common.cfg1, &cfg1);
325
326 mul = FIELD_GET(TH1520_PLL_FBDIV, cfg0);
327 div = FIELD_GET(TH1520_PLL_REFDIV, cfg0);
328 if (!(cfg1 & TH1520_PLL_DSMPD)) {
329 mul <<= TH1520_PLL_FRAC_BITS;
330 frac = FIELD_GET(TH1520_PLL_FRAC, cfg1);
331 mul += frac;
332 div <<= TH1520_PLL_FRAC_BITS;
333 }
334 rate = parent_rate * mul;
335 rate = rate / div;
336 return rate;
337 }
338
th1520_pll_postdiv_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)339 static unsigned long th1520_pll_postdiv_recalc_rate(struct clk_hw *hw,
340 unsigned long parent_rate)
341 {
342 struct ccu_pll *pll = hw_to_ccu_pll(hw);
343 unsigned long div, rate = parent_rate;
344 unsigned int cfg0, cfg1;
345
346 regmap_read(pll->common.map, pll->common.cfg0, &cfg0);
347 regmap_read(pll->common.map, pll->common.cfg1, &cfg1);
348
349 if (cfg1 & TH1520_PLL_BYPASS)
350 return rate;
351
352 div = FIELD_GET(TH1520_PLL_POSTDIV1, cfg0) *
353 FIELD_GET(TH1520_PLL_POSTDIV2, cfg0);
354
355 rate = rate / div;
356
357 return rate;
358 }
359
ccu_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)360 static unsigned long ccu_pll_recalc_rate(struct clk_hw *hw,
361 unsigned long parent_rate)
362 {
363 unsigned long rate = parent_rate;
364
365 rate = th1520_pll_vco_recalc_rate(hw, rate);
366 rate = th1520_pll_postdiv_recalc_rate(hw, rate);
367
368 return rate;
369 }
370
371 static const struct clk_ops clk_pll_ops = {
372 .disable = ccu_pll_disable,
373 .enable = ccu_pll_enable,
374 .is_enabled = ccu_pll_is_enabled,
375 .recalc_rate = ccu_pll_recalc_rate,
376 };
377
378 static const struct clk_parent_data osc_24m_clk[] = {
379 { .index = 0 }
380 };
381
382 static struct ccu_pll cpu_pll0_clk = {
383 .common = {
384 .clkid = CLK_CPU_PLL0,
385 .cfg0 = 0x000,
386 .cfg1 = 0x004,
387 .hw.init = CLK_HW_INIT_PARENTS_DATA("cpu-pll0",
388 osc_24m_clk,
389 &clk_pll_ops,
390 CLK_IS_CRITICAL),
391 },
392 };
393
394 static struct ccu_pll cpu_pll1_clk = {
395 .common = {
396 .clkid = CLK_CPU_PLL1,
397 .cfg0 = 0x010,
398 .cfg1 = 0x014,
399 .hw.init = CLK_HW_INIT_PARENTS_DATA("cpu-pll1",
400 osc_24m_clk,
401 &clk_pll_ops,
402 CLK_IS_CRITICAL),
403 },
404 };
405
406 static struct ccu_pll gmac_pll_clk = {
407 .common = {
408 .clkid = CLK_GMAC_PLL,
409 .cfg0 = 0x020,
410 .cfg1 = 0x024,
411 .hw.init = CLK_HW_INIT_PARENTS_DATA("gmac-pll",
412 osc_24m_clk,
413 &clk_pll_ops,
414 CLK_IS_CRITICAL),
415 },
416 };
417
418 static const struct clk_hw *gmac_pll_clk_parent[] = {
419 &gmac_pll_clk.common.hw
420 };
421
422 static const struct clk_parent_data gmac_pll_clk_pd[] = {
423 { .hw = &gmac_pll_clk.common.hw }
424 };
425
426 static struct ccu_pll video_pll_clk = {
427 .common = {
428 .clkid = CLK_VIDEO_PLL,
429 .cfg0 = 0x030,
430 .cfg1 = 0x034,
431 .hw.init = CLK_HW_INIT_PARENTS_DATA("video-pll",
432 osc_24m_clk,
433 &clk_pll_ops,
434 CLK_IS_CRITICAL),
435 },
436 };
437
438 static const struct clk_hw *video_pll_clk_parent[] = {
439 &video_pll_clk.common.hw
440 };
441
442 static const struct clk_parent_data video_pll_clk_pd[] = {
443 { .hw = &video_pll_clk.common.hw }
444 };
445
446 static struct ccu_pll dpu0_pll_clk = {
447 .common = {
448 .clkid = CLK_DPU0_PLL,
449 .cfg0 = 0x040,
450 .cfg1 = 0x044,
451 .hw.init = CLK_HW_INIT_PARENTS_DATA("dpu0-pll",
452 osc_24m_clk,
453 &clk_pll_ops,
454 0),
455 },
456 };
457
458 static const struct clk_hw *dpu0_pll_clk_parent[] = {
459 &dpu0_pll_clk.common.hw
460 };
461
462 static struct ccu_pll dpu1_pll_clk = {
463 .common = {
464 .clkid = CLK_DPU1_PLL,
465 .cfg0 = 0x050,
466 .cfg1 = 0x054,
467 .hw.init = CLK_HW_INIT_PARENTS_DATA("dpu1-pll",
468 osc_24m_clk,
469 &clk_pll_ops,
470 0),
471 },
472 };
473
474 static const struct clk_hw *dpu1_pll_clk_parent[] = {
475 &dpu1_pll_clk.common.hw
476 };
477
478 static struct ccu_pll tee_pll_clk = {
479 .common = {
480 .clkid = CLK_TEE_PLL,
481 .cfg0 = 0x060,
482 .cfg1 = 0x064,
483 .hw.init = CLK_HW_INIT_PARENTS_DATA("tee-pll",
484 osc_24m_clk,
485 &clk_pll_ops,
486 CLK_IS_CRITICAL),
487 },
488 };
489
490 static const struct clk_parent_data c910_i0_parents[] = {
491 { .hw = &cpu_pll0_clk.common.hw },
492 { .index = 0 }
493 };
494
495 static struct ccu_mux c910_i0_clk = {
496 .clkid = CLK_C910_I0,
497 .reg = 0x100,
498 .mux = TH_CCU_MUX("c910-i0", c910_i0_parents, 1, 1),
499 };
500
501 static const struct clk_parent_data c910_parents[] = {
502 { .hw = &c910_i0_clk.mux.hw },
503 { .hw = &cpu_pll1_clk.common.hw }
504 };
505
506 static struct ccu_mux c910_clk = {
507 .clkid = CLK_C910,
508 .reg = 0x100,
509 .mux = TH_CCU_MUX("c910", c910_parents, 0, 1),
510 };
511
512 static const struct clk_parent_data ahb2_cpusys_parents[] = {
513 { .hw = &gmac_pll_clk.common.hw },
514 { .index = 0 }
515 };
516
517 static struct ccu_div ahb2_cpusys_hclk = {
518 .div = TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED),
519 .mux = TH_CCU_ARG(5, 1),
520 .common = {
521 .clkid = CLK_AHB2_CPUSYS_HCLK,
522 .cfg0 = 0x120,
523 .hw.init = CLK_HW_INIT_PARENTS_DATA("ahb2-cpusys-hclk",
524 ahb2_cpusys_parents,
525 &ccu_div_ops,
526 0),
527 },
528 };
529
530 static const struct clk_parent_data ahb2_cpusys_hclk_pd[] = {
531 { .hw = &ahb2_cpusys_hclk.common.hw }
532 };
533
534 static const struct clk_hw *ahb2_cpusys_hclk_parent[] = {
535 &ahb2_cpusys_hclk.common.hw,
536 };
537
538 static struct ccu_div apb3_cpusys_pclk = {
539 .div = TH_CCU_ARG(0, 3),
540 .common = {
541 .clkid = CLK_APB3_CPUSYS_PCLK,
542 .cfg0 = 0x130,
543 .hw.init = CLK_HW_INIT_PARENTS_HW("apb3-cpusys-pclk",
544 ahb2_cpusys_hclk_parent,
545 &ccu_div_ops,
546 0),
547 },
548 };
549
550 static const struct clk_parent_data apb3_cpusys_pclk_pd[] = {
551 { .hw = &apb3_cpusys_pclk.common.hw }
552 };
553
554 static struct ccu_div axi4_cpusys2_aclk = {
555 .div = TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED),
556 .common = {
557 .clkid = CLK_AXI4_CPUSYS2_ACLK,
558 .cfg0 = 0x134,
559 .hw.init = CLK_HW_INIT_PARENTS_HW("axi4-cpusys2-aclk",
560 gmac_pll_clk_parent,
561 &ccu_div_ops,
562 CLK_IS_CRITICAL),
563 },
564 };
565
566 static const struct clk_parent_data axi4_cpusys2_aclk_pd[] = {
567 { .hw = &axi4_cpusys2_aclk.common.hw }
568 };
569
570 static const struct clk_parent_data axi_parents[] = {
571 { .hw = &video_pll_clk.common.hw },
572 { .index = 0 }
573 };
574
575 static struct ccu_div axi_aclk = {
576 .div = TH_CCU_DIV_FLAGS(0, 4, CLK_DIVIDER_ONE_BASED),
577 .mux = TH_CCU_ARG(5, 1),
578 .common = {
579 .clkid = CLK_AXI_ACLK,
580 .cfg0 = 0x138,
581 .hw.init = CLK_HW_INIT_PARENTS_DATA("axi-aclk",
582 axi_parents,
583 &ccu_div_ops,
584 CLK_IS_CRITICAL),
585 },
586 };
587
588 static const struct clk_parent_data axi_aclk_pd[] = {
589 { .hw = &axi_aclk.common.hw }
590 };
591
592 static const struct clk_parent_data perisys_ahb_hclk_parents[] = {
593 { .hw = &gmac_pll_clk.common.hw },
594 { .index = 0 },
595 };
596
597 static struct ccu_div perisys_ahb_hclk = {
598 .enable = BIT(6),
599 .div = TH_CCU_DIV_FLAGS(0, 4, CLK_DIVIDER_ONE_BASED),
600 .mux = TH_CCU_ARG(5, 1),
601 .common = {
602 .clkid = CLK_PERI_AHB_HCLK,
603 .cfg0 = 0x140,
604 .hw.init = CLK_HW_INIT_PARENTS_DATA("perisys-ahb-hclk",
605 perisys_ahb_hclk_parents,
606 &ccu_div_ops,
607 0),
608 },
609 };
610
611 static const struct clk_parent_data perisys_ahb_hclk_pd[] = {
612 { .hw = &perisys_ahb_hclk.common.hw }
613 };
614
615 static const struct clk_hw *perisys_ahb_hclk_parent[] = {
616 &perisys_ahb_hclk.common.hw
617 };
618
619 static struct ccu_div perisys_apb_pclk = {
620 .div = TH_CCU_ARG(0, 3),
621 .common = {
622 .clkid = CLK_PERI_APB_PCLK,
623 .cfg0 = 0x150,
624 .hw.init = CLK_HW_INIT_PARENTS_HW("perisys-apb-pclk",
625 perisys_ahb_hclk_parent,
626 &ccu_div_ops,
627 0),
628 },
629 };
630
631 static const struct clk_parent_data perisys_apb_pclk_pd[] = {
632 { .hw = &perisys_apb_pclk.common.hw }
633 };
634
635 static struct ccu_div peri2sys_apb_pclk = {
636 .div = TH_CCU_DIV_FLAGS(4, 3, CLK_DIVIDER_ONE_BASED),
637 .common = {
638 .clkid = CLK_PERI2APB_PCLK,
639 .cfg0 = 0x150,
640 .hw.init = CLK_HW_INIT_PARENTS_HW("peri2sys-apb-pclk",
641 gmac_pll_clk_parent,
642 &ccu_div_ops,
643 0),
644 },
645 };
646
647 static const struct clk_parent_data peri2sys_apb_pclk_pd[] = {
648 { .hw = &peri2sys_apb_pclk.common.hw }
649 };
650
651 static struct clk_fixed_factor osc12m_clk = {
652 .div = 2,
653 .mult = 1,
654 .hw.init = CLK_HW_INIT_PARENTS_DATA("osc_12m",
655 osc_24m_clk,
656 &clk_fixed_factor_ops,
657 0),
658 };
659
660 static const char * const out_parents[] = { "osc_24m", "osc_12m" };
661
662 static struct ccu_div out1_clk = {
663 .enable = BIT(5),
664 .div = TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED),
665 .mux = TH_CCU_ARG(4, 1),
666 .common = {
667 .clkid = CLK_OUT1,
668 .cfg0 = 0x1b4,
669 .hw.init = CLK_HW_INIT_PARENTS("out1",
670 out_parents,
671 &ccu_div_ops,
672 0),
673 },
674 };
675
676 static struct ccu_div out2_clk = {
677 .enable = BIT(5),
678 .div = TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED),
679 .mux = TH_CCU_ARG(4, 1),
680 .common = {
681 .clkid = CLK_OUT2,
682 .cfg0 = 0x1b8,
683 .hw.init = CLK_HW_INIT_PARENTS("out2",
684 out_parents,
685 &ccu_div_ops,
686 0),
687 },
688 };
689
690 static struct ccu_div out3_clk = {
691 .enable = BIT(5),
692 .div = TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED),
693 .mux = TH_CCU_ARG(4, 1),
694 .common = {
695 .clkid = CLK_OUT3,
696 .cfg0 = 0x1bc,
697 .hw.init = CLK_HW_INIT_PARENTS("out3",
698 out_parents,
699 &ccu_div_ops,
700 0),
701 },
702 };
703
704 static struct ccu_div out4_clk = {
705 .enable = BIT(5),
706 .div = TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED),
707 .mux = TH_CCU_ARG(4, 1),
708 .common = {
709 .clkid = CLK_OUT4,
710 .cfg0 = 0x1c0,
711 .hw.init = CLK_HW_INIT_PARENTS("out4",
712 out_parents,
713 &ccu_div_ops,
714 0),
715 },
716 };
717
718 static const struct clk_parent_data apb_parents[] = {
719 { .hw = &gmac_pll_clk.common.hw },
720 { .index = 0 },
721 };
722
723 static struct ccu_div apb_pclk = {
724 .enable = BIT(5),
725 .div = TH_CCU_DIV_FLAGS(0, 4, CLK_DIVIDER_ONE_BASED),
726 .mux = TH_CCU_ARG(7, 1),
727 .common = {
728 .clkid = CLK_APB_PCLK,
729 .cfg0 = 0x1c4,
730 .hw.init = CLK_HW_INIT_PARENTS_DATA("apb-pclk",
731 apb_parents,
732 &ccu_div_ops,
733 CLK_IS_CRITICAL),
734 },
735 };
736
737 static const struct clk_hw *npu_parents[] = {
738 &gmac_pll_clk.common.hw,
739 &video_pll_clk.common.hw
740 };
741
742 static struct ccu_div npu_clk = {
743 .enable = BIT(4),
744 .div = TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED),
745 .mux = TH_CCU_ARG(6, 1),
746 .common = {
747 .clkid = CLK_NPU,
748 .cfg0 = 0x1c8,
749 .hw.init = CLK_HW_INIT_PARENTS_HW("npu",
750 npu_parents,
751 &ccu_div_ops,
752 0),
753 },
754 };
755
756 static struct ccu_div vi_clk = {
757 .div = TH_CCU_DIV_FLAGS(16, 4, CLK_DIVIDER_ONE_BASED),
758 .common = {
759 .clkid = CLK_VI,
760 .cfg0 = 0x1d0,
761 .hw.init = CLK_HW_INIT_PARENTS_HW("vi",
762 video_pll_clk_parent,
763 &ccu_div_ops,
764 CLK_IS_CRITICAL),
765 },
766 };
767
768 static struct ccu_div vi_ahb_clk = {
769 .div = TH_CCU_DIV_FLAGS(0, 4, CLK_DIVIDER_ONE_BASED),
770 .common = {
771 .clkid = CLK_VI_AHB,
772 .cfg0 = 0x1d0,
773 .hw.init = CLK_HW_INIT_PARENTS_HW("vi-ahb",
774 video_pll_clk_parent,
775 &ccu_div_ops,
776 0),
777 },
778 };
779
780 static struct ccu_div vo_axi_clk = {
781 .enable = BIT(5),
782 .div = TH_CCU_DIV_FLAGS(0, 4, CLK_DIVIDER_ONE_BASED),
783 .common = {
784 .clkid = CLK_VO_AXI,
785 .cfg0 = 0x1dc,
786 .hw.init = CLK_HW_INIT_PARENTS_HW("vo-axi",
787 video_pll_clk_parent,
788 &ccu_div_ops,
789 CLK_IS_CRITICAL),
790 },
791 };
792
793 static struct ccu_div vp_apb_clk = {
794 .div = TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED),
795 .common = {
796 .clkid = CLK_VP_APB,
797 .cfg0 = 0x1e0,
798 .hw.init = CLK_HW_INIT_PARENTS_HW("vp-apb",
799 gmac_pll_clk_parent,
800 &ccu_div_ops,
801 0),
802 },
803 };
804
805 static struct ccu_div vp_axi_clk = {
806 .enable = BIT(15),
807 .div = TH_CCU_DIV_FLAGS(8, 4, CLK_DIVIDER_ONE_BASED),
808 .common = {
809 .clkid = CLK_VP_AXI,
810 .cfg0 = 0x1e0,
811 .hw.init = CLK_HW_INIT_PARENTS_HW("vp-axi",
812 video_pll_clk_parent,
813 &ccu_div_ops,
814 CLK_IS_CRITICAL),
815 },
816 };
817
818 static struct ccu_div venc_clk = {
819 .enable = BIT(5),
820 .div = TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED),
821 .common = {
822 .clkid = CLK_VENC,
823 .cfg0 = 0x1e4,
824 .hw.init = CLK_HW_INIT_PARENTS_HW("venc",
825 gmac_pll_clk_parent,
826 &ccu_div_ops,
827 0),
828 },
829 };
830
831 static struct ccu_div dpu0_clk = {
832 .div_en = BIT(8),
833 .div = TH_CCU_DIV_FLAGS(0, 8, CLK_DIVIDER_ONE_BASED),
834 .common = {
835 .clkid = CLK_DPU0,
836 .cfg0 = 0x1e8,
837 .hw.init = CLK_HW_INIT_PARENTS_HW("dpu0",
838 dpu0_pll_clk_parent,
839 &ccu_div_ops,
840 CLK_SET_RATE_UNGATE),
841 },
842 };
843
844 static const struct clk_parent_data dpu0_clk_pd[] = {
845 { .hw = &dpu0_clk.common.hw }
846 };
847
848 static struct ccu_div dpu1_clk = {
849 .div_en = BIT(8),
850 .div = TH_CCU_DIV_FLAGS(0, 8, CLK_DIVIDER_ONE_BASED),
851 .common = {
852 .clkid = CLK_DPU1,
853 .cfg0 = 0x1ec,
854 .hw.init = CLK_HW_INIT_PARENTS_HW("dpu1",
855 dpu1_pll_clk_parent,
856 &ccu_div_ops,
857 CLK_SET_RATE_UNGATE),
858 },
859 };
860
861 static const struct clk_parent_data dpu1_clk_pd[] = {
862 { .hw = &dpu1_clk.common.hw }
863 };
864
865 static CLK_FIXED_FACTOR_HW(emmc_sdio_ref_clk, "emmc-sdio-ref",
866 &video_pll_clk.common.hw, 4, 1, 0);
867
868 static const struct clk_parent_data emmc_sdio_ref_clk_pd[] = {
869 { .hw = &emmc_sdio_ref_clk.hw },
870 };
871
872 static CCU_GATE(CLK_BROM, brom_clk, "brom", ahb2_cpusys_hclk_pd, 0x100, 4, 0);
873 static CCU_GATE(CLK_BMU, bmu_clk, "bmu", axi4_cpusys2_aclk_pd, 0x100, 5, 0);
874 static CCU_GATE(CLK_AON2CPU_A2X, aon2cpu_a2x_clk, "aon2cpu-a2x", axi4_cpusys2_aclk_pd,
875 0x134, 8, CLK_IS_CRITICAL);
876 static CCU_GATE(CLK_X2X_CPUSYS, x2x_cpusys_clk, "x2x-cpusys", axi4_cpusys2_aclk_pd,
877 0x134, 7, CLK_IS_CRITICAL);
878 static CCU_GATE(CLK_CPU2AON_X2H, cpu2aon_x2h_clk, "cpu2aon-x2h", axi_aclk_pd,
879 0x138, 8, CLK_IS_CRITICAL);
880 static CCU_GATE(CLK_CPU2PERI_X2H, cpu2peri_x2h_clk, "cpu2peri-x2h", axi4_cpusys2_aclk_pd,
881 0x140, 9, CLK_IS_CRITICAL);
882 static CCU_GATE(CLK_PERISYS_APB1_HCLK, perisys_apb1_hclk, "perisys-apb1-hclk", perisys_ahb_hclk_pd,
883 0x150, 9, CLK_IS_CRITICAL);
884 static CCU_GATE(CLK_PERISYS_APB2_HCLK, perisys_apb2_hclk, "perisys-apb2-hclk", perisys_ahb_hclk_pd,
885 0x150, 10, CLK_IS_CRITICAL);
886 static CCU_GATE(CLK_PERISYS_APB3_HCLK, perisys_apb3_hclk, "perisys-apb3-hclk", perisys_ahb_hclk_pd,
887 0x150, 11, CLK_IS_CRITICAL);
888 static CCU_GATE(CLK_PERISYS_APB4_HCLK, perisys_apb4_hclk, "perisys-apb4-hclk", perisys_ahb_hclk_pd,
889 0x150, 12, 0);
890 static const struct clk_parent_data perisys_apb4_hclk_pd[] = {
891 { .hw = &perisys_apb4_hclk.gate.hw },
892 };
893
894 static CCU_GATE(CLK_NPU_AXI, npu_axi_clk, "npu-axi", axi_aclk_pd, 0x1c8, 5, CLK_IS_CRITICAL);
895 static CCU_GATE(CLK_CPU2VP, cpu2vp_clk, "cpu2vp", axi_aclk_pd, 0x1e0, 13, CLK_IS_CRITICAL);
896 static CCU_GATE(CLK_EMMC_SDIO, emmc_sdio_clk, "emmc-sdio", emmc_sdio_ref_clk_pd, 0x204, 30, 0);
897 static CCU_GATE(CLK_GMAC1, gmac1_clk, "gmac1", gmac_pll_clk_pd, 0x204, 26, 0);
898 static CCU_GATE(CLK_PADCTRL1, padctrl1_clk, "padctrl1", perisys_apb_pclk_pd, 0x204, 24, 0);
899 static CCU_GATE(CLK_DSMART, dsmart_clk, "dsmart", perisys_apb_pclk_pd, 0x204, 23, 0);
900 static CCU_GATE(CLK_PADCTRL0, padctrl0_clk, "padctrl0", perisys_apb4_hclk_pd, 0x204, 22, 0);
901 static CCU_GATE(CLK_GMAC_AXI, gmac_axi_clk, "gmac-axi", axi4_cpusys2_aclk_pd, 0x204, 21, 0);
902 static CCU_GATE(CLK_GPIO3, gpio3_clk, "gpio3-clk", peri2sys_apb_pclk_pd, 0x204, 20, 0);
903 static CCU_GATE(CLK_GMAC0, gmac0_clk, "gmac0", gmac_pll_clk_pd, 0x204, 19, 0);
904 static CCU_GATE(CLK_PWM, pwm_clk, "pwm", perisys_apb_pclk_pd, 0x204, 18, 0);
905 static CCU_GATE(CLK_QSPI0, qspi0_clk, "qspi0", video_pll_clk_pd, 0x204, 17, 0);
906 static CCU_GATE(CLK_QSPI1, qspi1_clk, "qspi1", video_pll_clk_pd, 0x204, 16, 0);
907 static CCU_GATE(CLK_SPI, spi_clk, "spi", video_pll_clk_pd, 0x204, 15, 0);
908 static CCU_GATE(CLK_UART0_PCLK, uart0_pclk, "uart0-pclk", perisys_apb_pclk_pd, 0x204, 14, 0);
909 static CCU_GATE(CLK_UART1_PCLK, uart1_pclk, "uart1-pclk", perisys_apb_pclk_pd, 0x204, 13, 0);
910 static CCU_GATE(CLK_UART2_PCLK, uart2_pclk, "uart2-pclk", perisys_apb_pclk_pd, 0x204, 12, 0);
911 static CCU_GATE(CLK_UART3_PCLK, uart3_pclk, "uart3-pclk", perisys_apb_pclk_pd, 0x204, 11, 0);
912 static CCU_GATE(CLK_UART4_PCLK, uart4_pclk, "uart4-pclk", perisys_apb_pclk_pd, 0x204, 10, 0);
913 static CCU_GATE(CLK_UART5_PCLK, uart5_pclk, "uart5-pclk", perisys_apb_pclk_pd, 0x204, 9, 0);
914 static CCU_GATE(CLK_GPIO0, gpio0_clk, "gpio0-clk", perisys_apb_pclk_pd, 0x204, 8, 0);
915 static CCU_GATE(CLK_GPIO1, gpio1_clk, "gpio1-clk", perisys_apb_pclk_pd, 0x204, 7, 0);
916 static CCU_GATE(CLK_GPIO2, gpio2_clk, "gpio2-clk", peri2sys_apb_pclk_pd, 0x204, 6, 0);
917 static CCU_GATE(CLK_I2C0, i2c0_clk, "i2c0", perisys_apb_pclk_pd, 0x204, 5, 0);
918 static CCU_GATE(CLK_I2C1, i2c1_clk, "i2c1", perisys_apb_pclk_pd, 0x204, 4, 0);
919 static CCU_GATE(CLK_I2C2, i2c2_clk, "i2c2", perisys_apb_pclk_pd, 0x204, 3, 0);
920 static CCU_GATE(CLK_I2C3, i2c3_clk, "i2c3", perisys_apb_pclk_pd, 0x204, 2, 0);
921 static CCU_GATE(CLK_I2C4, i2c4_clk, "i2c4", perisys_apb_pclk_pd, 0x204, 1, 0);
922 static CCU_GATE(CLK_I2C5, i2c5_clk, "i2c5", perisys_apb_pclk_pd, 0x204, 0, 0);
923 static CCU_GATE(CLK_SPINLOCK, spinlock_clk, "spinlock", ahb2_cpusys_hclk_pd, 0x208, 10, 0);
924 static CCU_GATE(CLK_DMA, dma_clk, "dma", axi4_cpusys2_aclk_pd, 0x208, 8, 0);
925 static CCU_GATE(CLK_MBOX0, mbox0_clk, "mbox0", apb3_cpusys_pclk_pd, 0x208, 7, 0);
926 static CCU_GATE(CLK_MBOX1, mbox1_clk, "mbox1", apb3_cpusys_pclk_pd, 0x208, 6, 0);
927 static CCU_GATE(CLK_MBOX2, mbox2_clk, "mbox2", apb3_cpusys_pclk_pd, 0x208, 5, 0);
928 static CCU_GATE(CLK_MBOX3, mbox3_clk, "mbox3", apb3_cpusys_pclk_pd, 0x208, 4, 0);
929 static CCU_GATE(CLK_WDT0, wdt0_clk, "wdt0", apb3_cpusys_pclk_pd, 0x208, 3, 0);
930 static CCU_GATE(CLK_WDT1, wdt1_clk, "wdt1", apb3_cpusys_pclk_pd, 0x208, 2, 0);
931 static CCU_GATE(CLK_TIMER0, timer0_clk, "timer0", apb3_cpusys_pclk_pd, 0x208, 1, 0);
932 static CCU_GATE(CLK_TIMER1, timer1_clk, "timer1", apb3_cpusys_pclk_pd, 0x208, 0, 0);
933 static CCU_GATE(CLK_SRAM0, sram0_clk, "sram0", axi_aclk_pd, 0x20c, 4, 0);
934 static CCU_GATE(CLK_SRAM1, sram1_clk, "sram1", axi_aclk_pd, 0x20c, 3, 0);
935 static CCU_GATE(CLK_SRAM2, sram2_clk, "sram2", axi_aclk_pd, 0x20c, 2, 0);
936 static CCU_GATE(CLK_SRAM3, sram3_clk, "sram3", axi_aclk_pd, 0x20c, 1, 0);
937
938 static CCU_GATE(CLK_AXI4_VO_ACLK, axi4_vo_aclk, "axi4-vo-aclk",
939 video_pll_clk_pd, 0x0, 0, CLK_IS_CRITICAL);
940 static CCU_GATE(CLK_GPU_CORE, gpu_core_clk, "gpu-core-clk", video_pll_clk_pd,
941 0x0, 3, 0);
942 static CCU_GATE(CLK_GPU_CFG_ACLK, gpu_cfg_aclk, "gpu-cfg-aclk",
943 video_pll_clk_pd, 0x0, 4, CLK_IS_CRITICAL);
944 static CCU_GATE(CLK_DPU_PIXELCLK0, dpu0_pixelclk, "dpu0-pixelclk",
945 dpu0_clk_pd, 0x0, 5, CLK_SET_RATE_PARENT);
946 static CCU_GATE(CLK_DPU_PIXELCLK1, dpu1_pixelclk, "dpu1-pixelclk",
947 dpu1_clk_pd, 0x0, 6, CLK_SET_RATE_PARENT);
948 static CCU_GATE(CLK_DPU_HCLK, dpu_hclk, "dpu-hclk", video_pll_clk_pd, 0x0,
949 7, 0);
950 static CCU_GATE(CLK_DPU_ACLK, dpu_aclk, "dpu-aclk", video_pll_clk_pd, 0x0,
951 8, 0);
952 static CCU_GATE(CLK_DPU_CCLK, dpu_cclk, "dpu-cclk", video_pll_clk_pd, 0x0,
953 9, 0);
954 static CCU_GATE(CLK_HDMI_SFR, hdmi_sfr_clk, "hdmi-sfr-clk", video_pll_clk_pd,
955 0x0, 10, 0);
956 static CCU_GATE(CLK_HDMI_PCLK, hdmi_pclk, "hdmi-pclk", video_pll_clk_pd, 0x0,
957 11, 0);
958 static CCU_GATE(CLK_HDMI_CEC, hdmi_cec_clk, "hdmi-cec-clk", video_pll_clk_pd,
959 0x0, 12, 0);
960 static CCU_GATE(CLK_MIPI_DSI0_PCLK, mipi_dsi0_pclk, "mipi-dsi0-pclk",
961 video_pll_clk_pd, 0x0, 13, 0);
962 static CCU_GATE(CLK_MIPI_DSI1_PCLK, mipi_dsi1_pclk, "mipi-dsi1-pclk",
963 video_pll_clk_pd, 0x0, 14, 0);
964 static CCU_GATE(CLK_MIPI_DSI0_CFG, mipi_dsi0_cfg_clk, "mipi-dsi0-cfg-clk",
965 video_pll_clk_pd, 0x0, 15, 0);
966 static CCU_GATE(CLK_MIPI_DSI1_CFG, mipi_dsi1_cfg_clk, "mipi-dsi1-cfg-clk",
967 video_pll_clk_pd, 0x0, 16, 0);
968 static CCU_GATE(CLK_MIPI_DSI0_REFCLK, mipi_dsi0_refclk, "mipi-dsi0-refclk",
969 video_pll_clk_pd, 0x0, 17, 0);
970 static CCU_GATE(CLK_MIPI_DSI1_REFCLK, mipi_dsi1_refclk, "mipi-dsi1-refclk",
971 video_pll_clk_pd, 0x0, 18, 0);
972 static CCU_GATE(CLK_HDMI_I2S, hdmi_i2s_clk, "hdmi-i2s-clk", video_pll_clk_pd,
973 0x0, 19, 0);
974 static CCU_GATE(CLK_X2H_DPU1_ACLK, x2h_dpu1_aclk, "x2h-dpu1-aclk",
975 video_pll_clk_pd, 0x0, 20, CLK_IS_CRITICAL);
976 static CCU_GATE(CLK_X2H_DPU_ACLK, x2h_dpu_aclk, "x2h-dpu-aclk",
977 video_pll_clk_pd, 0x0, 21, CLK_IS_CRITICAL);
978 static CCU_GATE(CLK_AXI4_VO_PCLK, axi4_vo_pclk, "axi4-vo-pclk",
979 video_pll_clk_pd, 0x0, 22, 0);
980 static CCU_GATE(CLK_IOPMP_VOSYS_DPU_PCLK, iopmp_vosys_dpu_pclk,
981 "iopmp-vosys-dpu-pclk", video_pll_clk_pd, 0x0, 23, 0);
982 static CCU_GATE(CLK_IOPMP_VOSYS_DPU1_PCLK, iopmp_vosys_dpu1_pclk,
983 "iopmp-vosys-dpu1-pclk", video_pll_clk_pd, 0x0, 24, 0);
984 static CCU_GATE(CLK_IOPMP_VOSYS_GPU_PCLK, iopmp_vosys_gpu_pclk,
985 "iopmp-vosys-gpu-pclk", video_pll_clk_pd, 0x0, 25, 0);
986 static CCU_GATE(CLK_IOPMP_DPU1_ACLK, iopmp_dpu1_aclk, "iopmp-dpu1-aclk",
987 video_pll_clk_pd, 0x0, 27, CLK_IS_CRITICAL);
988 static CCU_GATE(CLK_IOPMP_DPU_ACLK, iopmp_dpu_aclk, "iopmp-dpu-aclk",
989 video_pll_clk_pd, 0x0, 28, CLK_IS_CRITICAL);
990 static CCU_GATE(CLK_IOPMP_GPU_ACLK, iopmp_gpu_aclk, "iopmp-gpu-aclk",
991 video_pll_clk_pd, 0x0, 29, CLK_IS_CRITICAL);
992 static CCU_GATE(CLK_MIPIDSI0_PIXCLK, mipi_dsi0_pixclk, "mipi-dsi0-pixclk",
993 video_pll_clk_pd, 0x0, 30, 0);
994 static CCU_GATE(CLK_MIPIDSI1_PIXCLK, mipi_dsi1_pixclk, "mipi-dsi1-pixclk",
995 video_pll_clk_pd, 0x0, 31, 0);
996 static CCU_GATE(CLK_HDMI_PIXCLK, hdmi_pixclk, "hdmi-pixclk", video_pll_clk_pd,
997 0x4, 0, 0);
998
999 static CLK_FIXED_FACTOR_HW(gmac_pll_clk_100m, "gmac-pll-clk-100m",
1000 &gmac_pll_clk.common.hw, 10, 1, 0);
1001
1002 static const struct clk_parent_data uart_sclk_parents[] = {
1003 { .hw = &gmac_pll_clk_100m.hw },
1004 { .index = 0 },
1005 };
1006
1007 static struct ccu_mux uart_sclk = {
1008 .clkid = CLK_UART_SCLK,
1009 .reg = 0x210,
1010 .mux = TH_CCU_MUX("uart-sclk", uart_sclk_parents, 0, 1),
1011 };
1012
1013 static struct ccu_common *th1520_pll_clks[] = {
1014 &cpu_pll0_clk.common,
1015 &cpu_pll1_clk.common,
1016 &gmac_pll_clk.common,
1017 &video_pll_clk.common,
1018 &dpu0_pll_clk.common,
1019 &dpu1_pll_clk.common,
1020 &tee_pll_clk.common,
1021 };
1022
1023 static struct ccu_common *th1520_div_clks[] = {
1024 &ahb2_cpusys_hclk.common,
1025 &apb3_cpusys_pclk.common,
1026 &axi4_cpusys2_aclk.common,
1027 &perisys_ahb_hclk.common,
1028 &perisys_apb_pclk.common,
1029 &axi_aclk.common,
1030 &peri2sys_apb_pclk.common,
1031 &out1_clk.common,
1032 &out2_clk.common,
1033 &out3_clk.common,
1034 &out4_clk.common,
1035 &apb_pclk.common,
1036 &npu_clk.common,
1037 &vi_clk.common,
1038 &vi_ahb_clk.common,
1039 &vo_axi_clk.common,
1040 &vp_apb_clk.common,
1041 &vp_axi_clk.common,
1042 &venc_clk.common,
1043 &dpu0_clk.common,
1044 &dpu1_clk.common,
1045 };
1046
1047 static struct ccu_mux *th1520_mux_clks[] = {
1048 &c910_i0_clk,
1049 &c910_clk,
1050 &uart_sclk,
1051 };
1052
1053 static struct ccu_gate *th1520_gate_clks[] = {
1054 &emmc_sdio_clk,
1055 &aon2cpu_a2x_clk,
1056 &x2x_cpusys_clk,
1057 &brom_clk,
1058 &bmu_clk,
1059 &cpu2aon_x2h_clk,
1060 &cpu2peri_x2h_clk,
1061 &cpu2vp_clk,
1062 &perisys_apb1_hclk,
1063 &perisys_apb2_hclk,
1064 &perisys_apb3_hclk,
1065 &perisys_apb4_hclk,
1066 &npu_axi_clk,
1067 &gmac1_clk,
1068 &padctrl1_clk,
1069 &dsmart_clk,
1070 &padctrl0_clk,
1071 &gmac_axi_clk,
1072 &gpio3_clk,
1073 &gmac0_clk,
1074 &pwm_clk,
1075 &qspi0_clk,
1076 &qspi1_clk,
1077 &spi_clk,
1078 &uart0_pclk,
1079 &uart1_pclk,
1080 &uart2_pclk,
1081 &uart3_pclk,
1082 &uart4_pclk,
1083 &uart5_pclk,
1084 &gpio0_clk,
1085 &gpio1_clk,
1086 &gpio2_clk,
1087 &i2c0_clk,
1088 &i2c1_clk,
1089 &i2c2_clk,
1090 &i2c3_clk,
1091 &i2c4_clk,
1092 &i2c5_clk,
1093 &spinlock_clk,
1094 &dma_clk,
1095 &mbox0_clk,
1096 &mbox1_clk,
1097 &mbox2_clk,
1098 &mbox3_clk,
1099 &wdt0_clk,
1100 &wdt1_clk,
1101 &timer0_clk,
1102 &timer1_clk,
1103 &sram0_clk,
1104 &sram1_clk,
1105 &sram2_clk,
1106 &sram3_clk,
1107 };
1108
1109 static struct ccu_gate *th1520_vo_gate_clks[] = {
1110 &axi4_vo_aclk,
1111 &gpu_core_clk,
1112 &gpu_cfg_aclk,
1113 &dpu0_pixelclk,
1114 &dpu1_pixelclk,
1115 &dpu_hclk,
1116 &dpu_aclk,
1117 &dpu_cclk,
1118 &hdmi_sfr_clk,
1119 &hdmi_pclk,
1120 &hdmi_cec_clk,
1121 &mipi_dsi0_pclk,
1122 &mipi_dsi1_pclk,
1123 &mipi_dsi0_cfg_clk,
1124 &mipi_dsi1_cfg_clk,
1125 &mipi_dsi0_refclk,
1126 &mipi_dsi1_refclk,
1127 &hdmi_i2s_clk,
1128 &x2h_dpu1_aclk,
1129 &x2h_dpu_aclk,
1130 &axi4_vo_pclk,
1131 &iopmp_vosys_dpu_pclk,
1132 &iopmp_vosys_dpu1_pclk,
1133 &iopmp_vosys_gpu_pclk,
1134 &iopmp_dpu1_aclk,
1135 &iopmp_dpu_aclk,
1136 &iopmp_gpu_aclk,
1137 &mipi_dsi0_pixclk,
1138 &mipi_dsi1_pixclk,
1139 &hdmi_pixclk
1140 };
1141
1142 static const struct regmap_config th1520_clk_regmap_config = {
1143 .reg_bits = 32,
1144 .val_bits = 32,
1145 .reg_stride = 4,
1146 };
1147
1148 struct th1520_plat_data {
1149 struct ccu_common **th1520_pll_clks;
1150 struct ccu_common **th1520_div_clks;
1151 struct ccu_mux **th1520_mux_clks;
1152 struct ccu_gate **th1520_gate_clks;
1153
1154 int nr_clks;
1155 int nr_pll_clks;
1156 int nr_div_clks;
1157 int nr_mux_clks;
1158 int nr_gate_clks;
1159 };
1160
1161 static const struct th1520_plat_data th1520_ap_platdata = {
1162 .th1520_pll_clks = th1520_pll_clks,
1163 .th1520_div_clks = th1520_div_clks,
1164 .th1520_mux_clks = th1520_mux_clks,
1165 .th1520_gate_clks = th1520_gate_clks,
1166
1167 .nr_clks = CLK_UART_SCLK + 1,
1168
1169 .nr_pll_clks = ARRAY_SIZE(th1520_pll_clks),
1170 .nr_div_clks = ARRAY_SIZE(th1520_div_clks),
1171 .nr_mux_clks = ARRAY_SIZE(th1520_mux_clks),
1172 .nr_gate_clks = ARRAY_SIZE(th1520_gate_clks),
1173 };
1174
1175 static const struct th1520_plat_data th1520_vo_platdata = {
1176 .th1520_gate_clks = th1520_vo_gate_clks,
1177
1178 .nr_clks = CLK_HDMI_PIXCLK + 1,
1179
1180 .nr_gate_clks = ARRAY_SIZE(th1520_vo_gate_clks),
1181 };
1182
th1520_clk_probe(struct platform_device * pdev)1183 static int th1520_clk_probe(struct platform_device *pdev)
1184 {
1185 const struct th1520_plat_data *plat_data;
1186 struct device *dev = &pdev->dev;
1187 struct clk_hw_onecell_data *priv;
1188
1189 struct regmap *map;
1190 void __iomem *base;
1191 int ret, i;
1192
1193 plat_data = device_get_match_data(&pdev->dev);
1194 if (!plat_data)
1195 return dev_err_probe(&pdev->dev, -ENODEV,
1196 "No device match data found\n");
1197
1198 priv = devm_kzalloc(dev, struct_size(priv, hws, plat_data->nr_clks), GFP_KERNEL);
1199 if (!priv)
1200 return -ENOMEM;
1201
1202 priv->num = plat_data->nr_clks;
1203
1204 base = devm_platform_ioremap_resource(pdev, 0);
1205 if (IS_ERR(base))
1206 return PTR_ERR(base);
1207
1208 map = devm_regmap_init_mmio(dev, base, &th1520_clk_regmap_config);
1209 if (IS_ERR(map))
1210 return PTR_ERR(map);
1211
1212 for (i = 0; i < plat_data->nr_pll_clks; i++) {
1213 struct ccu_pll *cp = hw_to_ccu_pll(&plat_data->th1520_pll_clks[i]->hw);
1214
1215 plat_data->th1520_pll_clks[i]->map = map;
1216
1217 ret = devm_clk_hw_register(dev, &plat_data->th1520_pll_clks[i]->hw);
1218 if (ret)
1219 return ret;
1220
1221 priv->hws[cp->common.clkid] = &cp->common.hw;
1222 }
1223
1224 for (i = 0; i < plat_data->nr_div_clks; i++) {
1225 struct ccu_div *cd = hw_to_ccu_div(&plat_data->th1520_div_clks[i]->hw);
1226
1227 plat_data->th1520_div_clks[i]->map = map;
1228
1229 ret = devm_clk_hw_register(dev, &plat_data->th1520_div_clks[i]->hw);
1230 if (ret)
1231 return ret;
1232
1233 priv->hws[cd->common.clkid] = &cd->common.hw;
1234 }
1235
1236 for (i = 0; i < plat_data->nr_mux_clks; i++) {
1237 struct ccu_mux *cm = plat_data->th1520_mux_clks[i];
1238
1239 cm->mux.reg = base + cm->reg;
1240
1241 ret = devm_clk_hw_register(dev, &cm->mux.hw);
1242 if (ret)
1243 return ret;
1244
1245 priv->hws[cm->clkid] = &cm->mux.hw;
1246 }
1247
1248 for (i = 0; i < plat_data->nr_gate_clks; i++) {
1249 struct ccu_gate *cg = plat_data->th1520_gate_clks[i];
1250
1251 cg->gate.reg = base + cg->reg;
1252
1253 ret = devm_clk_hw_register(dev, &cg->gate.hw);
1254 if (ret)
1255 return ret;
1256
1257 priv->hws[cg->clkid] = &cg->gate.hw;
1258 }
1259
1260 if (plat_data == &th1520_ap_platdata) {
1261 ret = devm_clk_hw_register(dev, &osc12m_clk.hw);
1262 if (ret)
1263 return ret;
1264 priv->hws[CLK_OSC12M] = &osc12m_clk.hw;
1265
1266 ret = devm_clk_hw_register(dev, &gmac_pll_clk_100m.hw);
1267 if (ret)
1268 return ret;
1269 priv->hws[CLK_PLL_GMAC_100M] = &gmac_pll_clk_100m.hw;
1270
1271 ret = devm_clk_hw_register(dev, &emmc_sdio_ref_clk.hw);
1272 if (ret)
1273 return ret;
1274 }
1275
1276 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, priv);
1277 if (ret)
1278 return ret;
1279
1280 return 0;
1281 }
1282
1283 static const struct of_device_id th1520_clk_match[] = {
1284 {
1285 .compatible = "thead,th1520-clk-ap",
1286 .data = &th1520_ap_platdata,
1287 },
1288 {
1289 .compatible = "thead,th1520-clk-vo",
1290 .data = &th1520_vo_platdata,
1291 },
1292 { /* sentinel */ },
1293 };
1294 MODULE_DEVICE_TABLE(of, th1520_clk_match);
1295
1296 static struct platform_driver th1520_clk_driver = {
1297 .probe = th1520_clk_probe,
1298 .driver = {
1299 .name = "th1520-clk",
1300 .of_match_table = th1520_clk_match,
1301 },
1302 };
1303 module_platform_driver(th1520_clk_driver);
1304
1305 MODULE_DESCRIPTION("T-HEAD TH1520 AP Clock driver");
1306 MODULE_AUTHOR("Yangtao Li <frank.li@vivo.com>");
1307 MODULE_AUTHOR("Jisheng Zhang <jszhang@kernel.org>");
1308 MODULE_LICENSE("GPL");
1309