1// SPDX-License-Identifier: GPL-2.0 2 3#include <dt-bindings/clock/tegra234-clock.h> 4#include <dt-bindings/gpio/tegra234-gpio.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/mailbox/tegra186-hsp.h> 7#include <dt-bindings/memory/tegra234-mc.h> 8#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 9#include <dt-bindings/power/tegra234-powergate.h> 10#include <dt-bindings/reset/tegra234-reset.h> 11#include <dt-bindings/thermal/tegra234-bpmp-thermal.h> 12 13/ { 14 compatible = "nvidia,tegra234"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 i2c0 = &gen1_i2c; 21 i2c1 = &gen2_i2c; 22 i2c2 = &cam_i2c; 23 i2c3 = &dp_aux_ch1_i2c; 24 i2c4 = &bpmp_i2c; 25 i2c5 = &dp_aux_ch0_i2c; 26 i2c6 = &dp_aux_ch2_i2c; 27 i2c7 = &gen8_i2c; 28 i2c8 = &dp_aux_ch3_i2c; 29 }; 30 31 bus@0 { 32 compatible = "simple-bus"; 33 34 #address-cells = <2>; 35 #size-cells = <2>; 36 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 37 38 misc@100000 { 39 compatible = "nvidia,tegra234-misc"; 40 reg = <0x0 0x00100000 0x0 0xf000>, 41 <0x0 0x0010f000 0x0 0x1000>; 42 status = "okay"; 43 }; 44 45 timer@2080000 { 46 compatible = "nvidia,tegra234-timer"; 47 reg = <0x0 0x02080000 0x0 0x00121000>; 48 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 52 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 64 status = "okay"; 65 }; 66 67 gpio: gpio@2200000 { 68 compatible = "nvidia,tegra234-gpio"; 69 reg-names = "security", "gpio"; 70 reg = <0x0 0x02200000 0x0 0x10000>, 71 <0x0 0x02210000 0x0 0x10000>; 72 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 114 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 120 #interrupt-cells = <2>; 121 interrupt-controller; 122 #gpio-cells = <2>; 123 gpio-controller; 124 gpio-ranges = <&pinmux 0 0 164>; 125 }; 126 127 pinmux: pinmux@2430000 { 128 compatible = "nvidia,tegra234-pinmux"; 129 reg = <0x0 0x2430000 0x0 0x19100>; 130 }; 131 132 gpcdma: dma-controller@2600000 { 133 compatible = "nvidia,tegra234-gpcdma", 134 "nvidia,tegra186-gpcdma"; 135 reg = <0x0 0x2600000 0x0 0x210000>; 136 resets = <&bpmp TEGRA234_RESET_GPCDMA>; 137 reset-names = "gpcdma"; 138 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 170 #dma-cells = <1>; 171 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 172 dma-channel-mask = <0xfffffffe>; 173 dma-coherent; 174 }; 175 176 aconnect@2900000 { 177 compatible = "nvidia,tegra234-aconnect", 178 "nvidia,tegra210-aconnect"; 179 clocks = <&bpmp TEGRA234_CLK_APE>, 180 <&bpmp TEGRA234_CLK_APB2APE>; 181 clock-names = "ape", "apb2ape"; 182 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>; 183 status = "disabled"; 184 185 #address-cells = <2>; 186 #size-cells = <2>; 187 ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>; 188 189 tegra_ahub: ahub@2900800 { 190 compatible = "nvidia,tegra234-ahub"; 191 reg = <0x0 0x02900800 0x0 0x800>; 192 clocks = <&bpmp TEGRA234_CLK_AHUB>; 193 clock-names = "ahub"; 194 assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>; 195 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 196 assigned-clock-rates = <81600000>; 197 status = "disabled"; 198 199 #address-cells = <2>; 200 #size-cells = <2>; 201 ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>; 202 203 tegra_i2s1: i2s@2901000 { 204 compatible = "nvidia,tegra234-i2s", 205 "nvidia,tegra210-i2s"; 206 reg = <0x0 0x2901000 0x0 0x100>; 207 clocks = <&bpmp TEGRA234_CLK_I2S1>, 208 <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>; 209 clock-names = "i2s", "sync_input"; 210 assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>; 211 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 212 assigned-clock-rates = <1536000>; 213 sound-name-prefix = "I2S1"; 214 status = "disabled"; 215 216 ports { 217 #address-cells = <1>; 218 #size-cells = <0>; 219 220 port@0 { 221 reg = <0>; 222 223 i2s1_cif: endpoint { 224 remote-endpoint = <&xbar_i2s1>; 225 }; 226 }; 227 228 i2s1_port: port@1 { 229 reg = <1>; 230 231 i2s1_dap: endpoint { 232 dai-format = "i2s"; 233 /* placeholder for external codec */ 234 }; 235 }; 236 }; 237 }; 238 239 tegra_i2s2: i2s@2901100 { 240 compatible = "nvidia,tegra234-i2s", 241 "nvidia,tegra210-i2s"; 242 reg = <0x0 0x2901100 0x0 0x100>; 243 clocks = <&bpmp TEGRA234_CLK_I2S2>, 244 <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>; 245 clock-names = "i2s", "sync_input"; 246 assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>; 247 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 248 assigned-clock-rates = <1536000>; 249 sound-name-prefix = "I2S2"; 250 status = "disabled"; 251 252 ports { 253 #address-cells = <1>; 254 #size-cells = <0>; 255 256 port@0 { 257 reg = <0>; 258 259 i2s2_cif: endpoint { 260 remote-endpoint = <&xbar_i2s2>; 261 }; 262 }; 263 264 i2s2_port: port@1 { 265 reg = <1>; 266 267 i2s2_dap: endpoint { 268 dai-format = "i2s"; 269 /* placeholder for external codec */ 270 }; 271 }; 272 }; 273 }; 274 275 tegra_i2s3: i2s@2901200 { 276 compatible = "nvidia,tegra234-i2s", 277 "nvidia,tegra210-i2s"; 278 reg = <0x0 0x2901200 0x0 0x100>; 279 clocks = <&bpmp TEGRA234_CLK_I2S3>, 280 <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>; 281 clock-names = "i2s", "sync_input"; 282 assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>; 283 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 284 assigned-clock-rates = <1536000>; 285 sound-name-prefix = "I2S3"; 286 status = "disabled"; 287 288 ports { 289 #address-cells = <1>; 290 #size-cells = <0>; 291 292 port@0 { 293 reg = <0>; 294 295 i2s3_cif: endpoint { 296 remote-endpoint = <&xbar_i2s3>; 297 }; 298 }; 299 300 i2s3_port: port@1 { 301 reg = <1>; 302 303 i2s3_dap: endpoint { 304 dai-format = "i2s"; 305 /* placeholder for external codec */ 306 }; 307 }; 308 }; 309 }; 310 311 tegra_i2s4: i2s@2901300 { 312 compatible = "nvidia,tegra234-i2s", 313 "nvidia,tegra210-i2s"; 314 reg = <0x0 0x2901300 0x0 0x100>; 315 clocks = <&bpmp TEGRA234_CLK_I2S4>, 316 <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>; 317 clock-names = "i2s", "sync_input"; 318 assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>; 319 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 320 assigned-clock-rates = <1536000>; 321 sound-name-prefix = "I2S4"; 322 status = "disabled"; 323 324 ports { 325 #address-cells = <1>; 326 #size-cells = <0>; 327 328 port@0 { 329 reg = <0>; 330 331 i2s4_cif: endpoint { 332 remote-endpoint = <&xbar_i2s4>; 333 }; 334 }; 335 336 i2s4_port: port@1 { 337 reg = <1>; 338 339 i2s4_dap: endpoint { 340 dai-format = "i2s"; 341 /* placeholder for external codec */ 342 }; 343 }; 344 }; 345 }; 346 347 tegra_i2s5: i2s@2901400 { 348 compatible = "nvidia,tegra234-i2s", 349 "nvidia,tegra210-i2s"; 350 reg = <0x0 0x2901400 0x0 0x100>; 351 clocks = <&bpmp TEGRA234_CLK_I2S5>, 352 <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>; 353 clock-names = "i2s", "sync_input"; 354 assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>; 355 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 356 assigned-clock-rates = <1536000>; 357 sound-name-prefix = "I2S5"; 358 status = "disabled"; 359 360 ports { 361 #address-cells = <1>; 362 #size-cells = <0>; 363 364 port@0 { 365 reg = <0>; 366 367 i2s5_cif: endpoint { 368 remote-endpoint = <&xbar_i2s5>; 369 }; 370 }; 371 372 i2s5_port: port@1 { 373 reg = <1>; 374 375 i2s5_dap: endpoint { 376 dai-format = "i2s"; 377 /* placeholder for external codec */ 378 }; 379 }; 380 }; 381 }; 382 383 tegra_i2s6: i2s@2901500 { 384 compatible = "nvidia,tegra234-i2s", 385 "nvidia,tegra210-i2s"; 386 reg = <0x0 0x2901500 0x0 0x100>; 387 clocks = <&bpmp TEGRA234_CLK_I2S6>, 388 <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>; 389 clock-names = "i2s", "sync_input"; 390 assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>; 391 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 392 assigned-clock-rates = <1536000>; 393 sound-name-prefix = "I2S6"; 394 status = "disabled"; 395 396 ports { 397 #address-cells = <1>; 398 #size-cells = <0>; 399 400 port@0 { 401 reg = <0>; 402 403 i2s6_cif: endpoint { 404 remote-endpoint = <&xbar_i2s6>; 405 }; 406 }; 407 408 i2s6_port: port@1 { 409 reg = <1>; 410 411 i2s6_dap: endpoint { 412 dai-format = "i2s"; 413 /* placeholder for external codec */ 414 }; 415 }; 416 }; 417 }; 418 419 tegra_sfc1: sfc@2902000 { 420 compatible = "nvidia,tegra234-sfc", 421 "nvidia,tegra210-sfc"; 422 reg = <0x0 0x2902000 0x0 0x200>; 423 sound-name-prefix = "SFC1"; 424 425 ports { 426 #address-cells = <1>; 427 #size-cells = <0>; 428 429 port@0 { 430 reg = <0>; 431 432 sfc1_cif_in: endpoint { 433 remote-endpoint = <&xbar_sfc1_in>; 434 }; 435 }; 436 437 sfc1_out_port: port@1 { 438 reg = <1>; 439 440 sfc1_cif_out: endpoint { 441 remote-endpoint = <&xbar_sfc1_out>; 442 }; 443 }; 444 }; 445 }; 446 447 tegra_sfc2: sfc@2902200 { 448 compatible = "nvidia,tegra234-sfc", 449 "nvidia,tegra210-sfc"; 450 reg = <0x0 0x2902200 0x0 0x200>; 451 sound-name-prefix = "SFC2"; 452 453 ports { 454 #address-cells = <1>; 455 #size-cells = <0>; 456 457 port@0 { 458 reg = <0>; 459 460 sfc2_cif_in: endpoint { 461 remote-endpoint = <&xbar_sfc2_in>; 462 }; 463 }; 464 465 sfc2_out_port: port@1 { 466 reg = <1>; 467 468 sfc2_cif_out: endpoint { 469 remote-endpoint = <&xbar_sfc2_out>; 470 }; 471 }; 472 }; 473 }; 474 475 tegra_sfc3: sfc@2902400 { 476 compatible = "nvidia,tegra234-sfc", 477 "nvidia,tegra210-sfc"; 478 reg = <0x0 0x2902400 0x0 0x200>; 479 sound-name-prefix = "SFC3"; 480 481 ports { 482 #address-cells = <1>; 483 #size-cells = <0>; 484 485 port@0 { 486 reg = <0>; 487 488 sfc3_cif_in: endpoint { 489 remote-endpoint = <&xbar_sfc3_in>; 490 }; 491 }; 492 493 sfc3_out_port: port@1 { 494 reg = <1>; 495 496 sfc3_cif_out: endpoint { 497 remote-endpoint = <&xbar_sfc3_out>; 498 }; 499 }; 500 }; 501 }; 502 503 tegra_sfc4: sfc@2902600 { 504 compatible = "nvidia,tegra234-sfc", 505 "nvidia,tegra210-sfc"; 506 reg = <0x0 0x2902600 0x0 0x200>; 507 sound-name-prefix = "SFC4"; 508 509 ports { 510 #address-cells = <1>; 511 #size-cells = <0>; 512 513 port@0 { 514 reg = <0>; 515 516 sfc4_cif_in: endpoint { 517 remote-endpoint = <&xbar_sfc4_in>; 518 }; 519 }; 520 521 sfc4_out_port: port@1 { 522 reg = <1>; 523 524 sfc4_cif_out: endpoint { 525 remote-endpoint = <&xbar_sfc4_out>; 526 }; 527 }; 528 }; 529 }; 530 531 tegra_amx1: amx@2903000 { 532 compatible = "nvidia,tegra234-amx", 533 "nvidia,tegra194-amx"; 534 reg = <0x0 0x2903000 0x0 0x100>; 535 sound-name-prefix = "AMX1"; 536 537 ports { 538 #address-cells = <1>; 539 #size-cells = <0>; 540 541 port@0 { 542 reg = <0>; 543 544 amx1_in1: endpoint { 545 remote-endpoint = <&xbar_amx1_in1>; 546 }; 547 }; 548 549 port@1 { 550 reg = <1>; 551 552 amx1_in2: endpoint { 553 remote-endpoint = <&xbar_amx1_in2>; 554 }; 555 }; 556 557 port@2 { 558 reg = <2>; 559 560 amx1_in3: endpoint { 561 remote-endpoint = <&xbar_amx1_in3>; 562 }; 563 }; 564 565 port@3 { 566 reg = <3>; 567 568 amx1_in4: endpoint { 569 remote-endpoint = <&xbar_amx1_in4>; 570 }; 571 }; 572 573 amx1_out_port: port@4 { 574 reg = <4>; 575 576 amx1_out: endpoint { 577 remote-endpoint = <&xbar_amx1_out>; 578 }; 579 }; 580 }; 581 }; 582 583 tegra_amx2: amx@2903100 { 584 compatible = "nvidia,tegra234-amx", 585 "nvidia,tegra194-amx"; 586 reg = <0x0 0x2903100 0x0 0x100>; 587 sound-name-prefix = "AMX2"; 588 589 ports { 590 #address-cells = <1>; 591 #size-cells = <0>; 592 593 port@0 { 594 reg = <0>; 595 596 amx2_in1: endpoint { 597 remote-endpoint = <&xbar_amx2_in1>; 598 }; 599 }; 600 601 port@1 { 602 reg = <1>; 603 604 amx2_in2: endpoint { 605 remote-endpoint = <&xbar_amx2_in2>; 606 }; 607 }; 608 609 port@2 { 610 reg = <2>; 611 612 amx2_in3: endpoint { 613 remote-endpoint = <&xbar_amx2_in3>; 614 }; 615 }; 616 617 port@3 { 618 reg = <3>; 619 620 amx2_in4: endpoint { 621 remote-endpoint = <&xbar_amx2_in4>; 622 }; 623 }; 624 625 amx2_out_port: port@4 { 626 reg = <4>; 627 628 amx2_out: endpoint { 629 remote-endpoint = <&xbar_amx2_out>; 630 }; 631 }; 632 }; 633 }; 634 635 tegra_amx3: amx@2903200 { 636 compatible = "nvidia,tegra234-amx", 637 "nvidia,tegra194-amx"; 638 reg = <0x0 0x2903200 0x0 0x100>; 639 sound-name-prefix = "AMX3"; 640 641 ports { 642 #address-cells = <1>; 643 #size-cells = <0>; 644 645 port@0 { 646 reg = <0>; 647 648 amx3_in1: endpoint { 649 remote-endpoint = <&xbar_amx3_in1>; 650 }; 651 }; 652 653 port@1 { 654 reg = <1>; 655 656 amx3_in2: endpoint { 657 remote-endpoint = <&xbar_amx3_in2>; 658 }; 659 }; 660 661 port@2 { 662 reg = <2>; 663 664 amx3_in3: endpoint { 665 remote-endpoint = <&xbar_amx3_in3>; 666 }; 667 }; 668 669 port@3 { 670 reg = <3>; 671 672 amx3_in4: endpoint { 673 remote-endpoint = <&xbar_amx3_in4>; 674 }; 675 }; 676 677 amx3_out_port: port@4 { 678 reg = <4>; 679 680 amx3_out: endpoint { 681 remote-endpoint = <&xbar_amx3_out>; 682 }; 683 }; 684 }; 685 }; 686 687 tegra_amx4: amx@2903300 { 688 compatible = "nvidia,tegra234-amx", 689 "nvidia,tegra194-amx"; 690 reg = <0x0 0x2903300 0x0 0x100>; 691 sound-name-prefix = "AMX4"; 692 693 ports { 694 #address-cells = <1>; 695 #size-cells = <0>; 696 697 port@0 { 698 reg = <0>; 699 700 amx4_in1: endpoint { 701 remote-endpoint = <&xbar_amx4_in1>; 702 }; 703 }; 704 705 port@1 { 706 reg = <1>; 707 708 amx4_in2: endpoint { 709 remote-endpoint = <&xbar_amx4_in2>; 710 }; 711 }; 712 713 port@2 { 714 reg = <2>; 715 716 amx4_in3: endpoint { 717 remote-endpoint = <&xbar_amx4_in3>; 718 }; 719 }; 720 721 port@3 { 722 reg = <3>; 723 724 amx4_in4: endpoint { 725 remote-endpoint = <&xbar_amx4_in4>; 726 }; 727 }; 728 729 amx4_out_port: port@4 { 730 reg = <4>; 731 732 amx4_out: endpoint { 733 remote-endpoint = <&xbar_amx4_out>; 734 }; 735 }; 736 }; 737 }; 738 739 tegra_adx1: adx@2903800 { 740 compatible = "nvidia,tegra234-adx", 741 "nvidia,tegra210-adx"; 742 reg = <0x0 0x2903800 0x0 0x100>; 743 sound-name-prefix = "ADX1"; 744 745 ports { 746 #address-cells = <1>; 747 #size-cells = <0>; 748 749 port@0 { 750 reg = <0>; 751 752 adx1_in: endpoint { 753 remote-endpoint = <&xbar_adx1_in>; 754 }; 755 }; 756 757 adx1_out1_port: port@1 { 758 reg = <1>; 759 760 adx1_out1: endpoint { 761 remote-endpoint = <&xbar_adx1_out1>; 762 }; 763 }; 764 765 adx1_out2_port: port@2 { 766 reg = <2>; 767 768 adx1_out2: endpoint { 769 remote-endpoint = <&xbar_adx1_out2>; 770 }; 771 }; 772 773 adx1_out3_port: port@3 { 774 reg = <3>; 775 776 adx1_out3: endpoint { 777 remote-endpoint = <&xbar_adx1_out3>; 778 }; 779 }; 780 781 adx1_out4_port: port@4 { 782 reg = <4>; 783 784 adx1_out4: endpoint { 785 remote-endpoint = <&xbar_adx1_out4>; 786 }; 787 }; 788 }; 789 }; 790 791 tegra_adx2: adx@2903900 { 792 compatible = "nvidia,tegra234-adx", 793 "nvidia,tegra210-adx"; 794 reg = <0x0 0x2903900 0x0 0x100>; 795 sound-name-prefix = "ADX2"; 796 797 ports { 798 #address-cells = <1>; 799 #size-cells = <0>; 800 801 port@0 { 802 reg = <0>; 803 804 adx2_in: endpoint { 805 remote-endpoint = <&xbar_adx2_in>; 806 }; 807 }; 808 809 adx2_out1_port: port@1 { 810 reg = <1>; 811 812 adx2_out1: endpoint { 813 remote-endpoint = <&xbar_adx2_out1>; 814 }; 815 }; 816 817 adx2_out2_port: port@2 { 818 reg = <2>; 819 820 adx2_out2: endpoint { 821 remote-endpoint = <&xbar_adx2_out2>; 822 }; 823 }; 824 825 adx2_out3_port: port@3 { 826 reg = <3>; 827 828 adx2_out3: endpoint { 829 remote-endpoint = <&xbar_adx2_out3>; 830 }; 831 }; 832 833 adx2_out4_port: port@4 { 834 reg = <4>; 835 836 adx2_out4: endpoint { 837 remote-endpoint = <&xbar_adx2_out4>; 838 }; 839 }; 840 }; 841 }; 842 843 tegra_adx3: adx@2903a00 { 844 compatible = "nvidia,tegra234-adx", 845 "nvidia,tegra210-adx"; 846 reg = <0x0 0x2903a00 0x0 0x100>; 847 sound-name-prefix = "ADX3"; 848 849 ports { 850 #address-cells = <1>; 851 #size-cells = <0>; 852 853 port@0 { 854 reg = <0>; 855 856 adx3_in: endpoint { 857 remote-endpoint = <&xbar_adx3_in>; 858 }; 859 }; 860 861 adx3_out1_port: port@1 { 862 reg = <1>; 863 864 adx3_out1: endpoint { 865 remote-endpoint = <&xbar_adx3_out1>; 866 }; 867 }; 868 869 adx3_out2_port: port@2 { 870 reg = <2>; 871 872 adx3_out2: endpoint { 873 remote-endpoint = <&xbar_adx3_out2>; 874 }; 875 }; 876 877 adx3_out3_port: port@3 { 878 reg = <3>; 879 880 adx3_out3: endpoint { 881 remote-endpoint = <&xbar_adx3_out3>; 882 }; 883 }; 884 885 adx3_out4_port: port@4 { 886 reg = <4>; 887 888 adx3_out4: endpoint { 889 remote-endpoint = <&xbar_adx3_out4>; 890 }; 891 }; 892 }; 893 }; 894 895 tegra_adx4: adx@2903b00 { 896 compatible = "nvidia,tegra234-adx", 897 "nvidia,tegra210-adx"; 898 reg = <0x0 0x2903b00 0x0 0x100>; 899 sound-name-prefix = "ADX4"; 900 901 ports { 902 #address-cells = <1>; 903 #size-cells = <0>; 904 905 port@0 { 906 reg = <0>; 907 908 adx4_in: endpoint { 909 remote-endpoint = <&xbar_adx4_in>; 910 }; 911 }; 912 913 adx4_out1_port: port@1 { 914 reg = <1>; 915 916 adx4_out1: endpoint { 917 remote-endpoint = <&xbar_adx4_out1>; 918 }; 919 }; 920 921 adx4_out2_port: port@2 { 922 reg = <2>; 923 924 adx4_out2: endpoint { 925 remote-endpoint = <&xbar_adx4_out2>; 926 }; 927 }; 928 929 adx4_out3_port: port@3 { 930 reg = <3>; 931 932 adx4_out3: endpoint { 933 remote-endpoint = <&xbar_adx4_out3>; 934 }; 935 }; 936 937 adx4_out4_port: port@4 { 938 reg = <4>; 939 940 adx4_out4: endpoint { 941 remote-endpoint = <&xbar_adx4_out4>; 942 }; 943 }; 944 }; 945 }; 946 947 948 tegra_dmic1: dmic@2904000 { 949 compatible = "nvidia,tegra234-dmic", 950 "nvidia,tegra210-dmic"; 951 reg = <0x0 0x2904000 0x0 0x100>; 952 clocks = <&bpmp TEGRA234_CLK_DMIC1>; 953 clock-names = "dmic"; 954 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>; 955 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 956 assigned-clock-rates = <3072000>; 957 sound-name-prefix = "DMIC1"; 958 status = "disabled"; 959 960 ports { 961 #address-cells = <1>; 962 #size-cells = <0>; 963 964 port@0 { 965 reg = <0>; 966 967 dmic1_cif: endpoint { 968 remote-endpoint = <&xbar_dmic1>; 969 }; 970 }; 971 972 dmic1_port: port@1 { 973 reg = <1>; 974 975 dmic1_dap: endpoint { 976 /* placeholder for external codec */ 977 }; 978 }; 979 }; 980 }; 981 982 tegra_dmic2: dmic@2904100 { 983 compatible = "nvidia,tegra234-dmic", 984 "nvidia,tegra210-dmic"; 985 reg = <0x0 0x2904100 0x0 0x100>; 986 clocks = <&bpmp TEGRA234_CLK_DMIC2>; 987 clock-names = "dmic"; 988 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>; 989 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 990 assigned-clock-rates = <3072000>; 991 sound-name-prefix = "DMIC2"; 992 status = "disabled"; 993 994 ports { 995 #address-cells = <1>; 996 #size-cells = <0>; 997 998 port@0 { 999 reg = <0>; 1000 1001 dmic2_cif: endpoint { 1002 remote-endpoint = <&xbar_dmic2>; 1003 }; 1004 }; 1005 1006 dmic2_port: port@1 { 1007 reg = <1>; 1008 1009 dmic2_dap: endpoint { 1010 /* placeholder for external codec */ 1011 }; 1012 }; 1013 }; 1014 }; 1015 1016 tegra_dmic3: dmic@2904200 { 1017 compatible = "nvidia,tegra234-dmic", 1018 "nvidia,tegra210-dmic"; 1019 reg = <0x0 0x2904200 0x0 0x100>; 1020 clocks = <&bpmp TEGRA234_CLK_DMIC3>; 1021 clock-names = "dmic"; 1022 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>; 1023 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 1024 assigned-clock-rates = <3072000>; 1025 sound-name-prefix = "DMIC3"; 1026 status = "disabled"; 1027 1028 ports { 1029 #address-cells = <1>; 1030 #size-cells = <0>; 1031 1032 port@0 { 1033 reg = <0>; 1034 1035 dmic3_cif: endpoint { 1036 remote-endpoint = <&xbar_dmic3>; 1037 }; 1038 }; 1039 1040 dmic3_port: port@1 { 1041 reg = <1>; 1042 1043 dmic3_dap: endpoint { 1044 /* placeholder for external codec */ 1045 }; 1046 }; 1047 }; 1048 }; 1049 1050 tegra_dmic4: dmic@2904300 { 1051 compatible = "nvidia,tegra234-dmic", 1052 "nvidia,tegra210-dmic"; 1053 reg = <0x0 0x2904300 0x0 0x100>; 1054 clocks = <&bpmp TEGRA234_CLK_DMIC4>; 1055 clock-names = "dmic"; 1056 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>; 1057 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 1058 assigned-clock-rates = <3072000>; 1059 sound-name-prefix = "DMIC4"; 1060 status = "disabled"; 1061 1062 ports { 1063 #address-cells = <1>; 1064 #size-cells = <0>; 1065 1066 port@0 { 1067 reg = <0>; 1068 1069 dmic4_cif: endpoint { 1070 remote-endpoint = <&xbar_dmic4>; 1071 }; 1072 }; 1073 1074 dmic4_port: port@1 { 1075 reg = <1>; 1076 1077 dmic4_dap: endpoint { 1078 /* placeholder for external codec */ 1079 }; 1080 }; 1081 }; 1082 }; 1083 1084 tegra_dspk1: dspk@2905000 { 1085 compatible = "nvidia,tegra234-dspk", 1086 "nvidia,tegra186-dspk"; 1087 reg = <0x0 0x2905000 0x0 0x100>; 1088 clocks = <&bpmp TEGRA234_CLK_DSPK1>; 1089 clock-names = "dspk"; 1090 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>; 1091 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 1092 assigned-clock-rates = <12288000>; 1093 sound-name-prefix = "DSPK1"; 1094 status = "disabled"; 1095 1096 ports { 1097 #address-cells = <1>; 1098 #size-cells = <0>; 1099 1100 port@0 { 1101 reg = <0>; 1102 1103 dspk1_cif: endpoint { 1104 remote-endpoint = <&xbar_dspk1>; 1105 }; 1106 }; 1107 1108 dspk1_port: port@1 { 1109 reg = <1>; 1110 1111 dspk1_dap: endpoint { 1112 /* placeholder for external codec */ 1113 }; 1114 }; 1115 }; 1116 }; 1117 1118 tegra_dspk2: dspk@2905100 { 1119 compatible = "nvidia,tegra234-dspk", 1120 "nvidia,tegra186-dspk"; 1121 reg = <0x0 0x2905100 0x0 0x100>; 1122 clocks = <&bpmp TEGRA234_CLK_DSPK2>; 1123 clock-names = "dspk"; 1124 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>; 1125 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 1126 assigned-clock-rates = <12288000>; 1127 sound-name-prefix = "DSPK2"; 1128 status = "disabled"; 1129 1130 ports { 1131 #address-cells = <1>; 1132 #size-cells = <0>; 1133 1134 port@0 { 1135 reg = <0>; 1136 1137 dspk2_cif: endpoint { 1138 remote-endpoint = <&xbar_dspk2>; 1139 }; 1140 }; 1141 1142 dspk2_port: port@1 { 1143 reg = <1>; 1144 1145 dspk2_dap: endpoint { 1146 /* placeholder for external codec */ 1147 }; 1148 }; 1149 }; 1150 }; 1151 1152 tegra_ope1: processing-engine@2908000 { 1153 compatible = "nvidia,tegra234-ope", 1154 "nvidia,tegra210-ope"; 1155 reg = <0x0 0x2908000 0x0 0x100>; 1156 sound-name-prefix = "OPE1"; 1157 1158 #address-cells = <2>; 1159 #size-cells = <2>; 1160 ranges; 1161 1162 equalizer@2908100 { 1163 compatible = "nvidia,tegra234-peq", 1164 "nvidia,tegra210-peq"; 1165 reg = <0x0 0x2908100 0x0 0x100>; 1166 }; 1167 1168 dynamic-range-compressor@2908200 { 1169 compatible = "nvidia,tegra234-mbdrc", 1170 "nvidia,tegra210-mbdrc"; 1171 reg = <0x0 0x2908200 0x0 0x200>; 1172 }; 1173 1174 ports { 1175 #address-cells = <1>; 1176 #size-cells = <0>; 1177 1178 port@0 { 1179 reg = <0x0>; 1180 1181 ope1_cif_in_ep: endpoint { 1182 remote-endpoint = 1183 <&xbar_ope1_in_ep>; 1184 }; 1185 }; 1186 1187 ope1_out_port: port@1 { 1188 reg = <0x1>; 1189 1190 ope1_cif_out_ep: endpoint { 1191 remote-endpoint = 1192 <&xbar_ope1_out_ep>; 1193 }; 1194 }; 1195 }; 1196 }; 1197 1198 tegra_mvc1: mvc@290a000 { 1199 compatible = "nvidia,tegra234-mvc", 1200 "nvidia,tegra210-mvc"; 1201 reg = <0x0 0x290a000 0x0 0x200>; 1202 sound-name-prefix = "MVC1"; 1203 1204 ports { 1205 #address-cells = <1>; 1206 #size-cells = <0>; 1207 1208 port@0 { 1209 reg = <0>; 1210 1211 mvc1_cif_in: endpoint { 1212 remote-endpoint = <&xbar_mvc1_in>; 1213 }; 1214 }; 1215 1216 mvc1_out_port: port@1 { 1217 reg = <1>; 1218 1219 mvc1_cif_out: endpoint { 1220 remote-endpoint = <&xbar_mvc1_out>; 1221 }; 1222 }; 1223 }; 1224 }; 1225 1226 tegra_mvc2: mvc@290a200 { 1227 compatible = "nvidia,tegra234-mvc", 1228 "nvidia,tegra210-mvc"; 1229 reg = <0x0 0x290a200 0x0 0x200>; 1230 sound-name-prefix = "MVC2"; 1231 1232 ports { 1233 #address-cells = <1>; 1234 #size-cells = <0>; 1235 1236 port@0 { 1237 reg = <0>; 1238 1239 mvc2_cif_in: endpoint { 1240 remote-endpoint = <&xbar_mvc2_in>; 1241 }; 1242 }; 1243 1244 mvc2_out_port: port@1 { 1245 reg = <1>; 1246 1247 mvc2_cif_out: endpoint { 1248 remote-endpoint = <&xbar_mvc2_out>; 1249 }; 1250 }; 1251 }; 1252 }; 1253 1254 tegra_amixer: amixer@290bb00 { 1255 compatible = "nvidia,tegra234-amixer", 1256 "nvidia,tegra210-amixer"; 1257 reg = <0x0 0x290bb00 0x0 0x800>; 1258 sound-name-prefix = "MIXER1"; 1259 1260 ports { 1261 #address-cells = <1>; 1262 #size-cells = <0>; 1263 1264 port@0 { 1265 reg = <0x0>; 1266 1267 mix_in1: endpoint { 1268 remote-endpoint = <&xbar_mix_in1>; 1269 }; 1270 }; 1271 1272 port@1 { 1273 reg = <0x1>; 1274 1275 mix_in2: endpoint { 1276 remote-endpoint = <&xbar_mix_in2>; 1277 }; 1278 }; 1279 1280 port@2 { 1281 reg = <0x2>; 1282 1283 mix_in3: endpoint { 1284 remote-endpoint = <&xbar_mix_in3>; 1285 }; 1286 }; 1287 1288 port@3 { 1289 reg = <0x3>; 1290 1291 mix_in4: endpoint { 1292 remote-endpoint = <&xbar_mix_in4>; 1293 }; 1294 }; 1295 1296 port@4 { 1297 reg = <0x4>; 1298 1299 mix_in5: endpoint { 1300 remote-endpoint = <&xbar_mix_in5>; 1301 }; 1302 }; 1303 1304 port@5 { 1305 reg = <0x5>; 1306 1307 mix_in6: endpoint { 1308 remote-endpoint = <&xbar_mix_in6>; 1309 }; 1310 }; 1311 1312 port@6 { 1313 reg = <0x6>; 1314 1315 mix_in7: endpoint { 1316 remote-endpoint = <&xbar_mix_in7>; 1317 }; 1318 }; 1319 1320 port@7 { 1321 reg = <0x7>; 1322 1323 mix_in8: endpoint { 1324 remote-endpoint = <&xbar_mix_in8>; 1325 }; 1326 }; 1327 1328 port@8 { 1329 reg = <0x8>; 1330 1331 mix_in9: endpoint { 1332 remote-endpoint = <&xbar_mix_in9>; 1333 }; 1334 }; 1335 1336 port@9 { 1337 reg = <0x9>; 1338 1339 mix_in10: endpoint { 1340 remote-endpoint = <&xbar_mix_in10>; 1341 }; 1342 }; 1343 1344 mix_out1_port: port@a { 1345 reg = <0xa>; 1346 1347 mix_out1: endpoint { 1348 remote-endpoint = <&xbar_mix_out1>; 1349 }; 1350 }; 1351 1352 mix_out2_port: port@b { 1353 reg = <0xb>; 1354 1355 mix_out2: endpoint { 1356 remote-endpoint = <&xbar_mix_out2>; 1357 }; 1358 }; 1359 1360 mix_out3_port: port@c { 1361 reg = <0xc>; 1362 1363 mix_out3: endpoint { 1364 remote-endpoint = <&xbar_mix_out3>; 1365 }; 1366 }; 1367 1368 mix_out4_port: port@d { 1369 reg = <0xd>; 1370 1371 mix_out4: endpoint { 1372 remote-endpoint = <&xbar_mix_out4>; 1373 }; 1374 }; 1375 1376 mix_out5_port: port@e { 1377 reg = <0xe>; 1378 1379 mix_out5: endpoint { 1380 remote-endpoint = <&xbar_mix_out5>; 1381 }; 1382 }; 1383 }; 1384 }; 1385 1386 tegra_admaif: admaif@290f000 { 1387 compatible = "nvidia,tegra234-admaif", 1388 "nvidia,tegra186-admaif"; 1389 reg = <0x0 0x0290f000 0x0 0x1000>; 1390 dmas = <&adma 1>, <&adma 1>, 1391 <&adma 2>, <&adma 2>, 1392 <&adma 3>, <&adma 3>, 1393 <&adma 4>, <&adma 4>, 1394 <&adma 5>, <&adma 5>, 1395 <&adma 6>, <&adma 6>, 1396 <&adma 7>, <&adma 7>, 1397 <&adma 8>, <&adma 8>, 1398 <&adma 9>, <&adma 9>, 1399 <&adma 10>, <&adma 10>, 1400 <&adma 11>, <&adma 11>, 1401 <&adma 12>, <&adma 12>, 1402 <&adma 13>, <&adma 13>, 1403 <&adma 14>, <&adma 14>, 1404 <&adma 15>, <&adma 15>, 1405 <&adma 16>, <&adma 16>, 1406 <&adma 17>, <&adma 17>, 1407 <&adma 18>, <&adma 18>, 1408 <&adma 19>, <&adma 19>, 1409 <&adma 20>, <&adma 20>; 1410 dma-names = "rx1", "tx1", 1411 "rx2", "tx2", 1412 "rx3", "tx3", 1413 "rx4", "tx4", 1414 "rx5", "tx5", 1415 "rx6", "tx6", 1416 "rx7", "tx7", 1417 "rx8", "tx8", 1418 "rx9", "tx9", 1419 "rx10", "tx10", 1420 "rx11", "tx11", 1421 "rx12", "tx12", 1422 "rx13", "tx13", 1423 "rx14", "tx14", 1424 "rx15", "tx15", 1425 "rx16", "tx16", 1426 "rx17", "tx17", 1427 "rx18", "tx18", 1428 "rx19", "tx19", 1429 "rx20", "tx20"; 1430 interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>, 1431 <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>; 1432 interconnect-names = "dma-mem", "write"; 1433 iommus = <&smmu_niso0 TEGRA234_SID_APE>; 1434 1435 ports { 1436 #address-cells = <1>; 1437 #size-cells = <0>; 1438 1439 admaif0_port: port@0 { 1440 reg = <0x0>; 1441 1442 admaif0: endpoint { 1443 remote-endpoint = <&xbar_admaif0>; 1444 }; 1445 }; 1446 1447 admaif1_port: port@1 { 1448 reg = <0x1>; 1449 1450 admaif1: endpoint { 1451 remote-endpoint = <&xbar_admaif1>; 1452 }; 1453 }; 1454 1455 admaif2_port: port@2 { 1456 reg = <0x2>; 1457 1458 admaif2: endpoint { 1459 remote-endpoint = <&xbar_admaif2>; 1460 }; 1461 }; 1462 1463 admaif3_port: port@3 { 1464 reg = <0x3>; 1465 1466 admaif3: endpoint { 1467 remote-endpoint = <&xbar_admaif3>; 1468 }; 1469 }; 1470 1471 admaif4_port: port@4 { 1472 reg = <0x4>; 1473 1474 admaif4: endpoint { 1475 remote-endpoint = <&xbar_admaif4>; 1476 }; 1477 }; 1478 1479 admaif5_port: port@5 { 1480 reg = <0x5>; 1481 1482 admaif5: endpoint { 1483 remote-endpoint = <&xbar_admaif5>; 1484 }; 1485 }; 1486 1487 admaif6_port: port@6 { 1488 reg = <0x6>; 1489 1490 admaif6: endpoint { 1491 remote-endpoint = <&xbar_admaif6>; 1492 }; 1493 }; 1494 1495 admaif7_port: port@7 { 1496 reg = <0x7>; 1497 1498 admaif7: endpoint { 1499 remote-endpoint = <&xbar_admaif7>; 1500 }; 1501 }; 1502 1503 admaif8_port: port@8 { 1504 reg = <0x8>; 1505 1506 admaif8: endpoint { 1507 remote-endpoint = <&xbar_admaif8>; 1508 }; 1509 }; 1510 1511 admaif9_port: port@9 { 1512 reg = <0x9>; 1513 1514 admaif9: endpoint { 1515 remote-endpoint = <&xbar_admaif9>; 1516 }; 1517 }; 1518 1519 admaif10_port: port@a { 1520 reg = <0xa>; 1521 1522 admaif10: endpoint { 1523 remote-endpoint = <&xbar_admaif10>; 1524 }; 1525 }; 1526 1527 admaif11_port: port@b { 1528 reg = <0xb>; 1529 1530 admaif11: endpoint { 1531 remote-endpoint = <&xbar_admaif11>; 1532 }; 1533 }; 1534 1535 admaif12_port: port@c { 1536 reg = <0xc>; 1537 1538 admaif12: endpoint { 1539 remote-endpoint = <&xbar_admaif12>; 1540 }; 1541 }; 1542 1543 admaif13_port: port@d { 1544 reg = <0xd>; 1545 1546 admaif13: endpoint { 1547 remote-endpoint = <&xbar_admaif13>; 1548 }; 1549 }; 1550 1551 admaif14_port: port@e { 1552 reg = <0xe>; 1553 1554 admaif14: endpoint { 1555 remote-endpoint = <&xbar_admaif14>; 1556 }; 1557 }; 1558 1559 admaif15_port: port@f { 1560 reg = <0xf>; 1561 1562 admaif15: endpoint { 1563 remote-endpoint = <&xbar_admaif15>; 1564 }; 1565 }; 1566 1567 admaif16_port: port@10 { 1568 reg = <0x10>; 1569 1570 admaif16: endpoint { 1571 remote-endpoint = <&xbar_admaif16>; 1572 }; 1573 }; 1574 1575 admaif17_port: port@11 { 1576 reg = <0x11>; 1577 1578 admaif17: endpoint { 1579 remote-endpoint = <&xbar_admaif17>; 1580 }; 1581 }; 1582 1583 admaif18_port: port@12 { 1584 reg = <0x12>; 1585 1586 admaif18: endpoint { 1587 remote-endpoint = <&xbar_admaif18>; 1588 }; 1589 }; 1590 1591 admaif19_port: port@13 { 1592 reg = <0x13>; 1593 1594 admaif19: endpoint { 1595 remote-endpoint = <&xbar_admaif19>; 1596 }; 1597 }; 1598 }; 1599 }; 1600 1601 tegra_asrc: asrc@2910000 { 1602 compatible = "nvidia,tegra234-asrc", 1603 "nvidia,tegra186-asrc"; 1604 reg = <0x0 0x2910000 0x0 0x2000>; 1605 sound-name-prefix = "ASRC1"; 1606 1607 ports { 1608 #address-cells = <1>; 1609 #size-cells = <0>; 1610 1611 port@0 { 1612 reg = <0x0>; 1613 1614 asrc_in1_ep: endpoint { 1615 remote-endpoint = 1616 <&xbar_asrc_in1_ep>; 1617 }; 1618 }; 1619 1620 port@1 { 1621 reg = <0x1>; 1622 1623 asrc_in2_ep: endpoint { 1624 remote-endpoint = 1625 <&xbar_asrc_in2_ep>; 1626 }; 1627 }; 1628 1629 port@2 { 1630 reg = <0x2>; 1631 1632 asrc_in3_ep: endpoint { 1633 remote-endpoint = 1634 <&xbar_asrc_in3_ep>; 1635 }; 1636 }; 1637 1638 port@3 { 1639 reg = <0x3>; 1640 1641 asrc_in4_ep: endpoint { 1642 remote-endpoint = 1643 <&xbar_asrc_in4_ep>; 1644 }; 1645 }; 1646 1647 port@4 { 1648 reg = <0x4>; 1649 1650 asrc_in5_ep: endpoint { 1651 remote-endpoint = 1652 <&xbar_asrc_in5_ep>; 1653 }; 1654 }; 1655 1656 port@5 { 1657 reg = <0x5>; 1658 1659 asrc_in6_ep: endpoint { 1660 remote-endpoint = 1661 <&xbar_asrc_in6_ep>; 1662 }; 1663 }; 1664 1665 port@6 { 1666 reg = <0x6>; 1667 1668 asrc_in7_ep: endpoint { 1669 remote-endpoint = 1670 <&xbar_asrc_in7_ep>; 1671 }; 1672 }; 1673 1674 asrc_out1_port: port@7 { 1675 reg = <0x7>; 1676 1677 asrc_out1_ep: endpoint { 1678 remote-endpoint = 1679 <&xbar_asrc_out1_ep>; 1680 }; 1681 }; 1682 1683 asrc_out2_port: port@8 { 1684 reg = <0x8>; 1685 1686 asrc_out2_ep: endpoint { 1687 remote-endpoint = 1688 <&xbar_asrc_out2_ep>; 1689 }; 1690 }; 1691 1692 asrc_out3_port: port@9 { 1693 reg = <0x9>; 1694 1695 asrc_out3_ep: endpoint { 1696 remote-endpoint = 1697 <&xbar_asrc_out3_ep>; 1698 }; 1699 }; 1700 1701 asrc_out4_port: port@a { 1702 reg = <0xa>; 1703 1704 asrc_out4_ep: endpoint { 1705 remote-endpoint = 1706 <&xbar_asrc_out4_ep>; 1707 }; 1708 }; 1709 1710 asrc_out5_port: port@b { 1711 reg = <0xb>; 1712 1713 asrc_out5_ep: endpoint { 1714 remote-endpoint = 1715 <&xbar_asrc_out5_ep>; 1716 }; 1717 }; 1718 1719 asrc_out6_port: port@c { 1720 reg = <0xc>; 1721 1722 asrc_out6_ep: endpoint { 1723 remote-endpoint = 1724 <&xbar_asrc_out6_ep>; 1725 }; 1726 }; 1727 }; 1728 }; 1729 1730 ports { 1731 #address-cells = <1>; 1732 #size-cells = <0>; 1733 1734 port@0 { 1735 reg = <0x0>; 1736 1737 xbar_admaif0: endpoint { 1738 remote-endpoint = <&admaif0>; 1739 }; 1740 }; 1741 1742 port@1 { 1743 reg = <0x1>; 1744 1745 xbar_admaif1: endpoint { 1746 remote-endpoint = <&admaif1>; 1747 }; 1748 }; 1749 1750 port@2 { 1751 reg = <0x2>; 1752 1753 xbar_admaif2: endpoint { 1754 remote-endpoint = <&admaif2>; 1755 }; 1756 }; 1757 1758 port@3 { 1759 reg = <0x3>; 1760 1761 xbar_admaif3: endpoint { 1762 remote-endpoint = <&admaif3>; 1763 }; 1764 }; 1765 1766 port@4 { 1767 reg = <0x4>; 1768 1769 xbar_admaif4: endpoint { 1770 remote-endpoint = <&admaif4>; 1771 }; 1772 }; 1773 1774 port@5 { 1775 reg = <0x5>; 1776 1777 xbar_admaif5: endpoint { 1778 remote-endpoint = <&admaif5>; 1779 }; 1780 }; 1781 1782 port@6 { 1783 reg = <0x6>; 1784 1785 xbar_admaif6: endpoint { 1786 remote-endpoint = <&admaif6>; 1787 }; 1788 }; 1789 1790 port@7 { 1791 reg = <0x7>; 1792 1793 xbar_admaif7: endpoint { 1794 remote-endpoint = <&admaif7>; 1795 }; 1796 }; 1797 1798 port@8 { 1799 reg = <0x8>; 1800 1801 xbar_admaif8: endpoint { 1802 remote-endpoint = <&admaif8>; 1803 }; 1804 }; 1805 1806 port@9 { 1807 reg = <0x9>; 1808 1809 xbar_admaif9: endpoint { 1810 remote-endpoint = <&admaif9>; 1811 }; 1812 }; 1813 1814 port@a { 1815 reg = <0xa>; 1816 1817 xbar_admaif10: endpoint { 1818 remote-endpoint = <&admaif10>; 1819 }; 1820 }; 1821 1822 port@b { 1823 reg = <0xb>; 1824 1825 xbar_admaif11: endpoint { 1826 remote-endpoint = <&admaif11>; 1827 }; 1828 }; 1829 1830 port@c { 1831 reg = <0xc>; 1832 1833 xbar_admaif12: endpoint { 1834 remote-endpoint = <&admaif12>; 1835 }; 1836 }; 1837 1838 port@d { 1839 reg = <0xd>; 1840 1841 xbar_admaif13: endpoint { 1842 remote-endpoint = <&admaif13>; 1843 }; 1844 }; 1845 1846 port@e { 1847 reg = <0xe>; 1848 1849 xbar_admaif14: endpoint { 1850 remote-endpoint = <&admaif14>; 1851 }; 1852 }; 1853 1854 port@f { 1855 reg = <0xf>; 1856 1857 xbar_admaif15: endpoint { 1858 remote-endpoint = <&admaif15>; 1859 }; 1860 }; 1861 1862 port@10 { 1863 reg = <0x10>; 1864 1865 xbar_admaif16: endpoint { 1866 remote-endpoint = <&admaif16>; 1867 }; 1868 }; 1869 1870 port@11 { 1871 reg = <0x11>; 1872 1873 xbar_admaif17: endpoint { 1874 remote-endpoint = <&admaif17>; 1875 }; 1876 }; 1877 1878 port@12 { 1879 reg = <0x12>; 1880 1881 xbar_admaif18: endpoint { 1882 remote-endpoint = <&admaif18>; 1883 }; 1884 }; 1885 1886 port@13 { 1887 reg = <0x13>; 1888 1889 xbar_admaif19: endpoint { 1890 remote-endpoint = <&admaif19>; 1891 }; 1892 }; 1893 1894 xbar_i2s1_port: port@14 { 1895 reg = <0x14>; 1896 1897 xbar_i2s1: endpoint { 1898 remote-endpoint = <&i2s1_cif>; 1899 }; 1900 }; 1901 1902 xbar_i2s2_port: port@15 { 1903 reg = <0x15>; 1904 1905 xbar_i2s2: endpoint { 1906 remote-endpoint = <&i2s2_cif>; 1907 }; 1908 }; 1909 1910 xbar_i2s3_port: port@16 { 1911 reg = <0x16>; 1912 1913 xbar_i2s3: endpoint { 1914 remote-endpoint = <&i2s3_cif>; 1915 }; 1916 }; 1917 1918 xbar_i2s4_port: port@17 { 1919 reg = <0x17>; 1920 1921 xbar_i2s4: endpoint { 1922 remote-endpoint = <&i2s4_cif>; 1923 }; 1924 }; 1925 1926 xbar_i2s5_port: port@18 { 1927 reg = <0x18>; 1928 1929 xbar_i2s5: endpoint { 1930 remote-endpoint = <&i2s5_cif>; 1931 }; 1932 }; 1933 1934 xbar_i2s6_port: port@19 { 1935 reg = <0x19>; 1936 1937 xbar_i2s6: endpoint { 1938 remote-endpoint = <&i2s6_cif>; 1939 }; 1940 }; 1941 1942 xbar_dmic1_port: port@1a { 1943 reg = <0x1a>; 1944 1945 xbar_dmic1: endpoint { 1946 remote-endpoint = <&dmic1_cif>; 1947 }; 1948 }; 1949 1950 xbar_dmic2_port: port@1b { 1951 reg = <0x1b>; 1952 1953 xbar_dmic2: endpoint { 1954 remote-endpoint = <&dmic2_cif>; 1955 }; 1956 }; 1957 1958 xbar_dmic3_port: port@1c { 1959 reg = <0x1c>; 1960 1961 xbar_dmic3: endpoint { 1962 remote-endpoint = <&dmic3_cif>; 1963 }; 1964 }; 1965 1966 xbar_dmic4_port: port@1d { 1967 reg = <0x1d>; 1968 1969 xbar_dmic4: endpoint { 1970 remote-endpoint = <&dmic4_cif>; 1971 }; 1972 }; 1973 1974 xbar_dspk1_port: port@1e { 1975 reg = <0x1e>; 1976 1977 xbar_dspk1: endpoint { 1978 remote-endpoint = <&dspk1_cif>; 1979 }; 1980 }; 1981 1982 xbar_dspk2_port: port@1f { 1983 reg = <0x1f>; 1984 1985 xbar_dspk2: endpoint { 1986 remote-endpoint = <&dspk2_cif>; 1987 }; 1988 }; 1989 1990 xbar_sfc1_in_port: port@20 { 1991 reg = <0x20>; 1992 1993 xbar_sfc1_in: endpoint { 1994 remote-endpoint = <&sfc1_cif_in>; 1995 }; 1996 }; 1997 1998 port@21 { 1999 reg = <0x21>; 2000 2001 xbar_sfc1_out: endpoint { 2002 remote-endpoint = <&sfc1_cif_out>; 2003 }; 2004 }; 2005 2006 xbar_sfc2_in_port: port@22 { 2007 reg = <0x22>; 2008 2009 xbar_sfc2_in: endpoint { 2010 remote-endpoint = <&sfc2_cif_in>; 2011 }; 2012 }; 2013 2014 port@23 { 2015 reg = <0x23>; 2016 2017 xbar_sfc2_out: endpoint { 2018 remote-endpoint = <&sfc2_cif_out>; 2019 }; 2020 }; 2021 2022 xbar_sfc3_in_port: port@24 { 2023 reg = <0x24>; 2024 2025 xbar_sfc3_in: endpoint { 2026 remote-endpoint = <&sfc3_cif_in>; 2027 }; 2028 }; 2029 2030 port@25 { 2031 reg = <0x25>; 2032 2033 xbar_sfc3_out: endpoint { 2034 remote-endpoint = <&sfc3_cif_out>; 2035 }; 2036 }; 2037 2038 xbar_sfc4_in_port: port@26 { 2039 reg = <0x26>; 2040 2041 xbar_sfc4_in: endpoint { 2042 remote-endpoint = <&sfc4_cif_in>; 2043 }; 2044 }; 2045 2046 port@27 { 2047 reg = <0x27>; 2048 2049 xbar_sfc4_out: endpoint { 2050 remote-endpoint = <&sfc4_cif_out>; 2051 }; 2052 }; 2053 2054 xbar_mvc1_in_port: port@28 { 2055 reg = <0x28>; 2056 2057 xbar_mvc1_in: endpoint { 2058 remote-endpoint = <&mvc1_cif_in>; 2059 }; 2060 }; 2061 2062 port@29 { 2063 reg = <0x29>; 2064 2065 xbar_mvc1_out: endpoint { 2066 remote-endpoint = <&mvc1_cif_out>; 2067 }; 2068 }; 2069 2070 xbar_mvc2_in_port: port@2a { 2071 reg = <0x2a>; 2072 2073 xbar_mvc2_in: endpoint { 2074 remote-endpoint = <&mvc2_cif_in>; 2075 }; 2076 }; 2077 2078 port@2b { 2079 reg = <0x2b>; 2080 2081 xbar_mvc2_out: endpoint { 2082 remote-endpoint = <&mvc2_cif_out>; 2083 }; 2084 }; 2085 2086 xbar_amx1_in1_port: port@2c { 2087 reg = <0x2c>; 2088 2089 xbar_amx1_in1: endpoint { 2090 remote-endpoint = <&amx1_in1>; 2091 }; 2092 }; 2093 2094 xbar_amx1_in2_port: port@2d { 2095 reg = <0x2d>; 2096 2097 xbar_amx1_in2: endpoint { 2098 remote-endpoint = <&amx1_in2>; 2099 }; 2100 }; 2101 2102 xbar_amx1_in3_port: port@2e { 2103 reg = <0x2e>; 2104 2105 xbar_amx1_in3: endpoint { 2106 remote-endpoint = <&amx1_in3>; 2107 }; 2108 }; 2109 2110 xbar_amx1_in4_port: port@2f { 2111 reg = <0x2f>; 2112 2113 xbar_amx1_in4: endpoint { 2114 remote-endpoint = <&amx1_in4>; 2115 }; 2116 }; 2117 2118 port@30 { 2119 reg = <0x30>; 2120 2121 xbar_amx1_out: endpoint { 2122 remote-endpoint = <&amx1_out>; 2123 }; 2124 }; 2125 2126 xbar_amx2_in1_port: port@31 { 2127 reg = <0x31>; 2128 2129 xbar_amx2_in1: endpoint { 2130 remote-endpoint = <&amx2_in1>; 2131 }; 2132 }; 2133 2134 xbar_amx2_in2_port: port@32 { 2135 reg = <0x32>; 2136 2137 xbar_amx2_in2: endpoint { 2138 remote-endpoint = <&amx2_in2>; 2139 }; 2140 }; 2141 2142 xbar_amx2_in3_port: port@33 { 2143 reg = <0x33>; 2144 2145 xbar_amx2_in3: endpoint { 2146 remote-endpoint = <&amx2_in3>; 2147 }; 2148 }; 2149 2150 xbar_amx2_in4_port: port@34 { 2151 reg = <0x34>; 2152 2153 xbar_amx2_in4: endpoint { 2154 remote-endpoint = <&amx2_in4>; 2155 }; 2156 }; 2157 2158 port@35 { 2159 reg = <0x35>; 2160 2161 xbar_amx2_out: endpoint { 2162 remote-endpoint = <&amx2_out>; 2163 }; 2164 }; 2165 2166 xbar_amx3_in1_port: port@36 { 2167 reg = <0x36>; 2168 2169 xbar_amx3_in1: endpoint { 2170 remote-endpoint = <&amx3_in1>; 2171 }; 2172 }; 2173 2174 xbar_amx3_in2_port: port@37 { 2175 reg = <0x37>; 2176 2177 xbar_amx3_in2: endpoint { 2178 remote-endpoint = <&amx3_in2>; 2179 }; 2180 }; 2181 2182 xbar_amx3_in3_port: port@38 { 2183 reg = <0x38>; 2184 2185 xbar_amx3_in3: endpoint { 2186 remote-endpoint = <&amx3_in3>; 2187 }; 2188 }; 2189 2190 xbar_amx3_in4_port: port@39 { 2191 reg = <0x39>; 2192 2193 xbar_amx3_in4: endpoint { 2194 remote-endpoint = <&amx3_in4>; 2195 }; 2196 }; 2197 2198 port@3a { 2199 reg = <0x3a>; 2200 2201 xbar_amx3_out: endpoint { 2202 remote-endpoint = <&amx3_out>; 2203 }; 2204 }; 2205 2206 xbar_amx4_in1_port: port@3b { 2207 reg = <0x3b>; 2208 2209 xbar_amx4_in1: endpoint { 2210 remote-endpoint = <&amx4_in1>; 2211 }; 2212 }; 2213 2214 xbar_amx4_in2_port: port@3c { 2215 reg = <0x3c>; 2216 2217 xbar_amx4_in2: endpoint { 2218 remote-endpoint = <&amx4_in2>; 2219 }; 2220 }; 2221 2222 xbar_amx4_in3_port: port@3d { 2223 reg = <0x3d>; 2224 2225 xbar_amx4_in3: endpoint { 2226 remote-endpoint = <&amx4_in3>; 2227 }; 2228 }; 2229 2230 xbar_amx4_in4_port: port@3e { 2231 reg = <0x3e>; 2232 2233 xbar_amx4_in4: endpoint { 2234 remote-endpoint = <&amx4_in4>; 2235 }; 2236 }; 2237 2238 port@3f { 2239 reg = <0x3f>; 2240 2241 xbar_amx4_out: endpoint { 2242 remote-endpoint = <&amx4_out>; 2243 }; 2244 }; 2245 2246 xbar_adx1_in_port: port@40 { 2247 reg = <0x40>; 2248 2249 xbar_adx1_in: endpoint { 2250 remote-endpoint = <&adx1_in>; 2251 }; 2252 }; 2253 2254 port@41 { 2255 reg = <0x41>; 2256 2257 xbar_adx1_out1: endpoint { 2258 remote-endpoint = <&adx1_out1>; 2259 }; 2260 }; 2261 2262 port@42 { 2263 reg = <0x42>; 2264 2265 xbar_adx1_out2: endpoint { 2266 remote-endpoint = <&adx1_out2>; 2267 }; 2268 }; 2269 2270 port@43 { 2271 reg = <0x43>; 2272 2273 xbar_adx1_out3: endpoint { 2274 remote-endpoint = <&adx1_out3>; 2275 }; 2276 }; 2277 2278 port@44 { 2279 reg = <0x44>; 2280 2281 xbar_adx1_out4: endpoint { 2282 remote-endpoint = <&adx1_out4>; 2283 }; 2284 }; 2285 2286 xbar_adx2_in_port: port@45 { 2287 reg = <0x45>; 2288 2289 xbar_adx2_in: endpoint { 2290 remote-endpoint = <&adx2_in>; 2291 }; 2292 }; 2293 2294 port@46 { 2295 reg = <0x46>; 2296 2297 xbar_adx2_out1: endpoint { 2298 remote-endpoint = <&adx2_out1>; 2299 }; 2300 }; 2301 2302 port@47 { 2303 reg = <0x47>; 2304 2305 xbar_adx2_out2: endpoint { 2306 remote-endpoint = <&adx2_out2>; 2307 }; 2308 }; 2309 2310 port@48 { 2311 reg = <0x48>; 2312 2313 xbar_adx2_out3: endpoint { 2314 remote-endpoint = <&adx2_out3>; 2315 }; 2316 }; 2317 2318 port@49 { 2319 reg = <0x49>; 2320 2321 xbar_adx2_out4: endpoint { 2322 remote-endpoint = <&adx2_out4>; 2323 }; 2324 }; 2325 2326 xbar_adx3_in_port: port@4a { 2327 reg = <0x4a>; 2328 2329 xbar_adx3_in: endpoint { 2330 remote-endpoint = <&adx3_in>; 2331 }; 2332 }; 2333 2334 port@4b { 2335 reg = <0x4b>; 2336 2337 xbar_adx3_out1: endpoint { 2338 remote-endpoint = <&adx3_out1>; 2339 }; 2340 }; 2341 2342 port@4c { 2343 reg = <0x4c>; 2344 2345 xbar_adx3_out2: endpoint { 2346 remote-endpoint = <&adx3_out2>; 2347 }; 2348 }; 2349 2350 port@4d { 2351 reg = <0x4d>; 2352 2353 xbar_adx3_out3: endpoint { 2354 remote-endpoint = <&adx3_out3>; 2355 }; 2356 }; 2357 2358 port@4e { 2359 reg = <0x4e>; 2360 2361 xbar_adx3_out4: endpoint { 2362 remote-endpoint = <&adx3_out4>; 2363 }; 2364 }; 2365 2366 xbar_adx4_in_port: port@4f { 2367 reg = <0x4f>; 2368 2369 xbar_adx4_in: endpoint { 2370 remote-endpoint = <&adx4_in>; 2371 }; 2372 }; 2373 2374 port@50 { 2375 reg = <0x50>; 2376 2377 xbar_adx4_out1: endpoint { 2378 remote-endpoint = <&adx4_out1>; 2379 }; 2380 }; 2381 2382 port@51 { 2383 reg = <0x51>; 2384 2385 xbar_adx4_out2: endpoint { 2386 remote-endpoint = <&adx4_out2>; 2387 }; 2388 }; 2389 2390 port@52 { 2391 reg = <0x52>; 2392 2393 xbar_adx4_out3: endpoint { 2394 remote-endpoint = <&adx4_out3>; 2395 }; 2396 }; 2397 2398 port@53 { 2399 reg = <0x53>; 2400 2401 xbar_adx4_out4: endpoint { 2402 remote-endpoint = <&adx4_out4>; 2403 }; 2404 }; 2405 2406 xbar_mix_in1_port: port@54 { 2407 reg = <0x54>; 2408 2409 xbar_mix_in1: endpoint { 2410 remote-endpoint = <&mix_in1>; 2411 }; 2412 }; 2413 2414 xbar_mix_in2_port: port@55 { 2415 reg = <0x55>; 2416 2417 xbar_mix_in2: endpoint { 2418 remote-endpoint = <&mix_in2>; 2419 }; 2420 }; 2421 2422 xbar_mix_in3_port: port@56 { 2423 reg = <0x56>; 2424 2425 xbar_mix_in3: endpoint { 2426 remote-endpoint = <&mix_in3>; 2427 }; 2428 }; 2429 2430 xbar_mix_in4_port: port@57 { 2431 reg = <0x57>; 2432 2433 xbar_mix_in4: endpoint { 2434 remote-endpoint = <&mix_in4>; 2435 }; 2436 }; 2437 2438 xbar_mix_in5_port: port@58 { 2439 reg = <0x58>; 2440 2441 xbar_mix_in5: endpoint { 2442 remote-endpoint = <&mix_in5>; 2443 }; 2444 }; 2445 2446 xbar_mix_in6_port: port@59 { 2447 reg = <0x59>; 2448 2449 xbar_mix_in6: endpoint { 2450 remote-endpoint = <&mix_in6>; 2451 }; 2452 }; 2453 2454 xbar_mix_in7_port: port@5a { 2455 reg = <0x5a>; 2456 2457 xbar_mix_in7: endpoint { 2458 remote-endpoint = <&mix_in7>; 2459 }; 2460 }; 2461 2462 xbar_mix_in8_port: port@5b { 2463 reg = <0x5b>; 2464 2465 xbar_mix_in8: endpoint { 2466 remote-endpoint = <&mix_in8>; 2467 }; 2468 }; 2469 2470 xbar_mix_in9_port: port@5c { 2471 reg = <0x5c>; 2472 2473 xbar_mix_in9: endpoint { 2474 remote-endpoint = <&mix_in9>; 2475 }; 2476 }; 2477 2478 xbar_mix_in10_port: port@5d { 2479 reg = <0x5d>; 2480 2481 xbar_mix_in10: endpoint { 2482 remote-endpoint = <&mix_in10>; 2483 }; 2484 }; 2485 2486 port@5e { 2487 reg = <0x5e>; 2488 2489 xbar_mix_out1: endpoint { 2490 remote-endpoint = <&mix_out1>; 2491 }; 2492 }; 2493 2494 port@5f { 2495 reg = <0x5f>; 2496 2497 xbar_mix_out2: endpoint { 2498 remote-endpoint = <&mix_out2>; 2499 }; 2500 }; 2501 2502 port@60 { 2503 reg = <0x60>; 2504 2505 xbar_mix_out3: endpoint { 2506 remote-endpoint = <&mix_out3>; 2507 }; 2508 }; 2509 2510 port@61 { 2511 reg = <0x61>; 2512 2513 xbar_mix_out4: endpoint { 2514 remote-endpoint = <&mix_out4>; 2515 }; 2516 }; 2517 2518 port@62 { 2519 reg = <0x62>; 2520 2521 xbar_mix_out5: endpoint { 2522 remote-endpoint = <&mix_out5>; 2523 }; 2524 }; 2525 2526 xbar_asrc_in1_port: port@63 { 2527 reg = <0x63>; 2528 2529 xbar_asrc_in1_ep: endpoint { 2530 remote-endpoint = <&asrc_in1_ep>; 2531 }; 2532 }; 2533 2534 port@64 { 2535 reg = <0x64>; 2536 2537 xbar_asrc_out1_ep: endpoint { 2538 remote-endpoint = <&asrc_out1_ep>; 2539 }; 2540 }; 2541 2542 xbar_asrc_in2_port: port@65 { 2543 reg = <0x65>; 2544 2545 xbar_asrc_in2_ep: endpoint { 2546 remote-endpoint = <&asrc_in2_ep>; 2547 }; 2548 }; 2549 2550 port@66 { 2551 reg = <0x66>; 2552 2553 xbar_asrc_out2_ep: endpoint { 2554 remote-endpoint = <&asrc_out2_ep>; 2555 }; 2556 }; 2557 2558 xbar_asrc_in3_port: port@67 { 2559 reg = <0x67>; 2560 2561 xbar_asrc_in3_ep: endpoint { 2562 remote-endpoint = <&asrc_in3_ep>; 2563 }; 2564 }; 2565 2566 port@68 { 2567 reg = <0x68>; 2568 2569 xbar_asrc_out3_ep: endpoint { 2570 remote-endpoint = <&asrc_out3_ep>; 2571 }; 2572 }; 2573 2574 xbar_asrc_in4_port: port@69 { 2575 reg = <0x69>; 2576 2577 xbar_asrc_in4_ep: endpoint { 2578 remote-endpoint = <&asrc_in4_ep>; 2579 }; 2580 }; 2581 2582 port@6a { 2583 reg = <0x6a>; 2584 2585 xbar_asrc_out4_ep: endpoint { 2586 remote-endpoint = <&asrc_out4_ep>; 2587 }; 2588 }; 2589 2590 xbar_asrc_in5_port: port@6b { 2591 reg = <0x6b>; 2592 2593 xbar_asrc_in5_ep: endpoint { 2594 remote-endpoint = <&asrc_in5_ep>; 2595 }; 2596 }; 2597 2598 port@6c { 2599 reg = <0x6c>; 2600 2601 xbar_asrc_out5_ep: endpoint { 2602 remote-endpoint = <&asrc_out5_ep>; 2603 }; 2604 }; 2605 2606 xbar_asrc_in6_port: port@6d { 2607 reg = <0x6d>; 2608 2609 xbar_asrc_in6_ep: endpoint { 2610 remote-endpoint = <&asrc_in6_ep>; 2611 }; 2612 }; 2613 2614 port@6e { 2615 reg = <0x6e>; 2616 2617 xbar_asrc_out6_ep: endpoint { 2618 remote-endpoint = <&asrc_out6_ep>; 2619 }; 2620 }; 2621 2622 xbar_asrc_in7_port: port@6f { 2623 reg = <0x6f>; 2624 2625 xbar_asrc_in7_ep: endpoint { 2626 remote-endpoint = <&asrc_in7_ep>; 2627 }; 2628 }; 2629 2630 xbar_ope1_in_port: port@70 { 2631 reg = <0x70>; 2632 2633 xbar_ope1_in_ep: endpoint { 2634 remote-endpoint = <&ope1_cif_in_ep>; 2635 }; 2636 }; 2637 2638 port@71 { 2639 reg = <0x71>; 2640 2641 xbar_ope1_out_ep: endpoint { 2642 remote-endpoint = <&ope1_cif_out_ep>; 2643 }; 2644 }; 2645 }; 2646 }; 2647 2648 adma: dma-controller@2930000 { 2649 compatible = "nvidia,tegra234-adma", 2650 "nvidia,tegra186-adma"; 2651 reg = <0x0 0x02930000 0x0 0x20000>; 2652 interrupt-parent = <&agic>; 2653 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 2654 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 2655 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 2656 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2657 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2658 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 2659 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 2660 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 2661 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2662 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 2663 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 2664 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 2665 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 2666 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 2667 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 2668 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 2669 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 2670 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 2671 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 2672 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 2673 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 2674 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 2675 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 2676 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 2677 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 2678 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 2679 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 2680 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 2681 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 2682 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 2683 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 2684 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2685 #dma-cells = <1>; 2686 clocks = <&bpmp TEGRA234_CLK_AHUB>; 2687 clock-names = "d_audio"; 2688 status = "disabled"; 2689 }; 2690 2691 agic: interrupt-controller@2a40000 { 2692 compatible = "nvidia,tegra234-agic", 2693 "nvidia,tegra210-agic"; 2694 #interrupt-cells = <3>; 2695 interrupt-controller; 2696 reg = <0x0 0x02a41000 0x0 0x1000>, 2697 <0x0 0x02a42000 0x0 0x2000>; 2698 interrupts = <GIC_SPI 145 2699 (GIC_CPU_MASK_SIMPLE(4) | 2700 IRQ_TYPE_LEVEL_HIGH)>; 2701 clocks = <&bpmp TEGRA234_CLK_APE>; 2702 clock-names = "clk"; 2703 status = "disabled"; 2704 }; 2705 }; 2706 2707 mc: memory-controller@2c00000 { 2708 compatible = "nvidia,tegra234-mc"; 2709 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 2710 <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/ 2711 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 2712 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 2713 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 2714 <0x0 0x02c50000 0x0 0x10000>, /* MC3 */ 2715 <0x0 0x02b80000 0x0 0x10000>, /* MC4 */ 2716 <0x0 0x02b90000 0x0 0x10000>, /* MC5 */ 2717 <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */ 2718 <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */ 2719 <0x0 0x01700000 0x0 0x10000>, /* MC8 */ 2720 <0x0 0x01710000 0x0 0x10000>, /* MC9 */ 2721 <0x0 0x01720000 0x0 0x10000>, /* MC10 */ 2722 <0x0 0x01730000 0x0 0x10000>, /* MC11 */ 2723 <0x0 0x01740000 0x0 0x10000>, /* MC12 */ 2724 <0x0 0x01750000 0x0 0x10000>, /* MC13 */ 2725 <0x0 0x01760000 0x0 0x10000>, /* MC14 */ 2726 <0x0 0x01770000 0x0 0x10000>; /* MC15 */ 2727 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 2728 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 2729 "ch11", "ch12", "ch13", "ch14", "ch15"; 2730 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2731 #interconnect-cells = <1>; 2732 status = "okay"; 2733 2734 #address-cells = <2>; 2735 #size-cells = <2>; 2736 ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>, 2737 <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>, 2738 <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>; 2739 2740 /* 2741 * Bit 39 of addresses passing through the memory 2742 * controller selects the XBAR format used when memory 2743 * is accessed. This is used to transparently access 2744 * memory in the XBAR format used by the discrete GPU 2745 * (bit 39 set) or Tegra (bit 39 clear). 2746 * 2747 * As a consequence, the operating system must ensure 2748 * that bit 39 is never used implicitly, for example 2749 * via an I/O virtual address mapping of an IOMMU. If 2750 * devices require access to the XBAR switch, their 2751 * drivers must set this bit explicitly. 2752 * 2753 * Limit the DMA range for memory clients to [38:0]. 2754 */ 2755 dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>; 2756 2757 emc: external-memory-controller@2c60000 { 2758 compatible = "nvidia,tegra234-emc"; 2759 reg = <0x0 0x02c60000 0x0 0x90000>, 2760 <0x0 0x01780000 0x0 0x80000>; 2761 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 2762 clocks = <&bpmp TEGRA234_CLK_EMC>; 2763 clock-names = "emc"; 2764 status = "okay"; 2765 2766 #interconnect-cells = <0>; 2767 2768 nvidia,bpmp = <&bpmp>; 2769 }; 2770 }; 2771 2772 uarta: serial@3100000 { 2773 compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 2774 reg = <0x0 0x03100000 0x0 0x10000>; 2775 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2776 clocks = <&bpmp TEGRA234_CLK_UARTA>; 2777 resets = <&bpmp TEGRA234_RESET_UARTA>; 2778 dmas = <&gpcdma 8>, <&gpcdma 8>; 2779 dma-names = "rx", "tx"; 2780 status = "disabled"; 2781 }; 2782 2783 uarte: serial@3140000 { 2784 compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 2785 reg = <0x0 0x03140000 0x0 0x10000>; 2786 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 2787 clocks = <&bpmp TEGRA234_CLK_UARTE>; 2788 resets = <&bpmp TEGRA234_RESET_UARTE>; 2789 dmas = <&gpcdma 20>, <&gpcdma 20>; 2790 dma-names = "rx", "tx"; 2791 status = "disabled"; 2792 }; 2793 2794 gen1_i2c: i2c@3160000 { 2795 compatible = "nvidia,tegra194-i2c"; 2796 reg = <0x0 0x3160000 0x0 0x100>; 2797 status = "disabled"; 2798 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 2799 #address-cells = <1>; 2800 #size-cells = <0>; 2801 clock-frequency = <400000>; 2802 clocks = <&bpmp TEGRA234_CLK_I2C1>, 2803 <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2804 assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; 2805 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2806 clock-names = "div-clk", "parent"; 2807 resets = <&bpmp TEGRA234_RESET_I2C1>; 2808 reset-names = "i2c"; 2809 dmas = <&gpcdma 21>, <&gpcdma 21>; 2810 dma-names = "rx", "tx"; 2811 }; 2812 2813 cam_i2c: i2c@3180000 { 2814 compatible = "nvidia,tegra194-i2c"; 2815 reg = <0x0 0x3180000 0x0 0x100>; 2816 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 2817 #address-cells = <1>; 2818 #size-cells = <0>; 2819 status = "disabled"; 2820 clock-frequency = <400000>; 2821 clocks = <&bpmp TEGRA234_CLK_I2C3>, 2822 <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2823 assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>; 2824 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2825 clock-names = "div-clk", "parent"; 2826 resets = <&bpmp TEGRA234_RESET_I2C3>; 2827 reset-names = "i2c"; 2828 dmas = <&gpcdma 23>, <&gpcdma 23>; 2829 dma-names = "rx", "tx"; 2830 }; 2831 2832 dp_aux_ch1_i2c: i2c@3190000 { 2833 compatible = "nvidia,tegra194-i2c"; 2834 reg = <0x0 0x3190000 0x0 0x100>; 2835 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 2836 #address-cells = <1>; 2837 #size-cells = <0>; 2838 status = "disabled"; 2839 clock-frequency = <100000>; 2840 clocks = <&bpmp TEGRA234_CLK_I2C4>, 2841 <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2842 assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>; 2843 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2844 clock-names = "div-clk", "parent"; 2845 resets = <&bpmp TEGRA234_RESET_I2C4>; 2846 reset-names = "i2c"; 2847 dmas = <&gpcdma 26>, <&gpcdma 26>; 2848 dma-names = "rx", "tx"; 2849 }; 2850 2851 dp_aux_ch0_i2c: i2c@31b0000 { 2852 compatible = "nvidia,tegra194-i2c"; 2853 reg = <0x0 0x31b0000 0x0 0x100>; 2854 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 2855 #address-cells = <1>; 2856 #size-cells = <0>; 2857 status = "disabled"; 2858 clock-frequency = <100000>; 2859 clocks = <&bpmp TEGRA234_CLK_I2C6>, 2860 <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2861 assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>; 2862 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2863 clock-names = "div-clk", "parent"; 2864 resets = <&bpmp TEGRA234_RESET_I2C6>; 2865 reset-names = "i2c"; 2866 dmas = <&gpcdma 30>, <&gpcdma 30>; 2867 dma-names = "rx", "tx"; 2868 }; 2869 2870 dp_aux_ch2_i2c: i2c@31c0000 { 2871 compatible = "nvidia,tegra194-i2c"; 2872 reg = <0x0 0x31c0000 0x0 0x100>; 2873 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2874 #address-cells = <1>; 2875 #size-cells = <0>; 2876 status = "disabled"; 2877 clock-frequency = <100000>; 2878 clocks = <&bpmp TEGRA234_CLK_I2C7>, 2879 <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2880 assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>; 2881 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2882 clock-names = "div-clk", "parent"; 2883 resets = <&bpmp TEGRA234_RESET_I2C7>; 2884 reset-names = "i2c"; 2885 dmas = <&gpcdma 27>, <&gpcdma 27>; 2886 dma-names = "rx", "tx"; 2887 }; 2888 2889 uarti: serial@31d0000 { 2890 compatible = "arm,sbsa-uart"; 2891 reg = <0x0 0x31d0000 0x0 0x10000>; 2892 interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 2893 status = "disabled"; 2894 }; 2895 2896 dp_aux_ch3_i2c: i2c@31e0000 { 2897 compatible = "nvidia,tegra194-i2c"; 2898 reg = <0x0 0x31e0000 0x0 0x100>; 2899 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 2900 #address-cells = <1>; 2901 #size-cells = <0>; 2902 status = "disabled"; 2903 clock-frequency = <100000>; 2904 clocks = <&bpmp TEGRA234_CLK_I2C9>, 2905 <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2906 assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>; 2907 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2908 clock-names = "div-clk", "parent"; 2909 resets = <&bpmp TEGRA234_RESET_I2C9>; 2910 reset-names = "i2c"; 2911 dmas = <&gpcdma 31>, <&gpcdma 31>; 2912 dma-names = "rx", "tx"; 2913 }; 2914 2915 spi@3210000 { 2916 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 2917 reg = <0x0 0x03210000 0x0 0x1000>; 2918 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 2919 #address-cells = <1>; 2920 #size-cells = <0>; 2921 clocks = <&bpmp TEGRA234_CLK_SPI1>; 2922 assigned-clocks = <&bpmp TEGRA234_CLK_SPI1>; 2923 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2924 clock-names = "spi"; 2925 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 2926 resets = <&bpmp TEGRA234_RESET_SPI1>; 2927 reset-names = "spi"; 2928 dmas = <&gpcdma 15>, <&gpcdma 15>; 2929 dma-names = "rx", "tx"; 2930 dma-coherent; 2931 status = "disabled"; 2932 }; 2933 2934 spi@3230000 { 2935 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 2936 reg = <0x0 0x03230000 0x0 0x1000>; 2937 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 2938 #address-cells = <1>; 2939 #size-cells = <0>; 2940 clocks = <&bpmp TEGRA234_CLK_SPI3>; 2941 clock-names = "spi"; 2942 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 2943 assigned-clocks = <&bpmp TEGRA234_CLK_SPI3>; 2944 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2945 resets = <&bpmp TEGRA234_RESET_SPI3>; 2946 reset-names = "spi"; 2947 dmas = <&gpcdma 17>, <&gpcdma 17>; 2948 dma-names = "rx", "tx"; 2949 dma-coherent; 2950 status = "disabled"; 2951 }; 2952 2953 spi@3270000 { 2954 compatible = "nvidia,tegra234-qspi"; 2955 reg = <0x0 0x3270000 0x0 0x1000>; 2956 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 2957 #address-cells = <1>; 2958 #size-cells = <0>; 2959 clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>, 2960 <&bpmp TEGRA234_CLK_QSPI0_PM>; 2961 clock-names = "qspi", "qspi_out"; 2962 resets = <&bpmp TEGRA234_RESET_QSPI0>; 2963 iommus = <&smmu_niso1 TEGRA234_SID_QSPI0>; 2964 assigned-clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>, 2965 <&bpmp TEGRA234_CLK_QSPI0_PM>; 2966 assigned-clock-rates = <199999999 99999999>; 2967 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC>; 2968 status = "disabled"; 2969 }; 2970 2971 pwm1: pwm@3280000 { 2972 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 2973 reg = <0x0 0x3280000 0x0 0x10000>; 2974 clocks = <&bpmp TEGRA234_CLK_PWM1>; 2975 resets = <&bpmp TEGRA234_RESET_PWM1>; 2976 reset-names = "pwm"; 2977 status = "disabled"; 2978 #pwm-cells = <2>; 2979 }; 2980 2981 pwm2: pwm@3290000 { 2982 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 2983 reg = <0x0 0x3290000 0x0 0x10000>; 2984 clocks = <&bpmp TEGRA234_CLK_PWM2>; 2985 resets = <&bpmp TEGRA234_RESET_PWM2>; 2986 reset-names = "pwm"; 2987 status = "disabled"; 2988 #pwm-cells = <2>; 2989 }; 2990 2991 pwm3: pwm@32a0000 { 2992 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 2993 reg = <0x0 0x32a0000 0x0 0x10000>; 2994 clocks = <&bpmp TEGRA234_CLK_PWM3>; 2995 resets = <&bpmp TEGRA234_RESET_PWM3>; 2996 reset-names = "pwm"; 2997 status = "disabled"; 2998 #pwm-cells = <2>; 2999 }; 3000 3001 pwm5: pwm@32c0000 { 3002 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 3003 reg = <0x0 0x32c0000 0x0 0x10000>; 3004 clocks = <&bpmp TEGRA234_CLK_PWM5>; 3005 resets = <&bpmp TEGRA234_RESET_PWM5>; 3006 reset-names = "pwm"; 3007 status = "disabled"; 3008 #pwm-cells = <2>; 3009 }; 3010 3011 pwm6: pwm@32d0000 { 3012 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 3013 reg = <0x0 0x32d0000 0x0 0x10000>; 3014 clocks = <&bpmp TEGRA234_CLK_PWM6>; 3015 resets = <&bpmp TEGRA234_RESET_PWM6>; 3016 reset-names = "pwm"; 3017 status = "disabled"; 3018 #pwm-cells = <2>; 3019 }; 3020 3021 pwm7: pwm@32e0000 { 3022 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 3023 reg = <0x0 0x32e0000 0x0 0x10000>; 3024 clocks = <&bpmp TEGRA234_CLK_PWM7>; 3025 resets = <&bpmp TEGRA234_RESET_PWM7>; 3026 reset-names = "pwm"; 3027 status = "disabled"; 3028 #pwm-cells = <2>; 3029 }; 3030 3031 pwm8: pwm@32f0000 { 3032 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 3033 reg = <0x0 0x32f0000 0x0 0x10000>; 3034 clocks = <&bpmp TEGRA234_CLK_PWM8>; 3035 resets = <&bpmp TEGRA234_RESET_PWM8>; 3036 reset-names = "pwm"; 3037 status = "disabled"; 3038 #pwm-cells = <2>; 3039 }; 3040 3041 spi@3300000 { 3042 compatible = "nvidia,tegra234-qspi"; 3043 reg = <0x0 0x3300000 0x0 0x1000>; 3044 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 3045 #address-cells = <1>; 3046 #size-cells = <0>; 3047 clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>, 3048 <&bpmp TEGRA234_CLK_QSPI1_PM>; 3049 clock-names = "qspi", "qspi_out"; 3050 resets = <&bpmp TEGRA234_RESET_QSPI1>; 3051 iommus = <&smmu_niso1 TEGRA234_SID_QSPI1>; 3052 assigned-clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>, 3053 <&bpmp TEGRA234_CLK_QSPI1_PM>; 3054 assigned-clock-rates = <199999999 99999999>; 3055 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC>; 3056 status = "disabled"; 3057 }; 3058 3059 mmc@3400000 { 3060 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 3061 reg = <0x0 0x03400000 0x0 0x20000>; 3062 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 3063 clocks = <&bpmp TEGRA234_CLK_SDMMC1>, 3064 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 3065 clock-names = "sdhci", "tmclk"; 3066 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC1>, 3067 <&bpmp TEGRA234_CLK_PLLC4_MUXED>; 3068 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4_MUXED>, 3069 <&bpmp TEGRA234_CLK_PLLC4_VCO_DIV2>; 3070 resets = <&bpmp TEGRA234_RESET_SDMMC1>; 3071 reset-names = "sdhci"; 3072 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRA &emc>, 3073 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWA &emc>; 3074 interconnect-names = "dma-mem", "write"; 3075 iommus = <&smmu_niso1 TEGRA234_SID_SDMMC1A>; 3076 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 3077 pinctrl-0 = <&sdmmc1_3v3>; 3078 pinctrl-1 = <&sdmmc1_1v8>; 3079 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 3080 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>; 3081 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 3082 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 3083 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 3084 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 3085 nvidia,default-tap = <14>; 3086 nvidia,default-trim = <0x8>; 3087 sd-uhs-sdr25; 3088 sd-uhs-sdr50; 3089 sd-uhs-ddr50; 3090 sd-uhs-sdr104; 3091 status = "disabled"; 3092 }; 3093 3094 mmc@3460000 { 3095 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 3096 reg = <0x0 0x03460000 0x0 0x20000>; 3097 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 3098 clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 3099 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 3100 clock-names = "sdhci", "tmclk"; 3101 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 3102 <&bpmp TEGRA234_CLK_PLLC4>; 3103 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; 3104 resets = <&bpmp TEGRA234_RESET_SDMMC4>; 3105 reset-names = "sdhci"; 3106 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>, 3107 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>; 3108 interconnect-names = "dma-mem", "write"; 3109 iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>; 3110 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 3111 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 3112 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 3113 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 3114 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 3115 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 3116 nvidia,default-tap = <0x8>; 3117 nvidia,default-trim = <0x14>; 3118 nvidia,dqs-trim = <40>; 3119 supports-cqe; 3120 status = "disabled"; 3121 }; 3122 3123 hda@3510000 { 3124 compatible = "nvidia,tegra234-hda"; 3125 reg = <0x0 0x3510000 0x0 0x10000>; 3126 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 3127 clocks = <&bpmp TEGRA234_CLK_AZA_BIT>, 3128 <&bpmp TEGRA234_CLK_AZA_2XBIT>; 3129 clock-names = "hda", "hda2codec_2x"; 3130 resets = <&bpmp TEGRA234_RESET_HDA>, 3131 <&bpmp TEGRA234_RESET_HDACODEC>; 3132 reset-names = "hda", "hda2codec_2x"; 3133 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>; 3134 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HDAR &emc>, 3135 <&mc TEGRA234_MEMORY_CLIENT_HDAW &emc>; 3136 interconnect-names = "dma-mem", "write"; 3137 iommus = <&smmu_niso0 TEGRA234_SID_HDA>; 3138 status = "disabled"; 3139 }; 3140 3141 xusb_padctl: padctl@3520000 { 3142 compatible = "nvidia,tegra234-xusb-padctl"; 3143 reg = <0x0 0x03520000 0x0 0x20000>, 3144 <0x0 0x03540000 0x0 0x10000>; 3145 reg-names = "padctl", "ao"; 3146 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 3147 3148 resets = <&bpmp TEGRA234_RESET_XUSB_PADCTL>; 3149 reset-names = "padctl"; 3150 3151 status = "disabled"; 3152 3153 pads { 3154 usb2 { 3155 clocks = <&bpmp TEGRA234_CLK_USB2_TRK>; 3156 clock-names = "trk"; 3157 3158 lanes { 3159 usb2-0 { 3160 nvidia,function = "xusb"; 3161 status = "disabled"; 3162 #phy-cells = <0>; 3163 }; 3164 3165 usb2-1 { 3166 nvidia,function = "xusb"; 3167 status = "disabled"; 3168 #phy-cells = <0>; 3169 }; 3170 3171 usb2-2 { 3172 nvidia,function = "xusb"; 3173 status = "disabled"; 3174 #phy-cells = <0>; 3175 }; 3176 3177 usb2-3 { 3178 nvidia,function = "xusb"; 3179 status = "disabled"; 3180 #phy-cells = <0>; 3181 }; 3182 }; 3183 }; 3184 3185 usb3 { 3186 lanes { 3187 usb3-0 { 3188 nvidia,function = "xusb"; 3189 status = "disabled"; 3190 #phy-cells = <0>; 3191 }; 3192 3193 usb3-1 { 3194 nvidia,function = "xusb"; 3195 status = "disabled"; 3196 #phy-cells = <0>; 3197 }; 3198 3199 usb3-2 { 3200 nvidia,function = "xusb"; 3201 status = "disabled"; 3202 #phy-cells = <0>; 3203 }; 3204 3205 usb3-3 { 3206 nvidia,function = "xusb"; 3207 status = "disabled"; 3208 #phy-cells = <0>; 3209 }; 3210 }; 3211 }; 3212 }; 3213 3214 ports { 3215 usb2-0 { 3216 status = "disabled"; 3217 }; 3218 3219 usb2-1 { 3220 status = "disabled"; 3221 }; 3222 3223 usb2-2 { 3224 status = "disabled"; 3225 }; 3226 3227 usb2-3 { 3228 status = "disabled"; 3229 }; 3230 3231 usb3-0 { 3232 status = "disabled"; 3233 }; 3234 3235 usb3-1 { 3236 status = "disabled"; 3237 }; 3238 3239 usb3-2 { 3240 status = "disabled"; 3241 }; 3242 3243 usb3-3 { 3244 status = "disabled"; 3245 }; 3246 }; 3247 }; 3248 3249 usb@3550000 { 3250 compatible = "nvidia,tegra234-xudc"; 3251 reg = <0x0 0x03550000 0x0 0x8000>, 3252 <0x0 0x03558000 0x0 0x8000>; 3253 reg-names = "base", "fpci"; 3254 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 3255 clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_DEV>, 3256 <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, 3257 <&bpmp TEGRA234_CLK_XUSB_SS>, 3258 <&bpmp TEGRA234_CLK_XUSB_FS>; 3259 clock-names = "dev", "ss", "ss_src", "fs_src"; 3260 interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVR &emc>, 3261 <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVW &emc>; 3262 interconnect-names = "dma-mem", "write"; 3263 iommus = <&smmu_niso1 TEGRA234_SID_XUSB_DEV>; 3264 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBB>, 3265 <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; 3266 power-domain-names = "dev", "ss"; 3267 nvidia,xusb-padctl = <&xusb_padctl>; 3268 dma-coherent; 3269 status = "disabled"; 3270 }; 3271 3272 usb@3610000 { 3273 compatible = "nvidia,tegra234-xusb"; 3274 reg = <0x0 0x03610000 0x0 0x40000>, 3275 <0x0 0x03600000 0x0 0x10000>, 3276 <0x0 0x03650000 0x0 0x10000>; 3277 reg-names = "hcd", "fpci", "bar2"; 3278 3279 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 3280 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 3281 3282 clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>, 3283 <&bpmp TEGRA234_CLK_XUSB_FALCON>, 3284 <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, 3285 <&bpmp TEGRA234_CLK_XUSB_SS>, 3286 <&bpmp TEGRA234_CLK_CLK_M>, 3287 <&bpmp TEGRA234_CLK_XUSB_FS>, 3288 <&bpmp TEGRA234_CLK_UTMIP_PLL>, 3289 <&bpmp TEGRA234_CLK_CLK_M>, 3290 <&bpmp TEGRA234_CLK_PLLE>; 3291 clock-names = "xusb_host", "xusb_falcon_src", 3292 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 3293 "xusb_fs_src", "pll_u_480m", "clk_m", 3294 "pll_e"; 3295 interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTR &emc>, 3296 <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTW &emc>; 3297 interconnect-names = "dma-mem", "write"; 3298 iommus = <&smmu_niso1 TEGRA234_SID_XUSB_HOST>; 3299 3300 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>, 3301 <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; 3302 power-domain-names = "xusb_host", "xusb_ss"; 3303 3304 nvidia,xusb-padctl = <&xusb_padctl>; 3305 dma-coherent; 3306 status = "disabled"; 3307 }; 3308 3309 fuse@3810000 { 3310 compatible = "nvidia,tegra234-efuse"; 3311 reg = <0x0 0x03810000 0x0 0x10000>; 3312 clocks = <&bpmp TEGRA234_CLK_FUSE>; 3313 clock-names = "fuse"; 3314 }; 3315 3316 hte_lic: hardware-timestamp@3aa0000 { 3317 compatible = "nvidia,tegra234-gte-lic"; 3318 reg = <0x0 0x3aa0000 0x0 0x10000>; 3319 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3320 nvidia,int-threshold = <1>; 3321 #timestamp-cells = <1>; 3322 }; 3323 3324 hsp_top0: hsp@3c00000 { 3325 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 3326 reg = <0x0 0x03c00000 0x0 0xa0000>; 3327 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 3328 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 3329 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 3330 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 3331 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 3332 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 3333 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 3334 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 3335 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 3336 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 3337 "shared3", "shared4", "shared5", "shared6", 3338 "shared7"; 3339 #mbox-cells = <2>; 3340 }; 3341 3342 p2u_hsio_0: phy@3e00000 { 3343 compatible = "nvidia,tegra234-p2u"; 3344 reg = <0x0 0x03e00000 0x0 0x10000>; 3345 reg-names = "ctl"; 3346 3347 #phy-cells = <0>; 3348 }; 3349 3350 p2u_hsio_1: phy@3e10000 { 3351 compatible = "nvidia,tegra234-p2u"; 3352 reg = <0x0 0x03e10000 0x0 0x10000>; 3353 reg-names = "ctl"; 3354 3355 #phy-cells = <0>; 3356 }; 3357 3358 p2u_hsio_2: phy@3e20000 { 3359 compatible = "nvidia,tegra234-p2u"; 3360 reg = <0x0 0x03e20000 0x0 0x10000>; 3361 reg-names = "ctl"; 3362 3363 #phy-cells = <0>; 3364 }; 3365 3366 p2u_hsio_3: phy@3e30000 { 3367 compatible = "nvidia,tegra234-p2u"; 3368 reg = <0x0 0x03e30000 0x0 0x10000>; 3369 reg-names = "ctl"; 3370 3371 #phy-cells = <0>; 3372 }; 3373 3374 p2u_hsio_4: phy@3e40000 { 3375 compatible = "nvidia,tegra234-p2u"; 3376 reg = <0x0 0x03e40000 0x0 0x10000>; 3377 reg-names = "ctl"; 3378 3379 #phy-cells = <0>; 3380 }; 3381 3382 p2u_hsio_5: phy@3e50000 { 3383 compatible = "nvidia,tegra234-p2u"; 3384 reg = <0x0 0x03e50000 0x0 0x10000>; 3385 reg-names = "ctl"; 3386 3387 #phy-cells = <0>; 3388 }; 3389 3390 p2u_hsio_6: phy@3e60000 { 3391 compatible = "nvidia,tegra234-p2u"; 3392 reg = <0x0 0x03e60000 0x0 0x10000>; 3393 reg-names = "ctl"; 3394 3395 #phy-cells = <0>; 3396 }; 3397 3398 p2u_hsio_7: phy@3e70000 { 3399 compatible = "nvidia,tegra234-p2u"; 3400 reg = <0x0 0x03e70000 0x0 0x10000>; 3401 reg-names = "ctl"; 3402 3403 #phy-cells = <0>; 3404 }; 3405 3406 p2u_nvhs_0: phy@3e90000 { 3407 compatible = "nvidia,tegra234-p2u"; 3408 reg = <0x0 0x03e90000 0x0 0x10000>; 3409 reg-names = "ctl"; 3410 3411 #phy-cells = <0>; 3412 }; 3413 3414 p2u_nvhs_1: phy@3ea0000 { 3415 compatible = "nvidia,tegra234-p2u"; 3416 reg = <0x0 0x03ea0000 0x0 0x10000>; 3417 reg-names = "ctl"; 3418 3419 #phy-cells = <0>; 3420 }; 3421 3422 p2u_nvhs_2: phy@3eb0000 { 3423 compatible = "nvidia,tegra234-p2u"; 3424 reg = <0x0 0x03eb0000 0x0 0x10000>; 3425 reg-names = "ctl"; 3426 3427 #phy-cells = <0>; 3428 }; 3429 3430 p2u_nvhs_3: phy@3ec0000 { 3431 compatible = "nvidia,tegra234-p2u"; 3432 reg = <0x0 0x03ec0000 0x0 0x10000>; 3433 reg-names = "ctl"; 3434 3435 #phy-cells = <0>; 3436 }; 3437 3438 p2u_nvhs_4: phy@3ed0000 { 3439 compatible = "nvidia,tegra234-p2u"; 3440 reg = <0x0 0x03ed0000 0x0 0x10000>; 3441 reg-names = "ctl"; 3442 3443 #phy-cells = <0>; 3444 }; 3445 3446 p2u_nvhs_5: phy@3ee0000 { 3447 compatible = "nvidia,tegra234-p2u"; 3448 reg = <0x0 0x03ee0000 0x0 0x10000>; 3449 reg-names = "ctl"; 3450 3451 #phy-cells = <0>; 3452 }; 3453 3454 p2u_nvhs_6: phy@3ef0000 { 3455 compatible = "nvidia,tegra234-p2u"; 3456 reg = <0x0 0x03ef0000 0x0 0x10000>; 3457 reg-names = "ctl"; 3458 3459 #phy-cells = <0>; 3460 }; 3461 3462 p2u_nvhs_7: phy@3f00000 { 3463 compatible = "nvidia,tegra234-p2u"; 3464 reg = <0x0 0x03f00000 0x0 0x10000>; 3465 reg-names = "ctl"; 3466 3467 #phy-cells = <0>; 3468 }; 3469 3470 p2u_gbe_0: phy@3f20000 { 3471 compatible = "nvidia,tegra234-p2u"; 3472 reg = <0x0 0x03f20000 0x0 0x10000>; 3473 reg-names = "ctl"; 3474 3475 #phy-cells = <0>; 3476 }; 3477 3478 p2u_gbe_1: phy@3f30000 { 3479 compatible = "nvidia,tegra234-p2u"; 3480 reg = <0x0 0x03f30000 0x0 0x10000>; 3481 reg-names = "ctl"; 3482 3483 #phy-cells = <0>; 3484 }; 3485 3486 p2u_gbe_2: phy@3f40000 { 3487 compatible = "nvidia,tegra234-p2u"; 3488 reg = <0x0 0x03f40000 0x0 0x10000>; 3489 reg-names = "ctl"; 3490 3491 #phy-cells = <0>; 3492 }; 3493 3494 p2u_gbe_3: phy@3f50000 { 3495 compatible = "nvidia,tegra234-p2u"; 3496 reg = <0x0 0x03f50000 0x0 0x10000>; 3497 reg-names = "ctl"; 3498 3499 #phy-cells = <0>; 3500 }; 3501 3502 p2u_gbe_4: phy@3f60000 { 3503 compatible = "nvidia,tegra234-p2u"; 3504 reg = <0x0 0x03f60000 0x0 0x10000>; 3505 reg-names = "ctl"; 3506 3507 #phy-cells = <0>; 3508 }; 3509 3510 p2u_gbe_5: phy@3f70000 { 3511 compatible = "nvidia,tegra234-p2u"; 3512 reg = <0x0 0x03f70000 0x0 0x10000>; 3513 reg-names = "ctl"; 3514 3515 #phy-cells = <0>; 3516 }; 3517 3518 p2u_gbe_6: phy@3f80000 { 3519 compatible = "nvidia,tegra234-p2u"; 3520 reg = <0x0 0x03f80000 0x0 0x10000>; 3521 reg-names = "ctl"; 3522 3523 #phy-cells = <0>; 3524 }; 3525 3526 p2u_gbe_7: phy@3f90000 { 3527 compatible = "nvidia,tegra234-p2u"; 3528 reg = <0x0 0x03f90000 0x0 0x10000>; 3529 reg-names = "ctl"; 3530 3531 #phy-cells = <0>; 3532 }; 3533 3534 ethernet@6800000 { 3535 compatible = "nvidia,tegra234-mgbe"; 3536 reg = <0x0 0x06800000 0x0 0x10000>, 3537 <0x0 0x06810000 0x0 0x10000>, 3538 <0x0 0x068a0000 0x0 0x10000>; 3539 reg-names = "hypervisor", "mac", "xpcs"; 3540 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 3541 interrupt-names = "common"; 3542 clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>, 3543 <&bpmp TEGRA234_CLK_MGBE0_MAC>, 3544 <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>, 3545 <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>, 3546 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>, 3547 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>, 3548 <&bpmp TEGRA234_CLK_MGBE0_TX>, 3549 <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>, 3550 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>, 3551 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>, 3552 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>, 3553 <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>; 3554 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 3555 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 3556 "rx-pcs", "tx-pcs"; 3557 resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>, 3558 <&bpmp TEGRA234_RESET_MGBE0_PCS>; 3559 reset-names = "mac", "pcs"; 3560 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>, 3561 <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>; 3562 interconnect-names = "dma-mem", "write"; 3563 iommus = <&smmu_niso0 TEGRA234_SID_MGBE>; 3564 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>; 3565 status = "disabled"; 3566 3567 snps,axi-config = <&mgbe0_axi_setup>; 3568 3569 mgbe0_axi_setup: stmmac-axi-config { 3570 snps,blen = <256 128 64 32>; 3571 snps,rd_osr_lmt = <63>; 3572 snps,wr_osr_lmt = <63>; 3573 }; 3574 }; 3575 3576 ethernet@6900000 { 3577 compatible = "nvidia,tegra234-mgbe"; 3578 reg = <0x0 0x06900000 0x0 0x10000>, 3579 <0x0 0x06910000 0x0 0x10000>, 3580 <0x0 0x069a0000 0x0 0x10000>; 3581 reg-names = "hypervisor", "mac", "xpcs"; 3582 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; 3583 interrupt-names = "common"; 3584 clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>, 3585 <&bpmp TEGRA234_CLK_MGBE1_MAC>, 3586 <&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>, 3587 <&bpmp TEGRA234_CLK_MGBE1_PTP_REF>, 3588 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>, 3589 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>, 3590 <&bpmp TEGRA234_CLK_MGBE1_TX>, 3591 <&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>, 3592 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>, 3593 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>, 3594 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>, 3595 <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>; 3596 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 3597 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 3598 "rx-pcs", "tx-pcs"; 3599 resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>, 3600 <&bpmp TEGRA234_RESET_MGBE1_PCS>; 3601 reset-names = "mac", "pcs"; 3602 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEBRD &emc>, 3603 <&mc TEGRA234_MEMORY_CLIENT_MGBEBWR &emc>; 3604 interconnect-names = "dma-mem", "write"; 3605 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>; 3606 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>; 3607 status = "disabled"; 3608 3609 snps,axi-config = <&mgbe1_axi_setup>; 3610 3611 mgbe1_axi_setup: stmmac-axi-config { 3612 snps,blen = <256 128 64 32>; 3613 snps,rd_osr_lmt = <63>; 3614 snps,wr_osr_lmt = <63>; 3615 }; 3616 }; 3617 3618 ethernet@6a00000 { 3619 compatible = "nvidia,tegra234-mgbe"; 3620 reg = <0x0 0x06a00000 0x0 0x10000>, 3621 <0x0 0x06a10000 0x0 0x10000>, 3622 <0x0 0x06aa0000 0x0 0x10000>; 3623 reg-names = "hypervisor", "mac", "xpcs"; 3624 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>; 3625 interrupt-names = "common"; 3626 clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>, 3627 <&bpmp TEGRA234_CLK_MGBE2_MAC>, 3628 <&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>, 3629 <&bpmp TEGRA234_CLK_MGBE2_PTP_REF>, 3630 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>, 3631 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>, 3632 <&bpmp TEGRA234_CLK_MGBE2_TX>, 3633 <&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>, 3634 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>, 3635 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>, 3636 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>, 3637 <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>; 3638 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 3639 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 3640 "rx-pcs", "tx-pcs"; 3641 resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>, 3642 <&bpmp TEGRA234_RESET_MGBE2_PCS>; 3643 reset-names = "mac", "pcs"; 3644 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBECRD &emc>, 3645 <&mc TEGRA234_MEMORY_CLIENT_MGBECWR &emc>; 3646 interconnect-names = "dma-mem", "write"; 3647 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>; 3648 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>; 3649 status = "disabled"; 3650 3651 snps,axi-config = <&mgbe2_axi_setup>; 3652 3653 mgbe2_axi_setup: stmmac-axi-config { 3654 snps,blen = <256 128 64 32>; 3655 snps,rd_osr_lmt = <63>; 3656 snps,wr_osr_lmt = <63>; 3657 }; 3658 }; 3659 3660 ethernet@6b00000 { 3661 compatible = "nvidia,tegra234-mgbe"; 3662 reg = <0x0 0x06b00000 0x0 0x10000>, 3663 <0x0 0x06b10000 0x0 0x10000>, 3664 <0x0 0x06ba0000 0x0 0x10000>; 3665 reg-names = "hypervisor", "mac", "xpcs"; 3666 interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 3667 interrupt-names = "common"; 3668 clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>, 3669 <&bpmp TEGRA234_CLK_MGBE3_MAC>, 3670 <&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>, 3671 <&bpmp TEGRA234_CLK_MGBE3_PTP_REF>, 3672 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>, 3673 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>, 3674 <&bpmp TEGRA234_CLK_MGBE3_TX>, 3675 <&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>, 3676 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>, 3677 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>, 3678 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>, 3679 <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>; 3680 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 3681 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 3682 "rx-pcs", "tx-pcs"; 3683 resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>, 3684 <&bpmp TEGRA234_RESET_MGBE3_PCS>; 3685 reset-names = "mac", "pcs"; 3686 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEDRD &emc>, 3687 <&mc TEGRA234_MEMORY_CLIENT_MGBEDWR &emc>; 3688 interconnect-names = "dma-mem", "write"; 3689 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF3>; 3690 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>; 3691 status = "disabled"; 3692 }; 3693 3694 smmu_niso1: iommu@8000000 { 3695 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 3696 reg = <0x0 0x8000000 0x0 0x1000000>, 3697 <0x0 0x7000000 0x0 0x1000000>; 3698 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3699 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 3700 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3701 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 3702 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3703 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3704 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3705 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3706 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3707 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3708 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3709 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3710 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3711 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3712 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3713 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3714 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3715 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3716 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3717 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3718 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3719 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3720 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3721 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3722 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3723 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3724 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3725 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3726 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3727 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3728 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3729 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3730 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3731 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3732 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3733 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3734 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3735 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3736 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3737 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3738 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3739 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3740 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3741 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3742 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3743 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3744 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3745 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3746 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3747 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3748 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3749 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3750 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3751 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3752 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3753 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3754 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3755 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3756 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3757 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3758 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3759 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3760 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3761 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3762 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3763 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3764 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3765 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3766 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3767 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3768 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3769 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3770 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3771 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3772 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3773 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3774 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3775 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3776 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3777 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3778 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3779 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3780 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3781 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3782 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3783 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3784 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3785 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3786 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3787 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3788 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3789 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3790 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3791 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3792 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3793 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3794 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3795 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3796 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3797 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3798 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3799 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3800 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3801 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3802 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3803 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3804 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3805 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3806 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3807 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3808 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3809 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3810 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3811 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3812 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3813 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3814 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3815 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3816 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3817 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3818 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3819 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3820 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3821 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3822 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3823 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3824 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3825 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3826 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3827 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 3828 stream-match-mask = <0x7f80>; 3829 #global-interrupts = <2>; 3830 #iommu-cells = <1>; 3831 3832 nvidia,memory-controller = <&mc>; 3833 status = "okay"; 3834 }; 3835 3836 sce-fabric@b600000 { 3837 compatible = "nvidia,tegra234-sce-fabric"; 3838 reg = <0x0 0xb600000 0x0 0x40000>; 3839 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 3840 status = "disabled"; 3841 }; 3842 3843 rce-fabric@be00000 { 3844 compatible = "nvidia,tegra234-rce-fabric"; 3845 reg = <0x0 0xbe00000 0x0 0x40000>; 3846 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 3847 status = "okay"; 3848 }; 3849 3850 hsp_aon: hsp@c150000 { 3851 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 3852 reg = <0x0 0x0c150000 0x0 0x90000>; 3853 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 3854 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 3855 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 3856 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 3857 /* 3858 * Shared interrupt 0 is routed only to AON/SPE, so 3859 * we only have 4 shared interrupts for the CCPLEX. 3860 */ 3861 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 3862 #mbox-cells = <2>; 3863 }; 3864 3865 hte_aon: hardware-timestamp@c1e0000 { 3866 compatible = "nvidia,tegra234-gte-aon"; 3867 reg = <0x0 0xc1e0000 0x0 0x10000>; 3868 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3869 nvidia,int-threshold = <1>; 3870 nvidia,gpio-controller = <&gpio_aon>; 3871 #timestamp-cells = <1>; 3872 }; 3873 3874 gen2_i2c: i2c@c240000 { 3875 compatible = "nvidia,tegra194-i2c"; 3876 reg = <0x0 0xc240000 0x0 0x100>; 3877 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 3878 #address-cells = <1>; 3879 #size-cells = <0>; 3880 status = "disabled"; 3881 clock-frequency = <100000>; 3882 clocks = <&bpmp TEGRA234_CLK_I2C2>, 3883 <&bpmp TEGRA234_CLK_PLLP_OUT0>; 3884 clock-names = "div-clk", "parent"; 3885 assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>; 3886 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 3887 resets = <&bpmp TEGRA234_RESET_I2C2>; 3888 reset-names = "i2c"; 3889 dmas = <&gpcdma 22>, <&gpcdma 22>; 3890 dma-names = "rx", "tx"; 3891 }; 3892 3893 gen8_i2c: i2c@c250000 { 3894 compatible = "nvidia,tegra194-i2c"; 3895 reg = <0x0 0xc250000 0x0 0x100>; 3896 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3897 #address-cells = <1>; 3898 #size-cells = <0>; 3899 status = "disabled"; 3900 clock-frequency = <400000>; 3901 clocks = <&bpmp TEGRA234_CLK_I2C8>, 3902 <&bpmp TEGRA234_CLK_PLLP_OUT0>; 3903 clock-names = "div-clk", "parent"; 3904 assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>; 3905 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 3906 resets = <&bpmp TEGRA234_RESET_I2C8>; 3907 reset-names = "i2c"; 3908 dmas = <&gpcdma 0>, <&gpcdma 0>; 3909 dma-names = "rx", "tx"; 3910 }; 3911 3912 spi@c260000 { 3913 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 3914 reg = <0x0 0x0c260000 0x0 0x1000>; 3915 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 3916 #address-cells = <1>; 3917 #size-cells = <0>; 3918 clocks = <&bpmp TEGRA234_CLK_SPI2>; 3919 clock-names = "spi"; 3920 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 3921 assigned-clocks = <&bpmp TEGRA234_CLK_SPI2>; 3922 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 3923 resets = <&bpmp TEGRA234_RESET_SPI2>; 3924 reset-names = "spi"; 3925 dmas = <&gpcdma 16>, <&gpcdma 16>; 3926 dma-names = "rx", "tx"; 3927 dma-coherent; 3928 status = "disabled"; 3929 }; 3930 3931 rtc@c2a0000 { 3932 compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; 3933 reg = <0x0 0x0c2a0000 0x0 0x10000>; 3934 interrupt-parent = <&pmc>; 3935 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 3936 clocks = <&bpmp TEGRA234_CLK_CLK_32K>; 3937 clock-names = "rtc"; 3938 status = "disabled"; 3939 }; 3940 3941 gpio_aon: gpio@c2f0000 { 3942 compatible = "nvidia,tegra234-gpio-aon"; 3943 reg-names = "security", "gpio"; 3944 reg = <0x0 0x0c2f0000 0x0 0x1000>, 3945 <0x0 0x0c2f1000 0x0 0x1000>; 3946 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 3947 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 3948 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 3949 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 3950 #interrupt-cells = <2>; 3951 interrupt-controller; 3952 #gpio-cells = <2>; 3953 gpio-controller; 3954 gpio-ranges = <&pinmux_aon 0 0 32>; 3955 }; 3956 3957 pinmux_aon: pinmux@c300000 { 3958 compatible = "nvidia,tegra234-pinmux-aon"; 3959 reg = <0x0 0xc300000 0x0 0x4000>; 3960 }; 3961 3962 pwm4: pwm@c340000 { 3963 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 3964 reg = <0x0 0xc340000 0x0 0x10000>; 3965 clocks = <&bpmp TEGRA234_CLK_PWM4>; 3966 resets = <&bpmp TEGRA234_RESET_PWM4>; 3967 reset-names = "pwm"; 3968 status = "disabled"; 3969 #pwm-cells = <2>; 3970 }; 3971 3972 pmc: pmc@c360000 { 3973 compatible = "nvidia,tegra234-pmc"; 3974 reg = <0x0 0x0c360000 0x0 0x10000>, 3975 <0x0 0x0c370000 0x0 0x10000>, 3976 <0x0 0x0c380000 0x0 0x10000>, 3977 <0x0 0x0c390000 0x0 0x10000>, 3978 <0x0 0x0c3a0000 0x0 0x10000>; 3979 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 3980 3981 #interrupt-cells = <2>; 3982 interrupt-controller; 3983 3984 sdmmc1_1v8: sdmmc1-1v8 { 3985 pins = "sdmmc1-hv"; 3986 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 3987 }; 3988 3989 sdmmc1_3v3: sdmmc1-3v3 { 3990 pins = "sdmmc1-hv"; 3991 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 3992 }; 3993 3994 sdmmc3_1v8: sdmmc3-1v8 { 3995 pins = "sdmmc3-hv"; 3996 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 3997 }; 3998 3999 sdmmc3_3v3: sdmmc3-3v3 { 4000 pins = "sdmmc3-hv"; 4001 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 4002 }; 4003 }; 4004 4005 aon-fabric@c600000 { 4006 compatible = "nvidia,tegra234-aon-fabric"; 4007 reg = <0x0 0xc600000 0x0 0x40000>; 4008 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 4009 status = "okay"; 4010 }; 4011 4012 bpmp-fabric@d600000 { 4013 compatible = "nvidia,tegra234-bpmp-fabric"; 4014 reg = <0x0 0xd600000 0x0 0x40000>; 4015 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 4016 status = "okay"; 4017 }; 4018 4019 dce-fabric@de00000 { 4020 compatible = "nvidia,tegra234-dce-fabric"; 4021 reg = <0x0 0xde00000 0x0 0x40000>; 4022 interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; 4023 status = "okay"; 4024 }; 4025 4026 ccplex@e000000 { 4027 compatible = "nvidia,tegra234-ccplex-cluster"; 4028 reg = <0x0 0x0e000000 0x0 0x5ffff>; 4029 nvidia,bpmp = <&bpmp>; 4030 status = "okay"; 4031 }; 4032 4033 gic: interrupt-controller@f400000 { 4034 compatible = "arm,gic-v3"; 4035 reg = <0x0 0x0f400000 0x0 0x010000>, /* GICD */ 4036 <0x0 0x0f440000 0x0 0x200000>; /* GICR */ 4037 interrupt-parent = <&gic>; 4038 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 4039 4040 #redistributor-regions = <1>; 4041 #interrupt-cells = <3>; 4042 interrupt-controller; 4043 4044 #address-cells = <0>; 4045 }; 4046 4047 smmu_iso: iommu@10000000 { 4048 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 4049 reg = <0x0 0x10000000 0x0 0x1000000>; 4050 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4051 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4052 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4053 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4054 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4055 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4056 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4057 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4058 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4059 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4060 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4061 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4062 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4063 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4064 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4065 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4066 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4067 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4068 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4069 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4070 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4071 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4072 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4073 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4074 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4075 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4076 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4077 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4078 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4079 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4080 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4081 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4082 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4083 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4084 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4085 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4086 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4087 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4088 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4089 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4090 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4091 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4092 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4093 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4094 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4095 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4096 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4097 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4098 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4099 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4100 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4101 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4102 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4103 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4104 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4105 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4106 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4107 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4108 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4109 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4110 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4111 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4112 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4113 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4114 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4115 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4116 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4117 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4118 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4119 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4120 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4121 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4122 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4123 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4124 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4125 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4126 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4127 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4128 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4129 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4130 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4131 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4132 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4133 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4134 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4135 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4136 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4137 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4138 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4139 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4140 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4141 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4142 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4143 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4144 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4145 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4146 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4147 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4148 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4149 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4150 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4151 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4152 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4153 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4154 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4155 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4156 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4157 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4158 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4159 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4160 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4161 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4162 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4163 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4164 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4165 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4166 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4167 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4168 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4169 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4170 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4171 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4172 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4173 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4174 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4175 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4176 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4177 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4178 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 4179 stream-match-mask = <0x7f80>; 4180 #global-interrupts = <1>; 4181 #iommu-cells = <1>; 4182 4183 nvidia,memory-controller = <&mc>; 4184 status = "okay"; 4185 }; 4186 4187 smmu_niso0: iommu@12000000 { 4188 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 4189 reg = <0x0 0x12000000 0x0 0x1000000>, 4190 <0x0 0x11000000 0x0 0x1000000>; 4191 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4192 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 4193 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4194 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 4195 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4196 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4197 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4198 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4199 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4200 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4201 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4202 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4203 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4204 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4205 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4206 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4207 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4208 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4209 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4210 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4211 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4212 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4213 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4214 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4215 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4216 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4217 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4218 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4219 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4220 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4221 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4222 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4223 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4224 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4225 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4226 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4227 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4228 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4229 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4230 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4231 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4232 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4233 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4234 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4235 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4236 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4237 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4238 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4239 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4240 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4241 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4242 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4243 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4244 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4245 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4246 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4247 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4248 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4249 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4250 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4251 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4252 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4253 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4254 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4255 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4256 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4257 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4258 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4259 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4260 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4261 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4262 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4263 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4264 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4265 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4266 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4267 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4268 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4269 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4270 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4271 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4272 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4273 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4274 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4275 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4276 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4277 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4278 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4279 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4280 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4281 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4282 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4283 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4284 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4285 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4286 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4287 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4288 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4289 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4290 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4291 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4292 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4293 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4294 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4295 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4296 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4297 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4298 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4299 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4300 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4301 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4302 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4303 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4304 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4305 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4306 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4307 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4308 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4309 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4310 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4311 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4312 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4313 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4314 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4315 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4316 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4317 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4318 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4319 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4320 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 4321 stream-match-mask = <0x7f80>; 4322 #global-interrupts = <2>; 4323 #iommu-cells = <1>; 4324 4325 nvidia,memory-controller = <&mc>; 4326 status = "okay"; 4327 }; 4328 4329 cbb-fabric@13a00000 { 4330 compatible = "nvidia,tegra234-cbb-fabric"; 4331 reg = <0x0 0x13a00000 0x0 0x400000>; 4332 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 4333 status = "okay"; 4334 }; 4335 4336 host1x@13e00000 { 4337 compatible = "nvidia,tegra234-host1x"; 4338 reg = <0x0 0x13e00000 0x0 0x10000>, 4339 <0x0 0x13e10000 0x0 0x10000>, 4340 <0x0 0x13e40000 0x0 0x10000>; 4341 reg-names = "common", "hypervisor", "vm"; 4342 interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 4343 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 4344 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 4345 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 4346 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 4347 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 4348 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 4349 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 4350 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 4351 interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4", 4352 "syncpt5", "syncpt6", "syncpt7", "host1x"; 4353 clocks = <&bpmp TEGRA234_CLK_HOST1X>; 4354 clock-names = "host1x"; 4355 4356 #address-cells = <2>; 4357 #size-cells = <2>; 4358 ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02000000>; 4359 4360 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>; 4361 interconnect-names = "dma-mem"; 4362 iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>; 4363 dma-coherent; 4364 4365 /* Context isolation domains */ 4366 iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>, 4367 <1 &smmu_niso0 TEGRA234_SID_HOST1X_CTX1 1>, 4368 <2 &smmu_niso0 TEGRA234_SID_HOST1X_CTX2 1>, 4369 <3 &smmu_niso0 TEGRA234_SID_HOST1X_CTX3 1>, 4370 <4 &smmu_niso0 TEGRA234_SID_HOST1X_CTX4 1>, 4371 <5 &smmu_niso0 TEGRA234_SID_HOST1X_CTX5 1>, 4372 <6 &smmu_niso0 TEGRA234_SID_HOST1X_CTX6 1>, 4373 <7 &smmu_niso0 TEGRA234_SID_HOST1X_CTX7 1>, 4374 <8 &smmu_niso1 TEGRA234_SID_HOST1X_CTX0 1>, 4375 <9 &smmu_niso1 TEGRA234_SID_HOST1X_CTX1 1>, 4376 <10 &smmu_niso1 TEGRA234_SID_HOST1X_CTX2 1>, 4377 <11 &smmu_niso1 TEGRA234_SID_HOST1X_CTX3 1>, 4378 <12 &smmu_niso1 TEGRA234_SID_HOST1X_CTX4 1>, 4379 <13 &smmu_niso1 TEGRA234_SID_HOST1X_CTX5 1>, 4380 <14 &smmu_niso1 TEGRA234_SID_HOST1X_CTX6 1>, 4381 <15 &smmu_niso1 TEGRA234_SID_HOST1X_CTX7 1>; 4382 4383 vic@15340000 { 4384 compatible = "nvidia,tegra234-vic"; 4385 reg = <0x0 0x15340000 0x0 0x00040000>; 4386 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 4387 clocks = <&bpmp TEGRA234_CLK_VIC>; 4388 clock-names = "vic"; 4389 resets = <&bpmp TEGRA234_RESET_VIC>; 4390 reset-names = "vic"; 4391 4392 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>; 4393 interconnects = <&mc TEGRA234_MEMORY_CLIENT_VICSRD &emc>, 4394 <&mc TEGRA234_MEMORY_CLIENT_VICSWR &emc>; 4395 interconnect-names = "dma-mem", "write"; 4396 iommus = <&smmu_niso1 TEGRA234_SID_VIC>; 4397 dma-coherent; 4398 }; 4399 4400 nvdec@15480000 { 4401 compatible = "nvidia,tegra234-nvdec"; 4402 reg = <0x0 0x15480000 0x0 0x00040000>; 4403 clocks = <&bpmp TEGRA234_CLK_NVDEC>, 4404 <&bpmp TEGRA234_CLK_FUSE>, 4405 <&bpmp TEGRA234_CLK_TSEC_PKA>; 4406 clock-names = "nvdec", "fuse", "tsec_pka"; 4407 resets = <&bpmp TEGRA234_RESET_NVDEC>; 4408 reset-names = "nvdec"; 4409 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>; 4410 interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>, 4411 <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>; 4412 interconnect-names = "dma-mem", "write"; 4413 iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>; 4414 dma-coherent; 4415 4416 nvidia,memory-controller = <&mc>; 4417 4418 /* 4419 * Placeholder values that firmware needs to update with the real 4420 * offsets parsed from the microcode headers. 4421 */ 4422 nvidia,bl-manifest-offset = <0>; 4423 nvidia,bl-data-offset = <0>; 4424 nvidia,bl-code-offset = <0>; 4425 nvidia,os-manifest-offset = <0>; 4426 nvidia,os-data-offset = <0>; 4427 nvidia,os-code-offset = <0>; 4428 4429 /* 4430 * Firmware needs to set this to "okay" once the above values have 4431 * been updated. 4432 */ 4433 status = "disabled"; 4434 }; 4435 4436 crypto@15820000 { 4437 compatible = "nvidia,tegra234-se-aes"; 4438 reg = <0x00 0x15820000 0x00 0x10000>; 4439 clocks = <&bpmp TEGRA234_CLK_SE>; 4440 iommus = <&smmu_niso1 TEGRA234_SID_SES_SE1>; 4441 dma-coherent; 4442 }; 4443 4444 crypto@15840000 { 4445 compatible = "nvidia,tegra234-se-hash"; 4446 reg = <0x00 0x15840000 0x00 0x10000>; 4447 clocks = <&bpmp TEGRA234_CLK_SE>; 4448 iommus = <&smmu_niso1 TEGRA234_SID_SES_SE2>; 4449 dma-coherent; 4450 }; 4451 }; 4452 4453 pcie@140a0000 { 4454 compatible = "nvidia,tegra234-pcie"; 4455 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>; 4456 reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */ 4457 <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */ 4458 <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 4459 <0x00 0x2a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 4460 <0x35 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 4461 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 4462 4463 #address-cells = <3>; 4464 #size-cells = <2>; 4465 device_type = "pci"; 4466 num-lanes = <4>; 4467 num-viewport = <8>; 4468 linux,pci-domain = <8>; 4469 4470 clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>; 4471 clock-names = "core"; 4472 4473 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>, 4474 <&bpmp TEGRA234_RESET_PEX2_CORE_8>; 4475 reset-names = "apb", "core"; 4476 4477 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 4478 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 4479 interrupt-names = "intr", "msi"; 4480 4481 #interrupt-cells = <1>; 4482 interrupt-map-mask = <0 0 0 0>; 4483 interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 4484 4485 nvidia,bpmp = <&bpmp 8>; 4486 4487 nvidia,aspm-cmrt-us = <60>; 4488 nvidia,aspm-pwr-on-t-us = <20>; 4489 nvidia,aspm-l0s-entrance-latency-us = <3>; 4490 4491 bus-range = <0x0 0xff>; 4492 4493 ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 4494 <0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 4495 <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 4496 4497 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE8AR &emc>, 4498 <&mc TEGRA234_MEMORY_CLIENT_PCIE8AW &emc>; 4499 interconnect-names = "dma-mem", "write"; 4500 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>; 4501 iommu-map-mask = <0x0>; 4502 dma-coherent; 4503 4504 status = "disabled"; 4505 }; 4506 4507 pcie@140c0000 { 4508 compatible = "nvidia,tegra234-pcie"; 4509 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>; 4510 reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */ 4511 <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */ 4512 <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 4513 <0x00 0x2c080000 0x0 0x00040000>, /* DBI reg space (256K) */ 4514 <0x38 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 4515 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 4516 4517 #address-cells = <3>; 4518 #size-cells = <2>; 4519 device_type = "pci"; 4520 num-lanes = <4>; 4521 num-viewport = <8>; 4522 linux,pci-domain = <9>; 4523 4524 clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>; 4525 clock-names = "core"; 4526 4527 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>, 4528 <&bpmp TEGRA234_RESET_PEX2_CORE_9>; 4529 reset-names = "apb", "core"; 4530 4531 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 4532 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 4533 interrupt-names = "intr", "msi"; 4534 4535 #interrupt-cells = <1>; 4536 interrupt-map-mask = <0 0 0 0>; 4537 interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 4538 4539 nvidia,bpmp = <&bpmp 9>; 4540 4541 nvidia,aspm-cmrt-us = <60>; 4542 nvidia,aspm-pwr-on-t-us = <20>; 4543 nvidia,aspm-l0s-entrance-latency-us = <3>; 4544 4545 bus-range = <0x0 0xff>; 4546 4547 ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (11264 MB) */ 4548 <0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 4549 <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 4550 4551 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE9AR &emc>, 4552 <&mc TEGRA234_MEMORY_CLIENT_PCIE9AW &emc>; 4553 interconnect-names = "dma-mem", "write"; 4554 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>; 4555 iommu-map-mask = <0x0>; 4556 dma-coherent; 4557 4558 status = "disabled"; 4559 }; 4560 4561 pcie@140e0000 { 4562 compatible = "nvidia,tegra234-pcie"; 4563 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 4564 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 4565 <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */ 4566 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 4567 <0x00 0x2e080000 0x0 0x00040000>, /* DBI reg space (256K) */ 4568 <0x3b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 4569 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 4570 4571 #address-cells = <3>; 4572 #size-cells = <2>; 4573 device_type = "pci"; 4574 num-lanes = <4>; 4575 num-viewport = <8>; 4576 linux,pci-domain = <10>; 4577 4578 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 4579 clock-names = "core"; 4580 4581 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 4582 <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 4583 reset-names = "apb", "core"; 4584 4585 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 4586 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 4587 interrupt-names = "intr", "msi"; 4588 4589 #interrupt-cells = <1>; 4590 interrupt-map-mask = <0 0 0 0>; 4591 interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 4592 4593 nvidia,bpmp = <&bpmp 10>; 4594 4595 nvidia,aspm-cmrt-us = <60>; 4596 nvidia,aspm-pwr-on-t-us = <20>; 4597 nvidia,aspm-l0s-entrance-latency-us = <3>; 4598 4599 bus-range = <0x0 0xff>; 4600 4601 ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 4602 <0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 4603 <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 4604 4605 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 4606 <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 4607 interconnect-names = "dma-mem", "write"; 4608 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 4609 iommu-map-mask = <0x0>; 4610 dma-coherent; 4611 4612 status = "disabled"; 4613 }; 4614 4615 pcie-ep@140e0000 { 4616 compatible = "nvidia,tegra234-pcie-ep"; 4617 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 4618 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 4619 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 4620 <0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K) */ 4621 <0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 4622 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 4623 4624 num-lanes = <4>; 4625 4626 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 4627 clock-names = "core"; 4628 4629 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 4630 <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 4631 reset-names = "apb", "core"; 4632 4633 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 4634 interrupt-names = "intr"; 4635 4636 nvidia,bpmp = <&bpmp 10>; 4637 4638 nvidia,enable-ext-refclk; 4639 nvidia,aspm-cmrt-us = <60>; 4640 nvidia,aspm-pwr-on-t-us = <20>; 4641 nvidia,aspm-l0s-entrance-latency-us = <3>; 4642 4643 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 4644 <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 4645 interconnect-names = "dma-mem", "write"; 4646 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 4647 iommu-map-mask = <0x0>; 4648 dma-coherent; 4649 4650 status = "disabled"; 4651 }; 4652 4653 pcie@14100000 { 4654 compatible = "nvidia,tegra234-pcie"; 4655 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 4656 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 4657 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 4658 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 4659 <0x00 0x30080000 0x0 0x00040000>, /* DBI reg space (256K) */ 4660 <0x20 0xb0000000 0x0 0x10000000>; /* ECAM (256MB) */ 4661 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 4662 4663 #address-cells = <3>; 4664 #size-cells = <2>; 4665 device_type = "pci"; 4666 num-lanes = <1>; 4667 num-viewport = <8>; 4668 linux,pci-domain = <1>; 4669 4670 clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>; 4671 clock-names = "core"; 4672 4673 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>, 4674 <&bpmp TEGRA234_RESET_PEX0_CORE_1>; 4675 reset-names = "apb", "core"; 4676 4677 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 4678 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 4679 interrupt-names = "intr", "msi"; 4680 4681 #interrupt-cells = <1>; 4682 interrupt-map-mask = <0 0 0 0>; 4683 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 4684 4685 nvidia,bpmp = <&bpmp 1>; 4686 4687 nvidia,aspm-cmrt-us = <60>; 4688 nvidia,aspm-pwr-on-t-us = <20>; 4689 nvidia,aspm-l0s-entrance-latency-us = <3>; 4690 4691 bus-range = <0x0 0xff>; 4692 4693 ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 4694 <0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 4695 <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 4696 4697 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE1R &emc>, 4698 <&mc TEGRA234_MEMORY_CLIENT_PCIE1W &emc>; 4699 interconnect-names = "dma-mem", "write"; 4700 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>; 4701 iommu-map-mask = <0x0>; 4702 dma-coherent; 4703 4704 status = "disabled"; 4705 }; 4706 4707 pcie@14120000 { 4708 compatible = "nvidia,tegra234-pcie"; 4709 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 4710 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 4711 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 4712 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 4713 <0x00 0x32080000 0x0 0x00040000>, /* DBI reg space (256K) */ 4714 <0x20 0xf0000000 0x0 0x10000000>; /* ECAM (256MB) */ 4715 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 4716 4717 #address-cells = <3>; 4718 #size-cells = <2>; 4719 device_type = "pci"; 4720 num-lanes = <1>; 4721 num-viewport = <8>; 4722 linux,pci-domain = <2>; 4723 4724 clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>; 4725 clock-names = "core"; 4726 4727 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>, 4728 <&bpmp TEGRA234_RESET_PEX0_CORE_2>; 4729 reset-names = "apb", "core"; 4730 4731 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 4732 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 4733 interrupt-names = "intr", "msi"; 4734 4735 #interrupt-cells = <1>; 4736 interrupt-map-mask = <0 0 0 0>; 4737 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 4738 4739 nvidia,bpmp = <&bpmp 2>; 4740 4741 nvidia,aspm-cmrt-us = <60>; 4742 nvidia,aspm-pwr-on-t-us = <20>; 4743 nvidia,aspm-l0s-entrance-latency-us = <3>; 4744 4745 bus-range = <0x0 0xff>; 4746 4747 ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 4748 <0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 4749 <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 4750 4751 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE2AR &emc>, 4752 <&mc TEGRA234_MEMORY_CLIENT_PCIE2AW &emc>; 4753 interconnect-names = "dma-mem", "write"; 4754 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>; 4755 iommu-map-mask = <0x0>; 4756 dma-coherent; 4757 4758 status = "disabled"; 4759 }; 4760 4761 pcie@14140000 { 4762 compatible = "nvidia,tegra234-pcie"; 4763 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 4764 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 4765 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 4766 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 4767 <0x00 0x34080000 0x0 0x00040000>, /* DBI reg space (256K) */ 4768 <0x21 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 4769 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 4770 4771 #address-cells = <3>; 4772 #size-cells = <2>; 4773 device_type = "pci"; 4774 num-lanes = <1>; 4775 num-viewport = <8>; 4776 linux,pci-domain = <3>; 4777 4778 clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>; 4779 clock-names = "core"; 4780 4781 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>, 4782 <&bpmp TEGRA234_RESET_PEX0_CORE_3>; 4783 reset-names = "apb", "core"; 4784 4785 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 4786 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 4787 interrupt-names = "intr", "msi"; 4788 4789 #interrupt-cells = <1>; 4790 interrupt-map-mask = <0 0 0 0>; 4791 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 4792 4793 nvidia,bpmp = <&bpmp 3>; 4794 4795 nvidia,aspm-cmrt-us = <60>; 4796 nvidia,aspm-pwr-on-t-us = <20>; 4797 nvidia,aspm-l0s-entrance-latency-us = <3>; 4798 4799 bus-range = <0x0 0xff>; 4800 4801 ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 4802 <0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 4803 <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 4804 4805 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>, 4806 <&mc TEGRA234_MEMORY_CLIENT_PCIE3W &emc>; 4807 interconnect-names = "dma-mem", "write"; 4808 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>; 4809 iommu-map-mask = <0x0>; 4810 dma-coherent; 4811 4812 status = "disabled"; 4813 }; 4814 4815 pcie@14160000 { 4816 compatible = "nvidia,tegra234-pcie"; 4817 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>; 4818 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 4819 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 4820 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 4821 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 4822 <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 4823 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 4824 4825 #address-cells = <3>; 4826 #size-cells = <2>; 4827 device_type = "pci"; 4828 num-lanes = <4>; 4829 num-viewport = <8>; 4830 linux,pci-domain = <4>; 4831 4832 clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>; 4833 clock-names = "core"; 4834 4835 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>, 4836 <&bpmp TEGRA234_RESET_PEX0_CORE_4>; 4837 reset-names = "apb", "core"; 4838 4839 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 4840 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 4841 interrupt-names = "intr", "msi"; 4842 4843 #interrupt-cells = <1>; 4844 interrupt-map-mask = <0 0 0 0>; 4845 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 4846 4847 nvidia,bpmp = <&bpmp 4>; 4848 4849 nvidia,aspm-cmrt-us = <60>; 4850 nvidia,aspm-pwr-on-t-us = <20>; 4851 nvidia,aspm-l0s-entrance-latency-us = <3>; 4852 4853 bus-range = <0x0 0xff>; 4854 4855 ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 4856 <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 4857 <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 4858 4859 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>, 4860 <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>; 4861 interconnect-names = "dma-mem", "write"; 4862 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>; 4863 iommu-map-mask = <0x0>; 4864 dma-coherent; 4865 4866 status = "disabled"; 4867 }; 4868 4869 pcie-ep@14160000 { 4870 compatible = "nvidia,tegra234-pcie-ep"; 4871 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>; 4872 reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */ 4873 0x00 0x36040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 4874 0x00 0x36080000 0x0 0x00040000 /* DBI space (256K) */ 4875 0x21 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 4876 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 4877 num-lanes = <4>; 4878 clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>; 4879 clock-names = "core"; 4880 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>, 4881 <&bpmp TEGRA234_RESET_PEX0_CORE_4>; 4882 reset-names = "apb", "core"; 4883 4884 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 4885 interrupt-names = "intr"; 4886 nvidia,bpmp = <&bpmp 4>; 4887 nvidia,enable-ext-refclk; 4888 nvidia,aspm-cmrt-us = <60>; 4889 nvidia,aspm-pwr-on-t-us = <20>; 4890 nvidia,aspm-l0s-entrance-latency-us = <3>; 4891 4892 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>, 4893 <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>; 4894 interconnect-names = "dma-mem", "write"; 4895 iommus = <&smmu_niso0 TEGRA234_SID_PCIE4>; 4896 dma-coherent; 4897 status = "disabled"; 4898 }; 4899 4900 pcie@14180000 { 4901 compatible = "nvidia,tegra234-pcie"; 4902 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>; 4903 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 4904 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 4905 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 4906 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 4907 <0x27 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 4908 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 4909 4910 #address-cells = <3>; 4911 #size-cells = <2>; 4912 device_type = "pci"; 4913 num-lanes = <4>; 4914 num-viewport = <8>; 4915 linux,pci-domain = <0>; 4916 4917 clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>; 4918 clock-names = "core"; 4919 4920 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>, 4921 <&bpmp TEGRA234_RESET_PEX0_CORE_0>; 4922 reset-names = "apb", "core"; 4923 4924 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 4925 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 4926 interrupt-names = "intr", "msi"; 4927 4928 #interrupt-cells = <1>; 4929 interrupt-map-mask = <0 0 0 0>; 4930 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 4931 4932 nvidia,bpmp = <&bpmp 0>; 4933 4934 nvidia,aspm-cmrt-us = <60>; 4935 nvidia,aspm-pwr-on-t-us = <20>; 4936 nvidia,aspm-l0s-entrance-latency-us = <3>; 4937 4938 bus-range = <0x0 0xff>; 4939 4940 ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 4941 <0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 4942 <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 4943 4944 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE0R &emc>, 4945 <&mc TEGRA234_MEMORY_CLIENT_PCIE0W &emc>; 4946 interconnect-names = "dma-mem", "write"; 4947 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>; 4948 iommu-map-mask = <0x0>; 4949 dma-coherent; 4950 4951 status = "disabled"; 4952 }; 4953 4954 pcie@141a0000 { 4955 compatible = "nvidia,tegra234-pcie"; 4956 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 4957 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 4958 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 4959 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 4960 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 4961 <0x2b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 4962 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 4963 4964 #address-cells = <3>; 4965 #size-cells = <2>; 4966 device_type = "pci"; 4967 num-lanes = <8>; 4968 num-viewport = <8>; 4969 linux,pci-domain = <5>; 4970 4971 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 4972 clock-names = "core"; 4973 4974 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 4975 <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 4976 reset-names = "apb", "core"; 4977 4978 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 4979 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 4980 interrupt-names = "intr", "msi"; 4981 4982 #interrupt-cells = <1>; 4983 interrupt-map-mask = <0 0 0 0>; 4984 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 4985 4986 nvidia,bpmp = <&bpmp 5>; 4987 4988 nvidia,aspm-cmrt-us = <60>; 4989 nvidia,aspm-pwr-on-t-us = <20>; 4990 nvidia,aspm-l0s-entrance-latency-us = <3>; 4991 4992 bus-range = <0x0 0xff>; 4993 4994 ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */ 4995 <0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 4996 <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 4997 4998 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 4999 <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 5000 interconnect-names = "dma-mem", "write"; 5001 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 5002 iommu-map-mask = <0x0>; 5003 dma-coherent; 5004 5005 status = "disabled"; 5006 }; 5007 5008 pcie-ep@141a0000 { 5009 compatible = "nvidia,tegra234-pcie-ep"; 5010 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 5011 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 5012 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 5013 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 5014 <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 5015 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 5016 5017 num-lanes = <8>; 5018 5019 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 5020 clock-names = "core"; 5021 5022 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 5023 <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 5024 reset-names = "apb", "core"; 5025 5026 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 5027 interrupt-names = "intr"; 5028 5029 nvidia,bpmp = <&bpmp 5>; 5030 5031 nvidia,enable-ext-refclk; 5032 nvidia,aspm-cmrt-us = <60>; 5033 nvidia,aspm-pwr-on-t-us = <20>; 5034 nvidia,aspm-l0s-entrance-latency-us = <3>; 5035 5036 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 5037 <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 5038 interconnect-names = "dma-mem", "write"; 5039 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 5040 iommu-map-mask = <0x0>; 5041 dma-coherent; 5042 5043 status = "disabled"; 5044 }; 5045 5046 pcie@141c0000 { 5047 compatible = "nvidia,tegra234-pcie"; 5048 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 5049 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 5050 <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */ 5051 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 5052 <0x00 0x3c080000 0x0 0x00040000>, /* DBI reg space (256K) */ 5053 <0x2e 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 5054 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 5055 5056 #address-cells = <3>; 5057 #size-cells = <2>; 5058 device_type = "pci"; 5059 num-lanes = <4>; 5060 num-viewport = <8>; 5061 linux,pci-domain = <6>; 5062 5063 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 5064 clock-names = "core"; 5065 5066 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 5067 <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 5068 reset-names = "apb", "core"; 5069 5070 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 5071 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 5072 interrupt-names = "intr", "msi"; 5073 5074 #interrupt-cells = <1>; 5075 interrupt-map-mask = <0 0 0 0>; 5076 interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 5077 5078 nvidia,bpmp = <&bpmp 6>; 5079 5080 nvidia,aspm-cmrt-us = <60>; 5081 nvidia,aspm-pwr-on-t-us = <20>; 5082 nvidia,aspm-l0s-entrance-latency-us = <3>; 5083 5084 bus-range = <0x0 0xff>; 5085 5086 ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 5087 <0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 5088 <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 5089 5090 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 5091 <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 5092 interconnect-names = "dma-mem", "write"; 5093 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 5094 iommu-map-mask = <0x0>; 5095 dma-coherent; 5096 5097 status = "disabled"; 5098 }; 5099 5100 pcie-ep@141c0000 { 5101 compatible = "nvidia,tegra234-pcie-ep"; 5102 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 5103 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 5104 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 5105 <0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K) */ 5106 <0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 5107 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 5108 5109 num-lanes = <4>; 5110 5111 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 5112 clock-names = "core"; 5113 5114 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 5115 <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 5116 reset-names = "apb", "core"; 5117 5118 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 5119 interrupt-names = "intr"; 5120 5121 nvidia,bpmp = <&bpmp 6>; 5122 5123 nvidia,enable-ext-refclk; 5124 nvidia,aspm-cmrt-us = <60>; 5125 nvidia,aspm-pwr-on-t-us = <20>; 5126 nvidia,aspm-l0s-entrance-latency-us = <3>; 5127 5128 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 5129 <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 5130 interconnect-names = "dma-mem", "write"; 5131 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 5132 iommu-map-mask = <0x0>; 5133 dma-coherent; 5134 5135 status = "disabled"; 5136 }; 5137 5138 pcie@141e0000 { 5139 compatible = "nvidia,tegra234-pcie"; 5140 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 5141 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 5142 <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */ 5143 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 5144 <0x00 0x3e080000 0x0 0x00040000>, /* DBI reg space (256K) */ 5145 <0x32 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 5146 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 5147 5148 #address-cells = <3>; 5149 #size-cells = <2>; 5150 device_type = "pci"; 5151 num-lanes = <8>; 5152 num-viewport = <8>; 5153 linux,pci-domain = <7>; 5154 5155 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 5156 clock-names = "core"; 5157 5158 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 5159 <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 5160 reset-names = "apb", "core"; 5161 5162 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 5163 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 5164 interrupt-names = "intr", "msi"; 5165 5166 #interrupt-cells = <1>; 5167 interrupt-map-mask = <0 0 0 0>; 5168 interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 5169 5170 nvidia,bpmp = <&bpmp 7>; 5171 5172 nvidia,aspm-cmrt-us = <60>; 5173 nvidia,aspm-pwr-on-t-us = <20>; 5174 nvidia,aspm-l0s-entrance-latency-us = <3>; 5175 5176 bus-range = <0x0 0xff>; 5177 5178 ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832 MB) */ 5179 <0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 5180 <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 5181 5182 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 5183 <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 5184 interconnect-names = "dma-mem", "write"; 5185 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 5186 iommu-map-mask = <0x0>; 5187 dma-coherent; 5188 5189 status = "disabled"; 5190 }; 5191 5192 pcie-ep@141e0000 { 5193 compatible = "nvidia,tegra234-pcie-ep"; 5194 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 5195 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 5196 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 5197 <0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K) */ 5198 <0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 5199 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 5200 5201 num-lanes = <8>; 5202 5203 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 5204 clock-names = "core"; 5205 5206 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 5207 <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 5208 reset-names = "apb", "core"; 5209 5210 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 5211 interrupt-names = "intr"; 5212 5213 nvidia,bpmp = <&bpmp 7>; 5214 5215 nvidia,enable-ext-refclk; 5216 nvidia,aspm-cmrt-us = <60>; 5217 nvidia,aspm-pwr-on-t-us = <20>; 5218 nvidia,aspm-l0s-entrance-latency-us = <3>; 5219 5220 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 5221 <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 5222 interconnect-names = "dma-mem", "write"; 5223 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 5224 iommu-map-mask = <0x0>; 5225 dma-coherent; 5226 5227 status = "disabled"; 5228 }; 5229 }; 5230 5231 sram@40000000 { 5232 compatible = "nvidia,tegra234-sysram", "mmio-sram"; 5233 reg = <0x0 0x40000000 0x0 0x80000>; 5234 5235 #address-cells = <1>; 5236 #size-cells = <1>; 5237 ranges = <0x0 0x0 0x40000000 0x80000>; 5238 5239 no-memory-wc; 5240 5241 cpu_bpmp_tx: sram@70000 { 5242 reg = <0x70000 0x1000>; 5243 label = "cpu-bpmp-tx"; 5244 pool; 5245 }; 5246 5247 cpu_bpmp_rx: sram@71000 { 5248 reg = <0x71000 0x1000>; 5249 label = "cpu-bpmp-rx"; 5250 pool; 5251 }; 5252 }; 5253 5254 bpmp: bpmp { 5255 compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; 5256 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 5257 TEGRA_HSP_DB_MASTER_BPMP>; 5258 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 5259 #clock-cells = <1>; 5260 #reset-cells = <1>; 5261 #power-domain-cells = <1>; 5262 interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>, 5263 <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>, 5264 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>, 5265 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>; 5266 interconnect-names = "read", "write", "dma-mem", "dma-write"; 5267 iommus = <&smmu_niso1 TEGRA234_SID_BPMP>; 5268 5269 bpmp_i2c: i2c { 5270 compatible = "nvidia,tegra186-bpmp-i2c"; 5271 nvidia,bpmp-bus-id = <5>; 5272 #address-cells = <1>; 5273 #size-cells = <0>; 5274 }; 5275 5276 bpmp_thermal: thermal { 5277 compatible = "nvidia,tegra186-bpmp-thermal"; 5278 #thermal-sensor-cells = <1>; 5279 }; 5280 }; 5281 5282 cpus { 5283 #address-cells = <1>; 5284 #size-cells = <0>; 5285 5286 cpu0_0: cpu@0 { 5287 compatible = "arm,cortex-a78"; 5288 device_type = "cpu"; 5289 reg = <0x00000>; 5290 5291 enable-method = "psci"; 5292 5293 operating-points-v2 = <&cl0_opp_tbl>; 5294 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>; 5295 5296 i-cache-size = <65536>; 5297 i-cache-line-size = <64>; 5298 i-cache-sets = <256>; 5299 d-cache-size = <65536>; 5300 d-cache-line-size = <64>; 5301 d-cache-sets = <256>; 5302 next-level-cache = <&l2c0_0>; 5303 }; 5304 5305 cpu0_1: cpu@100 { 5306 compatible = "arm,cortex-a78"; 5307 device_type = "cpu"; 5308 reg = <0x00100>; 5309 5310 enable-method = "psci"; 5311 5312 operating-points-v2 = <&cl0_opp_tbl>; 5313 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>; 5314 5315 i-cache-size = <65536>; 5316 i-cache-line-size = <64>; 5317 i-cache-sets = <256>; 5318 d-cache-size = <65536>; 5319 d-cache-line-size = <64>; 5320 d-cache-sets = <256>; 5321 next-level-cache = <&l2c0_1>; 5322 }; 5323 5324 cpu0_2: cpu@200 { 5325 compatible = "arm,cortex-a78"; 5326 device_type = "cpu"; 5327 reg = <0x00200>; 5328 5329 enable-method = "psci"; 5330 5331 operating-points-v2 = <&cl0_opp_tbl>; 5332 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>; 5333 5334 i-cache-size = <65536>; 5335 i-cache-line-size = <64>; 5336 i-cache-sets = <256>; 5337 d-cache-size = <65536>; 5338 d-cache-line-size = <64>; 5339 d-cache-sets = <256>; 5340 next-level-cache = <&l2c0_2>; 5341 }; 5342 5343 cpu0_3: cpu@300 { 5344 compatible = "arm,cortex-a78"; 5345 device_type = "cpu"; 5346 reg = <0x00300>; 5347 5348 enable-method = "psci"; 5349 5350 operating-points-v2 = <&cl0_opp_tbl>; 5351 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>; 5352 5353 i-cache-size = <65536>; 5354 i-cache-line-size = <64>; 5355 i-cache-sets = <256>; 5356 d-cache-size = <65536>; 5357 d-cache-line-size = <64>; 5358 d-cache-sets = <256>; 5359 next-level-cache = <&l2c0_3>; 5360 }; 5361 5362 cpu1_0: cpu@10000 { 5363 compatible = "arm,cortex-a78"; 5364 device_type = "cpu"; 5365 reg = <0x10000>; 5366 5367 enable-method = "psci"; 5368 5369 operating-points-v2 = <&cl1_opp_tbl>; 5370 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; 5371 5372 i-cache-size = <65536>; 5373 i-cache-line-size = <64>; 5374 i-cache-sets = <256>; 5375 d-cache-size = <65536>; 5376 d-cache-line-size = <64>; 5377 d-cache-sets = <256>; 5378 next-level-cache = <&l2c1_0>; 5379 }; 5380 5381 cpu1_1: cpu@10100 { 5382 compatible = "arm,cortex-a78"; 5383 device_type = "cpu"; 5384 reg = <0x10100>; 5385 5386 enable-method = "psci"; 5387 5388 operating-points-v2 = <&cl1_opp_tbl>; 5389 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; 5390 5391 i-cache-size = <65536>; 5392 i-cache-line-size = <64>; 5393 i-cache-sets = <256>; 5394 d-cache-size = <65536>; 5395 d-cache-line-size = <64>; 5396 d-cache-sets = <256>; 5397 next-level-cache = <&l2c1_1>; 5398 }; 5399 5400 cpu1_2: cpu@10200 { 5401 compatible = "arm,cortex-a78"; 5402 device_type = "cpu"; 5403 reg = <0x10200>; 5404 5405 enable-method = "psci"; 5406 5407 operating-points-v2 = <&cl1_opp_tbl>; 5408 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; 5409 5410 i-cache-size = <65536>; 5411 i-cache-line-size = <64>; 5412 i-cache-sets = <256>; 5413 d-cache-size = <65536>; 5414 d-cache-line-size = <64>; 5415 d-cache-sets = <256>; 5416 next-level-cache = <&l2c1_2>; 5417 }; 5418 5419 cpu1_3: cpu@10300 { 5420 compatible = "arm,cortex-a78"; 5421 device_type = "cpu"; 5422 reg = <0x10300>; 5423 5424 enable-method = "psci"; 5425 5426 operating-points-v2 = <&cl1_opp_tbl>; 5427 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; 5428 5429 i-cache-size = <65536>; 5430 i-cache-line-size = <64>; 5431 i-cache-sets = <256>; 5432 d-cache-size = <65536>; 5433 d-cache-line-size = <64>; 5434 d-cache-sets = <256>; 5435 next-level-cache = <&l2c1_3>; 5436 }; 5437 5438 cpu2_0: cpu@20000 { 5439 compatible = "arm,cortex-a78"; 5440 device_type = "cpu"; 5441 reg = <0x20000>; 5442 5443 enable-method = "psci"; 5444 5445 operating-points-v2 = <&cl2_opp_tbl>; 5446 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>; 5447 5448 i-cache-size = <65536>; 5449 i-cache-line-size = <64>; 5450 i-cache-sets = <256>; 5451 d-cache-size = <65536>; 5452 d-cache-line-size = <64>; 5453 d-cache-sets = <256>; 5454 next-level-cache = <&l2c2_0>; 5455 }; 5456 5457 cpu2_1: cpu@20100 { 5458 compatible = "arm,cortex-a78"; 5459 device_type = "cpu"; 5460 reg = <0x20100>; 5461 5462 enable-method = "psci"; 5463 5464 operating-points-v2 = <&cl2_opp_tbl>; 5465 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>; 5466 5467 i-cache-size = <65536>; 5468 i-cache-line-size = <64>; 5469 i-cache-sets = <256>; 5470 d-cache-size = <65536>; 5471 d-cache-line-size = <64>; 5472 d-cache-sets = <256>; 5473 next-level-cache = <&l2c2_1>; 5474 }; 5475 5476 cpu2_2: cpu@20200 { 5477 compatible = "arm,cortex-a78"; 5478 device_type = "cpu"; 5479 reg = <0x20200>; 5480 5481 enable-method = "psci"; 5482 5483 operating-points-v2 = <&cl2_opp_tbl>; 5484 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>; 5485 5486 i-cache-size = <65536>; 5487 i-cache-line-size = <64>; 5488 i-cache-sets = <256>; 5489 d-cache-size = <65536>; 5490 d-cache-line-size = <64>; 5491 d-cache-sets = <256>; 5492 next-level-cache = <&l2c2_2>; 5493 }; 5494 5495 cpu2_3: cpu@20300 { 5496 compatible = "arm,cortex-a78"; 5497 device_type = "cpu"; 5498 reg = <0x20300>; 5499 5500 enable-method = "psci"; 5501 5502 operating-points-v2 = <&cl2_opp_tbl>; 5503 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>; 5504 5505 i-cache-size = <65536>; 5506 i-cache-line-size = <64>; 5507 i-cache-sets = <256>; 5508 d-cache-size = <65536>; 5509 d-cache-line-size = <64>; 5510 d-cache-sets = <256>; 5511 next-level-cache = <&l2c2_3>; 5512 }; 5513 5514 cpu-map { 5515 cluster0 { 5516 core0 { 5517 cpu = <&cpu0_0>; 5518 }; 5519 5520 core1 { 5521 cpu = <&cpu0_1>; 5522 }; 5523 5524 core2 { 5525 cpu = <&cpu0_2>; 5526 }; 5527 5528 core3 { 5529 cpu = <&cpu0_3>; 5530 }; 5531 }; 5532 5533 cluster1 { 5534 core0 { 5535 cpu = <&cpu1_0>; 5536 }; 5537 5538 core1 { 5539 cpu = <&cpu1_1>; 5540 }; 5541 5542 core2 { 5543 cpu = <&cpu1_2>; 5544 }; 5545 5546 core3 { 5547 cpu = <&cpu1_3>; 5548 }; 5549 }; 5550 5551 cluster2 { 5552 core0 { 5553 cpu = <&cpu2_0>; 5554 }; 5555 5556 core1 { 5557 cpu = <&cpu2_1>; 5558 }; 5559 5560 core2 { 5561 cpu = <&cpu2_2>; 5562 }; 5563 5564 core3 { 5565 cpu = <&cpu2_3>; 5566 }; 5567 }; 5568 }; 5569 5570 l2c0_0: l2-cache00 { 5571 compatible = "cache"; 5572 cache-size = <262144>; 5573 cache-line-size = <64>; 5574 cache-sets = <512>; 5575 cache-unified; 5576 cache-level = <2>; 5577 next-level-cache = <&l3c0>; 5578 }; 5579 5580 l2c0_1: l2-cache01 { 5581 compatible = "cache"; 5582 cache-size = <262144>; 5583 cache-line-size = <64>; 5584 cache-sets = <512>; 5585 cache-unified; 5586 cache-level = <2>; 5587 next-level-cache = <&l3c0>; 5588 }; 5589 5590 l2c0_2: l2-cache02 { 5591 compatible = "cache"; 5592 cache-size = <262144>; 5593 cache-line-size = <64>; 5594 cache-sets = <512>; 5595 cache-unified; 5596 cache-level = <2>; 5597 next-level-cache = <&l3c0>; 5598 }; 5599 5600 l2c0_3: l2-cache03 { 5601 compatible = "cache"; 5602 cache-size = <262144>; 5603 cache-line-size = <64>; 5604 cache-sets = <512>; 5605 cache-unified; 5606 cache-level = <2>; 5607 next-level-cache = <&l3c0>; 5608 }; 5609 5610 l2c1_0: l2-cache10 { 5611 compatible = "cache"; 5612 cache-size = <262144>; 5613 cache-line-size = <64>; 5614 cache-sets = <512>; 5615 cache-unified; 5616 cache-level = <2>; 5617 next-level-cache = <&l3c1>; 5618 }; 5619 5620 l2c1_1: l2-cache11 { 5621 compatible = "cache"; 5622 cache-size = <262144>; 5623 cache-line-size = <64>; 5624 cache-sets = <512>; 5625 cache-unified; 5626 cache-level = <2>; 5627 next-level-cache = <&l3c1>; 5628 }; 5629 5630 l2c1_2: l2-cache12 { 5631 compatible = "cache"; 5632 cache-size = <262144>; 5633 cache-line-size = <64>; 5634 cache-sets = <512>; 5635 cache-unified; 5636 cache-level = <2>; 5637 next-level-cache = <&l3c1>; 5638 }; 5639 5640 l2c1_3: l2-cache13 { 5641 compatible = "cache"; 5642 cache-size = <262144>; 5643 cache-line-size = <64>; 5644 cache-sets = <512>; 5645 cache-unified; 5646 cache-level = <2>; 5647 next-level-cache = <&l3c1>; 5648 }; 5649 5650 l2c2_0: l2-cache20 { 5651 compatible = "cache"; 5652 cache-size = <262144>; 5653 cache-line-size = <64>; 5654 cache-sets = <512>; 5655 cache-unified; 5656 cache-level = <2>; 5657 next-level-cache = <&l3c2>; 5658 }; 5659 5660 l2c2_1: l2-cache21 { 5661 compatible = "cache"; 5662 cache-size = <262144>; 5663 cache-line-size = <64>; 5664 cache-sets = <512>; 5665 cache-unified; 5666 cache-level = <2>; 5667 next-level-cache = <&l3c2>; 5668 }; 5669 5670 l2c2_2: l2-cache22 { 5671 compatible = "cache"; 5672 cache-size = <262144>; 5673 cache-line-size = <64>; 5674 cache-sets = <512>; 5675 cache-unified; 5676 cache-level = <2>; 5677 next-level-cache = <&l3c2>; 5678 }; 5679 5680 l2c2_3: l2-cache23 { 5681 compatible = "cache"; 5682 cache-size = <262144>; 5683 cache-line-size = <64>; 5684 cache-sets = <512>; 5685 cache-unified; 5686 cache-level = <2>; 5687 next-level-cache = <&l3c2>; 5688 }; 5689 5690 l3c0: l3-cache0 { 5691 compatible = "cache"; 5692 cache-unified; 5693 cache-size = <2097152>; 5694 cache-line-size = <64>; 5695 cache-sets = <2048>; 5696 cache-level = <3>; 5697 }; 5698 5699 l3c1: l3-cache1 { 5700 compatible = "cache"; 5701 cache-unified; 5702 cache-size = <2097152>; 5703 cache-line-size = <64>; 5704 cache-sets = <2048>; 5705 cache-level = <3>; 5706 }; 5707 5708 l3c2: l3-cache2 { 5709 compatible = "cache"; 5710 cache-unified; 5711 cache-size = <2097152>; 5712 cache-line-size = <64>; 5713 cache-sets = <2048>; 5714 cache-level = <3>; 5715 }; 5716 }; 5717 5718 dsu-pmu0 { 5719 compatible = "arm,dsu-pmu"; 5720 interrupts = <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>; 5721 cpus = <&cpu0_0>, <&cpu0_1>, <&cpu0_2>, <&cpu0_3>; 5722 }; 5723 5724 dsu-pmu1 { 5725 compatible = "arm,dsu-pmu"; 5726 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>; 5727 cpus = <&cpu1_0>, <&cpu1_1>, <&cpu1_2>, <&cpu1_3>; 5728 }; 5729 5730 dsu-pmu2 { 5731 compatible = "arm,dsu-pmu"; 5732 interrupts = <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; 5733 cpus = <&cpu2_0>, <&cpu2_1>, <&cpu2_2>, <&cpu2_3>; 5734 }; 5735 5736 pmu { 5737 compatible = "arm,cortex-a78-pmu"; 5738 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 5739 status = "okay"; 5740 }; 5741 5742 psci { 5743 compatible = "arm,psci-1.0"; 5744 status = "okay"; 5745 method = "smc"; 5746 }; 5747 5748 tcu: serial { 5749 compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu"; 5750 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 5751 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 5752 mbox-names = "rx", "tx"; 5753 status = "disabled"; 5754 }; 5755 5756 sound { 5757 status = "disabled"; 5758 5759 clocks = <&bpmp TEGRA234_CLK_PLLA>, 5760 <&bpmp TEGRA234_CLK_PLLA_OUT0>; 5761 clock-names = "pll_a", "plla_out0"; 5762 assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>, 5763 <&bpmp TEGRA234_CLK_PLLA_OUT0>, 5764 <&bpmp TEGRA234_CLK_AUD_MCLK>; 5765 assigned-clock-parents = <0>, 5766 <&bpmp TEGRA234_CLK_PLLA>, 5767 <&bpmp TEGRA234_CLK_PLLA_OUT0>; 5768 }; 5769 5770 thermal-zones { 5771 cpu-thermal { 5772 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CPU>; 5773 status = "disabled"; 5774 }; 5775 5776 gpu-thermal { 5777 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_GPU>; 5778 status = "disabled"; 5779 }; 5780 5781 cv0-thermal { 5782 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV0>; 5783 status = "disabled"; 5784 }; 5785 5786 cv1-thermal { 5787 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV1>; 5788 status = "disabled"; 5789 }; 5790 5791 cv2-thermal { 5792 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV2>; 5793 status = "disabled"; 5794 }; 5795 5796 soc0-thermal { 5797 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC0>; 5798 status = "disabled"; 5799 }; 5800 5801 soc1-thermal { 5802 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC1>; 5803 status = "disabled"; 5804 }; 5805 5806 soc2-thermal { 5807 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC2>; 5808 status = "disabled"; 5809 }; 5810 5811 tj-thermal { 5812 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_TJ_MAX>; 5813 status = "disabled"; 5814 }; 5815 }; 5816 5817 timer { 5818 compatible = "arm,armv8-timer"; 5819 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 5820 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 5821 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 5822 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 5823 interrupt-parent = <&gic>; 5824 always-on; 5825 }; 5826 5827 cl0_opp_tbl: opp-table-cluster0 { 5828 compatible = "operating-points-v2"; 5829 opp-shared; 5830 5831 cl0_ch1_opp1: opp-115200000 { 5832 opp-hz = /bits/ 64 <115200000>; 5833 opp-peak-kBps = <816000>; 5834 }; 5835 5836 cl0_ch1_opp2: opp-192000000 { 5837 opp-hz = /bits/ 64 <192000000>; 5838 opp-peak-kBps = <816000>; 5839 }; 5840 5841 cl0_ch1_opp3: opp-268800000 { 5842 opp-hz = /bits/ 64 <268800000>; 5843 opp-peak-kBps = <816000>; 5844 }; 5845 5846 cl0_ch1_opp4: opp-345600000 { 5847 opp-hz = /bits/ 64 <345600000>; 5848 opp-peak-kBps = <816000>; 5849 }; 5850 5851 cl0_ch1_opp5: opp-422400000 { 5852 opp-hz = /bits/ 64 <422400000>; 5853 opp-peak-kBps = <816000>; 5854 }; 5855 5856 cl0_ch1_opp6: opp-499200000 { 5857 opp-hz = /bits/ 64 <499200000>; 5858 opp-peak-kBps = <816000>; 5859 }; 5860 5861 cl0_ch1_opp7: opp-576000000 { 5862 opp-hz = /bits/ 64 <576000000>; 5863 opp-peak-kBps = <816000>; 5864 }; 5865 5866 cl0_ch1_opp8: opp-652800000 { 5867 opp-hz = /bits/ 64 <652800000>; 5868 opp-peak-kBps = <816000>; 5869 }; 5870 5871 cl0_ch1_opp9: opp-729600000 { 5872 opp-hz = /bits/ 64 <729600000>; 5873 opp-peak-kBps = <816000>; 5874 }; 5875 5876 cl0_ch1_opp10: opp-806400000 { 5877 opp-hz = /bits/ 64 <806400000>; 5878 opp-peak-kBps = <816000>; 5879 }; 5880 5881 cl0_ch1_opp11: opp-883200000 { 5882 opp-hz = /bits/ 64 <883200000>; 5883 opp-peak-kBps = <816000>; 5884 }; 5885 5886 cl0_ch1_opp12: opp-960000000 { 5887 opp-hz = /bits/ 64 <960000000>; 5888 opp-peak-kBps = <816000>; 5889 }; 5890 5891 cl0_ch1_opp13: opp-1036800000 { 5892 opp-hz = /bits/ 64 <1036800000>; 5893 opp-peak-kBps = <816000>; 5894 }; 5895 5896 cl0_ch1_opp14: opp-1113600000 { 5897 opp-hz = /bits/ 64 <1113600000>; 5898 opp-peak-kBps = <1632000>; 5899 }; 5900 5901 cl0_ch1_opp15: opp-1190400000 { 5902 opp-hz = /bits/ 64 <1190400000>; 5903 opp-peak-kBps = <1632000>; 5904 }; 5905 5906 cl0_ch1_opp16: opp-1267200000 { 5907 opp-hz = /bits/ 64 <1267200000>; 5908 opp-peak-kBps = <1632000>; 5909 }; 5910 5911 cl0_ch1_opp17: opp-1344000000 { 5912 opp-hz = /bits/ 64 <1344000000>; 5913 opp-peak-kBps = <1632000>; 5914 }; 5915 5916 cl0_ch1_opp18: opp-1420800000 { 5917 opp-hz = /bits/ 64 <1420800000>; 5918 opp-peak-kBps = <1632000>; 5919 }; 5920 5921 cl0_ch1_opp19: opp-1497600000 { 5922 opp-hz = /bits/ 64 <1497600000>; 5923 opp-peak-kBps = <3200000>; 5924 }; 5925 5926 cl0_ch1_opp20: opp-1574400000 { 5927 opp-hz = /bits/ 64 <1574400000>; 5928 opp-peak-kBps = <3200000>; 5929 }; 5930 5931 cl0_ch1_opp21: opp-1651200000 { 5932 opp-hz = /bits/ 64 <1651200000>; 5933 opp-peak-kBps = <3200000>; 5934 }; 5935 5936 cl0_ch1_opp22: opp-1728000000 { 5937 opp-hz = /bits/ 64 <1728000000>; 5938 opp-peak-kBps = <3200000>; 5939 }; 5940 5941 cl0_ch1_opp23: opp-1804800000 { 5942 opp-hz = /bits/ 64 <1804800000>; 5943 opp-peak-kBps = <3200000>; 5944 }; 5945 5946 cl0_ch1_opp24: opp-1881600000 { 5947 opp-hz = /bits/ 64 <1881600000>; 5948 opp-peak-kBps = <3200000>; 5949 }; 5950 5951 cl0_ch1_opp25: opp-1958400000 { 5952 opp-hz = /bits/ 64 <1958400000>; 5953 opp-peak-kBps = <3200000>; 5954 }; 5955 5956 cl0_ch1_opp26: opp-2035200000 { 5957 opp-hz = /bits/ 64 <2035200000>; 5958 opp-peak-kBps = <3200000>; 5959 }; 5960 5961 cl0_ch1_opp27: opp-2112000000 { 5962 opp-hz = /bits/ 64 <2112000000>; 5963 opp-peak-kBps = <6400000>; 5964 }; 5965 5966 cl0_ch1_opp28: opp-2188800000 { 5967 opp-hz = /bits/ 64 <2188800000>; 5968 opp-peak-kBps = <6400000>; 5969 }; 5970 5971 cl0_ch1_opp29: opp-2201600000 { 5972 opp-hz = /bits/ 64 <2201600000>; 5973 opp-peak-kBps = <6400000>; 5974 }; 5975 }; 5976 5977 cl1_opp_tbl: opp-table-cluster1 { 5978 compatible = "operating-points-v2"; 5979 opp-shared; 5980 5981 cl1_ch1_opp1: opp-115200000 { 5982 opp-hz = /bits/ 64 <115200000>; 5983 opp-peak-kBps = <816000>; 5984 }; 5985 5986 cl1_ch1_opp2: opp-192000000 { 5987 opp-hz = /bits/ 64 <192000000>; 5988 opp-peak-kBps = <816000>; 5989 }; 5990 5991 cl1_ch1_opp3: opp-268800000 { 5992 opp-hz = /bits/ 64 <268800000>; 5993 opp-peak-kBps = <816000>; 5994 }; 5995 5996 cl1_ch1_opp4: opp-345600000 { 5997 opp-hz = /bits/ 64 <345600000>; 5998 opp-peak-kBps = <816000>; 5999 }; 6000 6001 cl1_ch1_opp5: opp-422400000 { 6002 opp-hz = /bits/ 64 <422400000>; 6003 opp-peak-kBps = <816000>; 6004 }; 6005 6006 cl1_ch1_opp6: opp-499200000 { 6007 opp-hz = /bits/ 64 <499200000>; 6008 opp-peak-kBps = <816000>; 6009 }; 6010 6011 cl1_ch1_opp7: opp-576000000 { 6012 opp-hz = /bits/ 64 <576000000>; 6013 opp-peak-kBps = <816000>; 6014 }; 6015 6016 cl1_ch1_opp8: opp-652800000 { 6017 opp-hz = /bits/ 64 <652800000>; 6018 opp-peak-kBps = <816000>; 6019 }; 6020 6021 cl1_ch1_opp9: opp-729600000 { 6022 opp-hz = /bits/ 64 <729600000>; 6023 opp-peak-kBps = <816000>; 6024 }; 6025 6026 cl1_ch1_opp10: opp-806400000 { 6027 opp-hz = /bits/ 64 <806400000>; 6028 opp-peak-kBps = <816000>; 6029 }; 6030 6031 cl1_ch1_opp11: opp-883200000 { 6032 opp-hz = /bits/ 64 <883200000>; 6033 opp-peak-kBps = <816000>; 6034 }; 6035 6036 cl1_ch1_opp12: opp-960000000 { 6037 opp-hz = /bits/ 64 <960000000>; 6038 opp-peak-kBps = <816000>; 6039 }; 6040 6041 cl1_ch1_opp13: opp-1036800000 { 6042 opp-hz = /bits/ 64 <1036800000>; 6043 opp-peak-kBps = <816000>; 6044 }; 6045 6046 cl1_ch1_opp14: opp-1113600000 { 6047 opp-hz = /bits/ 64 <1113600000>; 6048 opp-peak-kBps = <1632000>; 6049 }; 6050 6051 cl1_ch1_opp15: opp-1190400000 { 6052 opp-hz = /bits/ 64 <1190400000>; 6053 opp-peak-kBps = <1632000>; 6054 }; 6055 6056 cl1_ch1_opp16: opp-1267200000 { 6057 opp-hz = /bits/ 64 <1267200000>; 6058 opp-peak-kBps = <1632000>; 6059 }; 6060 6061 cl1_ch1_opp17: opp-1344000000 { 6062 opp-hz = /bits/ 64 <1344000000>; 6063 opp-peak-kBps = <1632000>; 6064 }; 6065 6066 cl1_ch1_opp18: opp-1420800000 { 6067 opp-hz = /bits/ 64 <1420800000>; 6068 opp-peak-kBps = <1632000>; 6069 }; 6070 6071 cl1_ch1_opp19: opp-1497600000 { 6072 opp-hz = /bits/ 64 <1497600000>; 6073 opp-peak-kBps = <3200000>; 6074 }; 6075 6076 cl1_ch1_opp20: opp-1574400000 { 6077 opp-hz = /bits/ 64 <1574400000>; 6078 opp-peak-kBps = <3200000>; 6079 }; 6080 6081 cl1_ch1_opp21: opp-1651200000 { 6082 opp-hz = /bits/ 64 <1651200000>; 6083 opp-peak-kBps = <3200000>; 6084 }; 6085 6086 cl1_ch1_opp22: opp-1728000000 { 6087 opp-hz = /bits/ 64 <1728000000>; 6088 opp-peak-kBps = <3200000>; 6089 }; 6090 6091 cl1_ch1_opp23: opp-1804800000 { 6092 opp-hz = /bits/ 64 <1804800000>; 6093 opp-peak-kBps = <3200000>; 6094 }; 6095 6096 cl1_ch1_opp24: opp-1881600000 { 6097 opp-hz = /bits/ 64 <1881600000>; 6098 opp-peak-kBps = <3200000>; 6099 }; 6100 6101 cl1_ch1_opp25: opp-1958400000 { 6102 opp-hz = /bits/ 64 <1958400000>; 6103 opp-peak-kBps = <3200000>; 6104 }; 6105 6106 cl1_ch1_opp26: opp-2035200000 { 6107 opp-hz = /bits/ 64 <2035200000>; 6108 opp-peak-kBps = <3200000>; 6109 }; 6110 6111 cl1_ch1_opp27: opp-2112000000 { 6112 opp-hz = /bits/ 64 <2112000000>; 6113 opp-peak-kBps = <6400000>; 6114 }; 6115 6116 cl1_ch1_opp28: opp-2188800000 { 6117 opp-hz = /bits/ 64 <2188800000>; 6118 opp-peak-kBps = <6400000>; 6119 }; 6120 6121 cl1_ch1_opp29: opp-2201600000 { 6122 opp-hz = /bits/ 64 <2201600000>; 6123 opp-peak-kBps = <6400000>; 6124 }; 6125 }; 6126 6127 cl2_opp_tbl: opp-table-cluster2 { 6128 compatible = "operating-points-v2"; 6129 opp-shared; 6130 6131 cl2_ch1_opp1: opp-115200000 { 6132 opp-hz = /bits/ 64 <115200000>; 6133 opp-peak-kBps = <816000>; 6134 }; 6135 6136 cl2_ch1_opp2: opp-192000000 { 6137 opp-hz = /bits/ 64 <192000000>; 6138 opp-peak-kBps = <816000>; 6139 }; 6140 6141 cl2_ch1_opp3: opp-268800000 { 6142 opp-hz = /bits/ 64 <268800000>; 6143 opp-peak-kBps = <816000>; 6144 }; 6145 6146 cl2_ch1_opp4: opp-345600000 { 6147 opp-hz = /bits/ 64 <345600000>; 6148 opp-peak-kBps = <816000>; 6149 }; 6150 6151 cl2_ch1_opp5: opp-422400000 { 6152 opp-hz = /bits/ 64 <422400000>; 6153 opp-peak-kBps = <816000>; 6154 }; 6155 6156 cl2_ch1_opp6: opp-499200000 { 6157 opp-hz = /bits/ 64 <499200000>; 6158 opp-peak-kBps = <816000>; 6159 }; 6160 6161 cl2_ch1_opp7: opp-576000000 { 6162 opp-hz = /bits/ 64 <576000000>; 6163 opp-peak-kBps = <816000>; 6164 }; 6165 6166 cl2_ch1_opp8: opp-652800000 { 6167 opp-hz = /bits/ 64 <652800000>; 6168 opp-peak-kBps = <816000>; 6169 }; 6170 6171 cl2_ch1_opp9: opp-729600000 { 6172 opp-hz = /bits/ 64 <729600000>; 6173 opp-peak-kBps = <816000>; 6174 }; 6175 6176 cl2_ch1_opp10: opp-806400000 { 6177 opp-hz = /bits/ 64 <806400000>; 6178 opp-peak-kBps = <816000>; 6179 }; 6180 6181 cl2_ch1_opp11: opp-883200000 { 6182 opp-hz = /bits/ 64 <883200000>; 6183 opp-peak-kBps = <816000>; 6184 }; 6185 6186 cl2_ch1_opp12: opp-960000000 { 6187 opp-hz = /bits/ 64 <960000000>; 6188 opp-peak-kBps = <816000>; 6189 }; 6190 6191 cl2_ch1_opp13: opp-1036800000 { 6192 opp-hz = /bits/ 64 <1036800000>; 6193 opp-peak-kBps = <816000>; 6194 }; 6195 6196 cl2_ch1_opp14: opp-1113600000 { 6197 opp-hz = /bits/ 64 <1113600000>; 6198 opp-peak-kBps = <1632000>; 6199 }; 6200 6201 cl2_ch1_opp15: opp-1190400000 { 6202 opp-hz = /bits/ 64 <1190400000>; 6203 opp-peak-kBps = <1632000>; 6204 }; 6205 6206 cl2_ch1_opp16: opp-1267200000 { 6207 opp-hz = /bits/ 64 <1267200000>; 6208 opp-peak-kBps = <1632000>; 6209 }; 6210 6211 cl2_ch1_opp17: opp-1344000000 { 6212 opp-hz = /bits/ 64 <1344000000>; 6213 opp-peak-kBps = <1632000>; 6214 }; 6215 6216 cl2_ch1_opp18: opp-1420800000 { 6217 opp-hz = /bits/ 64 <1420800000>; 6218 opp-peak-kBps = <1632000>; 6219 }; 6220 6221 cl2_ch1_opp19: opp-1497600000 { 6222 opp-hz = /bits/ 64 <1497600000>; 6223 opp-peak-kBps = <3200000>; 6224 }; 6225 6226 cl2_ch1_opp20: opp-1574400000 { 6227 opp-hz = /bits/ 64 <1574400000>; 6228 opp-peak-kBps = <3200000>; 6229 }; 6230 6231 cl2_ch1_opp21: opp-1651200000 { 6232 opp-hz = /bits/ 64 <1651200000>; 6233 opp-peak-kBps = <3200000>; 6234 }; 6235 6236 cl2_ch1_opp22: opp-1728000000 { 6237 opp-hz = /bits/ 64 <1728000000>; 6238 opp-peak-kBps = <3200000>; 6239 }; 6240 6241 cl2_ch1_opp23: opp-1804800000 { 6242 opp-hz = /bits/ 64 <1804800000>; 6243 opp-peak-kBps = <3200000>; 6244 }; 6245 6246 cl2_ch1_opp24: opp-1881600000 { 6247 opp-hz = /bits/ 64 <1881600000>; 6248 opp-peak-kBps = <3200000>; 6249 }; 6250 6251 cl2_ch1_opp25: opp-1958400000 { 6252 opp-hz = /bits/ 64 <1958400000>; 6253 opp-peak-kBps = <3200000>; 6254 }; 6255 6256 cl2_ch1_opp26: opp-2035200000 { 6257 opp-hz = /bits/ 64 <2035200000>; 6258 opp-peak-kBps = <3200000>; 6259 }; 6260 6261 cl2_ch1_opp27: opp-2112000000 { 6262 opp-hz = /bits/ 64 <2112000000>; 6263 opp-peak-kBps = <6400000>; 6264 }; 6265 6266 cl2_ch1_opp28: opp-2188800000 { 6267 opp-hz = /bits/ 64 <2188800000>; 6268 opp-peak-kBps = <6400000>; 6269 }; 6270 6271 cl2_ch1_opp29: opp-2201600000 { 6272 opp-hz = /bits/ 64 <2201600000>; 6273 opp-peak-kBps = <6400000>; 6274 }; 6275 }; 6276}; 6277