1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Renesas RZ/V2H(P) WDT Watchdog Driver
4 *
5 * Copyright (C) 2024 Renesas Electronics Corporation.
6 */
7 #include <linux/clk.h>
8 #include <linux/delay.h>
9 #include <linux/io.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/reset.h>
16 #include <linux/units.h>
17 #include <linux/watchdog.h>
18
19 #define WDTRR 0x00 /* WDT Refresh Register RW, 8 */
20 #define WDTCR 0x02 /* WDT Control Register RW, 16 */
21 #define WDTSR 0x04 /* WDT Status Register RW, 16 */
22 #define WDTRCR 0x06 /* WDT Reset Control Register RW, 8 */
23
24 /* This register is only available on RZ/T2H and RZ/N2H SoCs */
25 #define WDTDCR 0x00 /* WDT Debug Control Register RW, 32 */
26
27 #define WDTCR_TOPS_1024 0x00
28 #define WDTCR_TOPS_4096 0x01
29 #define WDTCR_TOPS_16384 0x03
30
31 #define WDTCR_CKS_CLK_1 0x00
32 #define WDTCR_CKS_CLK_4 0x10
33 #define WDTCR_CKS_CLK_256 0x50
34 #define WDTCR_CKS_CLK_8192 0x80
35
36 #define WDTCR_RPES_0 0x300
37 #define WDTCR_RPES_75 0x000
38
39 #define WDTCR_RPSS_25 0x00
40 #define WDTCR_RPSS_100 0x3000
41
42 #define WDTRCR_RSTIRQS BIT(7)
43
44 #define WDTDCR_WDTSTOPCTRL BIT(0)
45
46 #define WDT_DEFAULT_TIMEOUT 60U
47
48 static bool nowayout = WATCHDOG_NOWAYOUT;
49 module_param(nowayout, bool, 0);
50 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
51 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
52
53 enum rzv2h_wdt_count_source {
54 COUNT_SOURCE_LOCO,
55 COUNT_SOURCE_PCLK,
56 };
57
58 struct rzv2h_of_data {
59 u8 cks_min;
60 u8 cks_max;
61 u16 cks_div;
62 u8 tops;
63 u16 timeout_cycles;
64 enum rzv2h_wdt_count_source count_source;
65 bool wdtdcr;
66 };
67
68 struct rzv2h_wdt_priv {
69 void __iomem *base;
70 void __iomem *wdtdcr;
71 struct clk *pclk;
72 struct clk *oscclk;
73 struct reset_control *rstc;
74 struct watchdog_device wdev;
75 const struct rzv2h_of_data *of_data;
76 };
77
rzv2h_wdt_ping(struct watchdog_device * wdev)78 static int rzv2h_wdt_ping(struct watchdog_device *wdev)
79 {
80 struct rzv2h_wdt_priv *priv = watchdog_get_drvdata(wdev);
81
82 /*
83 * The down-counter is refreshed and starts counting operation on
84 * a write of the values 00h and FFh to the WDTRR register.
85 */
86 writeb(0x0, priv->base + WDTRR);
87 writeb(0xFF, priv->base + WDTRR);
88
89 return 0;
90 }
91
rzt2h_wdt_wdtdcr_count_stop(struct rzv2h_wdt_priv * priv)92 static void rzt2h_wdt_wdtdcr_count_stop(struct rzv2h_wdt_priv *priv)
93 {
94 u32 reg = readl(priv->wdtdcr + WDTDCR);
95
96 writel(reg | WDTDCR_WDTSTOPCTRL, priv->wdtdcr + WDTDCR);
97 }
98
rzt2h_wdt_wdtdcr_count_start(struct rzv2h_wdt_priv * priv)99 static void rzt2h_wdt_wdtdcr_count_start(struct rzv2h_wdt_priv *priv)
100 {
101 u32 reg = readl(priv->wdtdcr + WDTDCR);
102
103 writel(reg & ~WDTDCR_WDTSTOPCTRL, priv->wdtdcr + WDTDCR);
104 }
105
rzv2h_wdt_setup(struct watchdog_device * wdev,u16 wdtcr)106 static void rzv2h_wdt_setup(struct watchdog_device *wdev, u16 wdtcr)
107 {
108 struct rzv2h_wdt_priv *priv = watchdog_get_drvdata(wdev);
109
110 /* Configure the timeout, clock division ratio, and window start and end positions. */
111 writew(wdtcr, priv->base + WDTCR);
112
113 /* Enable interrupt output to the ICU. */
114 writeb(0, priv->base + WDTRCR);
115
116 /* Clear underflow flag and refresh error flag. */
117 writew(0, priv->base + WDTSR);
118 }
119
rzv2h_wdt_start(struct watchdog_device * wdev)120 static int rzv2h_wdt_start(struct watchdog_device *wdev)
121 {
122 struct rzv2h_wdt_priv *priv = watchdog_get_drvdata(wdev);
123 const struct rzv2h_of_data *of_data = priv->of_data;
124 int ret;
125
126 ret = pm_runtime_resume_and_get(wdev->parent);
127 if (ret)
128 return ret;
129
130 ret = reset_control_deassert(priv->rstc);
131 if (ret) {
132 pm_runtime_put(wdev->parent);
133 return ret;
134 }
135
136 /* delay to handle clock halt after de-assert operation */
137 udelay(3);
138
139 /*
140 * WDTCR
141 * - CKS[7:4] - Clock Division Ratio Select
142 * - 0101b: oscclk/256 for RZ/V2H(P)
143 * - 1000b: pclkl/8192 for RZ/T2H
144 * - RPSS[13:12] - Window Start Position Select - 11b: 100%
145 * - RPES[9:8] - Window End Position Select - 11b: 0%
146 * - TOPS[1:0] - Timeout Period Select
147 * - 11b: 16384 cycles (3FFFh) for RZ/V2H(P)
148 * - 01b: 4096 cycles (0FFFh) for RZ/T2H
149 */
150 rzv2h_wdt_setup(wdev, of_data->cks_max | WDTCR_RPSS_100 |
151 WDTCR_RPES_0 | of_data->tops);
152
153 if (priv->of_data->wdtdcr)
154 rzt2h_wdt_wdtdcr_count_start(priv);
155
156 /*
157 * Down counting starts after writing the sequence 00h -> FFh to the
158 * WDTRR register. Hence, call the ping operation after loading the counter.
159 */
160 rzv2h_wdt_ping(wdev);
161
162 return 0;
163 }
164
rzv2h_wdt_stop(struct watchdog_device * wdev)165 static int rzv2h_wdt_stop(struct watchdog_device *wdev)
166 {
167 struct rzv2h_wdt_priv *priv = watchdog_get_drvdata(wdev);
168 int ret;
169
170 ret = reset_control_assert(priv->rstc);
171 if (ret)
172 return ret;
173
174 if (priv->of_data->wdtdcr)
175 rzt2h_wdt_wdtdcr_count_stop(priv);
176
177 ret = pm_runtime_put(wdev->parent);
178 if (ret < 0)
179 return ret;
180
181 return 0;
182 }
183
184 static const struct watchdog_info rzv2h_wdt_ident = {
185 .options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT,
186 .identity = "Renesas RZ/V2H WDT Watchdog",
187 };
188
rzv2h_wdt_restart(struct watchdog_device * wdev,unsigned long action,void * data)189 static int rzv2h_wdt_restart(struct watchdog_device *wdev,
190 unsigned long action, void *data)
191 {
192 struct rzv2h_wdt_priv *priv = watchdog_get_drvdata(wdev);
193 int ret;
194
195 if (!watchdog_active(wdev)) {
196 ret = clk_enable(priv->pclk);
197 if (ret)
198 return ret;
199
200 ret = clk_enable(priv->oscclk);
201 if (ret) {
202 clk_disable(priv->pclk);
203 return ret;
204 }
205
206 ret = reset_control_deassert(priv->rstc);
207 if (ret) {
208 clk_disable(priv->oscclk);
209 clk_disable(priv->pclk);
210 return ret;
211 }
212 } else {
213 /*
214 * Writing to the WDT Control Register (WDTCR) or WDT Reset
215 * Control Register (WDTRCR) is possible once between the
216 * release from the reset state and the first refresh operation.
217 * Therefore, issue a reset if the watchdog is active.
218 */
219 ret = reset_control_reset(priv->rstc);
220 if (ret)
221 return ret;
222 }
223
224 /* delay to handle clock halt after de-assert operation */
225 udelay(3);
226
227 /*
228 * WDTCR
229 * - CKS[7:4] - Clock Division Ratio Select
230 * - 0000b: oscclk/1 for RZ/V2H(P)
231 * - 0100b: pclkl/4 for RZ/T2H
232 * - RPSS[13:12] - Window Start Position Select - 00b: 25%
233 * - RPES[9:8] - Window End Position Select - 00b: 75%
234 * - TOPS[1:0] - Timeout Period Select - 00b: 1024 cycles (03FFh)
235 */
236 rzv2h_wdt_setup(wdev, priv->of_data->cks_min | WDTCR_RPSS_25 |
237 WDTCR_RPES_75 | WDTCR_TOPS_1024);
238
239 if (priv->of_data->wdtdcr)
240 rzt2h_wdt_wdtdcr_count_start(priv);
241
242 rzv2h_wdt_ping(wdev);
243
244 /* wait for underflow to trigger... */
245 udelay(5);
246
247 return 0;
248 }
249
250 static const struct watchdog_ops rzv2h_wdt_ops = {
251 .owner = THIS_MODULE,
252 .start = rzv2h_wdt_start,
253 .stop = rzv2h_wdt_stop,
254 .ping = rzv2h_wdt_ping,
255 .restart = rzv2h_wdt_restart,
256 };
257
rzt2h_wdt_wdtdcr_init(struct platform_device * pdev,struct rzv2h_wdt_priv * priv)258 static int rzt2h_wdt_wdtdcr_init(struct platform_device *pdev,
259 struct rzv2h_wdt_priv *priv)
260 {
261 int ret;
262
263 priv->wdtdcr = devm_platform_ioremap_resource(pdev, 1);
264 if (IS_ERR(priv->wdtdcr))
265 return PTR_ERR(priv->wdtdcr);
266
267 ret = pm_runtime_resume_and_get(&pdev->dev);
268 if (ret)
269 return ret;
270
271 rzt2h_wdt_wdtdcr_count_stop(priv);
272
273 ret = pm_runtime_put(&pdev->dev);
274 if (ret < 0)
275 return ret;
276
277 return 0;
278 }
279
rzv2h_wdt_probe(struct platform_device * pdev)280 static int rzv2h_wdt_probe(struct platform_device *pdev)
281 {
282 struct device *dev = &pdev->dev;
283 struct rzv2h_wdt_priv *priv;
284 struct clk *count_clk;
285 int ret;
286
287 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
288 if (!priv)
289 return -ENOMEM;
290
291 priv->of_data = of_device_get_match_data(dev);
292
293 priv->base = devm_platform_ioremap_resource(pdev, 0);
294 if (IS_ERR(priv->base))
295 return PTR_ERR(priv->base);
296
297 priv->pclk = devm_clk_get_prepared(dev, "pclk");
298 if (IS_ERR(priv->pclk))
299 return dev_err_probe(dev, PTR_ERR(priv->pclk), "Failed to get pclk\n");
300
301 priv->oscclk = devm_clk_get_optional_prepared(dev, "oscclk");
302 if (IS_ERR(priv->oscclk))
303 return dev_err_probe(dev, PTR_ERR(priv->oscclk), "Failed to get oscclk\n");
304
305 priv->rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
306 if (IS_ERR(priv->rstc))
307 return dev_err_probe(dev, PTR_ERR(priv->rstc),
308 "Failed to get cpg reset\n");
309
310 switch (priv->of_data->count_source) {
311 case COUNT_SOURCE_LOCO:
312 count_clk = priv->oscclk;
313 break;
314 case COUNT_SOURCE_PCLK:
315 count_clk = priv->pclk;
316 break;
317 default:
318 return dev_err_probe(dev, -EINVAL, "Invalid count source\n");
319 }
320
321 priv->wdev.max_hw_heartbeat_ms = (MILLI * priv->of_data->timeout_cycles *
322 priv->of_data->cks_div) / clk_get_rate(count_clk);
323 dev_dbg(dev, "max hw timeout of %dms\n", priv->wdev.max_hw_heartbeat_ms);
324
325 ret = devm_pm_runtime_enable(dev);
326 if (ret)
327 return ret;
328
329 if (priv->of_data->wdtdcr) {
330 ret = rzt2h_wdt_wdtdcr_init(pdev, priv);
331 if (ret)
332 return dev_err_probe(dev, ret, "WDTDCR init failed\n");
333 }
334
335 priv->wdev.min_timeout = 1;
336 priv->wdev.timeout = WDT_DEFAULT_TIMEOUT;
337 priv->wdev.info = &rzv2h_wdt_ident;
338 priv->wdev.ops = &rzv2h_wdt_ops;
339 priv->wdev.parent = dev;
340 watchdog_set_drvdata(&priv->wdev, priv);
341 watchdog_set_nowayout(&priv->wdev, nowayout);
342 watchdog_stop_on_unregister(&priv->wdev);
343
344 watchdog_init_timeout(&priv->wdev, 0, dev);
345
346 return devm_watchdog_register_device(dev, &priv->wdev);
347 }
348
349 static const struct rzv2h_of_data rzt2h_wdt_of_data = {
350 .cks_min = WDTCR_CKS_CLK_4,
351 .cks_max = WDTCR_CKS_CLK_8192,
352 .cks_div = 8192,
353 .tops = WDTCR_TOPS_4096,
354 .timeout_cycles = 4096,
355 .count_source = COUNT_SOURCE_PCLK,
356 .wdtdcr = true,
357 };
358
359 static const struct rzv2h_of_data rzv2h_wdt_of_data = {
360 .cks_min = WDTCR_CKS_CLK_1,
361 .cks_max = WDTCR_CKS_CLK_256,
362 .cks_div = 256,
363 .tops = WDTCR_TOPS_16384,
364 .timeout_cycles = 16384,
365 .count_source = COUNT_SOURCE_LOCO,
366 };
367
368 static const struct of_device_id rzv2h_wdt_ids[] = {
369 { .compatible = "renesas,r9a09g057-wdt", .data = &rzv2h_wdt_of_data },
370 { .compatible = "renesas,r9a09g077-wdt", .data = &rzt2h_wdt_of_data },
371 { /* sentinel */ }
372 };
373 MODULE_DEVICE_TABLE(of, rzv2h_wdt_ids);
374
375 static struct platform_driver rzv2h_wdt_driver = {
376 .driver = {
377 .name = "rzv2h_wdt",
378 .of_match_table = rzv2h_wdt_ids,
379 },
380 .probe = rzv2h_wdt_probe,
381 };
382 module_platform_driver(rzv2h_wdt_driver);
383 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
384 MODULE_DESCRIPTION("Renesas RZ/V2H(P) WDT Watchdog Driver");
385 MODULE_LICENSE("GPL");
386