1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4 /* Linux PRO/1000 Ethernet Driver main header file */
5
6 #ifndef _E1000_H_
7 #define _E1000_H_
8
9 #include <linux/bitops.h>
10 #include <linux/types.h>
11 #include <linux/timer.h>
12 #include <linux/workqueue.h>
13 #include <linux/io.h>
14 #include <linux/netdevice.h>
15 #include <linux/pci.h>
16 #include <linux/crc32.h>
17 #include <linux/if_vlan.h>
18 #include <linux/timecounter.h>
19 #include <linux/net_tstamp.h>
20 #include <linux/ptp_clock_kernel.h>
21 #include <linux/ptp_classify.h>
22 #include <linux/mii.h>
23 #include <linux/mdio.h>
24 #include <linux/mutex.h>
25 #include <linux/pm_qos.h>
26 #include "hw.h"
27
28 struct e1000_info;
29
30 #define e_dbg(format, arg...) \
31 netdev_dbg(hw->adapter->netdev, format, ## arg)
32 #define e_err(format, arg...) \
33 netdev_err(adapter->netdev, format, ## arg)
34 #define e_info(format, arg...) \
35 netdev_info(adapter->netdev, format, ## arg)
36 #define e_warn(format, arg...) \
37 netdev_warn(adapter->netdev, format, ## arg)
38 #define e_notice(format, arg...) \
39 netdev_notice(adapter->netdev, format, ## arg)
40
41 /* Interrupt modes, as used by the IntMode parameter */
42 #define E1000E_INT_MODE_LEGACY 0
43 #define E1000E_INT_MODE_MSI 1
44 #define E1000E_INT_MODE_MSIX 2
45
46 /* Tx/Rx descriptor defines */
47 #define E1000_DEFAULT_TXD 256
48 #define E1000_MAX_TXD 4096
49 #define E1000_MIN_TXD 64
50
51 #define E1000_DEFAULT_RXD 256
52 #define E1000_MAX_RXD 4096
53 #define E1000_MIN_RXD 64
54
55 #define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */
56 #define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */
57
58 #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */
59
60 /* How many Tx Descriptors do we need to call netif_wake_queue ? */
61 /* How many Rx Buffers do we bundle into one write to the hardware ? */
62 #define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */
63
64 #define AUTO_ALL_MODES 0
65 #define E1000_EEPROM_APME 0x0400
66
67 #define E1000_MNG_VLAN_NONE 0xFFFF
68
69 #define DEFAULT_JUMBO 9234
70
71 /* Time to wait before putting the device into D3 if there's no link (in ms). */
72 #define LINK_TIMEOUT 100
73
74 /* Count for polling __E1000_RESET condition every 10-20msec.
75 * Experimentation has shown the reset can take approximately 210msec.
76 */
77 #define E1000_CHECK_RESET_COUNT 25
78
79 #define PCICFG_DESC_RING_STATUS 0xe4
80 #define FLUSH_DESC_REQUIRED 0x100
81
82 /* in the case of WTHRESH, it appears at least the 82571/2 hardware
83 * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when
84 * WTHRESH=4, so a setting of 5 gives the most efficient bus
85 * utilization but to avoid possible Tx stalls, set it to 1
86 */
87 #define E1000_TXDCTL_DMA_BURST_ENABLE \
88 (E1000_TXDCTL_GRAN | /* set descriptor granularity */ \
89 E1000_TXDCTL_COUNT_DESC | \
90 (1u << 16) | /* wthresh must be +1 more than desired */\
91 (1u << 8) | /* hthresh */ \
92 0x1f) /* pthresh */
93
94 #define E1000_RXDCTL_DMA_BURST_ENABLE \
95 (0x01000000 | /* set descriptor granularity */ \
96 (4u << 16) | /* set writeback threshold */ \
97 (4u << 8) | /* set prefetch threshold */ \
98 0x20) /* set hthresh */
99
100 #define E1000_TIDV_FPD BIT(31)
101 #define E1000_RDTR_FPD BIT(31)
102
103 enum e1000_boards {
104 board_82571,
105 board_82572,
106 board_82573,
107 board_82574,
108 board_82583,
109 board_80003es2lan,
110 board_ich8lan,
111 board_ich9lan,
112 board_ich10lan,
113 board_pchlan,
114 board_pch2lan,
115 board_pch_lpt,
116 board_pch_spt,
117 board_pch_cnp,
118 board_pch_tgp,
119 board_pch_adp,
120 board_pch_mtp,
121 board_pch_ptp
122 };
123
124 struct e1000_ps_page {
125 struct page *page;
126 u64 dma; /* must be u64 - written to hw */
127 };
128
129 /* wrappers around a pointer to a socket buffer,
130 * so a DMA handle can be stored along with the buffer
131 */
132 struct e1000_buffer {
133 dma_addr_t dma;
134 struct sk_buff *skb;
135 union {
136 /* Tx */
137 struct {
138 unsigned long time_stamp;
139 u16 length;
140 u16 next_to_watch;
141 unsigned int segs;
142 unsigned int bytecount;
143 u16 mapped_as_page;
144 };
145 /* Rx */
146 struct {
147 /* arrays of page information for packet split */
148 struct e1000_ps_page *ps_pages;
149 struct page *page;
150 };
151 };
152 };
153
154 struct e1000_ring {
155 struct e1000_adapter *adapter; /* back pointer to adapter */
156 void *desc; /* pointer to ring memory */
157 dma_addr_t dma; /* phys address of ring */
158 unsigned int size; /* length of ring in bytes */
159 unsigned int count; /* number of desc. in ring */
160
161 u16 next_to_use;
162 u16 next_to_clean;
163
164 void __iomem *head;
165 void __iomem *tail;
166
167 /* array of buffer information structs */
168 struct e1000_buffer *buffer_info;
169
170 char name[IFNAMSIZ + 5];
171 u32 ims_val;
172 u32 itr_val;
173 void __iomem *itr_register;
174 int set_itr;
175
176 struct sk_buff *rx_skb_top;
177 };
178
179 /* PHY register snapshot values */
180 struct e1000_phy_regs {
181 u16 bmcr; /* basic mode control register */
182 u16 bmsr; /* basic mode status register */
183 u16 advertise; /* auto-negotiation advertisement */
184 u16 lpa; /* link partner ability register */
185 u16 expansion; /* auto-negotiation expansion reg */
186 u16 ctrl1000; /* 1000BASE-T control register */
187 u16 stat1000; /* 1000BASE-T status register */
188 u16 estatus; /* extended status register */
189 };
190
191 /* board specific private data structure */
192 struct e1000_adapter {
193 struct timer_list watchdog_timer;
194 struct timer_list phy_info_timer;
195 struct timer_list blink_timer;
196
197 struct work_struct reset_task;
198 struct work_struct watchdog_task;
199
200 const struct e1000_info *ei;
201
202 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
203 u32 bd_number;
204 u32 rx_buffer_len;
205 u16 mng_vlan_id;
206 u16 link_speed;
207 u16 link_duplex;
208 u16 eeprom_vers;
209
210 /* track device up/down/testing state */
211 unsigned long state;
212
213 /* Interrupt Throttle Rate */
214 u32 itr;
215 u32 itr_setting;
216 u16 tx_itr;
217 u16 rx_itr;
218
219 /* Tx - one ring per active queue */
220 struct e1000_ring *tx_ring ____cacheline_aligned_in_smp;
221 u32 tx_fifo_limit;
222
223 struct napi_struct napi;
224
225 unsigned int uncorr_errors; /* uncorrectable ECC errors */
226 unsigned int corr_errors; /* correctable ECC errors */
227 unsigned int restart_queue;
228 u32 txd_cmd;
229
230 bool detect_tx_hung;
231 bool tx_hang_recheck;
232 u8 tx_timeout_factor;
233
234 u32 tx_int_delay;
235 u32 tx_abs_int_delay;
236
237 unsigned int total_tx_bytes;
238 unsigned int total_tx_packets;
239 unsigned int total_rx_bytes;
240 unsigned int total_rx_packets;
241
242 /* Tx stats */
243 u64 tpt_old;
244 u64 colc_old;
245 u32 gotc;
246 u64 gotc_old;
247 u32 tx_timeout_count;
248 u32 tx_fifo_head;
249 u32 tx_head_addr;
250 u32 tx_fifo_size;
251 u32 tx_dma_failed;
252 u32 tx_hwtstamp_timeouts;
253 u32 tx_hwtstamp_skipped;
254
255 /* Rx */
256 bool (*clean_rx)(struct e1000_ring *ring, int *work_done,
257 int work_to_do) ____cacheline_aligned_in_smp;
258 void (*alloc_rx_buf)(struct e1000_ring *ring, int cleaned_count,
259 gfp_t gfp);
260 struct e1000_ring *rx_ring;
261
262 u32 rx_int_delay;
263 u32 rx_abs_int_delay;
264
265 /* Rx stats */
266 u64 hw_csum_err;
267 u64 hw_csum_good;
268 u64 rx_hdr_split;
269 u32 gorc;
270 u64 gorc_old;
271 u32 alloc_rx_buff_failed;
272 u32 rx_dma_failed;
273 u32 rx_hwtstamp_cleared;
274
275 unsigned int rx_ps_pages;
276 u16 rx_ps_bsize0;
277 u32 max_frame_size;
278 u32 min_frame_size;
279
280 /* OS defined structs */
281 struct net_device *netdev;
282 struct pci_dev *pdev;
283
284 /* structs defined in e1000_hw.h */
285 struct e1000_hw hw;
286
287 spinlock_t stats64_lock; /* protects statistics counters */
288 struct e1000_hw_stats stats;
289 struct e1000_phy_info phy_info;
290 struct e1000_phy_stats phy_stats;
291
292 /* Snapshot of PHY registers */
293 struct e1000_phy_regs phy_regs;
294
295 struct e1000_ring test_tx_ring;
296 struct e1000_ring test_rx_ring;
297 u32 test_icr;
298
299 u32 msg_enable;
300 unsigned int num_vectors;
301 struct msix_entry *msix_entries;
302 int int_mode;
303 u32 eiac_mask;
304
305 u32 eeprom_wol;
306 u32 wol;
307 u32 pba;
308 u32 max_hw_frame_size;
309
310 bool fc_autoneg;
311
312 unsigned int flags;
313 unsigned int flags2;
314 struct work_struct downshift_task;
315 struct work_struct update_phy_task;
316 struct work_struct print_hang_task;
317
318 int phy_hang_count;
319
320 u16 tx_ring_count;
321 u16 rx_ring_count;
322
323 struct kernel_hwtstamp_config hwtstamp_config;
324 struct delayed_work systim_overflow_work;
325 struct sk_buff *tx_hwtstamp_skb;
326 unsigned long tx_hwtstamp_start;
327 struct work_struct tx_hwtstamp_work;
328 spinlock_t systim_lock; /* protects SYSTIML/H regsters */
329 struct cyclecounter cc;
330 struct timecounter tc;
331 struct ptp_clock *ptp_clock;
332 struct ptp_clock_info ptp_clock_info;
333 struct pm_qos_request pm_qos_req;
334 long ptp_delta;
335
336 u16 eee_advert;
337 };
338
339 struct e1000_info {
340 enum e1000_mac_type mac;
341 unsigned int flags;
342 unsigned int flags2;
343 u32 pba;
344 u32 max_hw_frame_size;
345 s32 (*get_variants)(struct e1000_adapter *);
346 const struct e1000_mac_operations *mac_ops;
347 const struct e1000_phy_operations *phy_ops;
348 const struct e1000_nvm_operations *nvm_ops;
349 };
350
351 s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca);
352
353 /* The system time is maintained by a 64-bit counter comprised of the 32-bit
354 * SYSTIMH and SYSTIML registers. How the counter increments (and therefore
355 * its resolution) is based on the contents of the TIMINCA register - it
356 * increments every incperiod (bits 31:24) clock ticks by incvalue (bits 23:0).
357 * For the best accuracy, the incperiod should be as small as possible. The
358 * incvalue is scaled by a factor as large as possible (while still fitting
359 * in bits 23:0) so that relatively small clock corrections can be made.
360 *
361 * As a result, a shift of INCVALUE_SHIFT_n is used to fit a value of
362 * INCVALUE_n into the TIMINCA register allowing 32+8+(24-INCVALUE_SHIFT_n)
363 * bits to count nanoseconds leaving the rest for fractional nonseconds.
364 *
365 * Any given INCVALUE also has an associated maximum adjustment value. This
366 * maximum adjustment value is the largest increase (or decrease) which can be
367 * safely applied without overflowing the INCVALUE. Since INCVALUE has
368 * a maximum range of 24 bits, its largest value is 0xFFFFFF.
369 *
370 * To understand where the maximum value comes from, consider the following
371 * equation:
372 *
373 * new_incval = base_incval + (base_incval * adjustment) / 1billion
374 *
375 * To avoid overflow that means:
376 * max_incval = base_incval + (base_incval * max_adj) / billion
377 *
378 * Re-arranging:
379 * max_adj = floor(((max_incval - base_incval) * 1billion) / 1billion)
380 */
381 #define INCVALUE_96MHZ 125
382 #define INCVALUE_SHIFT_96MHZ 17
383 #define INCPERIOD_SHIFT_96MHZ 2
384 #define INCPERIOD_96MHZ (12 >> INCPERIOD_SHIFT_96MHZ)
385 #define MAX_PPB_96MHZ 23999900 /* 23,999,900 ppb */
386
387 #define INCVALUE_25MHZ 40
388 #define INCVALUE_SHIFT_25MHZ 18
389 #define INCPERIOD_25MHZ 1
390 #define MAX_PPB_25MHZ 599999900 /* 599,999,900 ppb */
391
392 #define INCVALUE_24MHZ 125
393 #define INCVALUE_SHIFT_24MHZ 14
394 #define INCPERIOD_24MHZ 3
395 #define MAX_PPB_24MHZ 999999999 /* 999,999,999 ppb */
396
397 #define INCVALUE_38400KHZ 26
398 #define INCVALUE_SHIFT_38400KHZ 19
399 #define INCPERIOD_38400KHZ 1
400 #define MAX_PPB_38400KHZ 230769100 /* 230,769,100 ppb */
401
402 /* Another drawback of scaling the incvalue by a large factor is the
403 * 64-bit SYSTIM register overflows more quickly. This is dealt with
404 * by simply reading the clock before it overflows.
405 *
406 * Clock ns bits Overflows after
407 * ~~~~~~ ~~~~~~~ ~~~~~~~~~~~~~~~
408 * 96MHz 47-bit 2^(47-INCPERIOD_SHIFT_96MHz) / 10^9 / 3600 = 9.77 hrs
409 * 25MHz 46-bit 2^46 / 10^9 / 3600 = 19.55 hours
410 */
411 #define E1000_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 60 * 4)
412 #define E1000_MAX_82574_SYSTIM_REREADS 50
413 #define E1000_82574_SYSTIM_EPSILON (1ULL << 35ULL)
414
415 /* hardware capability, feature, and workaround flags */
416 #define FLAG_HAS_AMT BIT(0)
417 #define FLAG_HAS_FLASH BIT(1)
418 #define FLAG_HAS_HW_VLAN_FILTER BIT(2)
419 #define FLAG_HAS_WOL BIT(3)
420 /* reserved BIT(4) */
421 #define FLAG_HAS_CTRLEXT_ON_LOAD BIT(5)
422 #define FLAG_HAS_SWSM_ON_LOAD BIT(6)
423 #define FLAG_HAS_JUMBO_FRAMES BIT(7)
424 #define FLAG_READ_ONLY_NVM BIT(8)
425 #define FLAG_IS_ICH BIT(9)
426 #define FLAG_HAS_MSIX BIT(10)
427 #define FLAG_HAS_SMART_POWER_DOWN BIT(11)
428 #define FLAG_IS_QUAD_PORT_A BIT(12)
429 #define FLAG_IS_QUAD_PORT BIT(13)
430 #define FLAG_HAS_HW_TIMESTAMP BIT(14)
431 #define FLAG_APME_IN_WUC BIT(15)
432 #define FLAG_APME_IN_CTRL3 BIT(16)
433 #define FLAG_APME_CHECK_PORT_B BIT(17)
434 #define FLAG_DISABLE_FC_PAUSE_TIME BIT(18)
435 #define FLAG_NO_WAKE_UCAST BIT(19)
436 #define FLAG_MNG_PT_ENABLED BIT(20)
437 #define FLAG_RESET_OVERWRITES_LAA BIT(21)
438 #define FLAG_TARC_SPEED_MODE_BIT BIT(22)
439 #define FLAG_TARC_SET_BIT_ZERO BIT(23)
440 #define FLAG_RX_NEEDS_RESTART BIT(24)
441 #define FLAG_LSC_GIG_SPEED_DROP BIT(25)
442 #define FLAG_SMART_POWER_DOWN BIT(26)
443 #define FLAG_MSI_ENABLED BIT(27)
444 /* reserved BIT(28) */
445 #define FLAG_TSO_FORCE BIT(29)
446 #define FLAG_RESTART_NOW BIT(30)
447 #define FLAG_MSI_TEST_FAILED BIT(31)
448
449 #define FLAG2_CRC_STRIPPING BIT(0)
450 #define FLAG2_HAS_PHY_WAKEUP BIT(1)
451 #define FLAG2_IS_DISCARDING BIT(2)
452 #define FLAG2_DISABLE_ASPM_L1 BIT(3)
453 #define FLAG2_HAS_PHY_STATS BIT(4)
454 #define FLAG2_HAS_EEE BIT(5)
455 #define FLAG2_DMA_BURST BIT(6)
456 #define FLAG2_DISABLE_ASPM_L0S BIT(7)
457 #define FLAG2_DISABLE_AIM BIT(8)
458 #define FLAG2_CHECK_PHY_HANG BIT(9)
459 #define FLAG2_NO_DISABLE_RX BIT(10)
460 #define FLAG2_PCIM2PCI_ARBITER_WA BIT(11)
461 #define FLAG2_DFLT_CRC_STRIPPING BIT(12)
462 #define FLAG2_CHECK_RX_HWTSTAMP BIT(13)
463 #define FLAG2_CHECK_SYSTIM_OVERFLOW BIT(14)
464 #define FLAG2_ENABLE_S0IX_FLOWS BIT(15)
465 #define FLAG2_DISABLE_K1 BIT(16)
466
467 #define E1000_RX_DESC_PS(R, i) \
468 (&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
469 #define E1000_RX_DESC_EXT(R, i) \
470 (&(((union e1000_rx_desc_extended *)((R).desc))[i]))
471 #define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
472 #define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc)
473 #define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc)
474
475 enum e1000_state_t {
476 __E1000_TESTING,
477 __E1000_RESETTING,
478 __E1000_ACCESS_SHARED_RESOURCE,
479 __E1000_DOWN
480 };
481
482 enum latency_range {
483 lowest_latency = 0,
484 low_latency = 1,
485 bulk_latency = 2,
486 latency_invalid = 255
487 };
488
489 extern char e1000e_driver_name[];
490
491 void e1000e_check_options(struct e1000_adapter *adapter);
492 void e1000e_set_ethtool_ops(struct net_device *netdev);
493
494 int e1000e_open(struct net_device *netdev);
495 int e1000e_close(struct net_device *netdev);
496 void e1000e_up(struct e1000_adapter *adapter);
497 void e1000e_down(struct e1000_adapter *adapter, bool reset);
498 void e1000e_reinit_locked(struct e1000_adapter *adapter);
499 void e1000e_reset(struct e1000_adapter *adapter);
500 void e1000e_power_up_phy(struct e1000_adapter *adapter);
501 int e1000e_setup_rx_resources(struct e1000_ring *ring);
502 int e1000e_setup_tx_resources(struct e1000_ring *ring);
503 void e1000e_free_rx_resources(struct e1000_ring *ring);
504 void e1000e_free_tx_resources(struct e1000_ring *ring);
505 void e1000e_get_stats64(struct net_device *netdev,
506 struct rtnl_link_stats64 *stats);
507 void e1000e_set_interrupt_capability(struct e1000_adapter *adapter);
508 void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter);
509 void e1000e_get_hw_control(struct e1000_adapter *adapter);
510 void e1000e_release_hw_control(struct e1000_adapter *adapter);
511 void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr);
512
513 extern unsigned int copybreak;
514
515 extern const struct e1000_info e1000_82571_info;
516 extern const struct e1000_info e1000_82572_info;
517 extern const struct e1000_info e1000_82573_info;
518 extern const struct e1000_info e1000_82574_info;
519 extern const struct e1000_info e1000_82583_info;
520 extern const struct e1000_info e1000_ich8_info;
521 extern const struct e1000_info e1000_ich9_info;
522 extern const struct e1000_info e1000_ich10_info;
523 extern const struct e1000_info e1000_pch_info;
524 extern const struct e1000_info e1000_pch2_info;
525 extern const struct e1000_info e1000_pch_lpt_info;
526 extern const struct e1000_info e1000_pch_spt_info;
527 extern const struct e1000_info e1000_pch_cnp_info;
528 extern const struct e1000_info e1000_pch_tgp_info;
529 extern const struct e1000_info e1000_pch_adp_info;
530 extern const struct e1000_info e1000_pch_mtp_info;
531 extern const struct e1000_info e1000_pch_ptp_info;
532 extern const struct e1000_info e1000_es2_info;
533
534 void e1000e_ptp_init(struct e1000_adapter *adapter);
535 void e1000e_ptp_remove(struct e1000_adapter *adapter);
536
537 u64 e1000e_read_systim(struct e1000_adapter *adapter,
538 struct ptp_system_timestamp *sts);
539
e1000_phy_hw_reset(struct e1000_hw * hw)540 static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw)
541 {
542 return hw->phy.ops.reset(hw);
543 }
544
e1e_rphy(struct e1000_hw * hw,u32 offset,u16 * data)545 static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data)
546 {
547 return hw->phy.ops.read_reg(hw, offset, data);
548 }
549
e1e_rphy_locked(struct e1000_hw * hw,u32 offset,u16 * data)550 static inline s32 e1e_rphy_locked(struct e1000_hw *hw, u32 offset, u16 *data)
551 {
552 return hw->phy.ops.read_reg_locked(hw, offset, data);
553 }
554
e1e_wphy(struct e1000_hw * hw,u32 offset,u16 data)555 static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data)
556 {
557 return hw->phy.ops.write_reg(hw, offset, data);
558 }
559
e1e_wphy_locked(struct e1000_hw * hw,u32 offset,u16 data)560 static inline s32 e1e_wphy_locked(struct e1000_hw *hw, u32 offset, u16 data)
561 {
562 return hw->phy.ops.write_reg_locked(hw, offset, data);
563 }
564
565 void e1000e_reload_nvm_generic(struct e1000_hw *hw);
566
e1000e_read_mac_addr(struct e1000_hw * hw)567 static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw)
568 {
569 if (hw->mac.ops.read_mac_addr)
570 return hw->mac.ops.read_mac_addr(hw);
571
572 return e1000_read_mac_addr_generic(hw);
573 }
574
e1000_validate_nvm_checksum(struct e1000_hw * hw)575 static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw)
576 {
577 return hw->nvm.ops.validate(hw);
578 }
579
e1000e_update_nvm_checksum(struct e1000_hw * hw)580 static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw)
581 {
582 return hw->nvm.ops.update(hw);
583 }
584
e1000_read_nvm(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)585 static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words,
586 u16 *data)
587 {
588 return hw->nvm.ops.read(hw, offset, words, data);
589 }
590
e1000_write_nvm(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)591 static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words,
592 u16 *data)
593 {
594 return hw->nvm.ops.write(hw, offset, words, data);
595 }
596
e1000_get_phy_info(struct e1000_hw * hw)597 static inline s32 e1000_get_phy_info(struct e1000_hw *hw)
598 {
599 return hw->phy.ops.get_info(hw);
600 }
601
__er32(struct e1000_hw * hw,unsigned long reg)602 static inline u32 __er32(struct e1000_hw *hw, unsigned long reg)
603 {
604 return readl(hw->hw_addr + reg);
605 }
606
607 #define er32(reg) __er32(hw, E1000_##reg)
608
609 void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val);
610
611 #define ew32(reg, val) __ew32(hw, E1000_##reg, (val))
612
613 #define e1e_flush() er32(STATUS)
614
615 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
616 (__ew32((a), (reg + ((offset) << 2)), (value)))
617
618 #define E1000_READ_REG_ARRAY(a, reg, offset) \
619 (readl((a)->hw_addr + reg + ((offset) << 2)))
620
621 #endif /* _E1000_H_ */
622