1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2017 Tony Lindgren <tony@atomide.com>
4 *
5 * Rewritten for Linux IIO framework with some code based on
6 * earlier driver found in the Motorola Linux kernel:
7 *
8 * Copyright (C) 2009-2010 Motorola, Inc.
9 */
10
11 #include <linux/delay.h>
12 #include <linux/device.h>
13 #include <linux/err.h>
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/property.h>
20 #include <linux/regmap.h>
21
22 #include <linux/iio/buffer.h>
23 #include <linux/iio/driver.h>
24 #include <linux/iio/iio.h>
25 #include <linux/iio/kfifo_buf.h>
26 #include <linux/mfd/motorola-cpcap.h>
27
28 /* Register CPCAP_REG_ADCC1 bits */
29 #define CPCAP_BIT_ADEN_AUTO_CLR BIT(15) /* Currently unused */
30 #define CPCAP_BIT_CAL_MODE BIT(14) /* Set with BIT_RAND0 */
31 #define CPCAP_BIT_ADC_CLK_SEL1 BIT(13) /* Currently unused */
32 #define CPCAP_BIT_ADC_CLK_SEL0 BIT(12) /* Currently unused */
33 #define CPCAP_BIT_ATOX BIT(11)
34 #define CPCAP_BIT_ATO3 BIT(10)
35 #define CPCAP_BIT_ATO2 BIT(9)
36 #define CPCAP_BIT_ATO1 BIT(8)
37 #define CPCAP_BIT_ATO0 BIT(7)
38 #define CPCAP_BIT_ADA2 BIT(6)
39 #define CPCAP_BIT_ADA1 BIT(5)
40 #define CPCAP_BIT_ADA0 BIT(4)
41 #define CPCAP_BIT_AD_SEL1 BIT(3) /* Set for bank1 */
42 #define CPCAP_BIT_RAND1 BIT(2) /* Set for channel 16 & 17 */
43 #define CPCAP_BIT_RAND0 BIT(1) /* Set with CAL_MODE */
44 #define CPCAP_BIT_ADEN BIT(0) /* Currently unused */
45
46 #define CPCAP_REG_ADCC1_DEFAULTS (CPCAP_BIT_ADEN_AUTO_CLR | \
47 CPCAP_BIT_ADC_CLK_SEL0 | \
48 CPCAP_BIT_RAND1)
49
50 /* Register CPCAP_REG_ADCC2 bits */
51 #define CPCAP_BIT_CAL_FACTOR_ENABLE BIT(15) /* Currently unused */
52 #define CPCAP_BIT_BATDETB_EN BIT(14) /* Currently unused */
53 #define CPCAP_BIT_ADTRIG_ONESHOT BIT(13) /* Set for !TIMING_IMM */
54 #define CPCAP_BIT_ASC BIT(12) /* Set for TIMING_IMM */
55 #define CPCAP_BIT_ATOX_PS_FACTOR BIT(11)
56 #define CPCAP_BIT_ADC_PS_FACTOR1 BIT(10)
57 #define CPCAP_BIT_ADC_PS_FACTOR0 BIT(9)
58 #define CPCAP_BIT_AD4_SELECT BIT(8) /* Currently unused */
59 #define CPCAP_BIT_ADC_BUSY BIT(7) /* Currently unused */
60 #define CPCAP_BIT_THERMBIAS_EN BIT(6) /* Bias for AD0_BATTDETB */
61 #define CPCAP_BIT_ADTRIG_DIS BIT(5) /* Disable interrupt */
62 #define CPCAP_BIT_LIADC BIT(4) /* Currently unused */
63 #define CPCAP_BIT_TS_REFEN BIT(3) /* Currently unused */
64 #define CPCAP_BIT_TS_M2 BIT(2) /* Currently unused */
65 #define CPCAP_BIT_TS_M1 BIT(1) /* Currently unused */
66 #define CPCAP_BIT_TS_M0 BIT(0) /* Currently unused */
67
68 #define CPCAP_REG_ADCC2_DEFAULTS (CPCAP_BIT_AD4_SELECT | \
69 CPCAP_BIT_ADTRIG_DIS | \
70 CPCAP_BIT_LIADC | \
71 CPCAP_BIT_TS_M2 | \
72 CPCAP_BIT_TS_M1)
73
74 #define CPCAP_MAX_TEMP_LVL 27
75 #define CPCAP_FOUR_POINT_TWO_ADC 801
76 #define ST_ADC_CAL_CHRGI_HIGH_THRESHOLD 530
77 #define ST_ADC_CAL_CHRGI_LOW_THRESHOLD 494
78 #define ST_ADC_CAL_BATTI_HIGH_THRESHOLD 530
79 #define ST_ADC_CAL_BATTI_LOW_THRESHOLD 494
80 #define ST_ADC_CALIBRATE_DIFF_THRESHOLD 3
81
82 #define CPCAP_ADC_MAX_RETRIES 5 /* Calibration */
83
84 /*
85 * struct cpcap_adc_ato - timing settings for cpcap adc
86 *
87 * Unfortunately no cpcap documentation available, please document when
88 * using these.
89 */
90 struct cpcap_adc_ato {
91 unsigned short ato_in;
92 unsigned short atox_in;
93 unsigned short adc_ps_factor_in;
94 unsigned short atox_ps_factor_in;
95 unsigned short ato_out;
96 unsigned short atox_out;
97 unsigned short adc_ps_factor_out;
98 unsigned short atox_ps_factor_out;
99 };
100
101 /**
102 * struct cpcap_adc - cpcap adc device driver data
103 * @reg: cpcap regmap
104 * @dev: struct device
105 * @vendor: cpcap vendor
106 * @irq: interrupt
107 * @lock: mutex
108 * @ato: request timings
109 * @wq_data_avail: work queue
110 * @done: work done
111 */
112 struct cpcap_adc {
113 struct regmap *reg;
114 struct device *dev;
115 u16 vendor;
116 int irq;
117 struct mutex lock; /* ADC register access lock */
118 const struct cpcap_adc_ato *ato;
119 wait_queue_head_t wq_data_avail;
120 bool done;
121 };
122
123 /*
124 * enum cpcap_adc_channel - cpcap adc channels
125 */
126 enum cpcap_adc_channel {
127 /* Bank0 channels */
128 CPCAP_ADC_AD0, /* Battery temperature */
129 CPCAP_ADC_BATTP, /* Battery voltage */
130 CPCAP_ADC_VBUS, /* USB VBUS voltage */
131 CPCAP_ADC_AD3, /* Die temperature when charging */
132 CPCAP_ADC_BPLUS_AD4, /* Another battery or system voltage */
133 CPCAP_ADC_CHG_ISENSE, /* Calibrated charge current */
134 CPCAP_ADC_BATTI, /* Calibrated system current */
135 CPCAP_ADC_USB_ID, /* USB OTG ID, unused on droid 4? */
136
137 /* Bank1 channels */
138 CPCAP_ADC_AD8, /* Seems unused */
139 CPCAP_ADC_AD9, /* Seems unused */
140 CPCAP_ADC_LICELL, /* Maybe system voltage? Always 3V */
141 CPCAP_ADC_HV_BATTP, /* Another battery detection? */
142 CPCAP_ADC_TSX1_AD12, /* Seems unused, for touchscreen? */
143 CPCAP_ADC_TSX2_AD13, /* Seems unused, for touchscreen? */
144 CPCAP_ADC_TSY1_AD14, /* Seems unused, for touchscreen? */
145 CPCAP_ADC_TSY2_AD15, /* Seems unused, for touchscreen? */
146
147 /* Remuxed channels using bank0 entries */
148 CPCAP_ADC_BATTP_PI16, /* Alternative mux mode for BATTP */
149 CPCAP_ADC_BATTI_PI17, /* Alternative mux mode for BATTI */
150
151 CPCAP_ADC_CHANNEL_NUM,
152 };
153
154 /*
155 * enum cpcap_adc_timing - cpcap adc timing options
156 *
157 * CPCAP_ADC_TIMING_IMM seems to be immediate with no timings.
158 * Please document when using.
159 */
160 enum cpcap_adc_timing {
161 CPCAP_ADC_TIMING_IMM,
162 CPCAP_ADC_TIMING_IN,
163 CPCAP_ADC_TIMING_OUT,
164 };
165
166 /**
167 * struct cpcap_adc_phasing_tbl - cpcap phasing table
168 * @offset: offset in the phasing table
169 * @multiplier: multiplier in the phasing table
170 * @divider: divider in the phasing table
171 * @min: minimum value
172 * @max: maximum value
173 */
174 struct cpcap_adc_phasing_tbl {
175 short offset;
176 unsigned short multiplier;
177 unsigned short divider;
178 short min;
179 short max;
180 };
181
182 /**
183 * struct cpcap_adc_conversion_tbl - cpcap conversion table
184 * @conv_type: conversion type
185 * @align_offset: align offset
186 * @conv_offset: conversion offset
187 * @cal_offset: calibration offset
188 * @multiplier: conversion multiplier
189 * @divider: conversion divider
190 */
191 struct cpcap_adc_conversion_tbl {
192 enum iio_chan_info_enum conv_type;
193 int align_offset;
194 int conv_offset;
195 int cal_offset;
196 int multiplier;
197 int divider;
198 };
199
200 /**
201 * struct cpcap_adc_request - cpcap adc request
202 * @channel: request channel
203 * @phase_tbl: channel phasing table
204 * @conv_tbl: channel conversion table
205 * @bank_index: channel index within the bank
206 * @timing: timing settings
207 * @result: result
208 */
209 struct cpcap_adc_request {
210 int channel;
211 const struct cpcap_adc_phasing_tbl *phase_tbl;
212 const struct cpcap_adc_conversion_tbl *conv_tbl;
213 int bank_index;
214 enum cpcap_adc_timing timing;
215 int result;
216 };
217
218 /* Phasing table for channels. Note that channels 16 & 17 use BATTP and BATTI */
219 static const struct cpcap_adc_phasing_tbl bank_phasing[] = {
220 /* Bank0 */
221 [CPCAP_ADC_AD0] = {0, 0x80, 0x80, 0, 1023},
222 [CPCAP_ADC_BATTP] = {0, 0x80, 0x80, 0, 1023},
223 [CPCAP_ADC_VBUS] = {0, 0x80, 0x80, 0, 1023},
224 [CPCAP_ADC_AD3] = {0, 0x80, 0x80, 0, 1023},
225 [CPCAP_ADC_BPLUS_AD4] = {0, 0x80, 0x80, 0, 1023},
226 [CPCAP_ADC_CHG_ISENSE] = {0, 0x80, 0x80, -512, 511},
227 [CPCAP_ADC_BATTI] = {0, 0x80, 0x80, -512, 511},
228 [CPCAP_ADC_USB_ID] = {0, 0x80, 0x80, 0, 1023},
229
230 /* Bank1 */
231 [CPCAP_ADC_AD8] = {0, 0x80, 0x80, 0, 1023},
232 [CPCAP_ADC_AD9] = {0, 0x80, 0x80, 0, 1023},
233 [CPCAP_ADC_LICELL] = {0, 0x80, 0x80, 0, 1023},
234 [CPCAP_ADC_HV_BATTP] = {0, 0x80, 0x80, 0, 1023},
235 [CPCAP_ADC_TSX1_AD12] = {0, 0x80, 0x80, 0, 1023},
236 [CPCAP_ADC_TSX2_AD13] = {0, 0x80, 0x80, 0, 1023},
237 [CPCAP_ADC_TSY1_AD14] = {0, 0x80, 0x80, 0, 1023},
238 [CPCAP_ADC_TSY2_AD15] = {0, 0x80, 0x80, 0, 1023},
239 };
240
241 /*
242 * Conversion table for channels. Updated during init based on calibration.
243 * Here too channels 16 & 17 use BATTP and BATTI.
244 */
245 static struct cpcap_adc_conversion_tbl bank_conversion[] = {
246 /* Bank0 */
247 [CPCAP_ADC_AD0] = {
248 IIO_CHAN_INFO_PROCESSED, 0, 0, 0, 1, 1,
249 },
250 [CPCAP_ADC_BATTP] = {
251 IIO_CHAN_INFO_PROCESSED, 0, 2400, 0, 2300, 1023,
252 },
253 [CPCAP_ADC_VBUS] = {
254 IIO_CHAN_INFO_PROCESSED, 0, 0, 0, 10000, 1023,
255 },
256 [CPCAP_ADC_AD3] = {
257 IIO_CHAN_INFO_PROCESSED, 0, 0, 0, 1, 1,
258 },
259 [CPCAP_ADC_BPLUS_AD4] = {
260 IIO_CHAN_INFO_PROCESSED, 0, 2400, 0, 2300, 1023,
261 },
262 [CPCAP_ADC_CHG_ISENSE] = {
263 IIO_CHAN_INFO_PROCESSED, -512, 2, 0, 5000, 1023,
264 },
265 [CPCAP_ADC_BATTI] = {
266 IIO_CHAN_INFO_PROCESSED, -512, 2, 0, 5000, 1023,
267 },
268 [CPCAP_ADC_USB_ID] = {
269 IIO_CHAN_INFO_RAW, 0, 0, 0, 1, 1,
270 },
271
272 /* Bank1 */
273 [CPCAP_ADC_AD8] = {
274 IIO_CHAN_INFO_RAW, 0, 0, 0, 1, 1,
275 },
276 [CPCAP_ADC_AD9] = {
277 IIO_CHAN_INFO_RAW, 0, 0, 0, 1, 1,
278 },
279 [CPCAP_ADC_LICELL] = {
280 IIO_CHAN_INFO_PROCESSED, 0, 0, 0, 3400, 1023,
281 },
282 [CPCAP_ADC_HV_BATTP] = {
283 IIO_CHAN_INFO_RAW, 0, 0, 0, 1, 1,
284 },
285 [CPCAP_ADC_TSX1_AD12] = {
286 IIO_CHAN_INFO_RAW, 0, 0, 0, 1, 1,
287 },
288 [CPCAP_ADC_TSX2_AD13] = {
289 IIO_CHAN_INFO_RAW, 0, 0, 0, 1, 1,
290 },
291 [CPCAP_ADC_TSY1_AD14] = {
292 IIO_CHAN_INFO_RAW, 0, 0, 0, 1, 1,
293 },
294 [CPCAP_ADC_TSY2_AD15] = {
295 IIO_CHAN_INFO_RAW, 0, 0, 0, 1, 1,
296 },
297 };
298
299 /*
300 * Temperature lookup table of register values to milliCelcius.
301 * REVISIT: Check the duplicate 0x3ff entry in a freezer
302 */
303 static const int temp_map[CPCAP_MAX_TEMP_LVL][2] = {
304 { 0x03ff, -40000 },
305 { 0x03ff, -35000 },
306 { 0x03ef, -30000 },
307 { 0x03b2, -25000 },
308 { 0x036c, -20000 },
309 { 0x0320, -15000 },
310 { 0x02d0, -10000 },
311 { 0x027f, -5000 },
312 { 0x022f, 0 },
313 { 0x01e4, 5000 },
314 { 0x019f, 10000 },
315 { 0x0161, 15000 },
316 { 0x012b, 20000 },
317 { 0x00fc, 25000 },
318 { 0x00d4, 30000 },
319 { 0x00b2, 35000 },
320 { 0x0095, 40000 },
321 { 0x007d, 45000 },
322 { 0x0069, 50000 },
323 { 0x0059, 55000 },
324 { 0x004b, 60000 },
325 { 0x003f, 65000 },
326 { 0x0036, 70000 },
327 { 0x002e, 75000 },
328 { 0x0027, 80000 },
329 { 0x0022, 85000 },
330 { 0x001d, 90000 },
331 };
332
333 #define CPCAP_CHAN(_type, _index, _address, _datasheet_name) { \
334 .type = (_type), \
335 .address = (_address), \
336 .indexed = 1, \
337 .channel = (_index), \
338 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
339 BIT(IIO_CHAN_INFO_PROCESSED), \
340 .scan_index = (_index), \
341 .scan_type = { \
342 .sign = 'u', \
343 .realbits = 10, \
344 .storagebits = 16, \
345 .endianness = IIO_CPU, \
346 }, \
347 .datasheet_name = (_datasheet_name), \
348 }
349
350 /*
351 * The datasheet names are from Motorola mapphone Linux kernel except
352 * for the last two which might be uncalibrated charge voltage and
353 * current.
354 */
355 static const struct iio_chan_spec cpcap_adc_channels[] = {
356 /* Bank0 */
357 CPCAP_CHAN(IIO_TEMP, 0, CPCAP_REG_ADCD0, "battdetb"),
358 CPCAP_CHAN(IIO_VOLTAGE, 1, CPCAP_REG_ADCD1, "battp"),
359 CPCAP_CHAN(IIO_VOLTAGE, 2, CPCAP_REG_ADCD2, "vbus"),
360 CPCAP_CHAN(IIO_TEMP, 3, CPCAP_REG_ADCD3, "ad3"),
361 CPCAP_CHAN(IIO_VOLTAGE, 4, CPCAP_REG_ADCD4, "ad4"),
362 CPCAP_CHAN(IIO_CURRENT, 5, CPCAP_REG_ADCD5, "chg_isense"),
363 CPCAP_CHAN(IIO_CURRENT, 6, CPCAP_REG_ADCD6, "batti"),
364 CPCAP_CHAN(IIO_VOLTAGE, 7, CPCAP_REG_ADCD7, "usb_id"),
365
366 /* Bank1 */
367 CPCAP_CHAN(IIO_CURRENT, 8, CPCAP_REG_ADCD0, "ad8"),
368 CPCAP_CHAN(IIO_VOLTAGE, 9, CPCAP_REG_ADCD1, "ad9"),
369 CPCAP_CHAN(IIO_VOLTAGE, 10, CPCAP_REG_ADCD2, "licell"),
370 CPCAP_CHAN(IIO_VOLTAGE, 11, CPCAP_REG_ADCD3, "hv_battp"),
371 CPCAP_CHAN(IIO_VOLTAGE, 12, CPCAP_REG_ADCD4, "tsx1_ad12"),
372 CPCAP_CHAN(IIO_VOLTAGE, 13, CPCAP_REG_ADCD5, "tsx2_ad13"),
373 CPCAP_CHAN(IIO_VOLTAGE, 14, CPCAP_REG_ADCD6, "tsy1_ad14"),
374 CPCAP_CHAN(IIO_VOLTAGE, 15, CPCAP_REG_ADCD7, "tsy2_ad15"),
375
376 /* There are two registers with multiplexed functionality */
377 CPCAP_CHAN(IIO_VOLTAGE, 16, CPCAP_REG_ADCD0, "chg_vsense"),
378 CPCAP_CHAN(IIO_CURRENT, 17, CPCAP_REG_ADCD1, "batti2"),
379 };
380
cpcap_adc_irq_thread(int irq,void * data)381 static irqreturn_t cpcap_adc_irq_thread(int irq, void *data)
382 {
383 struct iio_dev *indio_dev = data;
384 struct cpcap_adc *ddata = iio_priv(indio_dev);
385 int error;
386
387 error = regmap_set_bits(ddata->reg, CPCAP_REG_ADCC2,
388 CPCAP_BIT_ADTRIG_DIS);
389 if (error)
390 return IRQ_NONE;
391
392 ddata->done = true;
393 wake_up_interruptible(&ddata->wq_data_avail);
394
395 return IRQ_HANDLED;
396 }
397
398 /* ADC calibration functions */
cpcap_adc_setup_calibrate(struct cpcap_adc * ddata,enum cpcap_adc_channel chan)399 static void cpcap_adc_setup_calibrate(struct cpcap_adc *ddata,
400 enum cpcap_adc_channel chan)
401 {
402 unsigned int value = 0;
403 unsigned long timeout = jiffies + msecs_to_jiffies(3000);
404 int error;
405
406 if ((chan != CPCAP_ADC_CHG_ISENSE) &&
407 (chan != CPCAP_ADC_BATTI))
408 return;
409
410 value |= CPCAP_BIT_CAL_MODE | CPCAP_BIT_RAND0;
411 value |= ((chan << 4) &
412 (CPCAP_BIT_ADA2 | CPCAP_BIT_ADA1 | CPCAP_BIT_ADA0));
413
414 error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC1,
415 CPCAP_BIT_CAL_MODE | CPCAP_BIT_ATOX |
416 CPCAP_BIT_ATO3 | CPCAP_BIT_ATO2 |
417 CPCAP_BIT_ATO1 | CPCAP_BIT_ATO0 |
418 CPCAP_BIT_ADA2 | CPCAP_BIT_ADA1 |
419 CPCAP_BIT_ADA0 | CPCAP_BIT_AD_SEL1 |
420 CPCAP_BIT_RAND1 | CPCAP_BIT_RAND0,
421 value);
422 if (error)
423 return;
424
425 error = regmap_clear_bits(ddata->reg, CPCAP_REG_ADCC2,
426 CPCAP_BIT_ATOX_PS_FACTOR |
427 CPCAP_BIT_ADC_PS_FACTOR1 |
428 CPCAP_BIT_ADC_PS_FACTOR0);
429 if (error)
430 return;
431
432 error = regmap_set_bits(ddata->reg, CPCAP_REG_ADCC2,
433 CPCAP_BIT_ADTRIG_DIS);
434 if (error)
435 return;
436
437 error = regmap_set_bits(ddata->reg, CPCAP_REG_ADCC2, CPCAP_BIT_ASC);
438 if (error)
439 return;
440
441 do {
442 schedule_timeout_uninterruptible(1);
443 error = regmap_read(ddata->reg, CPCAP_REG_ADCC2, &value);
444 if (error)
445 return;
446 } while ((value & CPCAP_BIT_ASC) && time_before(jiffies, timeout));
447
448 if (value & CPCAP_BIT_ASC)
449 dev_err(ddata->dev,
450 "Timeout waiting for calibration to complete\n");
451
452 error = regmap_clear_bits(ddata->reg, CPCAP_REG_ADCC1,
453 CPCAP_BIT_CAL_MODE);
454 if (error)
455 return;
456 }
457
cpcap_adc_calibrate_one(struct cpcap_adc * ddata,int channel,u16 calibration_register,int lower_threshold,int upper_threshold)458 static int cpcap_adc_calibrate_one(struct cpcap_adc *ddata,
459 int channel,
460 u16 calibration_register,
461 int lower_threshold,
462 int upper_threshold)
463 {
464 unsigned int calibration_data[2];
465 unsigned short cal_data_diff;
466 int i, error;
467
468 for (i = 0; i < CPCAP_ADC_MAX_RETRIES; i++) {
469 calibration_data[0] = 0;
470 calibration_data[1] = 0;
471
472 cpcap_adc_setup_calibrate(ddata, channel);
473 error = regmap_read(ddata->reg, calibration_register,
474 &calibration_data[0]);
475 if (error)
476 return error;
477 cpcap_adc_setup_calibrate(ddata, channel);
478 error = regmap_read(ddata->reg, calibration_register,
479 &calibration_data[1]);
480 if (error)
481 return error;
482
483 if (calibration_data[0] > calibration_data[1])
484 cal_data_diff =
485 calibration_data[0] - calibration_data[1];
486 else
487 cal_data_diff =
488 calibration_data[1] - calibration_data[0];
489
490 if (((calibration_data[1] >= lower_threshold) &&
491 (calibration_data[1] <= upper_threshold) &&
492 (cal_data_diff <= ST_ADC_CALIBRATE_DIFF_THRESHOLD)) ||
493 (ddata->vendor == CPCAP_VENDOR_TI)) {
494 bank_conversion[channel].cal_offset =
495 ((short)calibration_data[1] * -1) + 512;
496 dev_dbg(ddata->dev, "ch%i calibration complete: %i\n",
497 channel, bank_conversion[channel].cal_offset);
498 break;
499 }
500 usleep_range(5000, 10000);
501 }
502
503 return 0;
504 }
505
cpcap_adc_calibrate(struct cpcap_adc * ddata)506 static int cpcap_adc_calibrate(struct cpcap_adc *ddata)
507 {
508 int error;
509
510 error = cpcap_adc_calibrate_one(ddata, CPCAP_ADC_CHG_ISENSE,
511 CPCAP_REG_ADCAL1,
512 ST_ADC_CAL_CHRGI_LOW_THRESHOLD,
513 ST_ADC_CAL_CHRGI_HIGH_THRESHOLD);
514 if (error)
515 return error;
516
517 error = cpcap_adc_calibrate_one(ddata, CPCAP_ADC_BATTI,
518 CPCAP_REG_ADCAL2,
519 ST_ADC_CAL_BATTI_LOW_THRESHOLD,
520 ST_ADC_CAL_BATTI_HIGH_THRESHOLD);
521 if (error)
522 return error;
523
524 return 0;
525 }
526
527 /* ADC setup, read and scale functions */
cpcap_adc_setup_bank(struct cpcap_adc * ddata,struct cpcap_adc_request * req)528 static void cpcap_adc_setup_bank(struct cpcap_adc *ddata,
529 struct cpcap_adc_request *req)
530 {
531 const struct cpcap_adc_ato *ato = ddata->ato;
532 unsigned short value1 = 0;
533 unsigned short value2 = 0;
534 int error;
535
536 if (!ato)
537 return;
538
539 switch (req->channel) {
540 case CPCAP_ADC_AD0:
541 value2 |= CPCAP_BIT_THERMBIAS_EN;
542 error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
543 CPCAP_BIT_THERMBIAS_EN,
544 value2);
545 if (error)
546 return;
547 usleep_range(800, 1000);
548 break;
549 case CPCAP_ADC_AD8 ... CPCAP_ADC_TSY2_AD15:
550 value1 |= CPCAP_BIT_AD_SEL1;
551 break;
552 case CPCAP_ADC_BATTP_PI16 ... CPCAP_ADC_BATTI_PI17:
553 value1 |= CPCAP_BIT_RAND1;
554 break;
555 default:
556 break;
557 }
558
559 switch (req->timing) {
560 case CPCAP_ADC_TIMING_IN:
561 value1 |= ato->ato_in;
562 value1 |= ato->atox_in;
563 value2 |= ato->adc_ps_factor_in;
564 value2 |= ato->atox_ps_factor_in;
565 break;
566 case CPCAP_ADC_TIMING_OUT:
567 value1 |= ato->ato_out;
568 value1 |= ato->atox_out;
569 value2 |= ato->adc_ps_factor_out;
570 value2 |= ato->atox_ps_factor_out;
571 break;
572
573 case CPCAP_ADC_TIMING_IMM:
574 default:
575 break;
576 }
577
578 error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC1,
579 CPCAP_BIT_CAL_MODE | CPCAP_BIT_ATOX |
580 CPCAP_BIT_ATO3 | CPCAP_BIT_ATO2 |
581 CPCAP_BIT_ATO1 | CPCAP_BIT_ATO0 |
582 CPCAP_BIT_ADA2 | CPCAP_BIT_ADA1 |
583 CPCAP_BIT_ADA0 | CPCAP_BIT_AD_SEL1 |
584 CPCAP_BIT_RAND1 | CPCAP_BIT_RAND0,
585 value1);
586 if (error)
587 return;
588
589 error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
590 CPCAP_BIT_ATOX_PS_FACTOR |
591 CPCAP_BIT_ADC_PS_FACTOR1 |
592 CPCAP_BIT_ADC_PS_FACTOR0 |
593 CPCAP_BIT_THERMBIAS_EN,
594 value2);
595 if (error)
596 return;
597
598 if (req->timing == CPCAP_ADC_TIMING_IMM) {
599 error = regmap_set_bits(ddata->reg, CPCAP_REG_ADCC2,
600 CPCAP_BIT_ADTRIG_DIS);
601 if (error)
602 return;
603
604 error = regmap_set_bits(ddata->reg, CPCAP_REG_ADCC2,
605 CPCAP_BIT_ASC);
606 if (error)
607 return;
608 } else {
609 error = regmap_set_bits(ddata->reg, CPCAP_REG_ADCC2,
610 CPCAP_BIT_ADTRIG_ONESHOT);
611 if (error)
612 return;
613
614 error = regmap_clear_bits(ddata->reg, CPCAP_REG_ADCC2,
615 CPCAP_BIT_ADTRIG_DIS);
616 if (error)
617 return;
618 }
619 }
620
cpcap_adc_start_bank(struct cpcap_adc * ddata,struct cpcap_adc_request * req)621 static int cpcap_adc_start_bank(struct cpcap_adc *ddata,
622 struct cpcap_adc_request *req)
623 {
624 int i, error;
625
626 req->timing = CPCAP_ADC_TIMING_IMM;
627 ddata->done = false;
628
629 for (i = 0; i < CPCAP_ADC_MAX_RETRIES; i++) {
630 cpcap_adc_setup_bank(ddata, req);
631 error = wait_event_interruptible_timeout(ddata->wq_data_avail,
632 ddata->done,
633 msecs_to_jiffies(50));
634 if (error > 0)
635 return 0;
636
637 if (error == 0) {
638 error = -ETIMEDOUT;
639 continue;
640 }
641
642 if (error < 0)
643 return error;
644 }
645
646 return error;
647 }
648
cpcap_adc_stop_bank(struct cpcap_adc * ddata)649 static int cpcap_adc_stop_bank(struct cpcap_adc *ddata)
650 {
651 int error;
652
653 error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC1,
654 0xffff,
655 CPCAP_REG_ADCC1_DEFAULTS);
656 if (error)
657 return error;
658
659 return regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
660 0xffff,
661 CPCAP_REG_ADCC2_DEFAULTS);
662 }
663
cpcap_adc_phase(struct cpcap_adc_request * req)664 static void cpcap_adc_phase(struct cpcap_adc_request *req)
665 {
666 const struct cpcap_adc_conversion_tbl *conv_tbl = req->conv_tbl;
667 const struct cpcap_adc_phasing_tbl *phase_tbl = req->phase_tbl;
668 int index = req->channel;
669
670 /* Remuxed channels 16 and 17 use BATTP and BATTI entries */
671 switch (req->channel) {
672 case CPCAP_ADC_BATTP:
673 case CPCAP_ADC_BATTP_PI16:
674 index = req->bank_index;
675 req->result -= phase_tbl[index].offset;
676 req->result -= CPCAP_FOUR_POINT_TWO_ADC;
677 req->result *= phase_tbl[index].multiplier;
678 if (phase_tbl[index].divider == 0)
679 return;
680 req->result /= phase_tbl[index].divider;
681 req->result += CPCAP_FOUR_POINT_TWO_ADC;
682 break;
683 case CPCAP_ADC_BATTI_PI17:
684 index = req->bank_index;
685 fallthrough;
686 default:
687 req->result += conv_tbl[index].cal_offset;
688 req->result += conv_tbl[index].align_offset;
689 req->result *= phase_tbl[index].multiplier;
690 if (phase_tbl[index].divider == 0)
691 return;
692 req->result /= phase_tbl[index].divider;
693 req->result += phase_tbl[index].offset;
694 break;
695 }
696
697 if (req->result < phase_tbl[index].min)
698 req->result = phase_tbl[index].min;
699 else if (req->result > phase_tbl[index].max)
700 req->result = phase_tbl[index].max;
701 }
702
703 /* Looks up temperatures in a table and calculates averages if needed */
cpcap_adc_table_to_millicelcius(unsigned short value)704 static int cpcap_adc_table_to_millicelcius(unsigned short value)
705 {
706 int i, result = 0, alpha;
707
708 if (value <= temp_map[CPCAP_MAX_TEMP_LVL - 1][0])
709 return temp_map[CPCAP_MAX_TEMP_LVL - 1][1];
710
711 if (value >= temp_map[0][0])
712 return temp_map[0][1];
713
714 for (i = 0; i < CPCAP_MAX_TEMP_LVL - 1; i++) {
715 if ((value <= temp_map[i][0]) &&
716 (value >= temp_map[i + 1][0])) {
717 if (value == temp_map[i][0]) {
718 result = temp_map[i][1];
719 } else if (value == temp_map[i + 1][0]) {
720 result = temp_map[i + 1][1];
721 } else {
722 alpha = ((value - temp_map[i][0]) * 1000) /
723 (temp_map[i + 1][0] - temp_map[i][0]);
724
725 result = temp_map[i][1] +
726 ((alpha * (temp_map[i + 1][1] -
727 temp_map[i][1])) / 1000);
728 }
729 break;
730 }
731 }
732
733 return result;
734 }
735
cpcap_adc_convert(struct cpcap_adc_request * req)736 static void cpcap_adc_convert(struct cpcap_adc_request *req)
737 {
738 const struct cpcap_adc_conversion_tbl *conv_tbl = req->conv_tbl;
739 int index = req->channel;
740
741 /* Remuxed channels 16 and 17 use BATTP and BATTI entries */
742 switch (req->channel) {
743 case CPCAP_ADC_BATTP_PI16:
744 index = CPCAP_ADC_BATTP;
745 break;
746 case CPCAP_ADC_BATTI_PI17:
747 index = CPCAP_ADC_BATTI;
748 break;
749 default:
750 break;
751 }
752
753 /* No conversion for raw channels */
754 if (conv_tbl[index].conv_type == IIO_CHAN_INFO_RAW)
755 return;
756
757 /* Temperatures use a lookup table instead of conversion table */
758 if ((req->channel == CPCAP_ADC_AD0) ||
759 (req->channel == CPCAP_ADC_AD3)) {
760 req->result =
761 cpcap_adc_table_to_millicelcius(req->result);
762
763 return;
764 }
765
766 /* All processed channels use a conversion table */
767 req->result *= conv_tbl[index].multiplier;
768 if (conv_tbl[index].divider == 0)
769 return;
770 req->result /= conv_tbl[index].divider;
771 req->result += conv_tbl[index].conv_offset;
772 }
773
774 /*
775 * REVISIT: Check if timed sampling can use multiple channels at the
776 * same time. If not, replace channel_mask with just channel.
777 */
cpcap_adc_read_bank_scaled(struct cpcap_adc * ddata,struct cpcap_adc_request * req)778 static int cpcap_adc_read_bank_scaled(struct cpcap_adc *ddata,
779 struct cpcap_adc_request *req)
780 {
781 int calibration_data, error, addr;
782
783 if (ddata->vendor == CPCAP_VENDOR_TI) {
784 error = regmap_read(ddata->reg, CPCAP_REG_ADCAL1,
785 &calibration_data);
786 if (error)
787 return error;
788 bank_conversion[CPCAP_ADC_CHG_ISENSE].cal_offset =
789 ((short)calibration_data * -1) + 512;
790
791 error = regmap_read(ddata->reg, CPCAP_REG_ADCAL2,
792 &calibration_data);
793 if (error)
794 return error;
795 bank_conversion[CPCAP_ADC_BATTI].cal_offset =
796 ((short)calibration_data * -1) + 512;
797 }
798
799 addr = CPCAP_REG_ADCD0 + req->bank_index * 4;
800
801 error = regmap_read(ddata->reg, addr, &req->result);
802 if (error)
803 return error;
804
805 req->result &= 0x3ff;
806 cpcap_adc_phase(req);
807 cpcap_adc_convert(req);
808
809 return 0;
810 }
811
cpcap_adc_init_request(struct cpcap_adc_request * req,int channel)812 static int cpcap_adc_init_request(struct cpcap_adc_request *req,
813 int channel)
814 {
815 req->channel = channel;
816 req->phase_tbl = bank_phasing;
817 req->conv_tbl = bank_conversion;
818
819 switch (channel) {
820 case CPCAP_ADC_AD0 ... CPCAP_ADC_USB_ID:
821 req->bank_index = channel;
822 break;
823 case CPCAP_ADC_AD8 ... CPCAP_ADC_TSY2_AD15:
824 req->bank_index = channel - 8;
825 break;
826 case CPCAP_ADC_BATTP_PI16:
827 req->bank_index = CPCAP_ADC_BATTP;
828 break;
829 case CPCAP_ADC_BATTI_PI17:
830 req->bank_index = CPCAP_ADC_BATTI;
831 break;
832 default:
833 return -EINVAL;
834 }
835
836 return 0;
837 }
838
cpcap_adc_read_st_die_temp(struct cpcap_adc * ddata,int addr,int * val)839 static int cpcap_adc_read_st_die_temp(struct cpcap_adc *ddata,
840 int addr, int *val)
841 {
842 int error;
843
844 error = regmap_read(ddata->reg, addr, val);
845 if (error)
846 return error;
847
848 *val -= 282;
849 *val *= 114;
850 *val += 25000;
851
852 return 0;
853 }
854
cpcap_adc_read(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)855 static int cpcap_adc_read(struct iio_dev *indio_dev,
856 struct iio_chan_spec const *chan,
857 int *val, int *val2, long mask)
858 {
859 struct cpcap_adc *ddata = iio_priv(indio_dev);
860 struct cpcap_adc_request req;
861 int error;
862
863 error = cpcap_adc_init_request(&req, chan->channel);
864 if (error)
865 return error;
866
867 switch (mask) {
868 case IIO_CHAN_INFO_RAW:
869 mutex_lock(&ddata->lock);
870 error = cpcap_adc_start_bank(ddata, &req);
871 if (error)
872 goto err_unlock;
873 error = regmap_read(ddata->reg, chan->address, val);
874 if (error)
875 goto err_unlock;
876 error = cpcap_adc_stop_bank(ddata);
877 if (error)
878 goto err_unlock;
879 mutex_unlock(&ddata->lock);
880 break;
881 case IIO_CHAN_INFO_PROCESSED:
882 mutex_lock(&ddata->lock);
883 error = cpcap_adc_start_bank(ddata, &req);
884 if (error)
885 goto err_unlock;
886 if ((ddata->vendor == CPCAP_VENDOR_ST) &&
887 (chan->channel == CPCAP_ADC_AD3)) {
888 error = cpcap_adc_read_st_die_temp(ddata,
889 chan->address,
890 &req.result);
891 if (error)
892 goto err_unlock;
893 } else {
894 error = cpcap_adc_read_bank_scaled(ddata, &req);
895 if (error)
896 goto err_unlock;
897 }
898 error = cpcap_adc_stop_bank(ddata);
899 if (error)
900 goto err_unlock;
901 mutex_unlock(&ddata->lock);
902 *val = req.result;
903 break;
904 default:
905 return -EINVAL;
906 }
907
908 return IIO_VAL_INT;
909
910 err_unlock:
911 mutex_unlock(&ddata->lock);
912 dev_err(ddata->dev, "error reading ADC: %i\n", error);
913
914 return error;
915 }
916
917 static const struct iio_info cpcap_adc_info = {
918 .read_raw = &cpcap_adc_read,
919 };
920
921 /*
922 * Configuration for Motorola mapphone series such as droid 4.
923 * Copied from the Motorola mapphone kernel tree.
924 */
925 static const struct cpcap_adc_ato mapphone_adc = {
926 .ato_in = 0x0480,
927 .atox_in = 0,
928 .adc_ps_factor_in = 0x0200,
929 .atox_ps_factor_in = 0,
930 .ato_out = 0,
931 .atox_out = 0,
932 .adc_ps_factor_out = 0,
933 .atox_ps_factor_out = 0,
934 };
935
936 static const struct cpcap_adc_ato mot_adc = {
937 .ato_in = 0x0300,
938 .atox_in = 0,
939 .adc_ps_factor_in = 0x0200,
940 .atox_ps_factor_in = 0,
941 .ato_out = 0x0780,
942 .atox_out = 0,
943 .adc_ps_factor_out = 0x0600,
944 .atox_ps_factor_out = 0,
945 };
946
947 static const struct of_device_id cpcap_adc_id_table[] = {
948 {
949 .compatible = "motorola,cpcap-adc",
950 },
951 {
952 .compatible = "motorola,mapphone-cpcap-adc",
953 .data = &mapphone_adc,
954 },
955 {
956 .compatible = "motorola,mot-cpcap-adc",
957 .data = &mot_adc,
958 },
959 { }
960 };
961 MODULE_DEVICE_TABLE(of, cpcap_adc_id_table);
962
cpcap_adc_probe(struct platform_device * pdev)963 static int cpcap_adc_probe(struct platform_device *pdev)
964 {
965 struct cpcap_adc *ddata;
966 struct iio_dev *indio_dev;
967 int error;
968
969 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*ddata));
970 if (!indio_dev)
971 return -ENOMEM;
972
973 ddata = iio_priv(indio_dev);
974 ddata->ato = device_get_match_data(&pdev->dev);
975 if (!ddata->ato)
976 return -ENODEV;
977 ddata->dev = &pdev->dev;
978
979 mutex_init(&ddata->lock);
980 init_waitqueue_head(&ddata->wq_data_avail);
981
982 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;
983 indio_dev->channels = cpcap_adc_channels;
984 indio_dev->num_channels = ARRAY_SIZE(cpcap_adc_channels);
985 indio_dev->name = dev_name(&pdev->dev);
986 indio_dev->info = &cpcap_adc_info;
987
988 ddata->reg = dev_get_regmap(pdev->dev.parent, NULL);
989 if (!ddata->reg)
990 return -ENODEV;
991
992 error = cpcap_get_vendor(ddata->dev, ddata->reg, &ddata->vendor);
993 if (error)
994 return error;
995
996 platform_set_drvdata(pdev, indio_dev);
997
998 ddata->irq = platform_get_irq_byname(pdev, "adcdone");
999 if (ddata->irq < 0)
1000 return -ENODEV;
1001
1002 error = devm_request_threaded_irq(&pdev->dev, ddata->irq, NULL,
1003 cpcap_adc_irq_thread,
1004 IRQF_TRIGGER_NONE | IRQF_ONESHOT,
1005 "cpcap-adc", indio_dev);
1006 if (error) {
1007 dev_err(&pdev->dev, "could not get irq: %i\n",
1008 error);
1009
1010 return error;
1011 }
1012
1013 error = cpcap_adc_calibrate(ddata);
1014 if (error)
1015 return error;
1016
1017 dev_info(&pdev->dev, "CPCAP ADC device probed\n");
1018
1019 return devm_iio_device_register(&pdev->dev, indio_dev);
1020 }
1021
1022 static struct platform_driver cpcap_adc_driver = {
1023 .driver = {
1024 .name = "cpcap_adc",
1025 .of_match_table = cpcap_adc_id_table,
1026 },
1027 .probe = cpcap_adc_probe,
1028 };
1029
1030 module_platform_driver(cpcap_adc_driver);
1031
1032 MODULE_ALIAS("platform:cpcap_adc");
1033 MODULE_DESCRIPTION("CPCAP ADC driver");
1034 MODULE_AUTHOR("Tony Lindgren <tony@atomide.com");
1035 MODULE_LICENSE("GPL v2");
1036