1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * drivers/net/phy/at803x.c
4 *
5 * Driver for Qualcomm Atheros AR803x PHY
6 *
7 * Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
8 */
9
10 #include <linux/phy.h>
11 #include <linux/module.h>
12 #include <linux/string.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/ethtool_netlink.h>
16 #include <linux/bitfield.h>
17 #include <linux/regulator/of_regulator.h>
18 #include <linux/regulator/driver.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/of.h>
21 #include <linux/phylink.h>
22 #include <linux/clk.h>
23 #include <linux/reset.h>
24 #include <linux/phy_port.h>
25 #include <dt-bindings/net/qca-ar803x.h>
26
27 #include "qcom.h"
28
29 #define AT803X_LED_CONTROL 0x18
30
31 #define AT803X_REG_CHIP_CONFIG 0x1f
32 #define AT803X_BT_BX_REG_SEL 0x8000
33
34 #define AT803X_MODE_CFG_MASK 0x0F
35 #define AT803X_MODE_CFG_BASET_RGMII 0x00
36 #define AT803X_MODE_CFG_BASET_SGMII 0x01
37 #define AT803X_MODE_CFG_BX1000_RGMII_50OHM 0x02
38 #define AT803X_MODE_CFG_BX1000_RGMII_75OHM 0x03
39 #define AT803X_MODE_CFG_BX1000_CONV_50OHM 0x04
40 #define AT803X_MODE_CFG_BX1000_CONV_75OHM 0x05
41 #define AT803X_MODE_CFG_FX100_RGMII_50OHM 0x06
42 #define AT803X_MODE_CFG_FX100_CONV_50OHM 0x07
43 #define AT803X_MODE_CFG_RGMII_AUTO_MDET 0x0B
44 #define AT803X_MODE_CFG_FX100_RGMII_75OHM 0x0E
45 #define AT803X_MODE_CFG_FX100_CONV_75OHM 0x0F
46
47 #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/
48 #define AT803X_PSSR_MR_AN_COMPLETE 0x0200
49
50 #define AT803X_DEBUG_REG_1F 0x1F
51 #define AT803X_DEBUG_PLL_ON BIT(2)
52 #define AT803X_DEBUG_RGMII_1V8 BIT(3)
53
54 /* AT803x supports either the XTAL input pad, an internal PLL or the
55 * DSP as clock reference for the clock output pad. The XTAL reference
56 * is only used for 25 MHz output, all other frequencies need the PLL.
57 * The DSP as a clock reference is used in synchronous ethernet
58 * applications.
59 *
60 * By default the PLL is only enabled if there is a link. Otherwise
61 * the PHY will go into low power state and disabled the PLL. You can
62 * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always
63 * enabled.
64 */
65 #define AT803X_MMD7_CLK25M 0x8016
66 #define AT803X_CLK_OUT_MASK GENMASK(4, 2)
67 #define AT803X_CLK_OUT_25MHZ_XTAL 0
68 #define AT803X_CLK_OUT_25MHZ_DSP 1
69 #define AT803X_CLK_OUT_50MHZ_PLL 2
70 #define AT803X_CLK_OUT_50MHZ_DSP 3
71 #define AT803X_CLK_OUT_62_5MHZ_PLL 4
72 #define AT803X_CLK_OUT_62_5MHZ_DSP 5
73 #define AT803X_CLK_OUT_125MHZ_PLL 6
74 #define AT803X_CLK_OUT_125MHZ_DSP 7
75
76 /* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask
77 * but doesn't support choosing between XTAL/PLL and DSP.
78 */
79 #define AT8035_CLK_OUT_MASK GENMASK(4, 3)
80
81 #define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7)
82 #define AT803X_CLK_OUT_STRENGTH_FULL 0
83 #define AT803X_CLK_OUT_STRENGTH_HALF 1
84 #define AT803X_CLK_OUT_STRENGTH_QUARTER 2
85
86 #define AT803X_MMD3_SMARTEEE_CTL1 0x805b
87 #define AT803X_MMD3_SMARTEEE_CTL2 0x805c
88 #define AT803X_MMD3_SMARTEEE_CTL3 0x805d
89 #define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN BIT(8)
90
91 #define ATH9331_PHY_ID 0x004dd041
92 #define ATH8030_PHY_ID 0x004dd076
93 #define ATH8031_PHY_ID 0x004dd074
94 #define ATH8032_PHY_ID 0x004dd023
95 #define ATH8035_PHY_ID 0x004dd072
96 #define AT8030_PHY_ID_MASK 0xffffffef
97
98 #define IPQ5018_PHY_ID 0x004dd0c0
99
100 #define QCA9561_PHY_ID 0x004dd042
101
102 #define AT803X_PAGE_FIBER 0
103 #define AT803X_PAGE_COPPER 1
104
105 /* don't turn off internal PLL */
106 #define AT803X_KEEP_PLL_ENABLED BIT(0)
107 #define AT803X_DISABLE_SMARTEEE BIT(1)
108
109 /* disable hibernation mode */
110 #define AT803X_DISABLE_HIBERNATION_MODE BIT(2)
111
112 #define IPQ5018_PHY_FIFO_CONTROL 0x19
113 #define IPQ5018_PHY_FIFO_RESET GENMASK(1, 0)
114
115 #define IPQ5018_PHY_DEBUG_EDAC 0x4380
116 #define IPQ5018_PHY_MMD1_MDAC 0x8100
117 #define IPQ5018_PHY_DAC_MASK GENMASK(15, 8)
118
119 /* MDAC and EDAC values for short cable length */
120 #define IPQ5018_PHY_DEBUG_EDAC_VAL 0x10
121 #define IPQ5018_PHY_MMD1_MDAC_VAL 0x10
122
123 #define IPQ5018_PHY_MMD1_MSE_THRESH1 0x1000
124 #define IPQ5018_PHY_MMD1_MSE_THRESH2 0x1001
125 #define IPQ5018_PHY_PCS_EEE_TX_TIMER 0x8008
126 #define IPQ5018_PHY_PCS_EEE_RX_TIMER 0x8009
127 #define IPQ5018_PHY_PCS_CDT_THRESH_CTRL3 0x8074
128 #define IPQ5018_PHY_PCS_CDT_THRESH_CTRL4 0x8075
129 #define IPQ5018_PHY_PCS_CDT_THRESH_CTRL5 0x8076
130 #define IPQ5018_PHY_PCS_CDT_THRESH_CTRL6 0x8077
131 #define IPQ5018_PHY_PCS_CDT_THRESH_CTRL7 0x8078
132 #define IPQ5018_PHY_PCS_CDT_THRESH_CTRL9 0x807a
133 #define IPQ5018_PHY_PCS_CDT_THRESH_CTRL13 0x807e
134 #define IPQ5018_PHY_PCS_CDT_THRESH_CTRL14 0x807f
135
136 #define IPQ5018_PHY_MMD1_MSE_THRESH1_VAL 0xf1
137 #define IPQ5018_PHY_MMD1_MSE_THRESH2_VAL 0x1f6
138 #define IPQ5018_PHY_PCS_EEE_TX_TIMER_VAL 0x7880
139 #define IPQ5018_PHY_PCS_EEE_RX_TIMER_VAL 0xc8
140 #define IPQ5018_PHY_PCS_CDT_THRESH_CTRL3_VAL 0xc040
141 #define IPQ5018_PHY_PCS_CDT_THRESH_CTRL4_VAL 0xa060
142 #define IPQ5018_PHY_PCS_CDT_THRESH_CTRL5_VAL 0xc040
143 #define IPQ5018_PHY_PCS_CDT_THRESH_CTRL6_VAL 0xa060
144 #define IPQ5018_PHY_PCS_CDT_THRESH_CTRL7_VAL 0xc24c
145 #define IPQ5018_PHY_PCS_CDT_THRESH_CTRL9_VAL 0xc060
146 #define IPQ5018_PHY_PCS_CDT_THRESH_CTRL13_VAL 0xb060
147 #define IPQ5018_PHY_PCS_NEAR_ECHO_THRESH_VAL 0x90b0
148
149 #define IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE 0x1
150 #define IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_MASK GENMASK(7, 4)
151 #define IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_DEFAULT 0x50
152 #define IPQ5018_PHY_DEBUG_ANA_DAC_FILTER 0xa080
153
154 MODULE_DESCRIPTION("Qualcomm Atheros AR803x PHY driver");
155 MODULE_AUTHOR("Matus Ujhelyi");
156 MODULE_LICENSE("GPL");
157
158 struct at803x_priv {
159 int flags;
160 u16 clk_25m_reg;
161 u16 clk_25m_mask;
162 u8 smarteee_lpi_tw_1g;
163 u8 smarteee_lpi_tw_100m;
164 bool is_fiber;
165 bool is_1000basex;
166 struct regulator_dev *vddio_rdev;
167 struct regulator_dev *vddh_rdev;
168 };
169
170 struct at803x_context {
171 u16 bmcr;
172 u16 advertise;
173 u16 control1000;
174 u16 int_enable;
175 u16 smart_speed;
176 u16 led_control;
177 };
178
179 struct ipq5018_priv {
180 struct reset_control *rst;
181 bool set_short_cable_dac;
182 };
183
at803x_write_page(struct phy_device * phydev,int page)184 static int at803x_write_page(struct phy_device *phydev, int page)
185 {
186 int mask;
187 int set;
188
189 if (page == AT803X_PAGE_COPPER) {
190 set = AT803X_BT_BX_REG_SEL;
191 mask = 0;
192 } else {
193 set = 0;
194 mask = AT803X_BT_BX_REG_SEL;
195 }
196
197 return __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set);
198 }
199
at803x_read_page(struct phy_device * phydev)200 static int at803x_read_page(struct phy_device *phydev)
201 {
202 int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG);
203
204 if (ccr < 0)
205 return ccr;
206
207 if (ccr & AT803X_BT_BX_REG_SEL)
208 return AT803X_PAGE_COPPER;
209
210 return AT803X_PAGE_FIBER;
211 }
212
at803x_enable_rx_delay(struct phy_device * phydev)213 static int at803x_enable_rx_delay(struct phy_device *phydev)
214 {
215 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0,
216 AT803X_DEBUG_RX_CLK_DLY_EN);
217 }
218
at803x_enable_tx_delay(struct phy_device * phydev)219 static int at803x_enable_tx_delay(struct phy_device *phydev)
220 {
221 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0,
222 AT803X_DEBUG_TX_CLK_DLY_EN);
223 }
224
at803x_disable_rx_delay(struct phy_device * phydev)225 static int at803x_disable_rx_delay(struct phy_device *phydev)
226 {
227 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
228 AT803X_DEBUG_RX_CLK_DLY_EN, 0);
229 }
230
at803x_disable_tx_delay(struct phy_device * phydev)231 static int at803x_disable_tx_delay(struct phy_device *phydev)
232 {
233 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE,
234 AT803X_DEBUG_TX_CLK_DLY_EN, 0);
235 }
236
237 /* save relevant PHY registers to private copy */
at803x_context_save(struct phy_device * phydev,struct at803x_context * context)238 static void at803x_context_save(struct phy_device *phydev,
239 struct at803x_context *context)
240 {
241 context->bmcr = phy_read(phydev, MII_BMCR);
242 context->advertise = phy_read(phydev, MII_ADVERTISE);
243 context->control1000 = phy_read(phydev, MII_CTRL1000);
244 context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE);
245 context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED);
246 context->led_control = phy_read(phydev, AT803X_LED_CONTROL);
247 }
248
249 /* restore relevant PHY registers from private copy */
at803x_context_restore(struct phy_device * phydev,const struct at803x_context * context)250 static void at803x_context_restore(struct phy_device *phydev,
251 const struct at803x_context *context)
252 {
253 phy_write(phydev, MII_BMCR, context->bmcr);
254 phy_write(phydev, MII_ADVERTISE, context->advertise);
255 phy_write(phydev, MII_CTRL1000, context->control1000);
256 phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable);
257 phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed);
258 phy_write(phydev, AT803X_LED_CONTROL, context->led_control);
259 }
260
at803x_suspend(struct phy_device * phydev)261 static int at803x_suspend(struct phy_device *phydev)
262 {
263 int value;
264 int wol_enabled;
265
266 value = phy_read(phydev, AT803X_INTR_ENABLE);
267 wol_enabled = value & AT803X_INTR_ENABLE_WOL;
268
269 if (wol_enabled)
270 value = BMCR_ISOLATE;
271 else
272 value = BMCR_PDOWN;
273
274 phy_modify(phydev, MII_BMCR, 0, value);
275
276 return 0;
277 }
278
at803x_resume(struct phy_device * phydev)279 static int at803x_resume(struct phy_device *phydev)
280 {
281 return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0);
282 }
283
at803x_parse_dt(struct phy_device * phydev)284 static int at803x_parse_dt(struct phy_device *phydev)
285 {
286 struct device_node *node = phydev->mdio.dev.of_node;
287 struct at803x_priv *priv = phydev->priv;
288 u32 freq, strength, tw;
289 unsigned int sel;
290 int ret;
291
292 if (!IS_ENABLED(CONFIG_OF_MDIO))
293 return 0;
294
295 if (of_property_read_bool(node, "qca,disable-smarteee"))
296 priv->flags |= AT803X_DISABLE_SMARTEEE;
297
298 if (of_property_read_bool(node, "qca,disable-hibernation-mode"))
299 priv->flags |= AT803X_DISABLE_HIBERNATION_MODE;
300
301 if (!of_property_read_u32(node, "qca,smarteee-tw-us-1g", &tw)) {
302 if (!tw || tw > 255) {
303 phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n");
304 return -EINVAL;
305 }
306 priv->smarteee_lpi_tw_1g = tw;
307 }
308
309 if (!of_property_read_u32(node, "qca,smarteee-tw-us-100m", &tw)) {
310 if (!tw || tw > 255) {
311 phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n");
312 return -EINVAL;
313 }
314 priv->smarteee_lpi_tw_100m = tw;
315 }
316
317 ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq);
318 if (!ret) {
319 switch (freq) {
320 case 25000000:
321 sel = AT803X_CLK_OUT_25MHZ_XTAL;
322 break;
323 case 50000000:
324 sel = AT803X_CLK_OUT_50MHZ_PLL;
325 break;
326 case 62500000:
327 sel = AT803X_CLK_OUT_62_5MHZ_PLL;
328 break;
329 case 125000000:
330 sel = AT803X_CLK_OUT_125MHZ_PLL;
331 break;
332 default:
333 phydev_err(phydev, "invalid qca,clk-out-frequency\n");
334 return -EINVAL;
335 }
336
337 priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel);
338 priv->clk_25m_mask |= AT803X_CLK_OUT_MASK;
339 }
340
341 ret = of_property_read_u32(node, "qca,clk-out-strength", &strength);
342 if (!ret) {
343 priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK;
344 switch (strength) {
345 case AR803X_STRENGTH_FULL:
346 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL;
347 break;
348 case AR803X_STRENGTH_HALF:
349 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF;
350 break;
351 case AR803X_STRENGTH_QUARTER:
352 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER;
353 break;
354 default:
355 phydev_err(phydev, "invalid qca,clk-out-strength\n");
356 return -EINVAL;
357 }
358 }
359
360 return 0;
361 }
362
at803x_probe(struct phy_device * phydev)363 static int at803x_probe(struct phy_device *phydev)
364 {
365 struct device *dev = &phydev->mdio.dev;
366 struct at803x_priv *priv;
367 int ret;
368
369 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
370 if (!priv)
371 return -ENOMEM;
372
373 phydev->priv = priv;
374
375 ret = at803x_parse_dt(phydev);
376 if (ret)
377 return ret;
378
379 return 0;
380 }
381
at803x_get_features(struct phy_device * phydev)382 static int at803x_get_features(struct phy_device *phydev)
383 {
384 struct at803x_priv *priv = phydev->priv;
385 int err;
386
387 err = genphy_read_abilities(phydev);
388 if (err)
389 return err;
390
391 if (phydev->drv->phy_id != ATH8031_PHY_ID)
392 return 0;
393
394 /* AR8031/AR8033 have different status registers
395 * for copper and fiber operation. However, the
396 * extended status register is the same for both
397 * operation modes.
398 *
399 * As a result of that, ESTATUS_1000_XFULL is set
400 * to 1 even when operating in copper TP mode.
401 *
402 * Remove this mode from the supported link modes
403 * when not operating in 1000BaseX mode.
404 */
405 if (!priv->is_1000basex)
406 linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
407 phydev->supported);
408
409 return 0;
410 }
411
at803x_smarteee_config(struct phy_device * phydev)412 static int at803x_smarteee_config(struct phy_device *phydev)
413 {
414 struct at803x_priv *priv = phydev->priv;
415 u16 mask = 0, val = 0;
416 int ret;
417
418 if (priv->flags & AT803X_DISABLE_SMARTEEE)
419 return phy_modify_mmd(phydev, MDIO_MMD_PCS,
420 AT803X_MMD3_SMARTEEE_CTL3,
421 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 0);
422
423 if (priv->smarteee_lpi_tw_1g) {
424 mask |= 0xff00;
425 val |= priv->smarteee_lpi_tw_1g << 8;
426 }
427 if (priv->smarteee_lpi_tw_100m) {
428 mask |= 0x00ff;
429 val |= priv->smarteee_lpi_tw_100m;
430 }
431 if (!mask)
432 return 0;
433
434 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1,
435 mask, val);
436 if (ret)
437 return ret;
438
439 return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3,
440 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN,
441 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN);
442 }
443
at803x_clk_out_config(struct phy_device * phydev)444 static int at803x_clk_out_config(struct phy_device *phydev)
445 {
446 struct at803x_priv *priv = phydev->priv;
447
448 if (!priv->clk_25m_mask)
449 return 0;
450
451 return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M,
452 priv->clk_25m_mask, priv->clk_25m_reg);
453 }
454
at8031_pll_config(struct phy_device * phydev)455 static int at8031_pll_config(struct phy_device *phydev)
456 {
457 struct at803x_priv *priv = phydev->priv;
458
459 /* The default after hardware reset is PLL OFF. After a soft reset, the
460 * values are retained.
461 */
462 if (priv->flags & AT803X_KEEP_PLL_ENABLED)
463 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
464 0, AT803X_DEBUG_PLL_ON);
465 else
466 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
467 AT803X_DEBUG_PLL_ON, 0);
468 }
469
at803x_hibernation_mode_config(struct phy_device * phydev)470 static int at803x_hibernation_mode_config(struct phy_device *phydev)
471 {
472 struct at803x_priv *priv = phydev->priv;
473
474 /* The default after hardware reset is hibernation mode enabled. After
475 * software reset, the value is retained.
476 */
477 if (!(priv->flags & AT803X_DISABLE_HIBERNATION_MODE) &&
478 !(phydev->dev_flags & PHY_F_RXC_ALWAYS_ON))
479 return 0;
480
481 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,
482 AT803X_DEBUG_HIB_CTRL_PS_HIB_EN, 0);
483 }
484
at803x_config_init(struct phy_device * phydev)485 static int at803x_config_init(struct phy_device *phydev)
486 {
487 int ret;
488
489 /* The RX and TX delay default is:
490 * after HW reset: RX delay enabled and TX delay disabled
491 * after SW reset: RX delay enabled, while TX delay retains the
492 * value before reset.
493 */
494 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
495 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
496 ret = at803x_enable_rx_delay(phydev);
497 else
498 ret = at803x_disable_rx_delay(phydev);
499 if (ret < 0)
500 return ret;
501
502 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
503 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
504 ret = at803x_enable_tx_delay(phydev);
505 else
506 ret = at803x_disable_tx_delay(phydev);
507 if (ret < 0)
508 return ret;
509
510 ret = at803x_smarteee_config(phydev);
511 if (ret < 0)
512 return ret;
513
514 ret = at803x_clk_out_config(phydev);
515 if (ret < 0)
516 return ret;
517
518 ret = at803x_hibernation_mode_config(phydev);
519 if (ret < 0)
520 return ret;
521
522 /* Ar803x extended next page bit is enabled by default. Cisco
523 * multigig switches read this bit and attempt to negotiate 10Gbps
524 * rates even if the next page bit is disabled. This is incorrect
525 * behaviour but we still need to accommodate it. XNP is only needed
526 * for 10Gbps support, so disable XNP.
527 */
528 return phy_modify(phydev, MII_ADVERTISE, ADVERTISE_XNP, 0);
529 }
530
at803x_link_change_notify(struct phy_device * phydev)531 static void at803x_link_change_notify(struct phy_device *phydev)
532 {
533 /*
534 * Conduct a hardware reset for AT8030 every time a link loss is
535 * signalled. This is necessary to circumvent a hardware bug that
536 * occurs when the cable is unplugged while TX packets are pending
537 * in the FIFO. In such cases, the FIFO enters an error mode it
538 * cannot recover from by software.
539 */
540 if (phydev->state == PHY_NOLINK && phy_device_has_reset(phydev)) {
541 struct at803x_context context;
542
543 at803x_context_save(phydev, &context);
544
545 phy_device_reset(phydev, 1);
546 usleep_range(1000, 2000);
547 phy_device_reset(phydev, 0);
548 usleep_range(1000, 2000);
549
550 at803x_context_restore(phydev, &context);
551
552 phydev_dbg(phydev, "%s(): phy was reset\n", __func__);
553 }
554 }
555
at803x_config_aneg(struct phy_device * phydev)556 static int at803x_config_aneg(struct phy_device *phydev)
557 {
558 struct at803x_priv *priv = phydev->priv;
559 int ret;
560
561 ret = at803x_prepare_config_aneg(phydev);
562 if (ret)
563 return ret;
564
565 if (priv->is_1000basex)
566 return genphy_c37_config_aneg(phydev);
567
568 return genphy_config_aneg(phydev);
569 }
570
at803x_cable_test_result_trans(u16 status)571 static int at803x_cable_test_result_trans(u16 status)
572 {
573 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
574 case AT803X_CDT_STATUS_STAT_NORMAL:
575 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
576 case AT803X_CDT_STATUS_STAT_SHORT:
577 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
578 case AT803X_CDT_STATUS_STAT_OPEN:
579 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
580 case AT803X_CDT_STATUS_STAT_FAIL:
581 default:
582 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
583 }
584 }
585
at803x_cdt_test_failed(u16 status)586 static bool at803x_cdt_test_failed(u16 status)
587 {
588 return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) ==
589 AT803X_CDT_STATUS_STAT_FAIL;
590 }
591
at803x_cdt_fault_length_valid(u16 status)592 static bool at803x_cdt_fault_length_valid(u16 status)
593 {
594 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
595 case AT803X_CDT_STATUS_STAT_OPEN:
596 case AT803X_CDT_STATUS_STAT_SHORT:
597 return true;
598 }
599 return false;
600 }
601
at803x_cable_test_one_pair(struct phy_device * phydev,int pair)602 static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair)
603 {
604 static const int ethtool_pair[] = {
605 ETHTOOL_A_CABLE_PAIR_A,
606 ETHTOOL_A_CABLE_PAIR_B,
607 ETHTOOL_A_CABLE_PAIR_C,
608 ETHTOOL_A_CABLE_PAIR_D,
609 };
610 int ret, val;
611
612 val = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) |
613 AT803X_CDT_ENABLE_TEST;
614 ret = at803x_cdt_start(phydev, val);
615 if (ret)
616 return ret;
617
618 ret = at803x_cdt_wait_for_completion(phydev, AT803X_CDT_ENABLE_TEST);
619 if (ret)
620 return ret;
621
622 val = phy_read(phydev, AT803X_CDT_STATUS);
623 if (val < 0)
624 return val;
625
626 if (at803x_cdt_test_failed(val))
627 return 0;
628
629 ethnl_cable_test_result(phydev, ethtool_pair[pair],
630 at803x_cable_test_result_trans(val));
631
632 if (at803x_cdt_fault_length_valid(val)) {
633 val = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, val);
634 ethnl_cable_test_fault_length(phydev, ethtool_pair[pair],
635 at803x_cdt_fault_length(val));
636 }
637
638 return 1;
639 }
640
at803x_cable_test_get_status(struct phy_device * phydev,bool * finished,unsigned long pair_mask)641 static int at803x_cable_test_get_status(struct phy_device *phydev,
642 bool *finished, unsigned long pair_mask)
643 {
644 int retries = 20;
645 int pair, ret;
646
647 *finished = false;
648
649 /* According to the datasheet the CDT can be performed when
650 * there is no link partner or when the link partner is
651 * auto-negotiating. Starting the test will restart the AN
652 * automatically. It seems that doing this repeatedly we will
653 * get a slot where our link partner won't disturb our
654 * measurement.
655 */
656 while (pair_mask && retries--) {
657 for_each_set_bit(pair, &pair_mask, 4) {
658 ret = at803x_cable_test_one_pair(phydev, pair);
659 if (ret < 0)
660 return ret;
661 if (ret)
662 clear_bit(pair, &pair_mask);
663 }
664 if (pair_mask)
665 msleep(250);
666 }
667
668 *finished = true;
669
670 return 0;
671 }
672
at803x_cable_test_autoneg(struct phy_device * phydev)673 static void at803x_cable_test_autoneg(struct phy_device *phydev)
674 {
675 /* Enable auto-negotiation, but advertise no capabilities, no link
676 * will be established. A restart of the auto-negotiation is not
677 * required, because the cable test will automatically break the link.
678 */
679 phy_write(phydev, MII_BMCR, BMCR_ANENABLE);
680 phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA);
681 }
682
at803x_cable_test_start(struct phy_device * phydev)683 static int at803x_cable_test_start(struct phy_device *phydev)
684 {
685 at803x_cable_test_autoneg(phydev);
686 /* we do all the (time consuming) work later */
687 return 0;
688 }
689
at8031_rgmii_reg_set_voltage_sel(struct regulator_dev * rdev,unsigned int selector)690 static int at8031_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev,
691 unsigned int selector)
692 {
693 struct phy_device *phydev = rdev_get_drvdata(rdev);
694
695 if (selector)
696 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
697 0, AT803X_DEBUG_RGMII_1V8);
698 else
699 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
700 AT803X_DEBUG_RGMII_1V8, 0);
701 }
702
at8031_rgmii_reg_get_voltage_sel(struct regulator_dev * rdev)703 static int at8031_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev)
704 {
705 struct phy_device *phydev = rdev_get_drvdata(rdev);
706 int val;
707
708 val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F);
709 if (val < 0)
710 return val;
711
712 return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0;
713 }
714
715 static const struct regulator_ops vddio_regulator_ops = {
716 .list_voltage = regulator_list_voltage_table,
717 .set_voltage_sel = at8031_rgmii_reg_set_voltage_sel,
718 .get_voltage_sel = at8031_rgmii_reg_get_voltage_sel,
719 };
720
721 static const unsigned int vddio_voltage_table[] = {
722 1500000,
723 1800000,
724 };
725
726 static const struct regulator_desc vddio_desc = {
727 .name = "vddio",
728 .of_match = of_match_ptr("vddio-regulator"),
729 .n_voltages = ARRAY_SIZE(vddio_voltage_table),
730 .volt_table = vddio_voltage_table,
731 .ops = &vddio_regulator_ops,
732 .type = REGULATOR_VOLTAGE,
733 .owner = THIS_MODULE,
734 };
735
736 static const struct regulator_ops vddh_regulator_ops = {
737 };
738
739 static const struct regulator_desc vddh_desc = {
740 .name = "vddh",
741 .of_match = of_match_ptr("vddh-regulator"),
742 .n_voltages = 1,
743 .fixed_uV = 2500000,
744 .ops = &vddh_regulator_ops,
745 .type = REGULATOR_VOLTAGE,
746 .owner = THIS_MODULE,
747 };
748
at8031_register_regulators(struct phy_device * phydev)749 static int at8031_register_regulators(struct phy_device *phydev)
750 {
751 struct at803x_priv *priv = phydev->priv;
752 struct device *dev = &phydev->mdio.dev;
753 struct regulator_config config = { };
754
755 config.dev = dev;
756 config.driver_data = phydev;
757
758 priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config);
759 if (IS_ERR(priv->vddio_rdev)) {
760 phydev_err(phydev, "failed to register VDDIO regulator\n");
761 return PTR_ERR(priv->vddio_rdev);
762 }
763
764 priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config);
765 if (IS_ERR(priv->vddh_rdev)) {
766 phydev_err(phydev, "failed to register VDDH regulator\n");
767 return PTR_ERR(priv->vddh_rdev);
768 }
769
770 return 0;
771 }
772
at803x_configure_mii(struct phy_port * port,bool enable,phy_interface_t interface)773 static int at803x_configure_mii(struct phy_port *port, bool enable,
774 phy_interface_t interface)
775 {
776 struct phy_device *phydev = port_phydev(port);
777
778 if (interface == PHY_INTERFACE_MODE_SGMII)
779 dev_warn(&phydev->mdio.dev,
780 "module may not function if 1000Base-X not supported\n");
781
782 return 0;
783 }
784
785 static const struct phy_port_ops at803x_port_ops = {
786 .configure_mii = at803x_configure_mii,
787 };
788
at8031_attach_mii_port(struct phy_device * phydev,struct phy_port * port)789 static int at8031_attach_mii_port(struct phy_device *phydev,
790 struct phy_port *port)
791 {
792 linkmode_zero(port->supported);
793 phylink_set(port->supported, 1000baseX_Full);
794 phylink_set(port->supported, 1000baseT_Full);
795 phylink_set(port->supported, Autoneg);
796 phylink_set(port->supported, Pause);
797 phylink_set(port->supported, Asym_Pause);
798
799 /* This device doesn't really support SGMII. However, do our best
800 * to be compatible with copper modules (that usually require SGMII),
801 * in a degraded mode as we only allow 1000BaseT Full
802 */
803 __set_bit(PHY_INTERFACE_MODE_SGMII, port->interfaces);
804 __set_bit(PHY_INTERFACE_MODE_1000BASEX, port->interfaces);
805
806 port->ops = &at803x_port_ops;
807
808 return 0;
809 }
810
at8031_parse_dt(struct phy_device * phydev)811 static int at8031_parse_dt(struct phy_device *phydev)
812 {
813 struct device_node *node = phydev->mdio.dev.of_node;
814 struct at803x_priv *priv = phydev->priv;
815 int ret;
816
817 if (of_property_read_bool(node, "qca,keep-pll-enabled"))
818 priv->flags |= AT803X_KEEP_PLL_ENABLED;
819
820 ret = at8031_register_regulators(phydev);
821 if (ret < 0)
822 return ret;
823
824 ret = devm_regulator_get_enable_optional(&phydev->mdio.dev,
825 "vddio");
826 if (ret) {
827 phydev_err(phydev, "failed to get VDDIO regulator\n");
828 return ret;
829 }
830
831 return 0;
832 }
833
at8031_probe(struct phy_device * phydev)834 static int at8031_probe(struct phy_device *phydev)
835 {
836 struct at803x_priv *priv;
837 int mode_cfg;
838 int ccr;
839 int ret;
840
841 ret = at803x_probe(phydev);
842 if (ret)
843 return ret;
844
845 priv = phydev->priv;
846
847 /* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping
848 * options.
849 */
850 ret = at8031_parse_dt(phydev);
851 if (ret)
852 return ret;
853
854 ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG);
855 if (ccr < 0)
856 return ccr;
857 mode_cfg = ccr & AT803X_MODE_CFG_MASK;
858
859 switch (mode_cfg) {
860 case AT803X_MODE_CFG_BX1000_RGMII_50OHM:
861 case AT803X_MODE_CFG_BX1000_RGMII_75OHM:
862 priv->is_1000basex = true;
863 fallthrough;
864 case AT803X_MODE_CFG_FX100_RGMII_50OHM:
865 case AT803X_MODE_CFG_FX100_RGMII_75OHM:
866 priv->is_fiber = true;
867 break;
868 }
869
870 /* Disable WoL in 1588 register which is enabled
871 * by default
872 */
873 return phy_modify_mmd(phydev, MDIO_MMD_PCS,
874 AT803X_PHY_MMD3_WOL_CTRL,
875 AT803X_WOL_EN, 0);
876 }
877
at8031_config_init(struct phy_device * phydev)878 static int at8031_config_init(struct phy_device *phydev)
879 {
880 struct at803x_priv *priv = phydev->priv;
881 int ret;
882
883 /* Some bootloaders leave the fiber page selected.
884 * Switch to the appropriate page (fiber or copper), as otherwise we
885 * read the PHY capabilities from the wrong page.
886 */
887 phy_lock_mdio_bus(phydev);
888 ret = at803x_write_page(phydev,
889 priv->is_fiber ? AT803X_PAGE_FIBER :
890 AT803X_PAGE_COPPER);
891 phy_unlock_mdio_bus(phydev);
892 if (ret)
893 return ret;
894
895 ret = at8031_pll_config(phydev);
896 if (ret < 0)
897 return ret;
898
899 return at803x_config_init(phydev);
900 }
901
at8031_config_intr(struct phy_device * phydev)902 static int at8031_config_intr(struct phy_device *phydev)
903 {
904 struct at803x_priv *priv = phydev->priv;
905 int err, value = 0;
906
907 if (phydev->interrupts == PHY_INTERRUPT_ENABLED &&
908 priv->is_fiber) {
909 /* Clear any pending interrupts */
910 err = at803x_ack_interrupt(phydev);
911 if (err)
912 return err;
913
914 value |= AT803X_INTR_ENABLE_LINK_FAIL_BX;
915 value |= AT803X_INTR_ENABLE_LINK_SUCCESS_BX;
916
917 err = phy_set_bits(phydev, AT803X_INTR_ENABLE, value);
918 if (err)
919 return err;
920 }
921
922 return at803x_config_intr(phydev);
923 }
924
925 /* AR8031 and AR8033 share the same read status logic */
at8031_read_status(struct phy_device * phydev)926 static int at8031_read_status(struct phy_device *phydev)
927 {
928 struct at803x_priv *priv = phydev->priv;
929 bool changed;
930
931 if (priv->is_1000basex)
932 return genphy_c37_read_status(phydev, &changed);
933
934 return at803x_read_status(phydev);
935 }
936
937 /* AR8031 and AR8035 share the same cable test get status reg */
at8031_cable_test_get_status(struct phy_device * phydev,bool * finished)938 static int at8031_cable_test_get_status(struct phy_device *phydev,
939 bool *finished)
940 {
941 return at803x_cable_test_get_status(phydev, finished, 0xf);
942 }
943
944 /* AR8031 and AR8035 share the same cable test start logic */
at8031_cable_test_start(struct phy_device * phydev)945 static int at8031_cable_test_start(struct phy_device *phydev)
946 {
947 at803x_cable_test_autoneg(phydev);
948 phy_write(phydev, MII_CTRL1000, 0);
949 /* we do all the (time consuming) work later */
950 return 0;
951 }
952
953 /* AR8032, AR9331 and QCA9561 share the same cable test get status reg */
at8032_cable_test_get_status(struct phy_device * phydev,bool * finished)954 static int at8032_cable_test_get_status(struct phy_device *phydev,
955 bool *finished)
956 {
957 return at803x_cable_test_get_status(phydev, finished, 0x3);
958 }
959
at8035_parse_dt(struct phy_device * phydev)960 static int at8035_parse_dt(struct phy_device *phydev)
961 {
962 struct at803x_priv *priv = phydev->priv;
963
964 /* Mask is set by the generic at803x_parse_dt
965 * if property is set. Assume property is set
966 * with the mask not zero.
967 */
968 if (priv->clk_25m_mask) {
969 /* Fixup for the AR8030/AR8035. This chip has another mask and
970 * doesn't support the DSP reference. Eg. the lowest bit of the
971 * mask. The upper two bits select the same frequencies. Mask
972 * the lowest bit here.
973 *
974 * Warning:
975 * There was no datasheet for the AR8030 available so this is
976 * just a guess. But the AR8035 is listed as pin compatible
977 * to the AR8030 so there might be a good chance it works on
978 * the AR8030 too.
979 */
980 priv->clk_25m_reg &= AT8035_CLK_OUT_MASK;
981 priv->clk_25m_mask &= AT8035_CLK_OUT_MASK;
982 }
983
984 return 0;
985 }
986
987 /* AR8030 and AR8035 shared the same special mask for clk_25m */
at8035_probe(struct phy_device * phydev)988 static int at8035_probe(struct phy_device *phydev)
989 {
990 int ret;
991
992 ret = at803x_probe(phydev);
993 if (ret)
994 return ret;
995
996 return at8035_parse_dt(phydev);
997 }
998
ipq5018_cable_test_start(struct phy_device * phydev)999 static int ipq5018_cable_test_start(struct phy_device *phydev)
1000 {
1001 phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL3,
1002 IPQ5018_PHY_PCS_CDT_THRESH_CTRL3_VAL);
1003 phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL4,
1004 IPQ5018_PHY_PCS_CDT_THRESH_CTRL4_VAL);
1005 phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL5,
1006 IPQ5018_PHY_PCS_CDT_THRESH_CTRL5_VAL);
1007 phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL6,
1008 IPQ5018_PHY_PCS_CDT_THRESH_CTRL6_VAL);
1009 phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL7,
1010 IPQ5018_PHY_PCS_CDT_THRESH_CTRL7_VAL);
1011 phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL9,
1012 IPQ5018_PHY_PCS_CDT_THRESH_CTRL9_VAL);
1013 phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL13,
1014 IPQ5018_PHY_PCS_CDT_THRESH_CTRL13_VAL);
1015 phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL3,
1016 IPQ5018_PHY_PCS_NEAR_ECHO_THRESH_VAL);
1017
1018 /* we do all the (time consuming) work later */
1019 return 0;
1020 }
1021
ipq5018_config_init(struct phy_device * phydev)1022 static int ipq5018_config_init(struct phy_device *phydev)
1023 {
1024 struct ipq5018_priv *priv = phydev->priv;
1025 u16 val;
1026
1027 /*
1028 * set LDO efuse: first temporarily store ANA_DAC_FILTER value from
1029 * debug register as it will be reset once the ANA_LDO_EFUSE register
1030 * is written to
1031 */
1032 val = at803x_debug_reg_read(phydev, IPQ5018_PHY_DEBUG_ANA_DAC_FILTER);
1033 at803x_debug_reg_mask(phydev, IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE,
1034 IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_MASK,
1035 IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_DEFAULT);
1036 at803x_debug_reg_write(phydev, IPQ5018_PHY_DEBUG_ANA_DAC_FILTER, val);
1037
1038 /* set 8023AZ EEE TX and RX timer values */
1039 phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_EEE_TX_TIMER,
1040 IPQ5018_PHY_PCS_EEE_TX_TIMER_VAL);
1041 phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_EEE_RX_TIMER,
1042 IPQ5018_PHY_PCS_EEE_RX_TIMER_VAL);
1043
1044 /* set MSE threshold values */
1045 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, IPQ5018_PHY_MMD1_MSE_THRESH1,
1046 IPQ5018_PHY_MMD1_MSE_THRESH1_VAL);
1047 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, IPQ5018_PHY_MMD1_MSE_THRESH2,
1048 IPQ5018_PHY_MMD1_MSE_THRESH2_VAL);
1049
1050 /* PHY DAC values are optional and only set in a PHY to PHY link architecture */
1051 if (priv->set_short_cable_dac) {
1052 /* setting MDAC (Multi-level Digital-to-Analog Converter) in MMD1 */
1053 phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, IPQ5018_PHY_MMD1_MDAC,
1054 IPQ5018_PHY_DAC_MASK, IPQ5018_PHY_MMD1_MDAC_VAL);
1055
1056 /* setting EDAC (Error-detection and Correction) in debug register */
1057 at803x_debug_reg_mask(phydev, IPQ5018_PHY_DEBUG_EDAC,
1058 IPQ5018_PHY_DAC_MASK, IPQ5018_PHY_DEBUG_EDAC_VAL);
1059 }
1060
1061 return 0;
1062 }
1063
ipq5018_link_change_notify(struct phy_device * phydev)1064 static void ipq5018_link_change_notify(struct phy_device *phydev)
1065 {
1066 /*
1067 * Reset the FIFO buffer upon link disconnects to clear any residual data
1068 * which may cause issues with the FIFO which it cannot recover from.
1069 */
1070 mdiobus_modify_changed(phydev->mdio.bus, phydev->mdio.addr,
1071 IPQ5018_PHY_FIFO_CONTROL, IPQ5018_PHY_FIFO_RESET,
1072 phydev->link ? IPQ5018_PHY_FIFO_RESET : 0);
1073 }
1074
ipq5018_probe(struct phy_device * phydev)1075 static int ipq5018_probe(struct phy_device *phydev)
1076 {
1077 struct device *dev = &phydev->mdio.dev;
1078 struct clk *rx_clk, *tx_clk;
1079 struct ipq5018_priv *priv;
1080 int ret;
1081
1082 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1083 if (!priv)
1084 return -ENOMEM;
1085
1086 priv->set_short_cable_dac = of_property_read_bool(dev->of_node,
1087 "qcom,dac-preset-short-cable");
1088
1089 rx_clk = devm_clk_get_enabled(dev, "rx");
1090 if (IS_ERR(rx_clk))
1091 return dev_err_probe(dev, PTR_ERR(rx_clk),
1092 "failed to get and enable RX clock\n");
1093
1094 tx_clk = devm_clk_get_enabled(dev, "tx");
1095 if (IS_ERR(tx_clk))
1096 return dev_err_probe(dev, PTR_ERR(tx_clk),
1097 "failed to get and enable TX clock\n");
1098
1099 priv->rst = devm_reset_control_array_get_exclusive(dev);
1100 if (IS_ERR(priv->rst))
1101 return dev_err_probe(dev, PTR_ERR(priv->rst),
1102 "failed to acquire reset\n");
1103
1104 ret = reset_control_reset(priv->rst);
1105 if (ret)
1106 return dev_err_probe(dev, ret, "failed to reset\n");
1107
1108 phydev->priv = priv;
1109
1110 return 0;
1111 }
1112
1113 static struct phy_driver at803x_driver[] = {
1114 {
1115 /* Qualcomm Atheros AR8035 */
1116 PHY_ID_MATCH_EXACT(ATH8035_PHY_ID),
1117 .name = "Qualcomm Atheros AR8035",
1118 .flags = PHY_POLL_CABLE_TEST,
1119 .probe = at8035_probe,
1120 .config_aneg = at803x_config_aneg,
1121 .config_init = at803x_config_init,
1122 .soft_reset = genphy_soft_reset,
1123 .set_wol = at803x_set_wol,
1124 .get_wol = at803x_get_wol,
1125 .suspend = at803x_suspend,
1126 .resume = at803x_resume,
1127 /* PHY_GBIT_FEATURES */
1128 .read_status = at803x_read_status,
1129 .config_intr = at803x_config_intr,
1130 .handle_interrupt = at803x_handle_interrupt,
1131 .get_tunable = at803x_get_tunable,
1132 .set_tunable = at803x_set_tunable,
1133 .cable_test_start = at8031_cable_test_start,
1134 .cable_test_get_status = at8031_cable_test_get_status,
1135 }, {
1136 /* Qualcomm Atheros AR8030 */
1137 .phy_id = ATH8030_PHY_ID,
1138 .name = "Qualcomm Atheros AR8030",
1139 .phy_id_mask = AT8030_PHY_ID_MASK,
1140 .probe = at8035_probe,
1141 .config_init = at803x_config_init,
1142 .link_change_notify = at803x_link_change_notify,
1143 .set_wol = at803x_set_wol,
1144 .get_wol = at803x_get_wol,
1145 .suspend = at803x_suspend,
1146 .resume = at803x_resume,
1147 /* PHY_BASIC_FEATURES */
1148 .config_intr = at803x_config_intr,
1149 .handle_interrupt = at803x_handle_interrupt,
1150 }, {
1151 /* Qualcomm Atheros AR8031/AR8033 */
1152 PHY_ID_MATCH_EXACT(ATH8031_PHY_ID),
1153 .name = "Qualcomm Atheros AR8031/AR8033",
1154 .flags = PHY_POLL_CABLE_TEST,
1155 .probe = at8031_probe,
1156 .config_init = at8031_config_init,
1157 .config_aneg = at803x_config_aneg,
1158 .soft_reset = genphy_soft_reset,
1159 .set_wol = at8031_set_wol,
1160 .get_wol = at803x_get_wol,
1161 .suspend = at803x_suspend,
1162 .resume = at803x_resume,
1163 .read_page = at803x_read_page,
1164 .write_page = at803x_write_page,
1165 .get_features = at803x_get_features,
1166 .read_status = at8031_read_status,
1167 .config_intr = at8031_config_intr,
1168 .handle_interrupt = at803x_handle_interrupt,
1169 .get_tunable = at803x_get_tunable,
1170 .set_tunable = at803x_set_tunable,
1171 .cable_test_start = at8031_cable_test_start,
1172 .cable_test_get_status = at8031_cable_test_get_status,
1173 .attach_mii_port = at8031_attach_mii_port,
1174 }, {
1175 /* Qualcomm Atheros AR8032 */
1176 PHY_ID_MATCH_EXACT(ATH8032_PHY_ID),
1177 .name = "Qualcomm Atheros AR8032",
1178 .probe = at803x_probe,
1179 .flags = PHY_POLL_CABLE_TEST,
1180 .config_init = at803x_config_init,
1181 .link_change_notify = at803x_link_change_notify,
1182 .suspend = at803x_suspend,
1183 .resume = at803x_resume,
1184 /* PHY_BASIC_FEATURES */
1185 .config_intr = at803x_config_intr,
1186 .handle_interrupt = at803x_handle_interrupt,
1187 .cable_test_start = at803x_cable_test_start,
1188 .cable_test_get_status = at8032_cable_test_get_status,
1189 }, {
1190 /* ATHEROS AR9331 */
1191 PHY_ID_MATCH_EXACT(ATH9331_PHY_ID),
1192 .name = "Qualcomm Atheros AR9331 built-in PHY",
1193 .probe = at803x_probe,
1194 .suspend = at803x_suspend,
1195 .resume = at803x_resume,
1196 .flags = PHY_POLL_CABLE_TEST,
1197 /* PHY_BASIC_FEATURES */
1198 .config_intr = at803x_config_intr,
1199 .handle_interrupt = at803x_handle_interrupt,
1200 .cable_test_start = at803x_cable_test_start,
1201 .cable_test_get_status = at8032_cable_test_get_status,
1202 .read_status = at803x_read_status,
1203 .soft_reset = genphy_soft_reset,
1204 .config_aneg = at803x_config_aneg,
1205 }, {
1206 PHY_ID_MATCH_EXACT(IPQ5018_PHY_ID),
1207 .name = "Qualcomm Atheros IPQ5018 internal PHY",
1208 .flags = PHY_IS_INTERNAL | PHY_POLL_CABLE_TEST,
1209 .probe = ipq5018_probe,
1210 .config_init = ipq5018_config_init,
1211 .link_change_notify = ipq5018_link_change_notify,
1212 .read_status = at803x_read_status,
1213 .config_intr = at803x_config_intr,
1214 .handle_interrupt = at803x_handle_interrupt,
1215 .cable_test_start = ipq5018_cable_test_start,
1216 .cable_test_get_status = qca808x_cable_test_get_status,
1217 .soft_reset = genphy_soft_reset,
1218 }, {
1219 /* Qualcomm Atheros QCA9561 */
1220 PHY_ID_MATCH_EXACT(QCA9561_PHY_ID),
1221 .name = "Qualcomm Atheros QCA9561 built-in PHY",
1222 .probe = at803x_probe,
1223 .suspend = at803x_suspend,
1224 .resume = at803x_resume,
1225 .flags = PHY_POLL_CABLE_TEST,
1226 /* PHY_BASIC_FEATURES */
1227 .config_intr = at803x_config_intr,
1228 .handle_interrupt = at803x_handle_interrupt,
1229 .cable_test_start = at803x_cable_test_start,
1230 .cable_test_get_status = at8032_cable_test_get_status,
1231 .read_status = at803x_read_status,
1232 .soft_reset = genphy_soft_reset,
1233 .config_aneg = at803x_config_aneg,
1234 }, };
1235
1236 module_phy_driver(at803x_driver);
1237
1238 static const struct mdio_device_id __maybe_unused atheros_tbl[] = {
1239 { ATH8030_PHY_ID, AT8030_PHY_ID_MASK },
1240 { PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) },
1241 { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) },
1242 { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) },
1243 { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) },
1244 { PHY_ID_MATCH_EXACT(IPQ5018_PHY_ID) },
1245 { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) },
1246 { }
1247 };
1248
1249 MODULE_DEVICE_TABLE(mdio, atheros_tbl);
1250