1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2020 HiSilicon Limited. */
3
4 #include <linux/gpio/driver.h>
5 #include <linux/gpio/generic.h>
6 #include <linux/module.h>
7 #include <linux/platform_device.h>
8 #include <linux/property.h>
9
10 #define HISI_GPIO_SWPORT_DR_SET_WX 0x000
11 #define HISI_GPIO_SWPORT_DR_CLR_WX 0x004
12 #define HISI_GPIO_SWPORT_DDR_SET_WX 0x010
13 #define HISI_GPIO_SWPORT_DDR_CLR_WX 0x014
14 #define HISI_GPIO_SWPORT_DDR_ST_WX 0x018
15 #define HISI_GPIO_INTEN_SET_WX 0x020
16 #define HISI_GPIO_INTEN_CLR_WX 0x024
17 #define HISI_GPIO_INTMASK_SET_WX 0x030
18 #define HISI_GPIO_INTMASK_CLR_WX 0x034
19 #define HISI_GPIO_INTTYPE_EDGE_SET_WX 0x040
20 #define HISI_GPIO_INTTYPE_EDGE_CLR_WX 0x044
21 #define HISI_GPIO_INT_POLARITY_SET_WX 0x050
22 #define HISI_GPIO_INT_POLARITY_CLR_WX 0x054
23 #define HISI_GPIO_DEBOUNCE_SET_WX 0x060
24 #define HISI_GPIO_DEBOUNCE_CLR_WX 0x064
25 #define HISI_GPIO_INTSTATUS_WX 0x070
26 #define HISI_GPIO_PORTA_EOI_WX 0x078
27 #define HISI_GPIO_EXT_PORT_WX 0x080
28 #define HISI_GPIO_INTCOMB_MASK_WX 0x0a0
29 #define HISI_GPIO_INT_DEDGE_SET 0x0b0
30 #define HISI_GPIO_INT_DEDGE_CLR 0x0b4
31 #define HISI_GPIO_INT_DEDGE_ST 0x0b8
32
33 #define HISI_GPIO_LINE_NUM_MAX 32
34 #define HISI_GPIO_DRIVER_NAME "gpio-hisi"
35
36 struct hisi_gpio {
37 struct gpio_generic_chip chip;
38 struct device *dev;
39 void __iomem *reg_base;
40 unsigned int line_num;
41 int irq;
42 };
43
hisi_gpio_read_reg(struct gpio_chip * chip,unsigned int off)44 static inline u32 hisi_gpio_read_reg(struct gpio_chip *chip,
45 unsigned int off)
46 {
47 struct hisi_gpio *hisi_gpio = container_of(to_gpio_generic_chip(chip),
48 struct hisi_gpio, chip);
49 void __iomem *reg = hisi_gpio->reg_base + off;
50
51 return readl(reg);
52 }
53
hisi_gpio_write_reg(struct gpio_chip * chip,unsigned int off,u32 val)54 static inline void hisi_gpio_write_reg(struct gpio_chip *chip,
55 unsigned int off, u32 val)
56 {
57 struct hisi_gpio *hisi_gpio = container_of(to_gpio_generic_chip(chip),
58 struct hisi_gpio, chip);
59 void __iomem *reg = hisi_gpio->reg_base + off;
60
61 writel(val, reg);
62 }
63
hisi_gpio_set_debounce(struct gpio_chip * chip,unsigned int off,u32 debounce)64 static void hisi_gpio_set_debounce(struct gpio_chip *chip, unsigned int off,
65 u32 debounce)
66 {
67 if (debounce)
68 hisi_gpio_write_reg(chip, HISI_GPIO_DEBOUNCE_SET_WX, BIT(off));
69 else
70 hisi_gpio_write_reg(chip, HISI_GPIO_DEBOUNCE_CLR_WX, BIT(off));
71 }
72
hisi_gpio_set_config(struct gpio_chip * chip,unsigned int offset,unsigned long config)73 static int hisi_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
74 unsigned long config)
75 {
76 u32 config_para = pinconf_to_config_param(config);
77 u32 config_arg;
78
79 switch (config_para) {
80 case PIN_CONFIG_INPUT_DEBOUNCE:
81 config_arg = pinconf_to_config_argument(config);
82 hisi_gpio_set_debounce(chip, offset, config_arg);
83 break;
84 default:
85 return -ENOTSUPP;
86 }
87
88 return 0;
89 }
90
hisi_gpio_set_ack(struct irq_data * d)91 static void hisi_gpio_set_ack(struct irq_data *d)
92 {
93 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
94
95 hisi_gpio_write_reg(chip, HISI_GPIO_PORTA_EOI_WX, BIT(irqd_to_hwirq(d)));
96 }
97
hisi_gpio_irq_set_mask(struct irq_data * d)98 static void hisi_gpio_irq_set_mask(struct irq_data *d)
99 {
100 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
101
102 hisi_gpio_write_reg(chip, HISI_GPIO_INTMASK_SET_WX, BIT(irqd_to_hwirq(d)));
103 gpiochip_disable_irq(chip, irqd_to_hwirq(d));
104 }
105
hisi_gpio_irq_clr_mask(struct irq_data * d)106 static void hisi_gpio_irq_clr_mask(struct irq_data *d)
107 {
108 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
109
110 gpiochip_enable_irq(chip, irqd_to_hwirq(d));
111 hisi_gpio_write_reg(chip, HISI_GPIO_INTMASK_CLR_WX, BIT(irqd_to_hwirq(d)));
112 }
113
hisi_gpio_irq_set_type(struct irq_data * d,u32 type)114 static int hisi_gpio_irq_set_type(struct irq_data *d, u32 type)
115 {
116 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
117 unsigned int mask = BIT(irqd_to_hwirq(d));
118
119 switch (type) {
120 case IRQ_TYPE_EDGE_BOTH:
121 hisi_gpio_write_reg(chip, HISI_GPIO_INT_DEDGE_SET, mask);
122 break;
123 case IRQ_TYPE_EDGE_RISING:
124 hisi_gpio_write_reg(chip, HISI_GPIO_INTTYPE_EDGE_SET_WX, mask);
125 hisi_gpio_write_reg(chip, HISI_GPIO_INT_POLARITY_SET_WX, mask);
126 break;
127 case IRQ_TYPE_EDGE_FALLING:
128 hisi_gpio_write_reg(chip, HISI_GPIO_INTTYPE_EDGE_SET_WX, mask);
129 hisi_gpio_write_reg(chip, HISI_GPIO_INT_POLARITY_CLR_WX, mask);
130 break;
131 case IRQ_TYPE_LEVEL_HIGH:
132 hisi_gpio_write_reg(chip, HISI_GPIO_INTTYPE_EDGE_CLR_WX, mask);
133 hisi_gpio_write_reg(chip, HISI_GPIO_INT_POLARITY_SET_WX, mask);
134 break;
135 case IRQ_TYPE_LEVEL_LOW:
136 hisi_gpio_write_reg(chip, HISI_GPIO_INTTYPE_EDGE_CLR_WX, mask);
137 hisi_gpio_write_reg(chip, HISI_GPIO_INT_POLARITY_CLR_WX, mask);
138 break;
139 default:
140 return -EINVAL;
141 }
142
143 /*
144 * The dual-edge interrupt and other interrupt's registers do not
145 * take effect at the same time. The registers of the two-edge
146 * interrupts have higher priorities, the configuration of
147 * the dual-edge interrupts must be disabled before the configuration
148 * of other kind of interrupts.
149 */
150 if (type != IRQ_TYPE_EDGE_BOTH) {
151 unsigned int both = hisi_gpio_read_reg(chip, HISI_GPIO_INT_DEDGE_ST);
152
153 if (both & mask)
154 hisi_gpio_write_reg(chip, HISI_GPIO_INT_DEDGE_CLR, mask);
155 }
156
157 if (type & IRQ_TYPE_LEVEL_MASK)
158 irq_set_handler_locked(d, handle_level_irq);
159 else if (type & IRQ_TYPE_EDGE_BOTH)
160 irq_set_handler_locked(d, handle_edge_irq);
161
162 return 0;
163 }
164
hisi_gpio_irq_enable(struct irq_data * d)165 static void hisi_gpio_irq_enable(struct irq_data *d)
166 {
167 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
168
169 hisi_gpio_irq_clr_mask(d);
170 hisi_gpio_write_reg(chip, HISI_GPIO_INTEN_SET_WX, BIT(irqd_to_hwirq(d)));
171 }
172
hisi_gpio_irq_disable(struct irq_data * d)173 static void hisi_gpio_irq_disable(struct irq_data *d)
174 {
175 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
176
177 hisi_gpio_irq_set_mask(d);
178 hisi_gpio_write_reg(chip, HISI_GPIO_INTEN_CLR_WX, BIT(irqd_to_hwirq(d)));
179 }
180
hisi_gpio_irq_handler(struct irq_desc * desc)181 static void hisi_gpio_irq_handler(struct irq_desc *desc)
182 {
183 struct hisi_gpio *hisi_gpio = irq_desc_get_handler_data(desc);
184 unsigned long irq_msk = hisi_gpio_read_reg(&hisi_gpio->chip.gc,
185 HISI_GPIO_INTSTATUS_WX);
186 struct irq_chip *irq_c = irq_desc_get_chip(desc);
187 int hwirq;
188
189 chained_irq_enter(irq_c, desc);
190 for_each_set_bit(hwirq, &irq_msk, HISI_GPIO_LINE_NUM_MAX)
191 generic_handle_domain_irq(hisi_gpio->chip.gc.irq.domain,
192 hwirq);
193 chained_irq_exit(irq_c, desc);
194 }
195
196 static const struct irq_chip hisi_gpio_irq_chip = {
197 .name = "HISI-GPIO",
198 .irq_ack = hisi_gpio_set_ack,
199 .irq_mask = hisi_gpio_irq_set_mask,
200 .irq_unmask = hisi_gpio_irq_clr_mask,
201 .irq_set_type = hisi_gpio_irq_set_type,
202 .irq_enable = hisi_gpio_irq_enable,
203 .irq_disable = hisi_gpio_irq_disable,
204 .flags = IRQCHIP_IMMUTABLE,
205 GPIOCHIP_IRQ_RESOURCE_HELPERS,
206 };
207
hisi_gpio_init_irq(struct hisi_gpio * hisi_gpio)208 static void hisi_gpio_init_irq(struct hisi_gpio *hisi_gpio)
209 {
210 struct gpio_chip *chip = &hisi_gpio->chip.gc;
211 struct gpio_irq_chip *girq_chip = &chip->irq;
212
213 gpio_irq_chip_set_chip(girq_chip, &hisi_gpio_irq_chip);
214 girq_chip->default_type = IRQ_TYPE_NONE;
215 girq_chip->num_parents = 1;
216 girq_chip->parents = &hisi_gpio->irq;
217 girq_chip->parent_handler = hisi_gpio_irq_handler;
218 girq_chip->parent_handler_data = hisi_gpio;
219
220 /* Clear Mask of GPIO controller combine IRQ */
221 hisi_gpio_write_reg(chip, HISI_GPIO_INTCOMB_MASK_WX, 1);
222 }
223
224 static const struct acpi_device_id hisi_gpio_acpi_match[] = {
225 {"HISI0184", 0},
226 {}
227 };
228 MODULE_DEVICE_TABLE(acpi, hisi_gpio_acpi_match);
229
230 static const struct of_device_id hisi_gpio_dts_match[] = {
231 { .compatible = "hisilicon,ascend910-gpio", },
232 { }
233 };
234 MODULE_DEVICE_TABLE(of, hisi_gpio_dts_match);
235
hisi_gpio_get_pdata(struct device * dev,struct hisi_gpio * hisi_gpio)236 static void hisi_gpio_get_pdata(struct device *dev,
237 struct hisi_gpio *hisi_gpio)
238 {
239 struct platform_device *pdev = to_platform_device(dev);
240 struct fwnode_handle *fwnode;
241 int idx = 0;
242
243 device_for_each_child_node(dev, fwnode) {
244 /* Cycle for once, no need for an array to save line_num */
245 if (fwnode_property_read_u32(fwnode, "ngpios",
246 &hisi_gpio->line_num)) {
247 dev_err(dev,
248 "failed to get number of lines for port%d and use default value instead\n",
249 idx);
250 hisi_gpio->line_num = HISI_GPIO_LINE_NUM_MAX;
251 }
252
253 if (WARN_ON(hisi_gpio->line_num > HISI_GPIO_LINE_NUM_MAX))
254 hisi_gpio->line_num = HISI_GPIO_LINE_NUM_MAX;
255
256 hisi_gpio->irq = platform_get_irq(pdev, idx);
257
258 dev_info(dev,
259 "get hisi_gpio[%d] with %u lines\n", idx,
260 hisi_gpio->line_num);
261
262 idx++;
263 }
264 }
265
hisi_gpio_probe(struct platform_device * pdev)266 static int hisi_gpio_probe(struct platform_device *pdev)
267 {
268 struct gpio_generic_chip_config config;
269 struct device *dev = &pdev->dev;
270 struct hisi_gpio *hisi_gpio;
271 int port_num;
272 int ret;
273
274 /*
275 * One GPIO controller own one port currently,
276 * if we get more from ACPI table, return error.
277 */
278 port_num = device_get_child_node_count(dev);
279 if (WARN_ON(port_num != 1))
280 return -ENODEV;
281
282 hisi_gpio = devm_kzalloc(dev, sizeof(*hisi_gpio), GFP_KERNEL);
283 if (!hisi_gpio)
284 return -ENOMEM;
285
286 hisi_gpio->reg_base = devm_platform_ioremap_resource(pdev, 0);
287 if (IS_ERR(hisi_gpio->reg_base))
288 return PTR_ERR(hisi_gpio->reg_base);
289
290 hisi_gpio_get_pdata(dev, hisi_gpio);
291
292 hisi_gpio->dev = dev;
293
294 config = (struct gpio_generic_chip_config) {
295 .dev = hisi_gpio->dev,
296 .sz = 4,
297 .dat = hisi_gpio->reg_base + HISI_GPIO_EXT_PORT_WX,
298 .set = hisi_gpio->reg_base + HISI_GPIO_SWPORT_DR_SET_WX,
299 .clr = hisi_gpio->reg_base + HISI_GPIO_SWPORT_DR_CLR_WX,
300 .dirout = hisi_gpio->reg_base + HISI_GPIO_SWPORT_DDR_SET_WX,
301 .dirin = hisi_gpio->reg_base + HISI_GPIO_SWPORT_DDR_CLR_WX,
302 .flags = GPIO_GENERIC_NO_SET_ON_INPUT |
303 GPIO_GENERIC_UNREADABLE_REG_DIR,
304 };
305
306 ret = gpio_generic_chip_init(&hisi_gpio->chip, &config);
307 if (ret) {
308 dev_err(dev, "failed to init, ret = %d\n", ret);
309 return ret;
310 }
311
312 hisi_gpio->chip.gc.set_config = hisi_gpio_set_config;
313 hisi_gpio->chip.gc.ngpio = hisi_gpio->line_num;
314 hisi_gpio->chip.gc.base = -1;
315
316 if (hisi_gpio->irq > 0)
317 hisi_gpio_init_irq(hisi_gpio);
318
319 ret = devm_gpiochip_add_data(dev, &hisi_gpio->chip.gc, hisi_gpio);
320 if (ret) {
321 dev_err(dev, "failed to register gpiochip, ret = %d\n", ret);
322 return ret;
323 }
324
325 return 0;
326 }
327
328 static struct platform_driver hisi_gpio_driver = {
329 .driver = {
330 .name = HISI_GPIO_DRIVER_NAME,
331 .acpi_match_table = hisi_gpio_acpi_match,
332 .of_match_table = hisi_gpio_dts_match,
333 },
334 .probe = hisi_gpio_probe,
335 };
336
337 module_platform_driver(hisi_gpio_driver);
338
339 MODULE_LICENSE("GPL");
340 MODULE_AUTHOR("Luo Jiaxing <luojiaxing@huawei.com>");
341 MODULE_DESCRIPTION("HiSilicon GPIO controller driver");
342 MODULE_ALIAS("platform:" HISI_GPIO_DRIVER_NAME);
343