1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) ST-Ericsson SA 2012
4 *
5 * Author: Ola Lilja <ola.o.lilja@stericsson.com>,
6 * Kristoffer Karlsson <kristoffer.karlsson@stericsson.com>,
7 * Roger Nilsson <roger.xr.nilsson@stericsson.com>,
8 * for ST-Ericsson.
9 *
10 * Based on the early work done by:
11 * Mikko J. Lehto <mikko.lehto@symbio.com>,
12 * Mikko Sarmanne <mikko.sarmanne@symbio.com>,
13 * Jarmo K. Kuronen <jarmo.kuronen@symbio.com>,
14 * for ST-Ericsson.
15 */
16
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/device.h>
20 #include <linux/slab.h>
21 #include <linux/moduleparam.h>
22 #include <linux/init.h>
23 #include <linux/pm.h>
24 #include <linux/platform_device.h>
25 #include <linux/mfd/abx500/ab8500.h>
26 #include <linux/mfd/abx500.h>
27 #include <linux/mfd/abx500/ab8500-sysctrl.h>
28 #include <linux/mfd/abx500/ab8500-codec.h>
29 #include <linux/regulator/consumer.h>
30 #include <linux/of.h>
31
32 #include <sound/core.h>
33 #include <sound/pcm.h>
34 #include <sound/pcm_params.h>
35 #include <sound/initval.h>
36 #include <sound/soc.h>
37 #include <sound/soc-dapm.h>
38 #include <sound/tlv.h>
39
40 #include "ab8500-codec.h"
41
42 /* Macrocell value definitions */
43 #define CLK_32K_OUT2_DISABLE 0x01
44 #define INACTIVE_RESET_AUDIO 0x02
45 #define ENABLE_AUDIO_CLK_TO_AUDIO_BLK 0x10
46 #define ENABLE_VINTCORE12_SUPPLY 0x04
47 #define GPIO27_DIR_OUTPUT 0x04
48 #define GPIO29_DIR_OUTPUT 0x10
49 #define GPIO31_DIR_OUTPUT 0x40
50
51 /* Macrocell register definitions */
52 #define AB8500_GPIO_DIR4_REG 0x13 /* Bank AB8500_MISC */
53
54 /* Private data for AB8500 device-driver */
55 struct ab8500_codec_drvdata {
56 struct regmap *regmap;
57 };
58
amic_micbias_str(enum amic_micbias micbias)59 static inline const char *amic_micbias_str(enum amic_micbias micbias)
60 {
61 switch (micbias) {
62 case AMIC_MICBIAS_VAMIC1:
63 return "VAMIC1";
64 case AMIC_MICBIAS_VAMIC2:
65 return "VAMIC2";
66 default:
67 return "Unknown";
68 }
69 }
70
amic_type_str(enum amic_type type)71 static inline const char *amic_type_str(enum amic_type type)
72 {
73 switch (type) {
74 case AMIC_TYPE_DIFFERENTIAL:
75 return "DIFFERENTIAL";
76 case AMIC_TYPE_SINGLE_ENDED:
77 return "SINGLE ENDED";
78 default:
79 return "Unknown";
80 }
81 }
82
83 /*
84 * Read'n'write functions
85 */
86
87 /* Read a register from the audio-bank of AB8500 */
ab8500_codec_read_reg(void * context,unsigned int reg,unsigned int * value)88 static int ab8500_codec_read_reg(void *context, unsigned int reg,
89 unsigned int *value)
90 {
91 struct device *dev = context;
92 int status;
93
94 u8 value8;
95 status = abx500_get_register_interruptible(dev, AB8500_AUDIO,
96 reg, &value8);
97 *value = (unsigned int)value8;
98
99 return status;
100 }
101
102 /* Write to a register in the audio-bank of AB8500 */
ab8500_codec_write_reg(void * context,unsigned int reg,unsigned int value)103 static int ab8500_codec_write_reg(void *context, unsigned int reg,
104 unsigned int value)
105 {
106 struct device *dev = context;
107
108 return abx500_set_register_interruptible(dev, AB8500_AUDIO,
109 reg, value);
110 }
111
112 static const struct regmap_config ab8500_codec_regmap = {
113 .reg_read = ab8500_codec_read_reg,
114 .reg_write = ab8500_codec_write_reg,
115 };
116
117 /*
118 * Controls - DAPM
119 */
120
121 /* Earpiece */
122
123 /* Earpiece source selector */
124 static const char * const enum_ear_lineout_source[] = {"Headset Left",
125 "Speaker Left"};
126 static SOC_ENUM_SINGLE_DECL(dapm_enum_ear_lineout_source, AB8500_DMICFILTCONF,
127 AB8500_DMICFILTCONF_DA3TOEAR, enum_ear_lineout_source);
128 static const struct snd_kcontrol_new dapm_ear_lineout_source =
129 SOC_DAPM_ENUM("Earpiece or LineOut Mono Source",
130 dapm_enum_ear_lineout_source);
131
132 /* LineOut */
133
134 /* LineOut source selector */
135 static const char * const enum_lineout_source[] = {"Mono Path", "Stereo Path"};
136 static SOC_ENUM_DOUBLE_DECL(dapm_enum_lineout_source, AB8500_ANACONF5,
137 AB8500_ANACONF5_HSLDACTOLOL,
138 AB8500_ANACONF5_HSRDACTOLOR, enum_lineout_source);
139 static const struct snd_kcontrol_new dapm_lineout_source[] = {
140 SOC_DAPM_ENUM("LineOut Source", dapm_enum_lineout_source),
141 };
142
143 /* Handsfree */
144
145 /* Speaker Left - ANC selector */
146 static const char * const enum_HFx_sel[] = {"Audio Path", "ANC"};
147 static SOC_ENUM_SINGLE_DECL(dapm_enum_HFl_sel, AB8500_DIGMULTCONF2,
148 AB8500_DIGMULTCONF2_HFLSEL, enum_HFx_sel);
149 static const struct snd_kcontrol_new dapm_HFl_select[] = {
150 SOC_DAPM_ENUM("Speaker Left Source", dapm_enum_HFl_sel),
151 };
152
153 /* Speaker Right - ANC selector */
154 static SOC_ENUM_SINGLE_DECL(dapm_enum_HFr_sel, AB8500_DIGMULTCONF2,
155 AB8500_DIGMULTCONF2_HFRSEL, enum_HFx_sel);
156 static const struct snd_kcontrol_new dapm_HFr_select[] = {
157 SOC_DAPM_ENUM("Speaker Right Source", dapm_enum_HFr_sel),
158 };
159
160 /* Mic 1 */
161
162 /* Mic 1 - Mic 1a or 1b selector */
163 static const char * const enum_mic1ab_sel[] = {"Mic 1b", "Mic 1a"};
164 static SOC_ENUM_SINGLE_DECL(dapm_enum_mic1ab_sel, AB8500_ANACONF3,
165 AB8500_ANACONF3_MIC1SEL, enum_mic1ab_sel);
166 static const struct snd_kcontrol_new dapm_mic1ab_mux[] = {
167 SOC_DAPM_ENUM("Mic 1a or 1b Select", dapm_enum_mic1ab_sel),
168 };
169
170 /* Mic 1 - AD3 - Mic 1 or DMic 3 selector */
171 static const char * const enum_ad3_sel[] = {"Mic 1", "DMic 3"};
172 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad3_sel, AB8500_DIGMULTCONF1,
173 AB8500_DIGMULTCONF1_AD3SEL, enum_ad3_sel);
174 static const struct snd_kcontrol_new dapm_ad3_select[] = {
175 SOC_DAPM_ENUM("AD3 Source Select", dapm_enum_ad3_sel),
176 };
177
178 /* Mic 1 - AD6 - Mic 1 or DMic 6 selector */
179 static const char * const enum_ad6_sel[] = {"Mic 1", "DMic 6"};
180 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad6_sel, AB8500_DIGMULTCONF1,
181 AB8500_DIGMULTCONF1_AD6SEL, enum_ad6_sel);
182 static const struct snd_kcontrol_new dapm_ad6_select[] = {
183 SOC_DAPM_ENUM("AD6 Source Select", dapm_enum_ad6_sel),
184 };
185
186 /* Mic 2 */
187
188 /* Mic 2 - AD5 - Mic 2 or DMic 5 selector */
189 static const char * const enum_ad5_sel[] = {"Mic 2", "DMic 5"};
190 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad5_sel, AB8500_DIGMULTCONF1,
191 AB8500_DIGMULTCONF1_AD5SEL, enum_ad5_sel);
192 static const struct snd_kcontrol_new dapm_ad5_select[] = {
193 SOC_DAPM_ENUM("AD5 Source Select", dapm_enum_ad5_sel),
194 };
195
196 /* LineIn */
197
198 /* LineIn left - AD1 - LineIn Left or DMic 1 selector */
199 static const char * const enum_ad1_sel[] = {"LineIn Left", "DMic 1"};
200 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad1_sel, AB8500_DIGMULTCONF1,
201 AB8500_DIGMULTCONF1_AD1SEL, enum_ad1_sel);
202 static const struct snd_kcontrol_new dapm_ad1_select[] = {
203 SOC_DAPM_ENUM("AD1 Source Select", dapm_enum_ad1_sel),
204 };
205
206 /* LineIn right - Mic 2 or LineIn Right selector */
207 static const char * const enum_mic2lr_sel[] = {"Mic 2", "LineIn Right"};
208 static SOC_ENUM_SINGLE_DECL(dapm_enum_mic2lr_sel, AB8500_ANACONF3,
209 AB8500_ANACONF3_LINRSEL, enum_mic2lr_sel);
210 static const struct snd_kcontrol_new dapm_mic2lr_select[] = {
211 SOC_DAPM_ENUM("Mic 2 or LINR Select", dapm_enum_mic2lr_sel),
212 };
213
214 /* LineIn right - AD2 - LineIn Right or DMic2 selector */
215 static const char * const enum_ad2_sel[] = {"LineIn Right", "DMic 2"};
216 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad2_sel, AB8500_DIGMULTCONF1,
217 AB8500_DIGMULTCONF1_AD2SEL, enum_ad2_sel);
218 static const struct snd_kcontrol_new dapm_ad2_select[] = {
219 SOC_DAPM_ENUM("AD2 Source Select", dapm_enum_ad2_sel),
220 };
221
222
223 /* ANC */
224
225 static const char * const enum_anc_in_sel[] = {"Mic 1 / DMic 6",
226 "Mic 2 / DMic 5"};
227 static SOC_ENUM_SINGLE_DECL(dapm_enum_anc_in_sel, AB8500_DMICFILTCONF,
228 AB8500_DMICFILTCONF_ANCINSEL, enum_anc_in_sel);
229 static const struct snd_kcontrol_new dapm_anc_in_select[] = {
230 SOC_DAPM_ENUM("ANC Source", dapm_enum_anc_in_sel),
231 };
232
233 /* ANC - Enable/Disable */
234 static const struct snd_kcontrol_new dapm_anc_enable[] = {
235 SOC_DAPM_SINGLE("Switch", AB8500_ANCCONF1,
236 AB8500_ANCCONF1_ENANC, 1, 0),
237 };
238
239 /* ANC to Earpiece - Mute */
240 static const struct snd_kcontrol_new dapm_anc_ear_mute[] = {
241 SOC_DAPM_SINGLE("Switch", AB8500_DIGMULTCONF1,
242 AB8500_DIGMULTCONF1_ANCSEL, 1, 0),
243 };
244
245
246
247 /* Sidetone left */
248
249 /* Sidetone left - Input selector */
250 static const char * const enum_stfir1_in_sel[] = {
251 "LineIn Left", "LineIn Right", "Mic 1", "Headset Left"
252 };
253 static SOC_ENUM_SINGLE_DECL(dapm_enum_stfir1_in_sel, AB8500_DIGMULTCONF2,
254 AB8500_DIGMULTCONF2_FIRSID1SEL, enum_stfir1_in_sel);
255 static const struct snd_kcontrol_new dapm_stfir1_in_select[] = {
256 SOC_DAPM_ENUM("Sidetone Left Source", dapm_enum_stfir1_in_sel),
257 };
258
259 /* Sidetone right path */
260
261 /* Sidetone right - Input selector */
262 static const char * const enum_stfir2_in_sel[] = {
263 "LineIn Right", "Mic 1", "DMic 4", "Headset Right"
264 };
265 static SOC_ENUM_SINGLE_DECL(dapm_enum_stfir2_in_sel, AB8500_DIGMULTCONF2,
266 AB8500_DIGMULTCONF2_FIRSID2SEL, enum_stfir2_in_sel);
267 static const struct snd_kcontrol_new dapm_stfir2_in_select[] = {
268 SOC_DAPM_ENUM("Sidetone Right Source", dapm_enum_stfir2_in_sel),
269 };
270
271 /* Vibra */
272
273 static const char * const enum_pwm2vibx[] = {"Audio Path", "PWM Generator"};
274
275 static SOC_ENUM_SINGLE_DECL(dapm_enum_pwm2vib1, AB8500_PWMGENCONF1,
276 AB8500_PWMGENCONF1_PWMTOVIB1, enum_pwm2vibx);
277
278 static const struct snd_kcontrol_new dapm_pwm2vib1[] = {
279 SOC_DAPM_ENUM("Vibra 1 Controller", dapm_enum_pwm2vib1),
280 };
281
282 static SOC_ENUM_SINGLE_DECL(dapm_enum_pwm2vib2, AB8500_PWMGENCONF1,
283 AB8500_PWMGENCONF1_PWMTOVIB2, enum_pwm2vibx);
284
285 static const struct snd_kcontrol_new dapm_pwm2vib2[] = {
286 SOC_DAPM_ENUM("Vibra 2 Controller", dapm_enum_pwm2vib2),
287 };
288
289 /*
290 * DAPM-widgets
291 */
292
293 static const struct snd_soc_dapm_widget ab8500_dapm_widgets[] = {
294
295 /* Clocks */
296 SND_SOC_DAPM_CLOCK_SUPPLY("audioclk"),
297
298 /* Regulators */
299 SND_SOC_DAPM_REGULATOR_SUPPLY("V-AUD", 0, 0),
300 SND_SOC_DAPM_REGULATOR_SUPPLY("V-AMIC1", 0, 0),
301 SND_SOC_DAPM_REGULATOR_SUPPLY("V-AMIC2", 0, 0),
302 SND_SOC_DAPM_REGULATOR_SUPPLY("V-DMIC", 0, 0),
303
304 /* Power */
305 SND_SOC_DAPM_SUPPLY("Audio Power",
306 AB8500_POWERUP, AB8500_POWERUP_POWERUP, 0,
307 NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
308 SND_SOC_DAPM_SUPPLY("Audio Analog Power",
309 AB8500_POWERUP, AB8500_POWERUP_ENANA, 0,
310 NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
311
312 /* Main supply node */
313 SND_SOC_DAPM_SUPPLY("Main Supply", SND_SOC_NOPM, 0, 0,
314 NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
315
316 /* DA/AD */
317
318 SND_SOC_DAPM_AIF_IN("DA_IN1", NULL, 0, SND_SOC_NOPM, 0, 0),
319 SND_SOC_DAPM_AIF_IN("DA_IN2", NULL, 0, SND_SOC_NOPM, 0, 0),
320 SND_SOC_DAPM_AIF_IN("DA_IN3", NULL, 0, SND_SOC_NOPM, 0, 0),
321 SND_SOC_DAPM_AIF_IN("DA_IN4", NULL, 0, SND_SOC_NOPM, 0, 0),
322 SND_SOC_DAPM_AIF_IN("DA_IN5", NULL, 0, SND_SOC_NOPM, 0, 0),
323 SND_SOC_DAPM_AIF_IN("DA_IN6", NULL, 0, SND_SOC_NOPM, 0, 0),
324 SND_SOC_DAPM_AIF_OUT("AD_OUT1", NULL, 0, SND_SOC_NOPM, 0, 0),
325 SND_SOC_DAPM_AIF_OUT("AD_OUT2", NULL, 0, SND_SOC_NOPM, 0, 0),
326 SND_SOC_DAPM_AIF_OUT("AD_OUT3", NULL, 0, SND_SOC_NOPM, 0, 0),
327 SND_SOC_DAPM_AIF_OUT("AD_OUT4", NULL, 0, SND_SOC_NOPM, 0, 0),
328 SND_SOC_DAPM_AIF_OUT("AD_OUT57", NULL, 0, SND_SOC_NOPM, 0, 0),
329 SND_SOC_DAPM_AIF_OUT("AD_OUT68", NULL, 0, SND_SOC_NOPM, 0, 0),
330
331 /* Headset path */
332
333 SND_SOC_DAPM_SUPPLY("Charge Pump", AB8500_ANACONF5,
334 AB8500_ANACONF5_ENCPHS, 0, NULL, 0),
335
336 SND_SOC_DAPM_DAC("DA1 Enable", "ab8500_0p",
337 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA1, 0),
338 SND_SOC_DAPM_DAC("DA2 Enable", "ab8500_0p",
339 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA2, 0),
340
341 SND_SOC_DAPM_PGA("HSL Digital Volume", SND_SOC_NOPM, 0, 0,
342 NULL, 0),
343 SND_SOC_DAPM_PGA("HSR Digital Volume", SND_SOC_NOPM, 0, 0,
344 NULL, 0),
345
346 SND_SOC_DAPM_DAC("HSL DAC", "ab8500_0p",
347 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACHSL, 0),
348 SND_SOC_DAPM_DAC("HSR DAC", "ab8500_0p",
349 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACHSR, 0),
350 SND_SOC_DAPM_MIXER("HSL DAC Mute", AB8500_MUTECONF,
351 AB8500_MUTECONF_MUTDACHSL, 1,
352 NULL, 0),
353 SND_SOC_DAPM_MIXER("HSR DAC Mute", AB8500_MUTECONF,
354 AB8500_MUTECONF_MUTDACHSR, 1,
355 NULL, 0),
356 SND_SOC_DAPM_DAC("HSL DAC Driver", "ab8500_0p",
357 AB8500_ANACONF3, AB8500_ANACONF3_ENDRVHSL, 0),
358 SND_SOC_DAPM_DAC("HSR DAC Driver", "ab8500_0p",
359 AB8500_ANACONF3, AB8500_ANACONF3_ENDRVHSR, 0),
360
361 SND_SOC_DAPM_MIXER("HSL Mute",
362 AB8500_MUTECONF, AB8500_MUTECONF_MUTHSL, 1,
363 NULL, 0),
364 SND_SOC_DAPM_MIXER("HSR Mute",
365 AB8500_MUTECONF, AB8500_MUTECONF_MUTHSR, 1,
366 NULL, 0),
367 SND_SOC_DAPM_MIXER("HSL Enable",
368 AB8500_ANACONF4, AB8500_ANACONF4_ENHSL, 0,
369 NULL, 0),
370 SND_SOC_DAPM_MIXER("HSR Enable",
371 AB8500_ANACONF4, AB8500_ANACONF4_ENHSR, 0,
372 NULL, 0),
373 SND_SOC_DAPM_PGA("HSL Volume",
374 SND_SOC_NOPM, 0, 0,
375 NULL, 0),
376 SND_SOC_DAPM_PGA("HSR Volume",
377 SND_SOC_NOPM, 0, 0,
378 NULL, 0),
379
380 SND_SOC_DAPM_OUTPUT("Headset Left"),
381 SND_SOC_DAPM_OUTPUT("Headset Right"),
382
383 /* LineOut path */
384
385 SND_SOC_DAPM_MUX("LineOut Source",
386 SND_SOC_NOPM, 0, 0, dapm_lineout_source),
387
388 SND_SOC_DAPM_MIXER("LOL Disable HFL",
389 AB8500_ANACONF4, AB8500_ANACONF4_ENHFL, 1,
390 NULL, 0),
391 SND_SOC_DAPM_MIXER("LOR Disable HFR",
392 AB8500_ANACONF4, AB8500_ANACONF4_ENHFR, 1,
393 NULL, 0),
394
395 SND_SOC_DAPM_MIXER("LOL Enable",
396 AB8500_ANACONF5, AB8500_ANACONF5_ENLOL, 0,
397 NULL, 0),
398 SND_SOC_DAPM_MIXER("LOR Enable",
399 AB8500_ANACONF5, AB8500_ANACONF5_ENLOR, 0,
400 NULL, 0),
401
402 SND_SOC_DAPM_OUTPUT("LineOut Left"),
403 SND_SOC_DAPM_OUTPUT("LineOut Right"),
404
405 /* Earpiece path */
406
407 SND_SOC_DAPM_MUX("Earpiece or LineOut Mono Source",
408 SND_SOC_NOPM, 0, 0, &dapm_ear_lineout_source),
409 SND_SOC_DAPM_MIXER("EAR DAC",
410 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACEAR, 0,
411 NULL, 0),
412 SND_SOC_DAPM_MIXER("EAR Mute",
413 AB8500_MUTECONF, AB8500_MUTECONF_MUTEAR, 1,
414 NULL, 0),
415 SND_SOC_DAPM_MIXER("EAR Enable",
416 AB8500_ANACONF4, AB8500_ANACONF4_ENEAR, 0,
417 NULL, 0),
418
419 SND_SOC_DAPM_OUTPUT("Earpiece"),
420
421 /* Handsfree path */
422
423 SND_SOC_DAPM_MIXER("DA3 Channel Volume",
424 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA3, 0,
425 NULL, 0),
426 SND_SOC_DAPM_MIXER("DA4 Channel Volume",
427 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA4, 0,
428 NULL, 0),
429 SND_SOC_DAPM_MUX("Speaker Left Source",
430 SND_SOC_NOPM, 0, 0, dapm_HFl_select),
431 SND_SOC_DAPM_MUX("Speaker Right Source",
432 SND_SOC_NOPM, 0, 0, dapm_HFr_select),
433 SND_SOC_DAPM_MIXER("HFL DAC", AB8500_DAPATHCONF,
434 AB8500_DAPATHCONF_ENDACHFL, 0,
435 NULL, 0),
436 SND_SOC_DAPM_MIXER("HFR DAC",
437 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACHFR, 0,
438 NULL, 0),
439 SND_SOC_DAPM_MIXER("DA4 or ANC path to HfR",
440 AB8500_DIGMULTCONF2, AB8500_DIGMULTCONF2_DATOHFREN, 0,
441 NULL, 0),
442 SND_SOC_DAPM_MIXER("DA3 or ANC path to HfL",
443 AB8500_DIGMULTCONF2, AB8500_DIGMULTCONF2_DATOHFLEN, 0,
444 NULL, 0),
445 SND_SOC_DAPM_MIXER("HFL Enable",
446 AB8500_ANACONF4, AB8500_ANACONF4_ENHFL, 0,
447 NULL, 0),
448 SND_SOC_DAPM_MIXER("HFR Enable",
449 AB8500_ANACONF4, AB8500_ANACONF4_ENHFR, 0,
450 NULL, 0),
451
452 SND_SOC_DAPM_OUTPUT("Speaker Left"),
453 SND_SOC_DAPM_OUTPUT("Speaker Right"),
454
455 /* Vibrator path */
456
457 SND_SOC_DAPM_INPUT("PWMGEN1"),
458 SND_SOC_DAPM_INPUT("PWMGEN2"),
459
460 SND_SOC_DAPM_MIXER("DA5 Channel Volume",
461 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA5, 0,
462 NULL, 0),
463 SND_SOC_DAPM_MIXER("DA6 Channel Volume",
464 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA6, 0,
465 NULL, 0),
466 SND_SOC_DAPM_MIXER("VIB1 DAC",
467 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACVIB1, 0,
468 NULL, 0),
469 SND_SOC_DAPM_MIXER("VIB2 DAC",
470 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACVIB2, 0,
471 NULL, 0),
472 SND_SOC_DAPM_MUX("Vibra 1 Controller",
473 SND_SOC_NOPM, 0, 0, dapm_pwm2vib1),
474 SND_SOC_DAPM_MUX("Vibra 2 Controller",
475 SND_SOC_NOPM, 0, 0, dapm_pwm2vib2),
476 SND_SOC_DAPM_MIXER("VIB1 Enable",
477 AB8500_ANACONF4, AB8500_ANACONF4_ENVIB1, 0,
478 NULL, 0),
479 SND_SOC_DAPM_MIXER("VIB2 Enable",
480 AB8500_ANACONF4, AB8500_ANACONF4_ENVIB2, 0,
481 NULL, 0),
482
483 SND_SOC_DAPM_OUTPUT("Vibra 1"),
484 SND_SOC_DAPM_OUTPUT("Vibra 2"),
485
486 /* Mic 1 */
487
488 SND_SOC_DAPM_INPUT("Mic 1"),
489
490 SND_SOC_DAPM_MUX("Mic 1a or 1b Select",
491 SND_SOC_NOPM, 0, 0, dapm_mic1ab_mux),
492 SND_SOC_DAPM_MIXER("MIC1 Mute",
493 AB8500_ANACONF2, AB8500_ANACONF2_MUTMIC1, 1,
494 NULL, 0),
495 SND_SOC_DAPM_MIXER("MIC1A V-AMICx Enable",
496 AB8500_ANACONF2, AB8500_ANACONF2_ENMIC1, 0,
497 NULL, 0),
498 SND_SOC_DAPM_MIXER("MIC1B V-AMICx Enable",
499 AB8500_ANACONF2, AB8500_ANACONF2_ENMIC1, 0,
500 NULL, 0),
501 SND_SOC_DAPM_MIXER("MIC1 ADC",
502 AB8500_ANACONF3, AB8500_ANACONF3_ENADCMIC, 0,
503 NULL, 0),
504 SND_SOC_DAPM_MUX("AD3 Source Select",
505 SND_SOC_NOPM, 0, 0, dapm_ad3_select),
506 SND_SOC_DAPM_MIXER("AD3 Channel Volume",
507 SND_SOC_NOPM, 0, 0,
508 NULL, 0),
509 SND_SOC_DAPM_SUPPLY("AD34 Enable", AB8500_ADPATHENA,
510 AB8500_ADPATHENA_ENAD34, 0, NULL, 0),
511
512 /* Mic 2 */
513
514 SND_SOC_DAPM_INPUT("Mic 2"),
515
516 SND_SOC_DAPM_MIXER("MIC2 Mute",
517 AB8500_ANACONF2, AB8500_ANACONF2_MUTMIC2, 1,
518 NULL, 0),
519 SND_SOC_DAPM_MIXER("MIC2 V-AMICx Enable", AB8500_ANACONF2,
520 AB8500_ANACONF2_ENMIC2, 0,
521 NULL, 0),
522
523 /* LineIn */
524
525 SND_SOC_DAPM_INPUT("LineIn Left"),
526 SND_SOC_DAPM_INPUT("LineIn Right"),
527
528 SND_SOC_DAPM_MIXER("LINL Mute",
529 AB8500_ANACONF2, AB8500_ANACONF2_MUTLINL, 1,
530 NULL, 0),
531 SND_SOC_DAPM_MIXER("LINR Mute",
532 AB8500_ANACONF2, AB8500_ANACONF2_MUTLINR, 1,
533 NULL, 0),
534 SND_SOC_DAPM_MIXER("LINL Enable", AB8500_ANACONF2,
535 AB8500_ANACONF2_ENLINL, 0,
536 NULL, 0),
537 SND_SOC_DAPM_MIXER("LINR Enable", AB8500_ANACONF2,
538 AB8500_ANACONF2_ENLINR, 0,
539 NULL, 0),
540
541 /* LineIn Bypass path */
542 SND_SOC_DAPM_MIXER("LINL to HSL Volume",
543 SND_SOC_NOPM, 0, 0,
544 NULL, 0),
545 SND_SOC_DAPM_MIXER("LINR to HSR Volume",
546 SND_SOC_NOPM, 0, 0,
547 NULL, 0),
548
549 /* LineIn, Mic 2 */
550 SND_SOC_DAPM_MUX("Mic 2 or LINR Select",
551 SND_SOC_NOPM, 0, 0, dapm_mic2lr_select),
552 SND_SOC_DAPM_MIXER("LINL ADC", AB8500_ANACONF3,
553 AB8500_ANACONF3_ENADCLINL, 0,
554 NULL, 0),
555 SND_SOC_DAPM_MIXER("LINR ADC", AB8500_ANACONF3,
556 AB8500_ANACONF3_ENADCLINR, 0,
557 NULL, 0),
558 SND_SOC_DAPM_MUX("AD1 Source Select",
559 SND_SOC_NOPM, 0, 0, dapm_ad1_select),
560 SND_SOC_DAPM_MUX("AD2 Source Select",
561 SND_SOC_NOPM, 0, 0, dapm_ad2_select),
562 SND_SOC_DAPM_MIXER("AD1 Channel Volume",
563 SND_SOC_NOPM, 0, 0,
564 NULL, 0),
565 SND_SOC_DAPM_MIXER("AD2 Channel Volume",
566 SND_SOC_NOPM, 0, 0,
567 NULL, 0),
568
569 SND_SOC_DAPM_SUPPLY("AD12 Enable", AB8500_ADPATHENA,
570 AB8500_ADPATHENA_ENAD12, 0, NULL, 0),
571
572 /* HD Capture path */
573
574 SND_SOC_DAPM_MUX("AD5 Source Select",
575 SND_SOC_NOPM, 0, 0, dapm_ad5_select),
576 SND_SOC_DAPM_MUX("AD6 Source Select",
577 SND_SOC_NOPM, 0, 0, dapm_ad6_select),
578 SND_SOC_DAPM_MIXER("AD5 Channel Volume",
579 SND_SOC_NOPM, 0, 0,
580 NULL, 0),
581 SND_SOC_DAPM_MIXER("AD6 Channel Volume",
582 SND_SOC_NOPM, 0, 0,
583 NULL, 0),
584 SND_SOC_DAPM_SUPPLY("AD5768 Enable", AB8500_ADPATHENA,
585 AB8500_ADPATHENA_ENAD5768, 0, NULL, 0),
586
587 /* Digital Microphone path */
588
589 SND_SOC_DAPM_INPUT("DMic 1"),
590 SND_SOC_DAPM_INPUT("DMic 2"),
591 SND_SOC_DAPM_INPUT("DMic 3"),
592 SND_SOC_DAPM_INPUT("DMic 4"),
593 SND_SOC_DAPM_INPUT("DMic 5"),
594 SND_SOC_DAPM_INPUT("DMic 6"),
595
596 SND_SOC_DAPM_MIXER("DMIC1",
597 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC1, 0,
598 NULL, 0),
599 SND_SOC_DAPM_MIXER("DMIC2",
600 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC2, 0,
601 NULL, 0),
602 SND_SOC_DAPM_MIXER("DMIC3",
603 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC3, 0,
604 NULL, 0),
605 SND_SOC_DAPM_MIXER("DMIC4",
606 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC4, 0,
607 NULL, 0),
608 SND_SOC_DAPM_MIXER("DMIC5",
609 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC5, 0,
610 NULL, 0),
611 SND_SOC_DAPM_MIXER("DMIC6",
612 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC6, 0,
613 NULL, 0),
614 SND_SOC_DAPM_MIXER("AD4 Channel Volume",
615 SND_SOC_NOPM, 0, 0,
616 NULL, 0),
617 /* Acoustical Noise Cancellation path */
618
619 SND_SOC_DAPM_MUX("ANC Source",
620 SND_SOC_NOPM, 0, 0,
621 dapm_anc_in_select),
622 SND_SOC_DAPM_SWITCH("ANC",
623 SND_SOC_NOPM, 0, 0,
624 dapm_anc_enable),
625 SND_SOC_DAPM_SWITCH("ANC to Earpiece",
626 SND_SOC_NOPM, 0, 0,
627 dapm_anc_ear_mute),
628
629 /* Sidetone Filter path */
630
631 SND_SOC_DAPM_MUX("Sidetone Left Source",
632 SND_SOC_NOPM, 0, 0,
633 dapm_stfir1_in_select),
634 SND_SOC_DAPM_MUX("Sidetone Right Source",
635 SND_SOC_NOPM, 0, 0,
636 dapm_stfir2_in_select),
637 SND_SOC_DAPM_MIXER("STFIR1 Control",
638 SND_SOC_NOPM, 0, 0,
639 NULL, 0),
640 SND_SOC_DAPM_MIXER("STFIR2 Control",
641 SND_SOC_NOPM, 0, 0,
642 NULL, 0),
643 SND_SOC_DAPM_MIXER("STFIR1 Volume",
644 SND_SOC_NOPM, 0, 0,
645 NULL, 0),
646 SND_SOC_DAPM_MIXER("STFIR2 Volume",
647 SND_SOC_NOPM, 0, 0,
648 NULL, 0),
649 };
650
651 /*
652 * DAPM-routes
653 */
654 static const struct snd_soc_dapm_route ab8500_dapm_routes[] = {
655 /* Power AB8500 audio-block when AD/DA is active */
656 {"Main Supply", NULL, "V-AUD"},
657 {"Main Supply", NULL, "audioclk"},
658 {"Main Supply", NULL, "Audio Power"},
659 {"Main Supply", NULL, "Audio Analog Power"},
660
661 /* Powerup charge pump if DA1/2 is in use */
662
663 {"DA_IN1", NULL, "ab8500_0p"},
664 {"DA_IN1", NULL, "Main Supply"},
665 {"DA_IN1", NULL, "Charge Pump"},
666 {"DA_IN2", NULL, "ab8500_0p"},
667 {"DA_IN2", NULL, "Main Supply"},
668 {"DA_IN2", NULL, "Charge Pump"},
669
670 /* Headset path */
671
672 {"DA1 Enable", NULL, "DA_IN1"},
673 {"DA2 Enable", NULL, "DA_IN2"},
674
675 {"HSL Digital Volume", NULL, "DA1 Enable"},
676 {"HSR Digital Volume", NULL, "DA2 Enable"},
677
678 {"HSL DAC", NULL, "HSL Digital Volume"},
679 {"HSR DAC", NULL, "HSR Digital Volume"},
680
681 {"HSL DAC Mute", NULL, "HSL DAC"},
682 {"HSR DAC Mute", NULL, "HSR DAC"},
683
684 {"HSL DAC Driver", NULL, "HSL DAC Mute"},
685 {"HSR DAC Driver", NULL, "HSR DAC Mute"},
686
687 {"HSL Mute", NULL, "HSL DAC Driver"},
688 {"HSR Mute", NULL, "HSR DAC Driver"},
689
690 {"HSL Enable", NULL, "HSL Mute"},
691 {"HSR Enable", NULL, "HSR Mute"},
692
693 {"HSL Volume", NULL, "HSL Enable"},
694 {"HSR Volume", NULL, "HSR Enable"},
695
696 {"Headset Left", NULL, "HSL Volume"},
697 {"Headset Right", NULL, "HSR Volume"},
698
699 /* HF or LineOut path */
700
701 {"DA_IN3", NULL, "ab8500_0p"},
702 {"DA_IN3", NULL, "Main Supply"},
703 {"DA3 Channel Volume", NULL, "DA_IN3"},
704 {"DA_IN4", NULL, "ab8500_0p"},
705 {"DA_IN4", NULL, "Main Supply"},
706 {"DA4 Channel Volume", NULL, "DA_IN4"},
707
708 {"Speaker Left Source", "Audio Path", "DA3 Channel Volume"},
709 {"Speaker Right Source", "Audio Path", "DA4 Channel Volume"},
710
711 {"DA3 or ANC path to HfL", NULL, "Speaker Left Source"},
712 {"DA4 or ANC path to HfR", NULL, "Speaker Right Source"},
713
714 /* HF path */
715
716 {"HFL DAC", NULL, "DA3 or ANC path to HfL"},
717 {"HFR DAC", NULL, "DA4 or ANC path to HfR"},
718
719 {"HFL Enable", NULL, "HFL DAC"},
720 {"HFR Enable", NULL, "HFR DAC"},
721
722 {"Speaker Left", NULL, "HFL Enable"},
723 {"Speaker Right", NULL, "HFR Enable"},
724
725 /* Earpiece path */
726
727 {"Earpiece or LineOut Mono Source", "Headset Left",
728 "HSL Digital Volume"},
729 {"Earpiece or LineOut Mono Source", "Speaker Left",
730 "DA3 or ANC path to HfL"},
731
732 {"EAR DAC", NULL, "Earpiece or LineOut Mono Source"},
733
734 {"EAR Mute", NULL, "EAR DAC"},
735
736 {"EAR Enable", NULL, "EAR Mute"},
737
738 {"Earpiece", NULL, "EAR Enable"},
739
740 /* LineOut path stereo */
741
742 {"LineOut Source", "Stereo Path", "HSL DAC Driver"},
743 {"LineOut Source", "Stereo Path", "HSR DAC Driver"},
744
745 /* LineOut path mono */
746
747 {"LineOut Source", "Mono Path", "EAR DAC"},
748
749 /* LineOut path */
750
751 {"LOL Disable HFL", NULL, "LineOut Source"},
752 {"LOR Disable HFR", NULL, "LineOut Source"},
753
754 {"LOL Enable", NULL, "LOL Disable HFL"},
755 {"LOR Enable", NULL, "LOR Disable HFR"},
756
757 {"LineOut Left", NULL, "LOL Enable"},
758 {"LineOut Right", NULL, "LOR Enable"},
759
760 /* Vibrator path */
761
762 {"DA_IN5", NULL, "ab8500_0p"},
763 {"DA_IN5", NULL, "Main Supply"},
764 {"DA5 Channel Volume", NULL, "DA_IN5"},
765 {"DA_IN6", NULL, "ab8500_0p"},
766 {"DA_IN6", NULL, "Main Supply"},
767 {"DA6 Channel Volume", NULL, "DA_IN6"},
768
769 {"VIB1 DAC", NULL, "DA5 Channel Volume"},
770 {"VIB2 DAC", NULL, "DA6 Channel Volume"},
771
772 {"Vibra 1 Controller", "Audio Path", "VIB1 DAC"},
773 {"Vibra 2 Controller", "Audio Path", "VIB2 DAC"},
774 {"Vibra 1 Controller", "PWM Generator", "PWMGEN1"},
775 {"Vibra 2 Controller", "PWM Generator", "PWMGEN2"},
776
777 {"VIB1 Enable", NULL, "Vibra 1 Controller"},
778 {"VIB2 Enable", NULL, "Vibra 2 Controller"},
779
780 {"Vibra 1", NULL, "VIB1 Enable"},
781 {"Vibra 2", NULL, "VIB2 Enable"},
782
783
784 /* Mic 2 */
785
786 {"MIC2 V-AMICx Enable", NULL, "Mic 2"},
787
788 /* LineIn */
789 {"LINL Mute", NULL, "LineIn Left"},
790 {"LINR Mute", NULL, "LineIn Right"},
791
792 {"LINL Enable", NULL, "LINL Mute"},
793 {"LINR Enable", NULL, "LINR Mute"},
794
795 /* LineIn, Mic 2 */
796 {"Mic 2 or LINR Select", "LineIn Right", "LINR Enable"},
797 {"Mic 2 or LINR Select", "Mic 2", "MIC2 V-AMICx Enable"},
798
799 {"LINL ADC", NULL, "LINL Enable"},
800 {"LINR ADC", NULL, "Mic 2 or LINR Select"},
801
802 {"AD1 Source Select", "LineIn Left", "LINL ADC"},
803 {"AD2 Source Select", "LineIn Right", "LINR ADC"},
804
805 {"AD1 Channel Volume", NULL, "AD1 Source Select"},
806 {"AD2 Channel Volume", NULL, "AD2 Source Select"},
807
808 {"AD1 Channel Volume", NULL, "AD12 Enable"},
809 {"AD2 Channel Volume", NULL, "AD12 Enable"},
810
811 {"ab8500_0c", NULL, "AD_OUT1"},
812 {"AD_OUT1", NULL, "Main Supply"},
813 {"AD_OUT1", NULL, "AD1 Channel Volume"},
814 {"ab8500_0c", NULL, "AD_OUT2"},
815 {"AD_OUT2", NULL, "Main Supply"},
816 {"AD_OUT2", NULL, "AD2 Channel Volume"},
817
818 /* Mic 1 */
819
820 {"MIC1 Mute", NULL, "Mic 1"},
821
822 {"MIC1A V-AMICx Enable", NULL, "MIC1 Mute"},
823 {"MIC1B V-AMICx Enable", NULL, "MIC1 Mute"},
824
825 {"Mic 1a or 1b Select", "Mic 1a", "MIC1A V-AMICx Enable"},
826 {"Mic 1a or 1b Select", "Mic 1b", "MIC1B V-AMICx Enable"},
827
828 {"MIC1 ADC", NULL, "Mic 1a or 1b Select"},
829
830 {"AD3 Source Select", "Mic 1", "MIC1 ADC"},
831
832 {"AD3 Channel Volume", NULL, "AD3 Source Select"},
833 {"AD3 Channel Volume", NULL, "AD34 Enable"},
834
835 {"ab8500_0c", NULL, "AD_OUT3"},
836 {"AD_OUT3", NULL, "Main Supply"},
837 {"AD_OUT3", NULL, "AD3 Channel Volume"},
838
839 /* HD Capture path */
840
841 {"AD5 Source Select", "Mic 2", "LINR ADC"},
842 {"AD6 Source Select", "Mic 1", "MIC1 ADC"},
843
844 {"AD5 Channel Volume", NULL, "AD5 Source Select"},
845 {"AD6 Channel Volume", NULL, "AD6 Source Select"},
846 {"AD5 Channel Volume", NULL, "AD5768 Enable"},
847 {"AD6 Channel Volume", NULL, "AD5768 Enable"},
848
849 {"ab8500_0c", NULL, "AD_OUT57"},
850 {"AD_OUT57", NULL, "Main Supply"},
851 {"AD_OUT57", NULL, "AD5 Channel Volume"},
852 {"ab8500_0c", NULL, "AD_OUT68"},
853 {"AD_OUT68", NULL, "Main Supply"},
854 {"AD_OUT68", NULL, "AD6 Channel Volume"},
855
856 /* Digital Microphone path */
857
858 {"DMic 1", NULL, "V-DMIC"},
859 {"DMic 2", NULL, "V-DMIC"},
860 {"DMic 3", NULL, "V-DMIC"},
861 {"DMic 4", NULL, "V-DMIC"},
862 {"DMic 5", NULL, "V-DMIC"},
863 {"DMic 6", NULL, "V-DMIC"},
864
865 {"DMIC1", NULL, "DMic 1"},
866 {"DMIC2", NULL, "DMic 2"},
867 {"DMIC3", NULL, "DMic 3"},
868 {"DMIC4", NULL, "DMic 4"},
869 {"DMIC5", NULL, "DMic 5"},
870 {"DMIC6", NULL, "DMic 6"},
871
872 {"AD1 Source Select", "DMic 1", "DMIC1"},
873 {"AD2 Source Select", "DMic 2", "DMIC2"},
874 {"AD3 Source Select", "DMic 3", "DMIC3"},
875 {"AD5 Source Select", "DMic 5", "DMIC5"},
876 {"AD6 Source Select", "DMic 6", "DMIC6"},
877
878 {"AD4 Channel Volume", NULL, "DMIC4"},
879 {"AD4 Channel Volume", NULL, "AD34 Enable"},
880
881 {"ab8500_0c", NULL, "AD_OUT4"},
882 {"AD_OUT4", NULL, "Main Supply"},
883 {"AD_OUT4", NULL, "AD4 Channel Volume"},
884
885 /* LineIn Bypass path */
886
887 {"LINL to HSL Volume", NULL, "LINL Enable"},
888 {"LINR to HSR Volume", NULL, "LINR Enable"},
889
890 {"HSL DAC Driver", NULL, "LINL to HSL Volume"},
891 {"HSR DAC Driver", NULL, "LINR to HSR Volume"},
892
893 /* ANC path (Acoustic Noise Cancellation) */
894
895 {"ANC Source", "Mic 2 / DMic 5", "AD5 Channel Volume"},
896 {"ANC Source", "Mic 1 / DMic 6", "AD6 Channel Volume"},
897
898 {"ANC", "Switch", "ANC Source"},
899
900 {"Speaker Left Source", "ANC", "ANC"},
901 {"Speaker Right Source", "ANC", "ANC"},
902 {"ANC to Earpiece", "Switch", "ANC"},
903
904 {"HSL Digital Volume", NULL, "ANC to Earpiece"},
905
906 /* Sidetone Filter path */
907
908 {"Sidetone Left Source", "LineIn Left", "AD1 Channel Volume"},
909 {"Sidetone Left Source", "LineIn Right", "AD2 Channel Volume"},
910 {"Sidetone Left Source", "Mic 1", "AD3 Channel Volume"},
911 {"Sidetone Left Source", "Headset Left", "DA_IN1"},
912 {"Sidetone Right Source", "LineIn Right", "AD2 Channel Volume"},
913 {"Sidetone Right Source", "Mic 1", "AD3 Channel Volume"},
914 {"Sidetone Right Source", "DMic 4", "AD4 Channel Volume"},
915 {"Sidetone Right Source", "Headset Right", "DA_IN2"},
916
917 {"STFIR1 Control", NULL, "Sidetone Left Source"},
918 {"STFIR2 Control", NULL, "Sidetone Right Source"},
919
920 {"STFIR1 Volume", NULL, "STFIR1 Control"},
921 {"STFIR2 Volume", NULL, "STFIR2 Control"},
922
923 {"DA1 Enable", NULL, "STFIR1 Volume"},
924 {"DA2 Enable", NULL, "STFIR2 Volume"},
925 };
926
927 static const struct snd_soc_dapm_route ab8500_dapm_routes_mic1a_vamicx[] = {
928 {"MIC1A V-AMICx Enable", NULL, "V-AMIC1"},
929 {"MIC1A V-AMICx Enable", NULL, "V-AMIC2"},
930 };
931
932 static const struct snd_soc_dapm_route ab8500_dapm_routes_mic1b_vamicx[] = {
933 {"MIC1B V-AMICx Enable", NULL, "V-AMIC1"},
934 {"MIC1B V-AMICx Enable", NULL, "V-AMIC2"},
935 };
936
937 static const struct snd_soc_dapm_route ab8500_dapm_routes_mic2_vamicx[] = {
938 {"MIC2 V-AMICx Enable", NULL, "V-AMIC1"},
939 {"MIC2 V-AMICx Enable", NULL, "V-AMIC2"},
940 };
941
942 /*
943 * Controls - Non-DAPM ASoC
944 */
945
946 static DECLARE_TLV_DB_SCALE(adx_dig_gain_tlv, -3200, 100, 1);
947 /* -32dB = Mute */
948
949 static DECLARE_TLV_DB_SCALE(dax_dig_gain_tlv, -6300, 100, 1);
950 /* -63dB = Mute */
951
952 static DECLARE_TLV_DB_SCALE(hs_ear_dig_gain_tlv, -100, 100, 1);
953 /* -1dB = Mute */
954
955 static const DECLARE_TLV_DB_RANGE(hs_gain_tlv,
956 0, 3, TLV_DB_SCALE_ITEM(-3200, 400, 0),
957 4, 15, TLV_DB_SCALE_ITEM(-1800, 200, 0)
958 );
959
960 static DECLARE_TLV_DB_SCALE(mic_gain_tlv, 0, 100, 0);
961
962 static DECLARE_TLV_DB_SCALE(lin_gain_tlv, -1000, 200, 0);
963
964 static DECLARE_TLV_DB_SCALE(lin2hs_gain_tlv, -3800, 200, 1);
965 /* -38dB = Mute */
966
967 static const char * const enum_hsfadspeed[] = {"2ms", "0.5ms", "10.6ms",
968 "5ms"};
969 static SOC_ENUM_SINGLE_DECL(soc_enum_hsfadspeed,
970 AB8500_DIGMICCONF, AB8500_DIGMICCONF_HSFADSPEED, enum_hsfadspeed);
971
972 static const char * const enum_envdetthre[] = {
973 "250mV", "300mV", "350mV", "400mV",
974 "450mV", "500mV", "550mV", "600mV",
975 "650mV", "700mV", "750mV", "800mV",
976 "850mV", "900mV", "950mV", "1.00V" };
977 static SOC_ENUM_SINGLE_DECL(soc_enum_envdeththre,
978 AB8500_ENVCPCONF, AB8500_ENVCPCONF_ENVDETHTHRE, enum_envdetthre);
979 static SOC_ENUM_SINGLE_DECL(soc_enum_envdetlthre,
980 AB8500_ENVCPCONF, AB8500_ENVCPCONF_ENVDETLTHRE, enum_envdetthre);
981 static const char * const enum_envdettime[] = {
982 "26.6us", "53.2us", "106us", "213us",
983 "426us", "851us", "1.70ms", "3.40ms",
984 "6.81ms", "13.6ms", "27.2ms", "54.5ms",
985 "109ms", "218ms", "436ms", "872ms" };
986 static SOC_ENUM_SINGLE_DECL(soc_enum_envdettime,
987 AB8500_SIGENVCONF, AB8500_SIGENVCONF_ENVDETTIME, enum_envdettime);
988
989 static const char * const enum_sinc31[] = {"Sinc 3", "Sinc 1"};
990 static SOC_ENUM_SINGLE_DECL(soc_enum_hsesinc, AB8500_HSLEARDIGGAIN,
991 AB8500_HSLEARDIGGAIN_HSSINC1, enum_sinc31);
992
993 static const char * const enum_fadespeed[] = {"1ms", "4ms", "8ms", "16ms"};
994 static SOC_ENUM_SINGLE_DECL(soc_enum_fadespeed, AB8500_HSRDIGGAIN,
995 AB8500_HSRDIGGAIN_FADESPEED, enum_fadespeed);
996
997 /* Earpiece */
998
999 static const char * const enum_lowpow[] = {"Normal", "Low Power"};
1000 static SOC_ENUM_SINGLE_DECL(soc_enum_eardaclowpow, AB8500_ANACONF1,
1001 AB8500_ANACONF1_EARDACLOWPOW, enum_lowpow);
1002 static SOC_ENUM_SINGLE_DECL(soc_enum_eardrvlowpow, AB8500_ANACONF1,
1003 AB8500_ANACONF1_EARDRVLOWPOW, enum_lowpow);
1004
1005 static const char * const enum_av_mode[] = {"Audio", "Voice"};
1006 static SOC_ENUM_DOUBLE_DECL(soc_enum_ad12voice, AB8500_ADFILTCONF,
1007 AB8500_ADFILTCONF_AD1VOICE, AB8500_ADFILTCONF_AD2VOICE, enum_av_mode);
1008 static SOC_ENUM_DOUBLE_DECL(soc_enum_ad34voice, AB8500_ADFILTCONF,
1009 AB8500_ADFILTCONF_AD3VOICE, AB8500_ADFILTCONF_AD4VOICE, enum_av_mode);
1010
1011 /* DA */
1012
1013 static SOC_ENUM_SINGLE_DECL(soc_enum_da12voice,
1014 AB8500_DASLOTCONF1, AB8500_DASLOTCONF1_DA12VOICE,
1015 enum_av_mode);
1016 static SOC_ENUM_SINGLE_DECL(soc_enum_da34voice,
1017 AB8500_DASLOTCONF3, AB8500_DASLOTCONF3_DA34VOICE,
1018 enum_av_mode);
1019 static SOC_ENUM_SINGLE_DECL(soc_enum_da56voice,
1020 AB8500_DASLOTCONF5, AB8500_DASLOTCONF5_DA56VOICE,
1021 enum_av_mode);
1022
1023 static const char * const enum_da2hslr[] = {"Sidetone", "Audio Path"};
1024 static SOC_ENUM_DOUBLE_DECL(soc_enum_da2hslr, AB8500_DIGMULTCONF1,
1025 AB8500_DIGMULTCONF1_DATOHSLEN,
1026 AB8500_DIGMULTCONF1_DATOHSREN, enum_da2hslr);
1027
1028 static const char * const enum_sinc53[] = {"Sinc 5", "Sinc 3"};
1029 static SOC_ENUM_DOUBLE_DECL(soc_enum_dmic12sinc, AB8500_DMICFILTCONF,
1030 AB8500_DMICFILTCONF_DMIC1SINC3,
1031 AB8500_DMICFILTCONF_DMIC2SINC3, enum_sinc53);
1032 static SOC_ENUM_DOUBLE_DECL(soc_enum_dmic34sinc, AB8500_DMICFILTCONF,
1033 AB8500_DMICFILTCONF_DMIC3SINC3,
1034 AB8500_DMICFILTCONF_DMIC4SINC3, enum_sinc53);
1035 static SOC_ENUM_DOUBLE_DECL(soc_enum_dmic56sinc, AB8500_DMICFILTCONF,
1036 AB8500_DMICFILTCONF_DMIC5SINC3,
1037 AB8500_DMICFILTCONF_DMIC6SINC3, enum_sinc53);
1038
1039 /* Digital interface - DA from slot mapping */
1040 static const char * const enum_da_from_slot_map[] = {"SLOT0",
1041 "SLOT1",
1042 "SLOT2",
1043 "SLOT3",
1044 "SLOT4",
1045 "SLOT5",
1046 "SLOT6",
1047 "SLOT7",
1048 "SLOT8",
1049 "SLOT9",
1050 "SLOT10",
1051 "SLOT11",
1052 "SLOT12",
1053 "SLOT13",
1054 "SLOT14",
1055 "SLOT15",
1056 "SLOT16",
1057 "SLOT17",
1058 "SLOT18",
1059 "SLOT19",
1060 "SLOT20",
1061 "SLOT21",
1062 "SLOT22",
1063 "SLOT23",
1064 "SLOT24",
1065 "SLOT25",
1066 "SLOT26",
1067 "SLOT27",
1068 "SLOT28",
1069 "SLOT29",
1070 "SLOT30",
1071 "SLOT31"};
1072 static SOC_ENUM_SINGLE_DECL(soc_enum_da1slotmap,
1073 AB8500_DASLOTCONF1, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1074 enum_da_from_slot_map);
1075 static SOC_ENUM_SINGLE_DECL(soc_enum_da2slotmap,
1076 AB8500_DASLOTCONF2, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1077 enum_da_from_slot_map);
1078 static SOC_ENUM_SINGLE_DECL(soc_enum_da3slotmap,
1079 AB8500_DASLOTCONF3, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1080 enum_da_from_slot_map);
1081 static SOC_ENUM_SINGLE_DECL(soc_enum_da4slotmap,
1082 AB8500_DASLOTCONF4, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1083 enum_da_from_slot_map);
1084 static SOC_ENUM_SINGLE_DECL(soc_enum_da5slotmap,
1085 AB8500_DASLOTCONF5, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1086 enum_da_from_slot_map);
1087 static SOC_ENUM_SINGLE_DECL(soc_enum_da6slotmap,
1088 AB8500_DASLOTCONF6, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1089 enum_da_from_slot_map);
1090 static SOC_ENUM_SINGLE_DECL(soc_enum_da7slotmap,
1091 AB8500_DASLOTCONF7, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1092 enum_da_from_slot_map);
1093 static SOC_ENUM_SINGLE_DECL(soc_enum_da8slotmap,
1094 AB8500_DASLOTCONF8, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1095 enum_da_from_slot_map);
1096
1097 /* Digital interface - AD to slot mapping */
1098 static const char * const enum_ad_to_slot_map[] = {"AD_OUT1",
1099 "AD_OUT2",
1100 "AD_OUT3",
1101 "AD_OUT4",
1102 "AD_OUT5",
1103 "AD_OUT6",
1104 "AD_OUT7",
1105 "AD_OUT8",
1106 "zeroes",
1107 "zeroes",
1108 "zeroes",
1109 "zeroes",
1110 "tristate",
1111 "tristate",
1112 "tristate",
1113 "tristate"};
1114 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot0map,
1115 AB8500_ADSLOTSEL1, AB8500_ADSLOTSELX_EVEN_SHIFT,
1116 enum_ad_to_slot_map);
1117 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot1map,
1118 AB8500_ADSLOTSEL1, AB8500_ADSLOTSELX_ODD_SHIFT,
1119 enum_ad_to_slot_map);
1120 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot2map,
1121 AB8500_ADSLOTSEL2, AB8500_ADSLOTSELX_EVEN_SHIFT,
1122 enum_ad_to_slot_map);
1123 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot3map,
1124 AB8500_ADSLOTSEL2, AB8500_ADSLOTSELX_ODD_SHIFT,
1125 enum_ad_to_slot_map);
1126 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot4map,
1127 AB8500_ADSLOTSEL3, AB8500_ADSLOTSELX_EVEN_SHIFT,
1128 enum_ad_to_slot_map);
1129 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot5map,
1130 AB8500_ADSLOTSEL3, AB8500_ADSLOTSELX_ODD_SHIFT,
1131 enum_ad_to_slot_map);
1132 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot6map,
1133 AB8500_ADSLOTSEL4, AB8500_ADSLOTSELX_EVEN_SHIFT,
1134 enum_ad_to_slot_map);
1135 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot7map,
1136 AB8500_ADSLOTSEL4, AB8500_ADSLOTSELX_ODD_SHIFT,
1137 enum_ad_to_slot_map);
1138 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot8map,
1139 AB8500_ADSLOTSEL5, AB8500_ADSLOTSELX_EVEN_SHIFT,
1140 enum_ad_to_slot_map);
1141 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot9map,
1142 AB8500_ADSLOTSEL5, AB8500_ADSLOTSELX_ODD_SHIFT,
1143 enum_ad_to_slot_map);
1144 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot10map,
1145 AB8500_ADSLOTSEL6, AB8500_ADSLOTSELX_EVEN_SHIFT,
1146 enum_ad_to_slot_map);
1147 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot11map,
1148 AB8500_ADSLOTSEL6, AB8500_ADSLOTSELX_ODD_SHIFT,
1149 enum_ad_to_slot_map);
1150 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot12map,
1151 AB8500_ADSLOTSEL7, AB8500_ADSLOTSELX_EVEN_SHIFT,
1152 enum_ad_to_slot_map);
1153 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot13map,
1154 AB8500_ADSLOTSEL7, AB8500_ADSLOTSELX_ODD_SHIFT,
1155 enum_ad_to_slot_map);
1156 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot14map,
1157 AB8500_ADSLOTSEL8, AB8500_ADSLOTSELX_EVEN_SHIFT,
1158 enum_ad_to_slot_map);
1159 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot15map,
1160 AB8500_ADSLOTSEL8, AB8500_ADSLOTSELX_ODD_SHIFT,
1161 enum_ad_to_slot_map);
1162 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot16map,
1163 AB8500_ADSLOTSEL9, AB8500_ADSLOTSELX_EVEN_SHIFT,
1164 enum_ad_to_slot_map);
1165 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot17map,
1166 AB8500_ADSLOTSEL9, AB8500_ADSLOTSELX_ODD_SHIFT,
1167 enum_ad_to_slot_map);
1168 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot18map,
1169 AB8500_ADSLOTSEL10, AB8500_ADSLOTSELX_EVEN_SHIFT,
1170 enum_ad_to_slot_map);
1171 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot19map,
1172 AB8500_ADSLOTSEL10, AB8500_ADSLOTSELX_ODD_SHIFT,
1173 enum_ad_to_slot_map);
1174 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot20map,
1175 AB8500_ADSLOTSEL11, AB8500_ADSLOTSELX_EVEN_SHIFT,
1176 enum_ad_to_slot_map);
1177 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot21map,
1178 AB8500_ADSLOTSEL11, AB8500_ADSLOTSELX_ODD_SHIFT,
1179 enum_ad_to_slot_map);
1180 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot22map,
1181 AB8500_ADSLOTSEL12, AB8500_ADSLOTSELX_EVEN_SHIFT,
1182 enum_ad_to_slot_map);
1183 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot23map,
1184 AB8500_ADSLOTSEL12, AB8500_ADSLOTSELX_ODD_SHIFT,
1185 enum_ad_to_slot_map);
1186 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot24map,
1187 AB8500_ADSLOTSEL13, AB8500_ADSLOTSELX_EVEN_SHIFT,
1188 enum_ad_to_slot_map);
1189 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot25map,
1190 AB8500_ADSLOTSEL13, AB8500_ADSLOTSELX_ODD_SHIFT,
1191 enum_ad_to_slot_map);
1192 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot26map,
1193 AB8500_ADSLOTSEL14, AB8500_ADSLOTSELX_EVEN_SHIFT,
1194 enum_ad_to_slot_map);
1195 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot27map,
1196 AB8500_ADSLOTSEL14, AB8500_ADSLOTSELX_ODD_SHIFT,
1197 enum_ad_to_slot_map);
1198 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot28map,
1199 AB8500_ADSLOTSEL15, AB8500_ADSLOTSELX_EVEN_SHIFT,
1200 enum_ad_to_slot_map);
1201 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot29map,
1202 AB8500_ADSLOTSEL15, AB8500_ADSLOTSELX_ODD_SHIFT,
1203 enum_ad_to_slot_map);
1204 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot30map,
1205 AB8500_ADSLOTSEL16, AB8500_ADSLOTSELX_EVEN_SHIFT,
1206 enum_ad_to_slot_map);
1207 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot31map,
1208 AB8500_ADSLOTSEL16, AB8500_ADSLOTSELX_ODD_SHIFT,
1209 enum_ad_to_slot_map);
1210
1211 /* Digital interface - Burst mode */
1212 static const char * const enum_mask[] = {"Unmasked", "Masked"};
1213 static SOC_ENUM_SINGLE_DECL(soc_enum_bfifomask,
1214 AB8500_FIFOCONF1, AB8500_FIFOCONF1_BFIFOMASK,
1215 enum_mask);
1216 static const char * const enum_bitclk0[] = {"19_2_MHz", "38_4_MHz"};
1217 static SOC_ENUM_SINGLE_DECL(soc_enum_bfifo19m2,
1218 AB8500_FIFOCONF1, AB8500_FIFOCONF1_BFIFO19M2,
1219 enum_bitclk0);
1220 static const char * const enum_slavemaster[] = {"Slave", "Master"};
1221 static SOC_ENUM_SINGLE_DECL(soc_enum_bfifomast,
1222 AB8500_FIFOCONF3, AB8500_FIFOCONF3_BFIFOMAST_SHIFT,
1223 enum_slavemaster);
1224
1225 /* ANC */
1226
1227 static struct snd_kcontrol_new ab8500_ctrls[] = {
1228 /* Charge pump */
1229 SOC_ENUM("Charge Pump High Threshold For Low Voltage",
1230 soc_enum_envdeththre),
1231 SOC_ENUM("Charge Pump Low Threshold For Low Voltage",
1232 soc_enum_envdetlthre),
1233 SOC_SINGLE("Charge Pump Envelope Detection Switch",
1234 AB8500_SIGENVCONF, AB8500_SIGENVCONF_ENVDETCPEN,
1235 1, 0),
1236 SOC_ENUM("Charge Pump Envelope Detection Decay Time",
1237 soc_enum_envdettime),
1238
1239 /* Headset */
1240 SOC_ENUM("Headset Mode", soc_enum_da12voice),
1241 SOC_SINGLE("Headset High Pass Switch",
1242 AB8500_ANACONF1, AB8500_ANACONF1_HSHPEN,
1243 1, 0),
1244 SOC_SINGLE("Headset Low Power Switch",
1245 AB8500_ANACONF1, AB8500_ANACONF1_HSLOWPOW,
1246 1, 0),
1247 SOC_SINGLE("Headset DAC Low Power Switch",
1248 AB8500_ANACONF1, AB8500_ANACONF1_DACLOWPOW1,
1249 1, 0),
1250 SOC_SINGLE("Headset DAC Drv Low Power Switch",
1251 AB8500_ANACONF1, AB8500_ANACONF1_DACLOWPOW0,
1252 1, 0),
1253 SOC_ENUM("Headset Fade Speed", soc_enum_hsfadspeed),
1254 SOC_ENUM("Headset Source", soc_enum_da2hslr),
1255 SOC_ENUM("Headset Filter", soc_enum_hsesinc),
1256 SOC_DOUBLE_R_TLV("Headset Master Volume",
1257 AB8500_DADIGGAIN1, AB8500_DADIGGAIN2,
1258 0, AB8500_DADIGGAINX_DAXGAIN_MAX, 1, dax_dig_gain_tlv),
1259 SOC_DOUBLE_R_TLV("Headset Digital Volume",
1260 AB8500_HSLEARDIGGAIN, AB8500_HSRDIGGAIN,
1261 0, AB8500_HSLEARDIGGAIN_HSLDGAIN_MAX, 1, hs_ear_dig_gain_tlv),
1262 SOC_DOUBLE_TLV("Headset Volume",
1263 AB8500_ANAGAIN3,
1264 AB8500_ANAGAIN3_HSLGAIN, AB8500_ANAGAIN3_HSRGAIN,
1265 AB8500_ANAGAIN3_HSXGAIN_MAX, 1, hs_gain_tlv),
1266
1267 /* Earpiece */
1268 SOC_ENUM("Earpiece DAC Mode",
1269 soc_enum_eardaclowpow),
1270 SOC_ENUM("Earpiece DAC Drv Mode",
1271 soc_enum_eardrvlowpow),
1272
1273 /* HandsFree */
1274 SOC_ENUM("HF Mode", soc_enum_da34voice),
1275 SOC_SINGLE("HF and Headset Swap Switch",
1276 AB8500_DASLOTCONF1, AB8500_DASLOTCONF1_SWAPDA12_34,
1277 1, 0),
1278 SOC_DOUBLE("HF Low EMI Mode Switch",
1279 AB8500_CLASSDCONF1,
1280 AB8500_CLASSDCONF1_HFLSWAPEN, AB8500_CLASSDCONF1_HFRSWAPEN,
1281 1, 0),
1282 SOC_DOUBLE("HF FIR Bypass Switch",
1283 AB8500_CLASSDCONF2,
1284 AB8500_CLASSDCONF2_FIRBYP0, AB8500_CLASSDCONF2_FIRBYP1,
1285 1, 0),
1286 SOC_DOUBLE("HF High Volume Switch",
1287 AB8500_CLASSDCONF2,
1288 AB8500_CLASSDCONF2_HIGHVOLEN0, AB8500_CLASSDCONF2_HIGHVOLEN1,
1289 1, 0),
1290 SOC_SINGLE("HF L and R Bridge Switch",
1291 AB8500_CLASSDCONF1, AB8500_CLASSDCONF1_PARLHF,
1292 1, 0),
1293 SOC_DOUBLE_R_TLV("HF Master Volume",
1294 AB8500_DADIGGAIN3, AB8500_DADIGGAIN4,
1295 0, AB8500_DADIGGAINX_DAXGAIN_MAX, 1, dax_dig_gain_tlv),
1296
1297 /* Vibra */
1298 SOC_DOUBLE("Vibra High Volume Switch",
1299 AB8500_CLASSDCONF2,
1300 AB8500_CLASSDCONF2_HIGHVOLEN2, AB8500_CLASSDCONF2_HIGHVOLEN3,
1301 1, 0),
1302 SOC_DOUBLE("Vibra Low EMI Mode Switch",
1303 AB8500_CLASSDCONF1,
1304 AB8500_CLASSDCONF1_VIB1SWAPEN, AB8500_CLASSDCONF1_VIB2SWAPEN,
1305 1, 0),
1306 SOC_DOUBLE("Vibra FIR Bypass Switch",
1307 AB8500_CLASSDCONF2,
1308 AB8500_CLASSDCONF2_FIRBYP2, AB8500_CLASSDCONF2_FIRBYP3,
1309 1, 0),
1310 SOC_ENUM("Vibra Mode", soc_enum_da56voice),
1311 SOC_DOUBLE_R("Vibra PWM Duty Cycle N",
1312 AB8500_PWMGENCONF3, AB8500_PWMGENCONF5,
1313 AB8500_PWMGENCONFX_PWMVIBXDUTCYC,
1314 AB8500_PWMGENCONFX_PWMVIBXDUTCYC_MAX, 0),
1315 SOC_DOUBLE_R("Vibra PWM Duty Cycle P",
1316 AB8500_PWMGENCONF2, AB8500_PWMGENCONF4,
1317 AB8500_PWMGENCONFX_PWMVIBXDUTCYC,
1318 AB8500_PWMGENCONFX_PWMVIBXDUTCYC_MAX, 0),
1319 SOC_SINGLE("Vibra 1 and 2 Bridge Switch",
1320 AB8500_CLASSDCONF1, AB8500_CLASSDCONF1_PARLVIB,
1321 1, 0),
1322 SOC_DOUBLE_R_TLV("Vibra Master Volume",
1323 AB8500_DADIGGAIN5, AB8500_DADIGGAIN6,
1324 0, AB8500_DADIGGAINX_DAXGAIN_MAX, 1, dax_dig_gain_tlv),
1325
1326 /* HandsFree, Vibra */
1327 SOC_SINGLE("ClassD High Pass Volume",
1328 AB8500_CLASSDCONF3, AB8500_CLASSDCONF3_DITHHPGAIN,
1329 AB8500_CLASSDCONF3_DITHHPGAIN_MAX, 0),
1330 SOC_SINGLE("ClassD White Volume",
1331 AB8500_CLASSDCONF3, AB8500_CLASSDCONF3_DITHWGAIN,
1332 AB8500_CLASSDCONF3_DITHWGAIN_MAX, 0),
1333
1334 /* Mic 1, Mic 2, LineIn */
1335 SOC_DOUBLE_R_TLV("Mic Master Volume",
1336 AB8500_ADDIGGAIN3, AB8500_ADDIGGAIN4,
1337 0, AB8500_ADDIGGAINX_ADXGAIN_MAX, 1, adx_dig_gain_tlv),
1338
1339 /* Mic 1 */
1340 SOC_SINGLE_TLV("Mic 1",
1341 AB8500_ANAGAIN1,
1342 AB8500_ANAGAINX_MICXGAIN,
1343 AB8500_ANAGAINX_MICXGAIN_MAX, 0, mic_gain_tlv),
1344 SOC_SINGLE("Mic 1 Low Power Switch",
1345 AB8500_ANAGAIN1, AB8500_ANAGAINX_LOWPOWMICX,
1346 1, 0),
1347
1348 /* Mic 2 */
1349 SOC_DOUBLE("Mic High Pass Switch",
1350 AB8500_ADFILTCONF,
1351 AB8500_ADFILTCONF_AD3NH, AB8500_ADFILTCONF_AD4NH,
1352 1, 1),
1353 SOC_ENUM("Mic Mode", soc_enum_ad34voice),
1354 SOC_ENUM("Mic Filter", soc_enum_dmic34sinc),
1355 SOC_SINGLE_TLV("Mic 2",
1356 AB8500_ANAGAIN2,
1357 AB8500_ANAGAINX_MICXGAIN,
1358 AB8500_ANAGAINX_MICXGAIN_MAX, 0, mic_gain_tlv),
1359 SOC_SINGLE("Mic 2 Low Power Switch",
1360 AB8500_ANAGAIN2, AB8500_ANAGAINX_LOWPOWMICX,
1361 1, 0),
1362
1363 /* LineIn */
1364 SOC_DOUBLE("LineIn High Pass Switch",
1365 AB8500_ADFILTCONF,
1366 AB8500_ADFILTCONF_AD1NH, AB8500_ADFILTCONF_AD2NH,
1367 1, 1),
1368 SOC_ENUM("LineIn Filter", soc_enum_dmic12sinc),
1369 SOC_ENUM("LineIn Mode", soc_enum_ad12voice),
1370 SOC_DOUBLE_R_TLV("LineIn Master Volume",
1371 AB8500_ADDIGGAIN1, AB8500_ADDIGGAIN2,
1372 0, AB8500_ADDIGGAINX_ADXGAIN_MAX, 1, adx_dig_gain_tlv),
1373 SOC_DOUBLE_TLV("LineIn",
1374 AB8500_ANAGAIN4,
1375 AB8500_ANAGAIN4_LINLGAIN, AB8500_ANAGAIN4_LINRGAIN,
1376 AB8500_ANAGAIN4_LINXGAIN_MAX, 0, lin_gain_tlv),
1377 SOC_DOUBLE_R_TLV("LineIn to Headset Volume",
1378 AB8500_DIGLINHSLGAIN, AB8500_DIGLINHSRGAIN,
1379 AB8500_DIGLINHSXGAIN_LINTOHSXGAIN,
1380 AB8500_DIGLINHSXGAIN_LINTOHSXGAIN_MAX,
1381 1, lin2hs_gain_tlv),
1382
1383 /* DMic */
1384 SOC_ENUM("DMic Filter", soc_enum_dmic56sinc),
1385 SOC_DOUBLE_R_TLV("DMic Master Volume",
1386 AB8500_ADDIGGAIN5, AB8500_ADDIGGAIN6,
1387 0, AB8500_ADDIGGAINX_ADXGAIN_MAX, 1, adx_dig_gain_tlv),
1388
1389 /* Digital gains */
1390 SOC_ENUM("Digital Gain Fade Speed", soc_enum_fadespeed),
1391
1392 /* Analog loopback */
1393 SOC_DOUBLE_R_TLV("Analog Loopback Volume",
1394 AB8500_ADDIGLOOPGAIN1, AB8500_ADDIGLOOPGAIN2,
1395 0, AB8500_ADDIGLOOPGAINX_ADXLBGAIN_MAX, 1, dax_dig_gain_tlv),
1396
1397 /* Digital interface - DA from slot mapping */
1398 SOC_ENUM("Digital Interface DA 1 From Slot Map", soc_enum_da1slotmap),
1399 SOC_ENUM("Digital Interface DA 2 From Slot Map", soc_enum_da2slotmap),
1400 SOC_ENUM("Digital Interface DA 3 From Slot Map", soc_enum_da3slotmap),
1401 SOC_ENUM("Digital Interface DA 4 From Slot Map", soc_enum_da4slotmap),
1402 SOC_ENUM("Digital Interface DA 5 From Slot Map", soc_enum_da5slotmap),
1403 SOC_ENUM("Digital Interface DA 6 From Slot Map", soc_enum_da6slotmap),
1404 SOC_ENUM("Digital Interface DA 7 From Slot Map", soc_enum_da7slotmap),
1405 SOC_ENUM("Digital Interface DA 8 From Slot Map", soc_enum_da8slotmap),
1406
1407 /* Digital interface - AD to slot mapping */
1408 SOC_ENUM("Digital Interface AD To Slot 0 Map", soc_enum_adslot0map),
1409 SOC_ENUM("Digital Interface AD To Slot 1 Map", soc_enum_adslot1map),
1410 SOC_ENUM("Digital Interface AD To Slot 2 Map", soc_enum_adslot2map),
1411 SOC_ENUM("Digital Interface AD To Slot 3 Map", soc_enum_adslot3map),
1412 SOC_ENUM("Digital Interface AD To Slot 4 Map", soc_enum_adslot4map),
1413 SOC_ENUM("Digital Interface AD To Slot 5 Map", soc_enum_adslot5map),
1414 SOC_ENUM("Digital Interface AD To Slot 6 Map", soc_enum_adslot6map),
1415 SOC_ENUM("Digital Interface AD To Slot 7 Map", soc_enum_adslot7map),
1416 SOC_ENUM("Digital Interface AD To Slot 8 Map", soc_enum_adslot8map),
1417 SOC_ENUM("Digital Interface AD To Slot 9 Map", soc_enum_adslot9map),
1418 SOC_ENUM("Digital Interface AD To Slot 10 Map", soc_enum_adslot10map),
1419 SOC_ENUM("Digital Interface AD To Slot 11 Map", soc_enum_adslot11map),
1420 SOC_ENUM("Digital Interface AD To Slot 12 Map", soc_enum_adslot12map),
1421 SOC_ENUM("Digital Interface AD To Slot 13 Map", soc_enum_adslot13map),
1422 SOC_ENUM("Digital Interface AD To Slot 14 Map", soc_enum_adslot14map),
1423 SOC_ENUM("Digital Interface AD To Slot 15 Map", soc_enum_adslot15map),
1424 SOC_ENUM("Digital Interface AD To Slot 16 Map", soc_enum_adslot16map),
1425 SOC_ENUM("Digital Interface AD To Slot 17 Map", soc_enum_adslot17map),
1426 SOC_ENUM("Digital Interface AD To Slot 18 Map", soc_enum_adslot18map),
1427 SOC_ENUM("Digital Interface AD To Slot 19 Map", soc_enum_adslot19map),
1428 SOC_ENUM("Digital Interface AD To Slot 20 Map", soc_enum_adslot20map),
1429 SOC_ENUM("Digital Interface AD To Slot 21 Map", soc_enum_adslot21map),
1430 SOC_ENUM("Digital Interface AD To Slot 22 Map", soc_enum_adslot22map),
1431 SOC_ENUM("Digital Interface AD To Slot 23 Map", soc_enum_adslot23map),
1432 SOC_ENUM("Digital Interface AD To Slot 24 Map", soc_enum_adslot24map),
1433 SOC_ENUM("Digital Interface AD To Slot 25 Map", soc_enum_adslot25map),
1434 SOC_ENUM("Digital Interface AD To Slot 26 Map", soc_enum_adslot26map),
1435 SOC_ENUM("Digital Interface AD To Slot 27 Map", soc_enum_adslot27map),
1436 SOC_ENUM("Digital Interface AD To Slot 28 Map", soc_enum_adslot28map),
1437 SOC_ENUM("Digital Interface AD To Slot 29 Map", soc_enum_adslot29map),
1438 SOC_ENUM("Digital Interface AD To Slot 30 Map", soc_enum_adslot30map),
1439 SOC_ENUM("Digital Interface AD To Slot 31 Map", soc_enum_adslot31map),
1440
1441 /* Digital interface - Loopback */
1442 SOC_SINGLE("Digital Interface AD 1 Loopback Switch",
1443 AB8500_DASLOTCONF1, AB8500_DASLOTCONF1_DAI7TOADO1,
1444 1, 0),
1445 SOC_SINGLE("Digital Interface AD 2 Loopback Switch",
1446 AB8500_DASLOTCONF2, AB8500_DASLOTCONF2_DAI8TOADO2,
1447 1, 0),
1448 SOC_SINGLE("Digital Interface AD 3 Loopback Switch",
1449 AB8500_DASLOTCONF3, AB8500_DASLOTCONF3_DAI7TOADO3,
1450 1, 0),
1451 SOC_SINGLE("Digital Interface AD 4 Loopback Switch",
1452 AB8500_DASLOTCONF4, AB8500_DASLOTCONF4_DAI8TOADO4,
1453 1, 0),
1454 SOC_SINGLE("Digital Interface AD 5 Loopback Switch",
1455 AB8500_DASLOTCONF5, AB8500_DASLOTCONF5_DAI7TOADO5,
1456 1, 0),
1457 SOC_SINGLE("Digital Interface AD 6 Loopback Switch",
1458 AB8500_DASLOTCONF6, AB8500_DASLOTCONF6_DAI8TOADO6,
1459 1, 0),
1460 SOC_SINGLE("Digital Interface AD 7 Loopback Switch",
1461 AB8500_DASLOTCONF7, AB8500_DASLOTCONF7_DAI8TOADO7,
1462 1, 0),
1463 SOC_SINGLE("Digital Interface AD 8 Loopback Switch",
1464 AB8500_DASLOTCONF8, AB8500_DASLOTCONF8_DAI7TOADO8,
1465 1, 0),
1466
1467 /* Digital interface - Burst FIFO */
1468 SOC_SINGLE("Digital Interface 0 FIFO Enable Switch",
1469 AB8500_DIGIFCONF3, AB8500_DIGIFCONF3_IF0BFIFOEN,
1470 1, 0),
1471 SOC_ENUM("Burst FIFO Mask", soc_enum_bfifomask),
1472 SOC_ENUM("Burst FIFO Bit-clock Frequency", soc_enum_bfifo19m2),
1473 SOC_SINGLE("Burst FIFO Threshold",
1474 AB8500_FIFOCONF1, AB8500_FIFOCONF1_BFIFOINT_SHIFT,
1475 AB8500_FIFOCONF1_BFIFOINT_MAX, 0),
1476 SOC_SINGLE("Burst FIFO Length",
1477 AB8500_FIFOCONF2, AB8500_FIFOCONF2_BFIFOTX_SHIFT,
1478 AB8500_FIFOCONF2_BFIFOTX_MAX, 0),
1479 SOC_SINGLE("Burst FIFO EOS Extra Slots",
1480 AB8500_FIFOCONF3, AB8500_FIFOCONF3_BFIFOEXSL_SHIFT,
1481 AB8500_FIFOCONF3_BFIFOEXSL_MAX, 0),
1482 SOC_SINGLE("Burst FIFO FS Extra Bit-clocks",
1483 AB8500_FIFOCONF3, AB8500_FIFOCONF3_PREBITCLK0_SHIFT,
1484 AB8500_FIFOCONF3_PREBITCLK0_MAX, 0),
1485 SOC_ENUM("Burst FIFO Interface Mode", soc_enum_bfifomast),
1486
1487 SOC_SINGLE("Burst FIFO Interface Switch",
1488 AB8500_FIFOCONF3, AB8500_FIFOCONF3_BFIFORUN_SHIFT,
1489 1, 0),
1490 SOC_SINGLE("Burst FIFO Switch Frame Number",
1491 AB8500_FIFOCONF4, AB8500_FIFOCONF4_BFIFOFRAMSW_SHIFT,
1492 AB8500_FIFOCONF4_BFIFOFRAMSW_MAX, 0),
1493 SOC_SINGLE("Burst FIFO Wake Up Delay",
1494 AB8500_FIFOCONF5, AB8500_FIFOCONF5_BFIFOWAKEUP_SHIFT,
1495 AB8500_FIFOCONF5_BFIFOWAKEUP_MAX, 0),
1496 SOC_SINGLE("Burst FIFO Samples In FIFO",
1497 AB8500_FIFOCONF6, AB8500_FIFOCONF6_BFIFOSAMPLE_SHIFT,
1498 AB8500_FIFOCONF6_BFIFOSAMPLE_MAX, 0),
1499
1500 /* ANC */
1501 SOC_SINGLE_XR_SX("ANC Warp Delay Shift",
1502 AB8500_ANCCONF2, 1, AB8500_ANCCONF2_SHIFT,
1503 AB8500_ANCCONF2_MIN, AB8500_ANCCONF2_MAX, 0),
1504 SOC_SINGLE_XR_SX("ANC FIR Output Shift",
1505 AB8500_ANCCONF3, 1, AB8500_ANCCONF3_SHIFT,
1506 AB8500_ANCCONF3_MIN, AB8500_ANCCONF3_MAX, 0),
1507 SOC_SINGLE_XR_SX("ANC IIR Output Shift",
1508 AB8500_ANCCONF4, 1, AB8500_ANCCONF4_SHIFT,
1509 AB8500_ANCCONF4_MIN, AB8500_ANCCONF4_MAX, 0),
1510 SOC_SINGLE_XR_SX("ANC Warp Delay",
1511 AB8500_ANCCONF9, 2, AB8500_ANC_WARP_DELAY_SHIFT,
1512 AB8500_ANC_WARP_DELAY_MIN, AB8500_ANC_WARP_DELAY_MAX, 0),
1513
1514 /* Sidetone */
1515 SOC_SINGLE_STROBE("Sidetone Reset",
1516 AB8500_SIDFIRADR, AB8500_SIDFIRADR_FIRSIDSET, 0),
1517 };
1518
1519 /*
1520 * Extended interface for codec-driver
1521 */
1522
ab8500_audio_init_audioblock(struct snd_soc_component * component)1523 static int ab8500_audio_init_audioblock(struct snd_soc_component *component)
1524 {
1525 int status;
1526 u8 mask = AB8500_STW4500CTRL3_CLK32KOUT2DIS |
1527 AB8500_STW4500CTRL3_RESETAUDN;
1528
1529 dev_dbg(component->dev, "%s: Enter.\n", __func__);
1530
1531 /* Reset the audio registers and disable the unused 32 kHz output. */
1532 status = ab8500_sysctrl_write(AB8500_STW4500CTRL3, mask,
1533 AB8500_STW4500CTRL3_CLK32KOUT2DIS);
1534 if (status < 0)
1535 return status;
1536
1537 return ab8500_sysctrl_write(AB8500_STW4500CTRL3, mask, mask);
1538 }
1539
ab8500_audio_setup_mics(struct snd_soc_component * component,struct amic_settings * amics)1540 static int ab8500_audio_setup_mics(struct snd_soc_component *component,
1541 struct amic_settings *amics)
1542 {
1543 struct device *dev = component->dev;
1544 struct ab8500 *ab8500 = dev_get_drvdata(dev->parent);
1545 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
1546 u8 value8;
1547 unsigned int value;
1548 int status;
1549 const struct snd_soc_dapm_route *route;
1550
1551 dev_dbg(component->dev, "%s: Enter.\n", __func__);
1552
1553 /* Set DMic-clocks to outputs; these GPIOs do not exist on AB8505. */
1554 if (!is_ab8505(ab8500)) {
1555 status = abx500_get_register_interruptible(dev, AB8500_MISC,
1556 AB8500_GPIO_DIR4_REG,
1557 &value8);
1558 if (status < 0)
1559 return status;
1560 value = value8 | GPIO27_DIR_OUTPUT | GPIO29_DIR_OUTPUT |
1561 GPIO31_DIR_OUTPUT;
1562 status = abx500_set_register_interruptible(dev, AB8500_MISC,
1563 AB8500_GPIO_DIR4_REG,
1564 value);
1565 if (status < 0)
1566 return status;
1567 }
1568
1569 /* Attach regulators to AMic DAPM-paths */
1570 dev_dbg(component->dev, "%s: Mic 1a regulator: %s\n", __func__,
1571 amic_micbias_str(amics->mic1a_micbias));
1572 route = &ab8500_dapm_routes_mic1a_vamicx[amics->mic1a_micbias];
1573 status = snd_soc_dapm_add_routes(dapm, route, 1);
1574 dev_dbg(component->dev, "%s: Mic 1b regulator: %s\n", __func__,
1575 amic_micbias_str(amics->mic1b_micbias));
1576 route = &ab8500_dapm_routes_mic1b_vamicx[amics->mic1b_micbias];
1577 status |= snd_soc_dapm_add_routes(dapm, route, 1);
1578 dev_dbg(component->dev, "%s: Mic 2 regulator: %s\n", __func__,
1579 amic_micbias_str(amics->mic2_micbias));
1580 route = &ab8500_dapm_routes_mic2_vamicx[amics->mic2_micbias];
1581 status |= snd_soc_dapm_add_routes(dapm, route, 1);
1582 if (status < 0) {
1583 dev_err(component->dev,
1584 "%s: Failed to add AMic-regulator DAPM-routes (%d).\n",
1585 __func__, status);
1586 return status;
1587 }
1588
1589 /* Set AMic-configuration */
1590 dev_dbg(component->dev, "%s: Mic 1 mic-type: %s\n", __func__,
1591 amic_type_str(amics->mic1_type));
1592 snd_soc_component_update_bits(component, AB8500_ANAGAIN1, AB8500_ANAGAINX_ENSEMICX,
1593 amics->mic1_type == AMIC_TYPE_DIFFERENTIAL ?
1594 0 : AB8500_ANAGAINX_ENSEMICX);
1595 dev_dbg(component->dev, "%s: Mic 2 mic-type: %s\n", __func__,
1596 amic_type_str(amics->mic2_type));
1597 snd_soc_component_update_bits(component, AB8500_ANAGAIN2, AB8500_ANAGAINX_ENSEMICX,
1598 amics->mic2_type == AMIC_TYPE_DIFFERENTIAL ?
1599 0 : AB8500_ANAGAINX_ENSEMICX);
1600
1601 return 0;
1602 }
1603
ab8500_audio_set_ear_cmv(struct snd_soc_component * component,enum ear_cm_voltage ear_cmv)1604 static int ab8500_audio_set_ear_cmv(struct snd_soc_component *component,
1605 enum ear_cm_voltage ear_cmv)
1606 {
1607 char *cmv_str;
1608
1609 switch (ear_cmv) {
1610 case EAR_CMV_0_95V:
1611 cmv_str = "0.95V";
1612 break;
1613 case EAR_CMV_1_10V:
1614 cmv_str = "1.10V";
1615 break;
1616 case EAR_CMV_1_27V:
1617 cmv_str = "1.27V";
1618 break;
1619 case EAR_CMV_1_58V:
1620 cmv_str = "1.58V";
1621 break;
1622 default:
1623 dev_err(component->dev,
1624 "%s: Unknown earpiece CM-voltage (%d)!\n",
1625 __func__, (int)ear_cmv);
1626 return -EINVAL;
1627 }
1628 dev_dbg(component->dev, "%s: Earpiece CM-voltage: %s\n", __func__,
1629 cmv_str);
1630 snd_soc_component_update_bits(component, AB8500_ANACONF1, AB8500_ANACONF1_EARSELCM,
1631 ear_cmv);
1632
1633 return 0;
1634 }
1635
ab8500_codec_set_dai_fmt(struct snd_soc_dai * dai,unsigned int fmt)1636 static int ab8500_codec_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1637 {
1638 struct snd_soc_component *component = dai->component;
1639 unsigned int conf1_mask, conf1_val = 0;
1640 unsigned int conf2_mask, conf2_val = 0;
1641 unsigned int conf3_mask, conf3_val = 0;
1642 bool provider = false;
1643 int ret;
1644
1645 dev_dbg(component->dev, "%s: Enter (fmt = 0x%x)\n", __func__, fmt);
1646
1647 conf3_mask = BIT(AB8500_DIGIFCONF3_IF1DATOIF0AD) |
1648 BIT(AB8500_DIGIFCONF3_IF1CLKTOIF0CLK) |
1649 BIT(AB8500_DIGIFCONF3_IF0BFIFOEN) |
1650 BIT(AB8500_DIGIFCONF3_IF0MASTER);
1651
1652 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
1653 case SND_SOC_DAIFMT_CBP_CFP:
1654 dev_dbg(component->dev,
1655 "%s: IF0 Master-mode: AB8500 provider.\n", __func__);
1656 conf3_val |= BIT(AB8500_DIGIFCONF3_IF0MASTER);
1657 provider = true;
1658 break;
1659 case SND_SOC_DAIFMT_CBC_CFC:
1660 dev_dbg(component->dev,
1661 "%s: IF0 Master-mode: AB8500 consumer.\n", __func__);
1662 break;
1663 case SND_SOC_DAIFMT_CBC_CFP:
1664 case SND_SOC_DAIFMT_CBP_CFC:
1665 dev_err(component->dev,
1666 "%s: ERROR: The device is either a provider or a consumer.\n",
1667 __func__);
1668 fallthrough;
1669 default:
1670 dev_err(component->dev,
1671 "%s: ERROR: Unsupported clocking mask 0x%x\n",
1672 __func__, fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK);
1673 return -EINVAL;
1674 }
1675
1676 conf1_mask = BIT(AB8500_DIGIFCONF1_ENMASTGEN) |
1677 BIT(AB8500_DIGIFCONF1_ENFSBITCLK0);
1678 switch (fmt & SND_SOC_DAIFMT_CLOCK_MASK) {
1679 case SND_SOC_DAIFMT_CONT:
1680 if (provider)
1681 conf1_val = conf1_mask;
1682 break;
1683 case SND_SOC_DAIFMT_GATED:
1684 if (provider)
1685 conf1_val = BIT(AB8500_DIGIFCONF1_ENMASTGEN);
1686 break;
1687 default:
1688 dev_err(component->dev, "%s: Unsupported clock mask 0x%x\n",
1689 __func__, fmt & SND_SOC_DAIFMT_CLOCK_MASK);
1690 return -EINVAL;
1691 }
1692
1693 conf2_mask = BIT(AB8500_DIGIFCONF2_IF0FORMAT0) |
1694 BIT(AB8500_DIGIFCONF2_IF0FORMAT1) |
1695 BIT(AB8500_DIGIFCONF2_IF0DEL) |
1696 BIT(AB8500_DIGIFCONF2_FSYNC0P) |
1697 BIT(AB8500_DIGIFCONF2_BITCLK0P);
1698
1699 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1700 case SND_SOC_DAIFMT_I2S: /* I2S mode */
1701 dev_dbg(component->dev, "%s: IF0 Protocol: I2S\n", __func__);
1702 conf2_val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT1) |
1703 BIT(AB8500_DIGIFCONF2_IF0DEL);
1704 break;
1705
1706 case SND_SOC_DAIFMT_DSP_A: /* L data MSB after FRM LRC */
1707 dev_dbg(component->dev,
1708 "%s: IF0 Protocol: DSP A (TDM)\n", __func__);
1709 conf2_val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT0) |
1710 BIT(AB8500_DIGIFCONF2_IF0DEL);
1711 break;
1712
1713 case SND_SOC_DAIFMT_DSP_B: /* L data MSB during FRM LRC */
1714 dev_dbg(component->dev,
1715 "%s: IF0 Protocol: DSP B (TDM)\n", __func__);
1716 conf2_val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT0);
1717 break;
1718
1719 default:
1720 dev_err(component->dev,
1721 "%s: ERROR: Unsupported format (0x%x)!\n",
1722 __func__, fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1723 return -EINVAL;
1724 }
1725
1726 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1727 case SND_SOC_DAIFMT_NB_NF: /* normal bit clock + frame */
1728 dev_dbg(component->dev,
1729 "%s: IF0: Normal bit clock, normal frame\n",
1730 __func__);
1731 break;
1732 case SND_SOC_DAIFMT_NB_IF: /* normal BCLK + inv FRM */
1733 dev_dbg(component->dev,
1734 "%s: IF0: Normal bit clock, inverted frame\n",
1735 __func__);
1736 conf2_val |= BIT(AB8500_DIGIFCONF2_FSYNC0P);
1737 break;
1738 case SND_SOC_DAIFMT_IB_NF: /* invert BCLK + nor FRM */
1739 dev_dbg(component->dev,
1740 "%s: IF0: Inverted bit clock, normal frame\n",
1741 __func__);
1742 conf2_val |= BIT(AB8500_DIGIFCONF2_BITCLK0P);
1743 break;
1744 case SND_SOC_DAIFMT_IB_IF: /* invert BCLK + FRM */
1745 dev_dbg(component->dev,
1746 "%s: IF0: Inverted bit clock, inverted frame\n",
1747 __func__);
1748 conf2_val |= BIT(AB8500_DIGIFCONF2_FSYNC0P) |
1749 BIT(AB8500_DIGIFCONF2_BITCLK0P);
1750 break;
1751 default:
1752 dev_err(component->dev,
1753 "%s: ERROR: Unsupported INV mask 0x%x\n",
1754 __func__, fmt & SND_SOC_DAIFMT_INV_MASK);
1755 return -EINVAL;
1756 }
1757
1758 ret = snd_soc_component_update_bits(component, AB8500_DIGIFCONF3,
1759 conf3_mask, conf3_val);
1760 if (ret < 0)
1761 return ret;
1762
1763 ret = snd_soc_component_update_bits(component, AB8500_DIGIFCONF1,
1764 conf1_mask, conf1_val);
1765 if (ret < 0)
1766 return ret;
1767
1768 ret = snd_soc_component_update_bits(component, AB8500_DIGIFCONF2,
1769 conf2_mask, conf2_val);
1770
1771 return ret < 0 ? ret : 0;
1772 }
1773
ab8500_codec_set_dai_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)1774 static int ab8500_codec_set_dai_tdm_slot(struct snd_soc_dai *dai,
1775 unsigned int tx_mask, unsigned int rx_mask,
1776 int slots, int slot_width)
1777 {
1778 struct snd_soc_component *component = dai->component;
1779 unsigned int active_mask, clock_ratio, slot, value, ad_out, reg;
1780 unsigned int tx_active, rx_active;
1781 unsigned int conf1_val, conf2_val;
1782 unsigned int mask;
1783 int channel, ret;
1784
1785 mask = BIT(AB8500_DIGIFCONF2_IF0WL0) |
1786 BIT(AB8500_DIGIFCONF2_IF0WL1);
1787 conf2_val = 0;
1788
1789 switch (slot_width) {
1790 case 16:
1791 break;
1792 case 20:
1793 conf2_val |= BIT(AB8500_DIGIFCONF2_IF0WL0);
1794 break;
1795 case 24:
1796 conf2_val |= BIT(AB8500_DIGIFCONF2_IF0WL1);
1797 break;
1798 case 32:
1799 conf2_val |= BIT(AB8500_DIGIFCONF2_IF0WL1) |
1800 BIT(AB8500_DIGIFCONF2_IF0WL0);
1801 break;
1802 default:
1803 dev_err(dai->component->dev, "%s: Unsupported slot-width 0x%x\n",
1804 __func__, slot_width);
1805 return -EINVAL;
1806 }
1807
1808 switch (slots) {
1809 case 2:
1810 case 4:
1811 case 8:
1812 case 16:
1813 break;
1814 default:
1815 dev_err(dai->component->dev,
1816 "%s: ERROR: Unsupported number of slots (%d)!\n",
1817 __func__, slots);
1818 return -EINVAL;
1819 }
1820
1821 clock_ratio = slots * slot_width;
1822 switch (clock_ratio) {
1823 case 32:
1824 conf1_val = 0;
1825 break;
1826 case 64:
1827 conf1_val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0);
1828 break;
1829 case 128:
1830 conf1_val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1);
1831 break;
1832 case 256:
1833 conf1_val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0) |
1834 BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1);
1835 break;
1836 default:
1837 dev_err(component->dev, "%s: Unsupported BCLK ratio (%u)!\n",
1838 __func__, clock_ratio);
1839 return -EINVAL;
1840 }
1841
1842 active_mask = GENMASK(min(slots, 8) - 1, 0);
1843 if ((tx_mask | rx_mask) & ~active_mask) {
1844 dev_err(component->dev, "%s: Slot mask exceeds slot count\n",
1845 __func__);
1846 return -EINVAL;
1847 }
1848
1849 tx_active = hweight32(tx_mask);
1850 rx_active = hweight32(rx_mask);
1851 if (tx_active != 0 && tx_active != 1 && tx_active != 2 &&
1852 tx_active != 8) {
1853 dev_err(component->dev, "%s: Unsupported active TX slots (%u)!\n",
1854 __func__, tx_active);
1855 return -EINVAL;
1856 }
1857 if (rx_active != 0 && rx_active != 1 && rx_active != 2 &&
1858 rx_active != 8) {
1859 dev_err(component->dev, "%s: Unsupported active RX slots (%u)!\n",
1860 __func__, rx_active);
1861 return -EINVAL;
1862 }
1863
1864 dev_dbg(component->dev,
1865 "%s: %d slots of %d bits, TX active: %u, RX active: %u\n",
1866 __func__, slots, slot_width, tx_active, rx_active);
1867
1868 ret = snd_soc_component_update_bits(component, AB8500_DIGIFCONF2,
1869 mask, conf2_val);
1870 if (ret < 0)
1871 return ret;
1872
1873 mask = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0) |
1874 BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1);
1875 ret = snd_soc_component_update_bits(component, AB8500_DIGIFCONF1,
1876 mask, conf1_val);
1877 if (ret < 0)
1878 return ret;
1879
1880 mask = AB8500_DASLOTCONFX_SLTODAX_MASK;
1881 if (tx_active == 1 || tx_active == 2) {
1882 slot = __ffs(tx_mask) + AB8500_DA_DATA0_OFFSET;
1883 reg = AB8500_DASLOTCONF1;
1884 ret = snd_soc_component_update_bits(component, reg, mask, slot);
1885 if (ret < 0)
1886 return ret;
1887 reg = AB8500_DASLOTCONF3;
1888 ret = snd_soc_component_update_bits(component, reg, mask, slot);
1889 if (ret < 0)
1890 return ret;
1891
1892 if (tx_active == 2)
1893 slot = __fls(tx_mask) + AB8500_DA_DATA0_OFFSET;
1894 reg = AB8500_DASLOTCONF2;
1895 ret = snd_soc_component_update_bits(component, reg, mask, slot);
1896 if (ret < 0)
1897 return ret;
1898 reg = AB8500_DASLOTCONF4;
1899 ret = snd_soc_component_update_bits(component, reg, mask, slot);
1900 if (ret < 0)
1901 return ret;
1902 } else if (tx_active == 8) {
1903 channel = 0;
1904 for (slot = 0; slot < 8; slot++) {
1905 if (!(tx_mask & BIT(slot)))
1906 continue;
1907 reg = AB8500_DASLOTCONF1 + channel++;
1908 value = slot + AB8500_DA_DATA0_OFFSET;
1909 ret = snd_soc_component_update_bits(component, reg, mask, value);
1910 if (ret < 0)
1911 return ret;
1912 }
1913 }
1914
1915 if (rx_active == 1 || rx_active == 2) {
1916 slot = __ffs(rx_mask) + AB8500_AD_DATA0_OFFSET;
1917 value = AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(AB8500_AD_OUT3,
1918 slot);
1919 reg = AB8500_ADSLOTSEL(slot);
1920 mask = AB8500_MASK_SLOT(slot);
1921 ret = snd_soc_component_update_bits(component, reg, mask, value);
1922 if (ret < 0)
1923 return ret;
1924
1925 if (rx_active == 2) {
1926 slot = __fls(rx_mask) + AB8500_AD_DATA0_OFFSET;
1927 value = AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(AB8500_AD_OUT2,
1928 slot);
1929 reg = AB8500_ADSLOTSEL(slot);
1930 mask = AB8500_MASK_SLOT(slot);
1931 ret = snd_soc_component_update_bits(component, reg, mask, value);
1932 if (ret < 0)
1933 return ret;
1934 }
1935 } else if (rx_active == 8) {
1936 channel = 0;
1937 for (slot = 0; slot < 8; slot++) {
1938 if (!(rx_mask & BIT(slot)))
1939 continue;
1940 ad_out = AB8500_AD_OUT1 + channel++;
1941 value = AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(ad_out, slot);
1942 reg = AB8500_ADSLOTSEL(slot);
1943 mask = AB8500_MASK_SLOT(slot);
1944 ret = snd_soc_component_update_bits(component, reg, mask, value);
1945 if (ret < 0)
1946 return ret;
1947 }
1948 }
1949
1950 return 0;
1951 }
1952
1953 static const struct snd_soc_dai_ops ab8500_codec_ops = {
1954 .set_fmt = ab8500_codec_set_dai_fmt,
1955 .set_tdm_slot = ab8500_codec_set_dai_tdm_slot,
1956 };
1957
1958 static struct snd_soc_dai_driver ab8500_codec_dai[] = {
1959 {
1960 .name = "ab8500-codec-dai.0",
1961 .id = 0,
1962 .playback = {
1963 .stream_name = "ab8500_0p",
1964 .channels_min = 1,
1965 .channels_max = 8,
1966 .rates = AB8500_SUPPORTED_RATE,
1967 .formats = AB8500_SUPPORTED_FMT,
1968 },
1969 .ops = &ab8500_codec_ops,
1970 .symmetric_rate = 1
1971 },
1972 {
1973 .name = "ab8500-codec-dai.1",
1974 .id = 1,
1975 .capture = {
1976 .stream_name = "ab8500_0c",
1977 .channels_min = 1,
1978 .channels_max = 8,
1979 .rates = AB8500_SUPPORTED_RATE,
1980 .formats = AB8500_SUPPORTED_FMT,
1981 },
1982 .ops = &ab8500_codec_ops,
1983 .symmetric_rate = 1
1984 }
1985 };
1986
ab8500_codec_of_probe(struct device * dev,struct device_node * np,struct ab8500_codec_platform_data * codec)1987 static void ab8500_codec_of_probe(struct device *dev, struct device_node *np,
1988 struct ab8500_codec_platform_data *codec)
1989 {
1990 u32 value;
1991
1992 if (of_property_read_bool(np, "stericsson,amic1-type-single-ended"))
1993 codec->amics.mic1_type = AMIC_TYPE_SINGLE_ENDED;
1994 else
1995 codec->amics.mic1_type = AMIC_TYPE_DIFFERENTIAL;
1996
1997 if (of_property_read_bool(np, "stericsson,amic2-type-single-ended"))
1998 codec->amics.mic2_type = AMIC_TYPE_SINGLE_ENDED;
1999 else
2000 codec->amics.mic2_type = AMIC_TYPE_DIFFERENTIAL;
2001
2002 /* Has a non-standard Vamic been requested? */
2003 if (of_property_read_bool(np, "stericsson,amic1a-bias-vamic2"))
2004 codec->amics.mic1a_micbias = AMIC_MICBIAS_VAMIC2;
2005 else
2006 codec->amics.mic1a_micbias = AMIC_MICBIAS_VAMIC1;
2007
2008 if (of_property_read_bool(np, "stericsson,amic1b-bias-vamic2"))
2009 codec->amics.mic1b_micbias = AMIC_MICBIAS_VAMIC2;
2010 else
2011 codec->amics.mic1b_micbias = AMIC_MICBIAS_VAMIC1;
2012
2013 if (of_property_read_bool(np, "stericsson,amic2-bias-vamic1"))
2014 codec->amics.mic2_micbias = AMIC_MICBIAS_VAMIC1;
2015 else
2016 codec->amics.mic2_micbias = AMIC_MICBIAS_VAMIC2;
2017
2018 if (!of_property_read_u32(np, "stericsson,earpeice-cmv", &value)) {
2019 switch (value) {
2020 case 950 :
2021 codec->ear_cmv = EAR_CMV_0_95V;
2022 break;
2023 case 1100 :
2024 codec->ear_cmv = EAR_CMV_1_10V;
2025 break;
2026 case 1270 :
2027 codec->ear_cmv = EAR_CMV_1_27V;
2028 break;
2029 case 1580 :
2030 codec->ear_cmv = EAR_CMV_1_58V;
2031 break;
2032 default :
2033 codec->ear_cmv = EAR_CMV_UNKNOWN;
2034 dev_err(dev, "Unsuitable earpiece voltage found in DT\n");
2035 }
2036 } else {
2037 dev_warn(dev, "No earpiece voltage found in DT - using default\n");
2038 codec->ear_cmv = EAR_CMV_0_95V;
2039 }
2040 }
2041
ab8500_codec_probe(struct snd_soc_component * component)2042 static int ab8500_codec_probe(struct snd_soc_component *component)
2043 {
2044 struct device *dev = component->dev;
2045 struct device_node *np = dev->of_node;
2046 struct ab8500_codec_platform_data codec_pdata;
2047 int status;
2048
2049 dev_dbg(dev, "%s: Enter.\n", __func__);
2050
2051 ab8500_codec_of_probe(dev, np, &codec_pdata);
2052
2053 status = ab8500_audio_init_audioblock(component);
2054 if (status < 0) {
2055 dev_err(dev, "%s: failed to init audio-block (%d)!\n",
2056 __func__, status);
2057 return status;
2058 }
2059
2060 status = ab8500_audio_setup_mics(component, &codec_pdata.amics);
2061 if (status < 0) {
2062 pr_err("%s: Failed to setup mics (%d)!\n", __func__, status);
2063 return status;
2064 }
2065 status = ab8500_audio_set_ear_cmv(component, codec_pdata.ear_cmv);
2066 if (status < 0) {
2067 pr_err("%s: Failed to set earpiece CM-voltage (%d)!\n",
2068 __func__, status);
2069 return status;
2070 }
2071
2072 /* Override HW-defaults */
2073 snd_soc_component_write(component, AB8500_ANACONF5,
2074 BIT(AB8500_ANACONF5_HSAUTOEN));
2075 snd_soc_component_write(component, AB8500_SHORTCIRCONF,
2076 BIT(AB8500_SHORTCIRCONF_HSZCDDIS));
2077
2078 return status;
2079 }
2080
2081 static const struct snd_soc_component_driver ab8500_component_driver = {
2082 .probe = ab8500_codec_probe,
2083 .controls = ab8500_ctrls,
2084 .num_controls = ARRAY_SIZE(ab8500_ctrls),
2085 .dapm_widgets = ab8500_dapm_widgets,
2086 .num_dapm_widgets = ARRAY_SIZE(ab8500_dapm_widgets),
2087 .dapm_routes = ab8500_dapm_routes,
2088 .num_dapm_routes = ARRAY_SIZE(ab8500_dapm_routes),
2089 .idle_bias_on = 1,
2090 .use_pmdown_time = 1,
2091 .endianness = 1,
2092 };
2093
ab8500_codec_driver_probe(struct platform_device * pdev)2094 static int ab8500_codec_driver_probe(struct platform_device *pdev)
2095 {
2096 int status;
2097 struct ab8500_codec_drvdata *drvdata;
2098
2099 dev_dbg(&pdev->dev, "%s: Enter.\n", __func__);
2100
2101 /* Create driver private-data struct */
2102 drvdata = devm_kzalloc(&pdev->dev, sizeof(struct ab8500_codec_drvdata),
2103 GFP_KERNEL);
2104 if (!drvdata)
2105 return -ENOMEM;
2106 dev_set_drvdata(&pdev->dev, drvdata);
2107
2108 drvdata->regmap = devm_regmap_init(&pdev->dev, NULL, &pdev->dev,
2109 &ab8500_codec_regmap);
2110 if (IS_ERR(drvdata->regmap)) {
2111 status = PTR_ERR(drvdata->regmap);
2112 dev_err(&pdev->dev, "%s: Failed to allocate regmap: %d\n",
2113 __func__, status);
2114 return status;
2115 }
2116
2117 dev_dbg(&pdev->dev, "%s: Register codec.\n", __func__);
2118 status = devm_snd_soc_register_component(&pdev->dev,
2119 &ab8500_component_driver,
2120 ab8500_codec_dai,
2121 ARRAY_SIZE(ab8500_codec_dai));
2122 if (status < 0)
2123 dev_err(&pdev->dev,
2124 "%s: Error: Failed to register codec (%d).\n",
2125 __func__, status);
2126
2127 return status;
2128 }
2129
2130 static struct platform_driver ab8500_codec_platform_driver = {
2131 .driver = {
2132 .name = "ab8500-codec",
2133 },
2134 .probe = ab8500_codec_driver_probe,
2135 };
2136 module_platform_driver(ab8500_codec_platform_driver);
2137
2138 MODULE_DESCRIPTION("ASoC AB8500 codec driver");
2139 MODULE_LICENSE("GPL v2");
2140