1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Renesas RZ/V2H Renesas Serial Peripheral Interface (RSPI)
4 *
5 * Copyright (C) 2025 Renesas Electronics Corporation
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/bitops.h>
10 #include <linux/bits.h>
11 #include <linux/clk.h>
12 #include <linux/dmaengine.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/limits.h>
16 #include <linux/log2.h>
17 #include <linux/math.h>
18 #include <linux/of.h>
19 #include <linux/platform_device.h>
20 #include <linux/property.h>
21 #include <linux/reset.h>
22 #include <linux/spi/spi.h>
23 #include <linux/wait.h>
24
25 #include "internals.h"
26
27 /* Registers */
28 #define RSPI_SPDR 0x00
29 #define RSPI_SPCR 0x08
30 #define RSPI_SPPCR 0x0e
31 #define RSPI_SSLP 0x10
32 #define RSPI_SPBR 0x11
33 #define RSPI_SPSCR 0x13
34 #define RSPI_SPCMD 0x14
35 #define RSPI_SPDCR2 0x44
36 #define RSPI_SPSR 0x52
37 #define RSPI_SPSRC 0x6a
38 #define RSPI_SPFCR 0x6c
39
40 /* Register SPCR */
41 #define RSPI_SPCR_BPEN BIT(31)
42 #define RSPI_SPCR_MSTR BIT(30)
43 #define RSPI_SPCR_SPTIE BIT(20)
44 #define RSPI_SPCR_SPRIE BIT(17)
45 #define RSPI_SPCR_SCKASE BIT(12)
46 #define RSPI_SPCR_SPE BIT(0)
47
48 /* Register SPPCR */
49 #define RSPI_SPPCR_SPLP2 BIT(1)
50
51 /* Register SPBR */
52 #define RSPI_SPBR_SPR_MIN 0
53 #define RSPI_SPBR_SPR_MAX 255
54
55 /* Register SPCMD */
56 #define RSPI_SPCMD_SSLA GENMASK(25, 24)
57 #define RSPI_SPCMD_SPB GENMASK(20, 16)
58 #define RSPI_SPCMD_LSBF BIT(12)
59 #define RSPI_SPCMD_SSLKP BIT(7)
60 #define RSPI_SPCMD_BRDV GENMASK(3, 2)
61 #define RSPI_SPCMD_CPOL BIT(1)
62 #define RSPI_SPCMD_CPHA BIT(0)
63
64 #define RSPI_SPCMD_BRDV_MIN 0
65 #define RSPI_SPCMD_BRDV_MAX 3
66
67 /* Register SPDCR2 */
68 #define RSPI_SPDCR2_TTRG GENMASK(11, 8)
69 #define RSPI_SPDCR2_RTRG GENMASK(3, 0)
70
71 /* Register SPSR */
72 #define RSPI_SPSR_SPRF BIT(15)
73
74 /* Register RSPI_SPSRC */
75 #define RSPI_SPSRC_CLEAR 0xfd80
76
77 #define RSPI_RESET_NUM 2
78
79 #define RSPI_MAX_SPEED_HZ 50000000
80
81 struct rzv2h_rspi_best_clock {
82 struct clk *clk;
83 unsigned long clk_rate;
84 unsigned long error;
85 u32 actual_hz;
86 u8 brdv;
87 u8 spr;
88 };
89
90 struct rzv2h_rspi_info {
91 void (*find_tclk_rate)(struct clk *clk, u32 hz,
92 struct rzv2h_rspi_best_clock *best_clk);
93 void (*find_pclk_rate)(struct clk *clk, u32 hz,
94 struct rzv2h_rspi_best_clock *best_clk);
95 const char *tclk_name;
96 unsigned int fifo_size;
97 unsigned int num_clks;
98 };
99
100 struct rzv2h_rspi_priv {
101 struct spi_controller *controller;
102 const struct rzv2h_rspi_info *info;
103 struct platform_device *pdev;
104 void __iomem *base;
105 struct clk *tclk;
106 struct clk *pclk;
107 wait_queue_head_t wait;
108 unsigned int bytes_per_word;
109 int irq_rx;
110 u32 last_speed_hz;
111 u32 freq;
112 u16 status;
113 u8 spr;
114 u8 brdv;
115 bool use_pclk;
116 bool dma_callbacked;
117 };
118
119 #define RZV2H_RSPI_TX(func, type) \
120 static inline void rzv2h_rspi_tx_##type(struct rzv2h_rspi_priv *rspi, \
121 const void *txbuf, \
122 unsigned int index) { \
123 type buf = ((type *)txbuf)[index]; \
124 func(buf, rspi->base + RSPI_SPDR); \
125 }
126
127 #define RZV2H_RSPI_RX(func, type) \
128 static inline void rzv2h_rspi_rx_##type(struct rzv2h_rspi_priv *rspi, \
129 void *rxbuf, \
130 unsigned int index) { \
131 type buf = func(rspi->base + RSPI_SPDR); \
132 ((type *)rxbuf)[index] = buf; \
133 }
134
RZV2H_RSPI_TX(writel,u32)135 RZV2H_RSPI_TX(writel, u32)
136 RZV2H_RSPI_TX(writew, u16)
137 RZV2H_RSPI_TX(writeb, u8)
138 /* The read access size for RSPI_SPDR is fixed at 32 bits */
139 RZV2H_RSPI_RX(readl, u32)
140 RZV2H_RSPI_RX(readl, u16)
141 RZV2H_RSPI_RX(readl, u8)
142
143 static void rzv2h_rspi_reg_rmw(const struct rzv2h_rspi_priv *rspi,
144 int reg_offs, u32 bit_mask, u32 value)
145 {
146 u32 tmp;
147
148 value <<= __ffs(bit_mask);
149 tmp = (readl(rspi->base + reg_offs) & ~bit_mask) | value;
150 writel(tmp, rspi->base + reg_offs);
151 }
152
rzv2h_rspi_spe_disable(const struct rzv2h_rspi_priv * rspi)153 static inline void rzv2h_rspi_spe_disable(const struct rzv2h_rspi_priv *rspi)
154 {
155 rzv2h_rspi_reg_rmw(rspi, RSPI_SPCR, RSPI_SPCR_SPE, 0);
156 }
157
rzv2h_rspi_spe_enable(const struct rzv2h_rspi_priv * rspi)158 static inline void rzv2h_rspi_spe_enable(const struct rzv2h_rspi_priv *rspi)
159 {
160 rzv2h_rspi_reg_rmw(rspi, RSPI_SPCR, RSPI_SPCR_SPE, 1);
161 }
162
rzv2h_rspi_clear_fifos(const struct rzv2h_rspi_priv * rspi)163 static inline void rzv2h_rspi_clear_fifos(const struct rzv2h_rspi_priv *rspi)
164 {
165 writeb(1, rspi->base + RSPI_SPFCR);
166 }
167
rzv2h_rspi_clear_all_irqs(struct rzv2h_rspi_priv * rspi)168 static inline void rzv2h_rspi_clear_all_irqs(struct rzv2h_rspi_priv *rspi)
169 {
170 writew(RSPI_SPSRC_CLEAR, rspi->base + RSPI_SPSRC);
171 rspi->status = 0;
172 }
173
rzv2h_rx_irq_handler(int irq,void * data)174 static irqreturn_t rzv2h_rx_irq_handler(int irq, void *data)
175 {
176 struct rzv2h_rspi_priv *rspi = data;
177
178 rspi->status = readw(rspi->base + RSPI_SPSR);
179 wake_up(&rspi->wait);
180
181 return IRQ_HANDLED;
182 }
183
rzv2h_rspi_wait_for_interrupt(struct rzv2h_rspi_priv * rspi,u32 wait_mask)184 static inline int rzv2h_rspi_wait_for_interrupt(struct rzv2h_rspi_priv *rspi,
185 u32 wait_mask)
186 {
187 return wait_event_timeout(rspi->wait, (rspi->status & wait_mask),
188 HZ) == 0 ? -ETIMEDOUT : 0;
189 }
190
rzv2h_rspi_send(struct rzv2h_rspi_priv * rspi,const void * txbuf,unsigned int index)191 static void rzv2h_rspi_send(struct rzv2h_rspi_priv *rspi, const void *txbuf,
192 unsigned int index)
193 {
194 switch (rspi->bytes_per_word) {
195 case 4:
196 rzv2h_rspi_tx_u32(rspi, txbuf, index);
197 break;
198 case 2:
199 rzv2h_rspi_tx_u16(rspi, txbuf, index);
200 break;
201 default:
202 rzv2h_rspi_tx_u8(rspi, txbuf, index);
203 }
204 }
205
rzv2h_rspi_receive(struct rzv2h_rspi_priv * rspi,void * rxbuf,unsigned int index)206 static int rzv2h_rspi_receive(struct rzv2h_rspi_priv *rspi, void *rxbuf,
207 unsigned int index)
208 {
209 int ret;
210
211 ret = rzv2h_rspi_wait_for_interrupt(rspi, RSPI_SPSR_SPRF);
212 if (ret)
213 return ret;
214
215 switch (rspi->bytes_per_word) {
216 case 4:
217 rzv2h_rspi_rx_u32(rspi, rxbuf, index);
218 break;
219 case 2:
220 rzv2h_rspi_rx_u16(rspi, rxbuf, index);
221 break;
222 default:
223 rzv2h_rspi_rx_u8(rspi, rxbuf, index);
224 }
225
226 return 0;
227 }
228
rzv2h_rspi_can_dma(struct spi_controller * ctlr,struct spi_device * spi,struct spi_transfer * xfer)229 static bool rzv2h_rspi_can_dma(struct spi_controller *ctlr, struct spi_device *spi,
230 struct spi_transfer *xfer)
231 {
232 struct rzv2h_rspi_priv *rspi = spi_controller_get_devdata(ctlr);
233
234 if (ctlr->fallback)
235 return false;
236
237 if (!ctlr->dma_tx || !ctlr->dma_rx)
238 return false;
239
240 return xfer->len > rspi->info->fifo_size;
241 }
242
rzv2h_rspi_transfer_pio(struct rzv2h_rspi_priv * rspi,struct spi_device * spi,struct spi_transfer * transfer,unsigned int words_to_transfer)243 static int rzv2h_rspi_transfer_pio(struct rzv2h_rspi_priv *rspi,
244 struct spi_device *spi,
245 struct spi_transfer *transfer,
246 unsigned int words_to_transfer)
247 {
248 unsigned int i;
249 int ret = 0;
250
251 for (i = 0; i < words_to_transfer; i++) {
252 rzv2h_rspi_clear_all_irqs(rspi);
253
254 rzv2h_rspi_send(rspi, transfer->tx_buf, i);
255
256 ret = rzv2h_rspi_receive(rspi, transfer->rx_buf, i);
257 if (ret)
258 break;
259 }
260
261 return ret;
262 }
263
rzv2h_rspi_dma_complete(void * arg)264 static void rzv2h_rspi_dma_complete(void *arg)
265 {
266 struct rzv2h_rspi_priv *rspi = arg;
267
268 rspi->dma_callbacked = 1;
269 wake_up_interruptible(&rspi->wait);
270 }
271
272 static struct dma_async_tx_descriptor *
rzv2h_rspi_setup_dma_channel(struct rzv2h_rspi_priv * rspi,struct dma_chan * chan,struct sg_table * sg,enum dma_slave_buswidth width,enum dma_transfer_direction direction)273 rzv2h_rspi_setup_dma_channel(struct rzv2h_rspi_priv *rspi,
274 struct dma_chan *chan, struct sg_table *sg,
275 enum dma_slave_buswidth width,
276 enum dma_transfer_direction direction)
277 {
278 struct dma_slave_config config = {
279 .dst_addr = rspi->pdev->resource->start + RSPI_SPDR,
280 .src_addr = rspi->pdev->resource->start + RSPI_SPDR,
281 .dst_addr_width = width,
282 .src_addr_width = width,
283 .direction = direction,
284 };
285 struct dma_async_tx_descriptor *desc;
286 int ret;
287
288 ret = dmaengine_slave_config(chan, &config);
289 if (ret)
290 return ERR_PTR(ret);
291
292 desc = dmaengine_prep_slave_sg(chan, sg->sgl, sg->nents, direction,
293 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
294 if (!desc)
295 return ERR_PTR(-EAGAIN);
296
297 if (direction == DMA_DEV_TO_MEM) {
298 desc->callback = rzv2h_rspi_dma_complete;
299 desc->callback_param = rspi;
300 }
301
302 return desc;
303 }
304
305 static enum dma_slave_buswidth
rzv2h_rspi_dma_width(struct rzv2h_rspi_priv * rspi)306 rzv2h_rspi_dma_width(struct rzv2h_rspi_priv *rspi)
307 {
308 switch (rspi->bytes_per_word) {
309 case 4:
310 return DMA_SLAVE_BUSWIDTH_4_BYTES;
311 case 2:
312 return DMA_SLAVE_BUSWIDTH_2_BYTES;
313 case 1:
314 return DMA_SLAVE_BUSWIDTH_1_BYTE;
315 default:
316 return DMA_SLAVE_BUSWIDTH_UNDEFINED;
317 }
318 }
319
rzv2h_rspi_transfer_dma(struct rzv2h_rspi_priv * rspi,struct spi_device * spi,struct spi_transfer * transfer,unsigned int words_to_transfer)320 static int rzv2h_rspi_transfer_dma(struct rzv2h_rspi_priv *rspi,
321 struct spi_device *spi,
322 struct spi_transfer *transfer,
323 unsigned int words_to_transfer)
324 {
325 struct dma_async_tx_descriptor *tx_desc = NULL, *rx_desc = NULL;
326 enum dma_slave_buswidth width;
327 dma_cookie_t cookie;
328 int ret;
329
330 width = rzv2h_rspi_dma_width(rspi);
331 if (width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
332 return -EINVAL;
333
334 rx_desc = rzv2h_rspi_setup_dma_channel(rspi, rspi->controller->dma_rx,
335 &transfer->rx_sg, width,
336 DMA_DEV_TO_MEM);
337 if (IS_ERR(rx_desc))
338 return PTR_ERR(rx_desc);
339
340 tx_desc = rzv2h_rspi_setup_dma_channel(rspi, rspi->controller->dma_tx,
341 &transfer->tx_sg, width,
342 DMA_MEM_TO_DEV);
343 if (IS_ERR(tx_desc))
344 return PTR_ERR(tx_desc);
345
346 cookie = dmaengine_submit(rx_desc);
347 if (dma_submit_error(cookie))
348 return cookie;
349
350 cookie = dmaengine_submit(tx_desc);
351 if (dma_submit_error(cookie)) {
352 dmaengine_terminate_sync(rspi->controller->dma_rx);
353 return cookie;
354 }
355
356 /*
357 * DMA transfer does not need IRQs to be enabled.
358 * For PIO, we only use RX IRQ, so disable that.
359 */
360 disable_irq(rspi->irq_rx);
361
362 rspi->dma_callbacked = 0;
363
364 dma_async_issue_pending(rspi->controller->dma_rx);
365 dma_async_issue_pending(rspi->controller->dma_tx);
366 rzv2h_rspi_clear_all_irqs(rspi);
367
368 ret = wait_event_interruptible_timeout(rspi->wait, rspi->dma_callbacked, HZ);
369 if (ret > 0) {
370 dmaengine_synchronize(rspi->controller->dma_tx);
371 dmaengine_synchronize(rspi->controller->dma_rx);
372 ret = 0;
373 } else {
374 dmaengine_terminate_sync(rspi->controller->dma_tx);
375 dmaengine_terminate_sync(rspi->controller->dma_rx);
376 ret = ret ?: -ETIMEDOUT;
377 }
378
379 enable_irq(rspi->irq_rx);
380
381 return ret;
382 }
383
rzv2h_rspi_transfer_one(struct spi_controller * controller,struct spi_device * spi,struct spi_transfer * transfer)384 static int rzv2h_rspi_transfer_one(struct spi_controller *controller,
385 struct spi_device *spi,
386 struct spi_transfer *transfer)
387 {
388 struct rzv2h_rspi_priv *rspi = spi_controller_get_devdata(controller);
389 bool is_dma = spi_xfer_is_dma_mapped(controller, spi, transfer);
390 unsigned int words_to_transfer;
391 int ret;
392
393 transfer->effective_speed_hz = rspi->freq;
394 words_to_transfer = transfer->len / rspi->bytes_per_word;
395
396 if (is_dma)
397 ret = rzv2h_rspi_transfer_dma(rspi, spi, transfer, words_to_transfer);
398 else
399 ret = rzv2h_rspi_transfer_pio(rspi, spi, transfer, words_to_transfer);
400
401 rzv2h_rspi_clear_all_irqs(rspi);
402
403 if (is_dma && ret == -EAGAIN)
404 /* Retry with PIO */
405 transfer->error = SPI_TRANS_FAIL_NO_START;
406
407 return ret;
408 }
409
rzv2h_rspi_calc_bitrate(unsigned long tclk_rate,u8 spr,u8 brdv)410 static inline u32 rzv2h_rspi_calc_bitrate(unsigned long tclk_rate, u8 spr,
411 u8 brdv)
412 {
413 return DIV_ROUND_UP(tclk_rate, (2 * (spr + 1) * (1 << brdv)));
414 }
415
rzv2h_rspi_find_rate_variable(struct clk * clk,u32 hz,struct rzv2h_rspi_best_clock * best)416 static void rzv2h_rspi_find_rate_variable(struct clk *clk, u32 hz,
417 struct rzv2h_rspi_best_clock *best)
418 {
419 long clk_rate, clk_min_rate, clk_max_rate;
420 int min_rate_spr, max_rate_spr;
421 unsigned long error;
422 u32 actual_hz;
423 u8 brdv;
424 int spr;
425
426 /*
427 * On T2H / N2H, the source for the SPI clock is PCLKSPIn, which is a
428 * 1/32, 1/30, 1/25 or 1/24 divider of PLL4, which is 2400MHz,
429 * resulting in either 75MHz, 80MHz, 96MHz or 100MHz.
430 */
431 clk_min_rate = clk_round_rate(clk, 0);
432 if (clk_min_rate < 0)
433 return;
434
435 clk_max_rate = clk_round_rate(clk, ULONG_MAX);
436 if (clk_max_rate < 0)
437 return;
438
439 /*
440 * From the manual:
441 * Bit rate = f(PCLKSPIn) / (2 * (n + 1) * 2^N)
442 *
443 * If we adapt it to the current context, we get the following:
444 * hz = rate / ((spr + 1) * (1 << (brdv + 1)))
445 *
446 * This can be written in multiple forms depending on what we want to
447 * determine.
448 *
449 * To find the rate, having hz, spr and brdv:
450 * rate = hz * (spr + 1) * (1 << (brdv + 1)
451 *
452 * To find the spr, having rate, hz, and spr:
453 * spr = rate / (hz * (1 << (brdv + 1)) - 1
454 */
455
456 for (brdv = RSPI_SPCMD_BRDV_MIN; brdv <= RSPI_SPCMD_BRDV_MAX; brdv++) {
457 /* Calculate the divisor needed to find the SPR from a rate. */
458 u32 rate_div = hz * (1 << (brdv + 1));
459
460 /*
461 * If the SPR for the minimum rate is greater than the maximum
462 * allowed value skip this BRDV. The divisor increases with each
463 * BRDV iteration, so the following BRDV might result in a
464 * minimum SPR that is in the valid range.
465 */
466 min_rate_spr = DIV_ROUND_CLOSEST(clk_min_rate, rate_div) - 1;
467 if (min_rate_spr > RSPI_SPBR_SPR_MAX)
468 continue;
469
470 /*
471 * If the SPR for the maximum rate is less than the minimum
472 * allowed value, exit. The divisor only increases with each
473 * BRDV iteration, so the following BRDV cannot result in a
474 * maximum SPR that is in the valid range.
475 */
476 max_rate_spr = DIV_ROUND_CLOSEST(clk_max_rate, rate_div) - 1;
477 if (max_rate_spr < RSPI_SPBR_SPR_MIN)
478 break;
479
480 if (min_rate_spr < RSPI_SPBR_SPR_MIN)
481 min_rate_spr = RSPI_SPBR_SPR_MIN;
482
483 if (max_rate_spr > RSPI_SPBR_SPR_MAX)
484 max_rate_spr = RSPI_SPBR_SPR_MAX;
485
486 for (spr = min_rate_spr; spr <= max_rate_spr; spr++) {
487 clk_rate = (spr + 1) * rate_div;
488
489 clk_rate = clk_round_rate(clk, clk_rate);
490 if (clk_rate <= 0)
491 continue;
492
493 actual_hz = rzv2h_rspi_calc_bitrate(clk_rate, spr, brdv);
494 error = abs((long)hz - (long)actual_hz);
495
496 if (error >= best->error)
497 continue;
498
499 *best = (struct rzv2h_rspi_best_clock) {
500 .clk = clk,
501 .clk_rate = clk_rate,
502 .error = error,
503 .actual_hz = actual_hz,
504 .brdv = brdv,
505 .spr = spr,
506 };
507
508 if (!error)
509 return;
510 }
511 }
512 }
513
rzv2h_rspi_find_rate_fixed(struct clk * clk,u32 hz,struct rzv2h_rspi_best_clock * best)514 static void rzv2h_rspi_find_rate_fixed(struct clk *clk, u32 hz,
515 struct rzv2h_rspi_best_clock *best)
516 {
517 unsigned long clk_rate;
518 unsigned long error;
519 u32 actual_hz;
520 int spr;
521 u8 brdv;
522
523 /*
524 * From the manual:
525 * Bit rate = f(RSPI_n_TCLK)/(2*(n+1)*2^(N))
526 *
527 * Where:
528 * * RSPI_n_TCLK is fixed to 200MHz on V2H
529 * * n = SPR - is RSPI_SPBR.SPR (from 0 to 255)
530 * * N = BRDV - is RSPI_SPCMD.BRDV (from 0 to 3)
531 */
532 clk_rate = clk_get_rate(clk);
533 for (brdv = RSPI_SPCMD_BRDV_MIN; brdv <= RSPI_SPCMD_BRDV_MAX; brdv++) {
534 spr = DIV_ROUND_UP(clk_rate, hz * (1 << (brdv + 1)));
535 spr--;
536 /*
537 * Skip SPR=0 and BRDV=0 as it is not a valid combination:
538 * - On RZ/G3E, RZ/G3L, RZ/V2H(P) and RZ/V2N, RSPI_n_TCLK is
539 * fixed at 200MHz and SPR=0 and BRDV=0 results in the maximum
540 * bit rate of 100Mbps which is prohibited.
541 * - On RZ/T2H and RZ/N2H, when PCLK (125MHz) is used as
542 * the clock source, SPR=0 and BRDV=0 is explicitly listed
543 * as unsupported in the hardware manual (Table 36.7).
544 */
545 if (!spr && !brdv)
546 continue;
547 if (spr >= RSPI_SPBR_SPR_MIN && spr <= RSPI_SPBR_SPR_MAX)
548 goto clock_found;
549 }
550
551 return;
552
553 clock_found:
554 actual_hz = rzv2h_rspi_calc_bitrate(clk_rate, spr, brdv);
555 error = abs((long)hz - (long)actual_hz);
556
557 if (error >= best->error)
558 return;
559
560 *best = (struct rzv2h_rspi_best_clock) {
561 .clk = clk,
562 .clk_rate = clk_rate,
563 .error = error,
564 .actual_hz = actual_hz,
565 .brdv = brdv,
566 .spr = spr,
567 };
568 }
569
rzv2h_rspi_setup_clock(struct rzv2h_rspi_priv * rspi,u32 hz)570 static u32 rzv2h_rspi_setup_clock(struct rzv2h_rspi_priv *rspi, u32 hz)
571 {
572 struct rzv2h_rspi_best_clock best_clock = {
573 .error = ULONG_MAX,
574 };
575 int ret;
576
577 rspi->info->find_tclk_rate(rspi->tclk, hz, &best_clock);
578
579 if (best_clock.error && rspi->info->find_pclk_rate)
580 rspi->info->find_pclk_rate(rspi->pclk, hz, &best_clock);
581
582 if (!best_clock.clk_rate)
583 return 0;
584
585 ret = clk_set_rate(best_clock.clk, best_clock.clk_rate);
586 if (ret)
587 return 0;
588
589 rspi->use_pclk = best_clock.clk == rspi->pclk;
590 rspi->spr = best_clock.spr;
591 rspi->brdv = best_clock.brdv;
592
593 return best_clock.actual_hz;
594 }
595
rzv2h_rspi_prepare_message(struct spi_controller * ctlr,struct spi_message * message)596 static int rzv2h_rspi_prepare_message(struct spi_controller *ctlr,
597 struct spi_message *message)
598 {
599 struct rzv2h_rspi_priv *rspi = spi_controller_get_devdata(ctlr);
600 const struct spi_device *spi = message->spi;
601 struct spi_transfer *xfer;
602 u32 speed_hz = U32_MAX;
603 u8 bits_per_word;
604 u32 conf32;
605 u16 conf16;
606 u8 conf8;
607
608 /* Make sure SPCR.SPE is 0 before amending the configuration */
609 rzv2h_rspi_spe_disable(rspi);
610
611 list_for_each_entry(xfer, &message->transfers, transfer_list) {
612 if (!xfer->speed_hz)
613 continue;
614
615 speed_hz = min(xfer->speed_hz, speed_hz);
616 bits_per_word = xfer->bits_per_word;
617 }
618
619 if (speed_hz == U32_MAX)
620 return -EINVAL;
621
622 rspi->bytes_per_word = roundup_pow_of_two(BITS_TO_BYTES(bits_per_word));
623
624 if (speed_hz != rspi->last_speed_hz) {
625 rspi->freq = rzv2h_rspi_setup_clock(rspi, speed_hz);
626 if (!rspi->freq)
627 return -EINVAL;
628
629 rspi->last_speed_hz = speed_hz;
630 }
631
632 writeb(rspi->spr, rspi->base + RSPI_SPBR);
633
634 /* Configure the device to work in "host" mode */
635 conf32 = RSPI_SPCR_MSTR;
636
637 /* Auto-stop function */
638 conf32 |= RSPI_SPCR_SCKASE;
639
640 /* SPI receive buffer full interrupt enable */
641 conf32 |= RSPI_SPCR_SPRIE;
642
643 /* SPI transmit buffer empty interrupt enable */
644 conf32 |= RSPI_SPCR_SPTIE;
645
646 /* Bypass synchronization circuit */
647 conf32 |= FIELD_PREP(RSPI_SPCR_BPEN, rspi->use_pclk);
648
649 writel(conf32, rspi->base + RSPI_SPCR);
650
651 /* Use SPCMD0 only */
652 writeb(0x0, rspi->base + RSPI_SPSCR);
653
654 /* Setup loopback */
655 conf8 = FIELD_PREP(RSPI_SPPCR_SPLP2, !!(spi->mode & SPI_LOOP));
656 writeb(conf8, rspi->base + RSPI_SPPCR);
657
658 /* Setup mode */
659 conf32 = FIELD_PREP(RSPI_SPCMD_CPOL, !!(spi->mode & SPI_CPOL));
660 conf32 |= FIELD_PREP(RSPI_SPCMD_CPHA, !!(spi->mode & SPI_CPHA));
661 conf32 |= FIELD_PREP(RSPI_SPCMD_LSBF, !!(spi->mode & SPI_LSB_FIRST));
662 conf32 |= FIELD_PREP(RSPI_SPCMD_SPB, bits_per_word - 1);
663 conf32 |= FIELD_PREP(RSPI_SPCMD_BRDV, rspi->brdv);
664 conf32 |= FIELD_PREP(RSPI_SPCMD_SSLKP, 1);
665 conf32 |= FIELD_PREP(RSPI_SPCMD_SSLA, spi_get_chipselect(spi, 0));
666 writel(conf32, rspi->base + RSPI_SPCMD);
667 if (spi->mode & SPI_CS_HIGH)
668 writeb(BIT(spi_get_chipselect(spi, 0)), rspi->base + RSPI_SSLP);
669 else
670 writeb(0, rspi->base + RSPI_SSLP);
671
672 /* Setup FIFO thresholds */
673 conf16 = FIELD_PREP(RSPI_SPDCR2_TTRG, 0);
674 conf16 |= FIELD_PREP(RSPI_SPDCR2_RTRG, 0);
675 writew(conf16, rspi->base + RSPI_SPDCR2);
676
677 rzv2h_rspi_clear_fifos(rspi);
678
679 rzv2h_rspi_spe_enable(rspi);
680
681 return 0;
682 }
683
rzv2h_rspi_unprepare_message(struct spi_controller * ctlr,struct spi_message * message)684 static int rzv2h_rspi_unprepare_message(struct spi_controller *ctlr,
685 struct spi_message *message)
686 {
687 struct rzv2h_rspi_priv *rspi = spi_controller_get_devdata(ctlr);
688
689 rzv2h_rspi_spe_disable(rspi);
690
691 return 0;
692 }
693
rzv2h_rspi_probe(struct platform_device * pdev)694 static int rzv2h_rspi_probe(struct platform_device *pdev)
695 {
696 struct spi_controller *controller;
697 struct device *dev = &pdev->dev;
698 struct rzv2h_rspi_priv *rspi;
699 struct reset_control *reset;
700 struct clk_bulk_data *clks;
701 long tclk_rate;
702 int ret, i;
703
704 controller = devm_spi_alloc_host(dev, sizeof(*rspi));
705 if (!controller)
706 return -ENOMEM;
707
708 rspi = spi_controller_get_devdata(controller);
709 platform_set_drvdata(pdev, rspi);
710
711 rspi->controller = controller;
712 rspi->pdev = pdev;
713
714 rspi->info = device_get_match_data(dev);
715
716 rspi->base = devm_platform_ioremap_resource(pdev, 0);
717 if (IS_ERR(rspi->base))
718 return PTR_ERR(rspi->base);
719
720 ret = devm_clk_bulk_get_all_enabled(dev, &clks);
721 if (ret != rspi->info->num_clks)
722 return dev_err_probe(dev, ret >= 0 ? -EINVAL : ret,
723 "cannot get clocks\n");
724 for (i = 0; i < rspi->info->num_clks; i++) {
725 if (!strcmp(clks[i].id, rspi->info->tclk_name)) {
726 rspi->tclk = clks[i].clk;
727 } else if (rspi->info->find_pclk_rate &&
728 !strcmp(clks[i].id, "pclk")) {
729 rspi->pclk = clks[i].clk;
730 }
731 }
732
733 if (!rspi->tclk)
734 return dev_err_probe(dev, -EINVAL, "Failed to get tclk\n");
735
736 reset = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev,
737 "presetn");
738 if (IS_ERR(reset))
739 return dev_err_probe(&pdev->dev, PTR_ERR(reset),
740 "cannot get presetn reset\n");
741
742 reset = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev,
743 "tresetn");
744 if (IS_ERR(reset))
745 return dev_err_probe(&pdev->dev, PTR_ERR(reset),
746 "cannot get tresetn reset\n");
747
748 rspi->irq_rx = platform_get_irq_byname(pdev, "rx");
749 if (rspi->irq_rx < 0)
750 return dev_err_probe(dev, rspi->irq_rx, "cannot get IRQ 'rx'\n");
751
752 init_waitqueue_head(&rspi->wait);
753
754 ret = devm_request_irq(dev, rspi->irq_rx, rzv2h_rx_irq_handler, 0,
755 dev_name(dev), rspi);
756 if (ret) {
757 dev_err(dev, "cannot request `rx` IRQ\n");
758 return ret;
759 }
760
761 controller->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH |
762 SPI_LSB_FIRST | SPI_LOOP;
763 controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
764 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
765 controller->prepare_message = rzv2h_rspi_prepare_message;
766 controller->unprepare_message = rzv2h_rspi_unprepare_message;
767 controller->num_chipselect = 4;
768 controller->transfer_one = rzv2h_rspi_transfer_one;
769 controller->can_dma = rzv2h_rspi_can_dma;
770
771 tclk_rate = clk_round_rate(rspi->tclk, 0);
772 if (tclk_rate < 0)
773 return tclk_rate;
774
775 controller->min_speed_hz = rzv2h_rspi_calc_bitrate(tclk_rate,
776 RSPI_SPBR_SPR_MAX,
777 RSPI_SPCMD_BRDV_MAX);
778
779 controller->max_speed_hz = RSPI_MAX_SPEED_HZ;
780
781 controller->dma_tx = devm_dma_request_chan(dev, "tx");
782 if (IS_ERR(controller->dma_tx)) {
783 ret = dev_warn_probe(dev, PTR_ERR(controller->dma_tx),
784 "failed to request TX DMA channel\n");
785 if (ret == -EPROBE_DEFER)
786 return ret;
787 controller->dma_tx = NULL;
788 }
789
790 controller->dma_rx = devm_dma_request_chan(dev, "rx");
791 if (IS_ERR(controller->dma_rx)) {
792 ret = dev_warn_probe(dev, PTR_ERR(controller->dma_rx),
793 "failed to request RX DMA channel\n");
794 if (ret == -EPROBE_DEFER)
795 return ret;
796 controller->dma_rx = NULL;
797 }
798
799 ret = devm_spi_register_controller(dev, controller);
800 if (ret)
801 dev_err(dev, "register controller failed\n");
802
803 return ret;
804 }
805
rzv2h_rspi_suspend(struct device * dev)806 static int rzv2h_rspi_suspend(struct device *dev)
807 {
808 struct rzv2h_rspi_priv *rspi = dev_get_drvdata(dev);
809
810 return spi_controller_suspend(rspi->controller);
811 }
812
rzv2h_rspi_resume(struct device * dev)813 static int rzv2h_rspi_resume(struct device *dev)
814 {
815 struct rzv2h_rspi_priv *rspi = dev_get_drvdata(dev);
816
817 return spi_controller_resume(rspi->controller);
818 }
819
820 static DEFINE_SIMPLE_DEV_PM_OPS(rzv2h_rspi_pm_ops, rzv2h_rspi_suspend,
821 rzv2h_rspi_resume);
822
823 static const struct rzv2h_rspi_info rzv2h_info = {
824 .find_tclk_rate = rzv2h_rspi_find_rate_fixed,
825 .tclk_name = "tclk",
826 .fifo_size = 16,
827 .num_clks = 3,
828 };
829
830 static const struct rzv2h_rspi_info rzg3l_info = {
831 .find_tclk_rate = rzv2h_rspi_find_rate_fixed,
832 .tclk_name = "tclk",
833 .fifo_size = 16,
834 .num_clks = 2,
835 };
836
837 static const struct rzv2h_rspi_info rzt2h_info = {
838 .find_tclk_rate = rzv2h_rspi_find_rate_variable,
839 .find_pclk_rate = rzv2h_rspi_find_rate_fixed,
840 .tclk_name = "pclkspi",
841 .fifo_size = 4,
842 .num_clks = 2,
843 };
844
845 static const struct of_device_id rzv2h_rspi_match[] = {
846 { .compatible = "renesas,r9a08g046-rspi", &rzg3l_info },
847 { .compatible = "renesas,r9a09g057-rspi", &rzv2h_info },
848 { .compatible = "renesas,r9a09g077-rspi", &rzt2h_info },
849 { /* sentinel */ }
850 };
851 MODULE_DEVICE_TABLE(of, rzv2h_rspi_match);
852
853 static struct platform_driver rzv2h_rspi_drv = {
854 .probe = rzv2h_rspi_probe,
855 .driver = {
856 .name = "rzv2h_rspi",
857 .of_match_table = rzv2h_rspi_match,
858 .pm = pm_sleep_ptr(&rzv2h_rspi_pm_ops),
859 },
860 };
861 module_platform_driver(rzv2h_rspi_drv);
862
863 MODULE_LICENSE("GPL");
864 MODULE_AUTHOR("Fabrizio Castro <fabrizio.castro.jz@renesas.com>");
865 MODULE_DESCRIPTION("Renesas RZ/V2H(P) Serial Peripheral Interface Driver");
866