1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Renesas RZ/V2H Renesas Serial Peripheral Interface (RSPI)
4 *
5 * Copyright (C) 2025 Renesas Electronics Corporation
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/bitops.h>
10 #include <linux/bits.h>
11 #include <linux/clk.h>
12 #include <linux/dmaengine.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/limits.h>
16 #include <linux/log2.h>
17 #include <linux/math.h>
18 #include <linux/of.h>
19 #include <linux/platform_device.h>
20 #include <linux/property.h>
21 #include <linux/reset.h>
22 #include <linux/spi/spi.h>
23 #include <linux/wait.h>
24
25 #include "internals.h"
26
27 /* Registers */
28 #define RSPI_SPDR 0x00
29 #define RSPI_SPCR 0x08
30 #define RSPI_SPPCR 0x0e
31 #define RSPI_SSLP 0x10
32 #define RSPI_SPBR 0x11
33 #define RSPI_SPSCR 0x13
34 #define RSPI_SPCMD 0x14
35 #define RSPI_SPDCR2 0x44
36 #define RSPI_SPSR 0x52
37 #define RSPI_SPSRC 0x6a
38 #define RSPI_SPFCR 0x6c
39
40 /* Register SPCR */
41 #define RSPI_SPCR_BPEN BIT(31)
42 #define RSPI_SPCR_MSTR BIT(30)
43 #define RSPI_SPCR_SPTIE BIT(20)
44 #define RSPI_SPCR_SPRIE BIT(17)
45 #define RSPI_SPCR_SCKASE BIT(12)
46 #define RSPI_SPCR_SPE BIT(0)
47
48 /* Register SPPCR */
49 #define RSPI_SPPCR_SPLP2 BIT(1)
50
51 /* Register SPBR */
52 #define RSPI_SPBR_SPR_MIN 0
53 #define RSPI_SPBR_SPR_MAX 255
54
55 /* Register SPCMD */
56 #define RSPI_SPCMD_SSLA GENMASK(25, 24)
57 #define RSPI_SPCMD_SPB GENMASK(20, 16)
58 #define RSPI_SPCMD_LSBF BIT(12)
59 #define RSPI_SPCMD_SSLKP BIT(7)
60 #define RSPI_SPCMD_BRDV GENMASK(3, 2)
61 #define RSPI_SPCMD_CPOL BIT(1)
62 #define RSPI_SPCMD_CPHA BIT(0)
63
64 #define RSPI_SPCMD_BRDV_MIN 0
65 #define RSPI_SPCMD_BRDV_MAX 3
66
67 /* Register SPDCR2 */
68 #define RSPI_SPDCR2_TTRG GENMASK(11, 8)
69 #define RSPI_SPDCR2_RTRG GENMASK(3, 0)
70
71 /* Register SPSR */
72 #define RSPI_SPSR_SPRF BIT(15)
73
74 /* Register RSPI_SPSRC */
75 #define RSPI_SPSRC_CLEAR 0xfd80
76
77 #define RSPI_RESET_NUM 2
78
79 #define RSPI_MAX_SPEED_HZ 50000000
80
81 struct rzv2h_rspi_best_clock {
82 struct clk *clk;
83 unsigned long clk_rate;
84 unsigned long error;
85 u32 actual_hz;
86 u8 brdv;
87 u8 spr;
88 };
89
90 struct rzv2h_rspi_info {
91 void (*find_tclk_rate)(struct clk *clk, u32 hz,
92 struct rzv2h_rspi_best_clock *best_clk);
93 void (*find_pclk_rate)(struct clk *clk, u32 hz,
94 struct rzv2h_rspi_best_clock *best_clk);
95 const char *tclk_name;
96 unsigned int fifo_size;
97 unsigned int num_clks;
98 };
99
100 struct rzv2h_rspi_priv {
101 struct spi_controller *controller;
102 const struct rzv2h_rspi_info *info;
103 struct platform_device *pdev;
104 void __iomem *base;
105 struct clk *tclk;
106 struct clk *pclk;
107 wait_queue_head_t wait;
108 unsigned int bytes_per_word;
109 int irq_rx;
110 u32 last_speed_hz;
111 u32 freq;
112 u16 status;
113 u8 spr;
114 u8 brdv;
115 bool use_pclk;
116 bool dma_callbacked;
117 };
118
119 #define RZV2H_RSPI_TX(func, type) \
120 static inline void rzv2h_rspi_tx_##type(struct rzv2h_rspi_priv *rspi, \
121 const void *txbuf, \
122 unsigned int index) { \
123 type buf = ((type *)txbuf)[index]; \
124 func(buf, rspi->base + RSPI_SPDR); \
125 }
126
127 #define RZV2H_RSPI_RX(func, type) \
128 static inline void rzv2h_rspi_rx_##type(struct rzv2h_rspi_priv *rspi, \
129 void *rxbuf, \
130 unsigned int index) { \
131 type buf = func(rspi->base + RSPI_SPDR); \
132 ((type *)rxbuf)[index] = buf; \
133 }
134
RZV2H_RSPI_TX(writel,u32)135 RZV2H_RSPI_TX(writel, u32)
136 RZV2H_RSPI_TX(writew, u16)
137 RZV2H_RSPI_TX(writeb, u8)
138 RZV2H_RSPI_RX(readl, u32)
139 RZV2H_RSPI_RX(readw, u16)
140 RZV2H_RSPI_RX(readl, u8)
141
142 static void rzv2h_rspi_reg_rmw(const struct rzv2h_rspi_priv *rspi,
143 int reg_offs, u32 bit_mask, u32 value)
144 {
145 u32 tmp;
146
147 value <<= __ffs(bit_mask);
148 tmp = (readl(rspi->base + reg_offs) & ~bit_mask) | value;
149 writel(tmp, rspi->base + reg_offs);
150 }
151
rzv2h_rspi_spe_disable(const struct rzv2h_rspi_priv * rspi)152 static inline void rzv2h_rspi_spe_disable(const struct rzv2h_rspi_priv *rspi)
153 {
154 rzv2h_rspi_reg_rmw(rspi, RSPI_SPCR, RSPI_SPCR_SPE, 0);
155 }
156
rzv2h_rspi_spe_enable(const struct rzv2h_rspi_priv * rspi)157 static inline void rzv2h_rspi_spe_enable(const struct rzv2h_rspi_priv *rspi)
158 {
159 rzv2h_rspi_reg_rmw(rspi, RSPI_SPCR, RSPI_SPCR_SPE, 1);
160 }
161
rzv2h_rspi_clear_fifos(const struct rzv2h_rspi_priv * rspi)162 static inline void rzv2h_rspi_clear_fifos(const struct rzv2h_rspi_priv *rspi)
163 {
164 writeb(1, rspi->base + RSPI_SPFCR);
165 }
166
rzv2h_rspi_clear_all_irqs(struct rzv2h_rspi_priv * rspi)167 static inline void rzv2h_rspi_clear_all_irqs(struct rzv2h_rspi_priv *rspi)
168 {
169 writew(RSPI_SPSRC_CLEAR, rspi->base + RSPI_SPSRC);
170 rspi->status = 0;
171 }
172
rzv2h_rx_irq_handler(int irq,void * data)173 static irqreturn_t rzv2h_rx_irq_handler(int irq, void *data)
174 {
175 struct rzv2h_rspi_priv *rspi = data;
176
177 rspi->status = readw(rspi->base + RSPI_SPSR);
178 wake_up(&rspi->wait);
179
180 return IRQ_HANDLED;
181 }
182
rzv2h_rspi_wait_for_interrupt(struct rzv2h_rspi_priv * rspi,u32 wait_mask)183 static inline int rzv2h_rspi_wait_for_interrupt(struct rzv2h_rspi_priv *rspi,
184 u32 wait_mask)
185 {
186 return wait_event_timeout(rspi->wait, (rspi->status & wait_mask),
187 HZ) == 0 ? -ETIMEDOUT : 0;
188 }
189
rzv2h_rspi_send(struct rzv2h_rspi_priv * rspi,const void * txbuf,unsigned int index)190 static void rzv2h_rspi_send(struct rzv2h_rspi_priv *rspi, const void *txbuf,
191 unsigned int index)
192 {
193 switch (rspi->bytes_per_word) {
194 case 4:
195 rzv2h_rspi_tx_u32(rspi, txbuf, index);
196 break;
197 case 2:
198 rzv2h_rspi_tx_u16(rspi, txbuf, index);
199 break;
200 default:
201 rzv2h_rspi_tx_u8(rspi, txbuf, index);
202 }
203 }
204
rzv2h_rspi_receive(struct rzv2h_rspi_priv * rspi,void * rxbuf,unsigned int index)205 static int rzv2h_rspi_receive(struct rzv2h_rspi_priv *rspi, void *rxbuf,
206 unsigned int index)
207 {
208 int ret;
209
210 ret = rzv2h_rspi_wait_for_interrupt(rspi, RSPI_SPSR_SPRF);
211 if (ret)
212 return ret;
213
214 switch (rspi->bytes_per_word) {
215 case 4:
216 rzv2h_rspi_rx_u32(rspi, rxbuf, index);
217 break;
218 case 2:
219 rzv2h_rspi_rx_u16(rspi, rxbuf, index);
220 break;
221 default:
222 rzv2h_rspi_rx_u8(rspi, rxbuf, index);
223 }
224
225 return 0;
226 }
227
rzv2h_rspi_can_dma(struct spi_controller * ctlr,struct spi_device * spi,struct spi_transfer * xfer)228 static bool rzv2h_rspi_can_dma(struct spi_controller *ctlr, struct spi_device *spi,
229 struct spi_transfer *xfer)
230 {
231 struct rzv2h_rspi_priv *rspi = spi_controller_get_devdata(ctlr);
232
233 if (ctlr->fallback)
234 return false;
235
236 if (!ctlr->dma_tx || !ctlr->dma_rx)
237 return false;
238
239 return xfer->len > rspi->info->fifo_size;
240 }
241
rzv2h_rspi_transfer_pio(struct rzv2h_rspi_priv * rspi,struct spi_device * spi,struct spi_transfer * transfer,unsigned int words_to_transfer)242 static int rzv2h_rspi_transfer_pio(struct rzv2h_rspi_priv *rspi,
243 struct spi_device *spi,
244 struct spi_transfer *transfer,
245 unsigned int words_to_transfer)
246 {
247 unsigned int i;
248 int ret = 0;
249
250 for (i = 0; i < words_to_transfer; i++) {
251 rzv2h_rspi_clear_all_irqs(rspi);
252
253 rzv2h_rspi_send(rspi, transfer->tx_buf, i);
254
255 ret = rzv2h_rspi_receive(rspi, transfer->rx_buf, i);
256 if (ret)
257 break;
258 }
259
260 return ret;
261 }
262
rzv2h_rspi_dma_complete(void * arg)263 static void rzv2h_rspi_dma_complete(void *arg)
264 {
265 struct rzv2h_rspi_priv *rspi = arg;
266
267 rspi->dma_callbacked = 1;
268 wake_up_interruptible(&rspi->wait);
269 }
270
271 static struct dma_async_tx_descriptor *
rzv2h_rspi_setup_dma_channel(struct rzv2h_rspi_priv * rspi,struct dma_chan * chan,struct sg_table * sg,enum dma_slave_buswidth width,enum dma_transfer_direction direction)272 rzv2h_rspi_setup_dma_channel(struct rzv2h_rspi_priv *rspi,
273 struct dma_chan *chan, struct sg_table *sg,
274 enum dma_slave_buswidth width,
275 enum dma_transfer_direction direction)
276 {
277 struct dma_slave_config config = {
278 .dst_addr = rspi->pdev->resource->start + RSPI_SPDR,
279 .src_addr = rspi->pdev->resource->start + RSPI_SPDR,
280 .dst_addr_width = width,
281 .src_addr_width = width,
282 .direction = direction,
283 };
284 struct dma_async_tx_descriptor *desc;
285 int ret;
286
287 ret = dmaengine_slave_config(chan, &config);
288 if (ret)
289 return ERR_PTR(ret);
290
291 desc = dmaengine_prep_slave_sg(chan, sg->sgl, sg->nents, direction,
292 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
293 if (!desc)
294 return ERR_PTR(-EAGAIN);
295
296 if (direction == DMA_DEV_TO_MEM) {
297 desc->callback = rzv2h_rspi_dma_complete;
298 desc->callback_param = rspi;
299 }
300
301 return desc;
302 }
303
304 static enum dma_slave_buswidth
rzv2h_rspi_dma_width(struct rzv2h_rspi_priv * rspi)305 rzv2h_rspi_dma_width(struct rzv2h_rspi_priv *rspi)
306 {
307 switch (rspi->bytes_per_word) {
308 case 4:
309 return DMA_SLAVE_BUSWIDTH_4_BYTES;
310 case 2:
311 return DMA_SLAVE_BUSWIDTH_2_BYTES;
312 case 1:
313 return DMA_SLAVE_BUSWIDTH_1_BYTE;
314 default:
315 return DMA_SLAVE_BUSWIDTH_UNDEFINED;
316 }
317 }
318
rzv2h_rspi_transfer_dma(struct rzv2h_rspi_priv * rspi,struct spi_device * spi,struct spi_transfer * transfer,unsigned int words_to_transfer)319 static int rzv2h_rspi_transfer_dma(struct rzv2h_rspi_priv *rspi,
320 struct spi_device *spi,
321 struct spi_transfer *transfer,
322 unsigned int words_to_transfer)
323 {
324 struct dma_async_tx_descriptor *tx_desc = NULL, *rx_desc = NULL;
325 enum dma_slave_buswidth width;
326 dma_cookie_t cookie;
327 int ret;
328
329 width = rzv2h_rspi_dma_width(rspi);
330 if (width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
331 return -EINVAL;
332
333 rx_desc = rzv2h_rspi_setup_dma_channel(rspi, rspi->controller->dma_rx,
334 &transfer->rx_sg, width,
335 DMA_DEV_TO_MEM);
336 if (IS_ERR(rx_desc))
337 return PTR_ERR(rx_desc);
338
339 tx_desc = rzv2h_rspi_setup_dma_channel(rspi, rspi->controller->dma_tx,
340 &transfer->tx_sg, width,
341 DMA_MEM_TO_DEV);
342 if (IS_ERR(tx_desc))
343 return PTR_ERR(tx_desc);
344
345 cookie = dmaengine_submit(rx_desc);
346 if (dma_submit_error(cookie))
347 return cookie;
348
349 cookie = dmaengine_submit(tx_desc);
350 if (dma_submit_error(cookie)) {
351 dmaengine_terminate_sync(rspi->controller->dma_rx);
352 return cookie;
353 }
354
355 /*
356 * DMA transfer does not need IRQs to be enabled.
357 * For PIO, we only use RX IRQ, so disable that.
358 */
359 disable_irq(rspi->irq_rx);
360
361 rspi->dma_callbacked = 0;
362
363 dma_async_issue_pending(rspi->controller->dma_rx);
364 dma_async_issue_pending(rspi->controller->dma_tx);
365 rzv2h_rspi_clear_all_irqs(rspi);
366
367 ret = wait_event_interruptible_timeout(rspi->wait, rspi->dma_callbacked, HZ);
368 if (ret) {
369 dmaengine_synchronize(rspi->controller->dma_tx);
370 dmaengine_synchronize(rspi->controller->dma_rx);
371 ret = 0;
372 } else {
373 dmaengine_terminate_sync(rspi->controller->dma_tx);
374 dmaengine_terminate_sync(rspi->controller->dma_rx);
375 ret = -ETIMEDOUT;
376 }
377
378 enable_irq(rspi->irq_rx);
379
380 return ret;
381 }
382
rzv2h_rspi_transfer_one(struct spi_controller * controller,struct spi_device * spi,struct spi_transfer * transfer)383 static int rzv2h_rspi_transfer_one(struct spi_controller *controller,
384 struct spi_device *spi,
385 struct spi_transfer *transfer)
386 {
387 struct rzv2h_rspi_priv *rspi = spi_controller_get_devdata(controller);
388 bool is_dma = spi_xfer_is_dma_mapped(controller, spi, transfer);
389 unsigned int words_to_transfer;
390 int ret;
391
392 transfer->effective_speed_hz = rspi->freq;
393 words_to_transfer = transfer->len / rspi->bytes_per_word;
394
395 if (is_dma)
396 ret = rzv2h_rspi_transfer_dma(rspi, spi, transfer, words_to_transfer);
397 else
398 ret = rzv2h_rspi_transfer_pio(rspi, spi, transfer, words_to_transfer);
399
400 rzv2h_rspi_clear_all_irqs(rspi);
401
402 if (is_dma && ret == -EAGAIN)
403 /* Retry with PIO */
404 transfer->error = SPI_TRANS_FAIL_NO_START;
405
406 return ret;
407 }
408
rzv2h_rspi_calc_bitrate(unsigned long tclk_rate,u8 spr,u8 brdv)409 static inline u32 rzv2h_rspi_calc_bitrate(unsigned long tclk_rate, u8 spr,
410 u8 brdv)
411 {
412 return DIV_ROUND_UP(tclk_rate, (2 * (spr + 1) * (1 << brdv)));
413 }
414
rzv2h_rspi_find_rate_variable(struct clk * clk,u32 hz,struct rzv2h_rspi_best_clock * best)415 static void rzv2h_rspi_find_rate_variable(struct clk *clk, u32 hz,
416 struct rzv2h_rspi_best_clock *best)
417 {
418 long clk_rate, clk_min_rate, clk_max_rate;
419 int min_rate_spr, max_rate_spr;
420 unsigned long error;
421 u32 actual_hz;
422 u8 brdv;
423 int spr;
424
425 /*
426 * On T2H / N2H, the source for the SPI clock is PCLKSPIn, which is a
427 * 1/32, 1/30, 1/25 or 1/24 divider of PLL4, which is 2400MHz,
428 * resulting in either 75MHz, 80MHz, 96MHz or 100MHz.
429 */
430 clk_min_rate = clk_round_rate(clk, 0);
431 if (clk_min_rate < 0)
432 return;
433
434 clk_max_rate = clk_round_rate(clk, ULONG_MAX);
435 if (clk_max_rate < 0)
436 return;
437
438 /*
439 * From the manual:
440 * Bit rate = f(PCLKSPIn) / (2 * (n + 1) * 2^N)
441 *
442 * If we adapt it to the current context, we get the following:
443 * hz = rate / ((spr + 1) * (1 << (brdv + 1)))
444 *
445 * This can be written in multiple forms depending on what we want to
446 * determine.
447 *
448 * To find the rate, having hz, spr and brdv:
449 * rate = hz * (spr + 1) * (1 << (brdv + 1)
450 *
451 * To find the spr, having rate, hz, and spr:
452 * spr = rate / (hz * (1 << (brdv + 1)) - 1
453 */
454
455 for (brdv = RSPI_SPCMD_BRDV_MIN; brdv <= RSPI_SPCMD_BRDV_MAX; brdv++) {
456 /* Calculate the divisor needed to find the SPR from a rate. */
457 u32 rate_div = hz * (1 << (brdv + 1));
458
459 /*
460 * If the SPR for the minimum rate is greater than the maximum
461 * allowed value skip this BRDV. The divisor increases with each
462 * BRDV iteration, so the following BRDV might result in a
463 * minimum SPR that is in the valid range.
464 */
465 min_rate_spr = DIV_ROUND_CLOSEST(clk_min_rate, rate_div) - 1;
466 if (min_rate_spr > RSPI_SPBR_SPR_MAX)
467 continue;
468
469 /*
470 * If the SPR for the maximum rate is less than the minimum
471 * allowed value, exit. The divisor only increases with each
472 * BRDV iteration, so the following BRDV cannot result in a
473 * maximum SPR that is in the valid range.
474 */
475 max_rate_spr = DIV_ROUND_CLOSEST(clk_max_rate, rate_div) - 1;
476 if (max_rate_spr < RSPI_SPBR_SPR_MIN)
477 break;
478
479 if (min_rate_spr < RSPI_SPBR_SPR_MIN)
480 min_rate_spr = RSPI_SPBR_SPR_MIN;
481
482 if (max_rate_spr > RSPI_SPBR_SPR_MAX)
483 max_rate_spr = RSPI_SPBR_SPR_MAX;
484
485 for (spr = min_rate_spr; spr <= max_rate_spr; spr++) {
486 clk_rate = (spr + 1) * rate_div;
487
488 clk_rate = clk_round_rate(clk, clk_rate);
489 if (clk_rate <= 0)
490 continue;
491
492 actual_hz = rzv2h_rspi_calc_bitrate(clk_rate, spr, brdv);
493 error = abs((long)hz - (long)actual_hz);
494
495 if (error >= best->error)
496 continue;
497
498 *best = (struct rzv2h_rspi_best_clock) {
499 .clk = clk,
500 .clk_rate = clk_rate,
501 .error = error,
502 .actual_hz = actual_hz,
503 .brdv = brdv,
504 .spr = spr,
505 };
506
507 if (!error)
508 return;
509 }
510 }
511 }
512
rzv2h_rspi_find_rate_fixed(struct clk * clk,u32 hz,struct rzv2h_rspi_best_clock * best)513 static void rzv2h_rspi_find_rate_fixed(struct clk *clk, u32 hz,
514 struct rzv2h_rspi_best_clock *best)
515 {
516 unsigned long clk_rate;
517 unsigned long error;
518 u32 actual_hz;
519 int spr;
520 u8 brdv;
521
522 /*
523 * From the manual:
524 * Bit rate = f(RSPI_n_TCLK)/(2*(n+1)*2^(N))
525 *
526 * Where:
527 * * RSPI_n_TCLK is fixed to 200MHz on V2H
528 * * n = SPR - is RSPI_SPBR.SPR (from 0 to 255)
529 * * N = BRDV - is RSPI_SPCMD.BRDV (from 0 to 3)
530 */
531 clk_rate = clk_get_rate(clk);
532 for (brdv = RSPI_SPCMD_BRDV_MIN; brdv <= RSPI_SPCMD_BRDV_MAX; brdv++) {
533 spr = DIV_ROUND_UP(clk_rate, hz * (1 << (brdv + 1)));
534 spr--;
535 /*
536 * Skip SPR=0 and BRDV=0 as it is not a valid combination:
537 * - On RZ/G3E, RZ/G3L, RZ/V2H(P) and RZ/V2N, RSPI_n_TCLK is
538 * fixed at 200MHz and SPR=0 and BRDV=0 results in the maximum
539 * bit rate of 100Mbps which is prohibited.
540 * - On RZ/T2H and RZ/N2H, when PCLK (125MHz) is used as
541 * the clock source, SPR=0 and BRDV=0 is explicitly listed
542 * as unsupported in the hardware manual (Table 36.7).
543 */
544 if (!spr && !brdv)
545 continue;
546 if (spr >= RSPI_SPBR_SPR_MIN && spr <= RSPI_SPBR_SPR_MAX)
547 goto clock_found;
548 }
549
550 return;
551
552 clock_found:
553 actual_hz = rzv2h_rspi_calc_bitrate(clk_rate, spr, brdv);
554 error = abs((long)hz - (long)actual_hz);
555
556 if (error >= best->error)
557 return;
558
559 *best = (struct rzv2h_rspi_best_clock) {
560 .clk = clk,
561 .clk_rate = clk_rate,
562 .error = error,
563 .actual_hz = actual_hz,
564 .brdv = brdv,
565 .spr = spr,
566 };
567 }
568
rzv2h_rspi_setup_clock(struct rzv2h_rspi_priv * rspi,u32 hz)569 static u32 rzv2h_rspi_setup_clock(struct rzv2h_rspi_priv *rspi, u32 hz)
570 {
571 struct rzv2h_rspi_best_clock best_clock = {
572 .error = ULONG_MAX,
573 };
574 int ret;
575
576 rspi->info->find_tclk_rate(rspi->tclk, hz, &best_clock);
577
578 if (best_clock.error && rspi->info->find_pclk_rate)
579 rspi->info->find_pclk_rate(rspi->pclk, hz, &best_clock);
580
581 if (!best_clock.clk_rate)
582 return 0;
583
584 ret = clk_set_rate(best_clock.clk, best_clock.clk_rate);
585 if (ret)
586 return 0;
587
588 rspi->use_pclk = best_clock.clk == rspi->pclk;
589 rspi->spr = best_clock.spr;
590 rspi->brdv = best_clock.brdv;
591
592 return best_clock.actual_hz;
593 }
594
rzv2h_rspi_prepare_message(struct spi_controller * ctlr,struct spi_message * message)595 static int rzv2h_rspi_prepare_message(struct spi_controller *ctlr,
596 struct spi_message *message)
597 {
598 struct rzv2h_rspi_priv *rspi = spi_controller_get_devdata(ctlr);
599 const struct spi_device *spi = message->spi;
600 struct spi_transfer *xfer;
601 u32 speed_hz = U32_MAX;
602 u8 bits_per_word;
603 u32 conf32;
604 u16 conf16;
605 u8 conf8;
606
607 /* Make sure SPCR.SPE is 0 before amending the configuration */
608 rzv2h_rspi_spe_disable(rspi);
609
610 list_for_each_entry(xfer, &message->transfers, transfer_list) {
611 if (!xfer->speed_hz)
612 continue;
613
614 speed_hz = min(xfer->speed_hz, speed_hz);
615 bits_per_word = xfer->bits_per_word;
616 }
617
618 if (speed_hz == U32_MAX)
619 return -EINVAL;
620
621 rspi->bytes_per_word = roundup_pow_of_two(BITS_TO_BYTES(bits_per_word));
622
623 if (speed_hz != rspi->last_speed_hz) {
624 rspi->freq = rzv2h_rspi_setup_clock(rspi, speed_hz);
625 if (!rspi->freq)
626 return -EINVAL;
627
628 rspi->last_speed_hz = speed_hz;
629 }
630
631 writeb(rspi->spr, rspi->base + RSPI_SPBR);
632
633 /* Configure the device to work in "host" mode */
634 conf32 = RSPI_SPCR_MSTR;
635
636 /* Auto-stop function */
637 conf32 |= RSPI_SPCR_SCKASE;
638
639 /* SPI receive buffer full interrupt enable */
640 conf32 |= RSPI_SPCR_SPRIE;
641
642 /* SPI transmit buffer empty interrupt enable */
643 conf32 |= RSPI_SPCR_SPTIE;
644
645 /* Bypass synchronization circuit */
646 conf32 |= FIELD_PREP(RSPI_SPCR_BPEN, rspi->use_pclk);
647
648 writel(conf32, rspi->base + RSPI_SPCR);
649
650 /* Use SPCMD0 only */
651 writeb(0x0, rspi->base + RSPI_SPSCR);
652
653 /* Setup loopback */
654 conf8 = FIELD_PREP(RSPI_SPPCR_SPLP2, !!(spi->mode & SPI_LOOP));
655 writeb(conf8, rspi->base + RSPI_SPPCR);
656
657 /* Setup mode */
658 conf32 = FIELD_PREP(RSPI_SPCMD_CPOL, !!(spi->mode & SPI_CPOL));
659 conf32 |= FIELD_PREP(RSPI_SPCMD_CPHA, !!(spi->mode & SPI_CPHA));
660 conf32 |= FIELD_PREP(RSPI_SPCMD_LSBF, !!(spi->mode & SPI_LSB_FIRST));
661 conf32 |= FIELD_PREP(RSPI_SPCMD_SPB, bits_per_word - 1);
662 conf32 |= FIELD_PREP(RSPI_SPCMD_BRDV, rspi->brdv);
663 conf32 |= FIELD_PREP(RSPI_SPCMD_SSLKP, 1);
664 conf32 |= FIELD_PREP(RSPI_SPCMD_SSLA, spi_get_chipselect(spi, 0));
665 writel(conf32, rspi->base + RSPI_SPCMD);
666 if (spi->mode & SPI_CS_HIGH)
667 writeb(BIT(spi_get_chipselect(spi, 0)), rspi->base + RSPI_SSLP);
668 else
669 writeb(0, rspi->base + RSPI_SSLP);
670
671 /* Setup FIFO thresholds */
672 conf16 = FIELD_PREP(RSPI_SPDCR2_TTRG, 0);
673 conf16 |= FIELD_PREP(RSPI_SPDCR2_RTRG, 0);
674 writew(conf16, rspi->base + RSPI_SPDCR2);
675
676 rzv2h_rspi_clear_fifos(rspi);
677
678 rzv2h_rspi_spe_enable(rspi);
679
680 return 0;
681 }
682
rzv2h_rspi_unprepare_message(struct spi_controller * ctlr,struct spi_message * message)683 static int rzv2h_rspi_unprepare_message(struct spi_controller *ctlr,
684 struct spi_message *message)
685 {
686 struct rzv2h_rspi_priv *rspi = spi_controller_get_devdata(ctlr);
687
688 rzv2h_rspi_spe_disable(rspi);
689
690 return 0;
691 }
692
rzv2h_rspi_probe(struct platform_device * pdev)693 static int rzv2h_rspi_probe(struct platform_device *pdev)
694 {
695 struct spi_controller *controller;
696 struct device *dev = &pdev->dev;
697 struct rzv2h_rspi_priv *rspi;
698 struct reset_control *reset;
699 struct clk_bulk_data *clks;
700 long tclk_rate;
701 int ret, i;
702
703 controller = devm_spi_alloc_host(dev, sizeof(*rspi));
704 if (!controller)
705 return -ENOMEM;
706
707 rspi = spi_controller_get_devdata(controller);
708 platform_set_drvdata(pdev, rspi);
709
710 rspi->controller = controller;
711 rspi->pdev = pdev;
712
713 rspi->info = device_get_match_data(dev);
714
715 rspi->base = devm_platform_ioremap_resource(pdev, 0);
716 if (IS_ERR(rspi->base))
717 return PTR_ERR(rspi->base);
718
719 ret = devm_clk_bulk_get_all_enabled(dev, &clks);
720 if (ret != rspi->info->num_clks)
721 return dev_err_probe(dev, ret >= 0 ? -EINVAL : ret,
722 "cannot get clocks\n");
723 for (i = 0; i < rspi->info->num_clks; i++) {
724 if (!strcmp(clks[i].id, rspi->info->tclk_name)) {
725 rspi->tclk = clks[i].clk;
726 } else if (rspi->info->find_pclk_rate &&
727 !strcmp(clks[i].id, "pclk")) {
728 rspi->pclk = clks[i].clk;
729 }
730 }
731
732 if (!rspi->tclk)
733 return dev_err_probe(dev, -EINVAL, "Failed to get tclk\n");
734
735 reset = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev,
736 "presetn");
737 if (IS_ERR(reset))
738 return dev_err_probe(&pdev->dev, PTR_ERR(reset),
739 "cannot get presetn reset\n");
740
741 reset = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev,
742 "tresetn");
743 if (IS_ERR(reset))
744 return dev_err_probe(&pdev->dev, PTR_ERR(reset),
745 "cannot get tresetn reset\n");
746
747 rspi->irq_rx = platform_get_irq_byname(pdev, "rx");
748 if (rspi->irq_rx < 0)
749 return dev_err_probe(dev, rspi->irq_rx, "cannot get IRQ 'rx'\n");
750
751 init_waitqueue_head(&rspi->wait);
752
753 ret = devm_request_irq(dev, rspi->irq_rx, rzv2h_rx_irq_handler, 0,
754 dev_name(dev), rspi);
755 if (ret) {
756 dev_err(dev, "cannot request `rx` IRQ\n");
757 return ret;
758 }
759
760 controller->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH |
761 SPI_LSB_FIRST | SPI_LOOP;
762 controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
763 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
764 controller->prepare_message = rzv2h_rspi_prepare_message;
765 controller->unprepare_message = rzv2h_rspi_unprepare_message;
766 controller->num_chipselect = 4;
767 controller->transfer_one = rzv2h_rspi_transfer_one;
768 controller->can_dma = rzv2h_rspi_can_dma;
769
770 tclk_rate = clk_round_rate(rspi->tclk, 0);
771 if (tclk_rate < 0)
772 return tclk_rate;
773
774 controller->min_speed_hz = rzv2h_rspi_calc_bitrate(tclk_rate,
775 RSPI_SPBR_SPR_MAX,
776 RSPI_SPCMD_BRDV_MAX);
777
778 controller->max_speed_hz = RSPI_MAX_SPEED_HZ;
779
780 controller->dma_tx = devm_dma_request_chan(dev, "tx");
781 if (IS_ERR(controller->dma_tx)) {
782 ret = dev_warn_probe(dev, PTR_ERR(controller->dma_tx),
783 "failed to request TX DMA channel\n");
784 if (ret == -EPROBE_DEFER)
785 return ret;
786 controller->dma_tx = NULL;
787 }
788
789 controller->dma_rx = devm_dma_request_chan(dev, "rx");
790 if (IS_ERR(controller->dma_rx)) {
791 ret = dev_warn_probe(dev, PTR_ERR(controller->dma_rx),
792 "failed to request RX DMA channel\n");
793 if (ret == -EPROBE_DEFER)
794 return ret;
795 controller->dma_rx = NULL;
796 }
797
798 ret = devm_spi_register_controller(dev, controller);
799 if (ret)
800 dev_err(dev, "register controller failed\n");
801
802 return ret;
803 }
804
805 static const struct rzv2h_rspi_info rzv2h_info = {
806 .find_tclk_rate = rzv2h_rspi_find_rate_fixed,
807 .tclk_name = "tclk",
808 .fifo_size = 16,
809 .num_clks = 3,
810 };
811
812 static const struct rzv2h_rspi_info rzg3l_info = {
813 .find_tclk_rate = rzv2h_rspi_find_rate_fixed,
814 .tclk_name = "tclk",
815 .fifo_size = 16,
816 .num_clks = 2,
817 };
818
819 static const struct rzv2h_rspi_info rzt2h_info = {
820 .find_tclk_rate = rzv2h_rspi_find_rate_variable,
821 .find_pclk_rate = rzv2h_rspi_find_rate_fixed,
822 .tclk_name = "pclkspi",
823 .fifo_size = 4,
824 .num_clks = 2,
825 };
826
827 static const struct of_device_id rzv2h_rspi_match[] = {
828 { .compatible = "renesas,r9a08g046-rspi", &rzg3l_info },
829 { .compatible = "renesas,r9a09g057-rspi", &rzv2h_info },
830 { .compatible = "renesas,r9a09g077-rspi", &rzt2h_info },
831 { /* sentinel */ }
832 };
833 MODULE_DEVICE_TABLE(of, rzv2h_rspi_match);
834
835 static struct platform_driver rzv2h_rspi_drv = {
836 .probe = rzv2h_rspi_probe,
837 .driver = {
838 .name = "rzv2h_rspi",
839 .of_match_table = rzv2h_rspi_match,
840 },
841 };
842 module_platform_driver(rzv2h_rspi_drv);
843
844 MODULE_LICENSE("GPL");
845 MODULE_AUTHOR("Fabrizio Castro <fabrizio.castro.jz@renesas.com>");
846 MODULE_DESCRIPTION("Renesas RZ/V2H(P) Serial Peripheral Interface Driver");
847