1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2020 Intel Corporation.
4 *
5 * Limitations:
6 * - The hardware supports fixed period & configures only 2-wire mode.
7 * - Supports normal polarity. Does not support changing polarity.
8 * - When PWM is disabled, output of PWM will become 0(inactive). It doesn't
9 * keep track of running period.
10 * - When duty cycle is changed, PWM output may be a mix of previous setting
11 * and new setting for the first period. From second period, the output is
12 * based on new setting.
13 * - It is a dedicated PWM fan controller. There are no other consumers for
14 * this PWM controller.
15 */
16 #include <linux/bitfield.h>
17 #include <linux/clk.h>
18 #include <linux/module.h>
19 #include <linux/platform_device.h>
20 #include <linux/pwm.h>
21 #include <linux/regmap.h>
22 #include <linux/reset.h>
23
24 #define LGM_PWM_FAN_CON0 0x0
25 #define LGM_PWM_FAN_EN_EN BIT(0)
26 #define LGM_PWM_FAN_EN_DIS 0x0
27 #define LGM_PWM_FAN_EN_MSK BIT(0)
28 #define LGM_PWM_FAN_MODE_2WIRE 0x0
29 #define LGM_PWM_FAN_MODE_MSK BIT(1)
30 #define LGM_PWM_FAN_DC_MSK GENMASK(23, 16)
31
32 #define LGM_PWM_FAN_CON1 0x4
33 #define LGM_PWM_FAN_MAX_RPM_MSK GENMASK(15, 0)
34
35 #define LGM_PWM_MAX_RPM (BIT(16) - 1)
36 #define LGM_PWM_DEFAULT_RPM 4000
37 #define LGM_PWM_MAX_DUTY_CYCLE (BIT(8) - 1)
38
39 #define LGM_PWM_DC_BITS 8
40
41 #define LGM_PWM_PERIOD_2WIRE_NS (40 * NSEC_PER_MSEC)
42
43 struct lgm_pwm_chip {
44 struct regmap *regmap;
45 u32 period;
46 };
47
to_lgm_pwm_chip(struct pwm_chip * chip)48 static inline struct lgm_pwm_chip *to_lgm_pwm_chip(struct pwm_chip *chip)
49 {
50 return pwmchip_get_drvdata(chip);
51 }
52
lgm_pwm_enable(struct pwm_chip * chip,bool enable)53 static int lgm_pwm_enable(struct pwm_chip *chip, bool enable)
54 {
55 struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
56 struct regmap *regmap = pc->regmap;
57
58 return regmap_update_bits(regmap, LGM_PWM_FAN_CON0, LGM_PWM_FAN_EN_MSK,
59 enable ? LGM_PWM_FAN_EN_EN : LGM_PWM_FAN_EN_DIS);
60 }
61
lgm_pwm_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)62 static int lgm_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
63 const struct pwm_state *state)
64 {
65 struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
66 u32 duty_cycle, val;
67 int ret;
68
69 /* The hardware only supports normal polarity and fixed period. */
70 if (state->polarity != PWM_POLARITY_NORMAL || state->period < pc->period)
71 return -EINVAL;
72
73 if (!state->enabled)
74 return lgm_pwm_enable(chip, 0);
75
76 duty_cycle = min_t(u64, state->duty_cycle, pc->period);
77 val = duty_cycle * LGM_PWM_MAX_DUTY_CYCLE / pc->period;
78
79 ret = regmap_update_bits(pc->regmap, LGM_PWM_FAN_CON0, LGM_PWM_FAN_DC_MSK,
80 FIELD_PREP(LGM_PWM_FAN_DC_MSK, val));
81 if (ret)
82 return ret;
83
84 return lgm_pwm_enable(chip, 1);
85 }
86
lgm_pwm_get_state(struct pwm_chip * chip,struct pwm_device * pwm,struct pwm_state * state)87 static int lgm_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
88 struct pwm_state *state)
89 {
90 struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
91 u32 duty, val;
92
93 state->enabled = regmap_test_bits(pc->regmap, LGM_PWM_FAN_CON0,
94 LGM_PWM_FAN_EN_EN);
95 state->polarity = PWM_POLARITY_NORMAL;
96 state->period = pc->period; /* fixed period */
97
98 regmap_read(pc->regmap, LGM_PWM_FAN_CON0, &val);
99 duty = FIELD_GET(LGM_PWM_FAN_DC_MSK, val);
100 state->duty_cycle = DIV_ROUND_UP(duty * pc->period, LGM_PWM_MAX_DUTY_CYCLE);
101
102 return 0;
103 }
104
105 static const struct pwm_ops lgm_pwm_ops = {
106 .get_state = lgm_pwm_get_state,
107 .apply = lgm_pwm_apply,
108 };
109
lgm_pwm_init(struct lgm_pwm_chip * pc)110 static void lgm_pwm_init(struct lgm_pwm_chip *pc)
111 {
112 struct regmap *regmap = pc->regmap;
113 u32 con0_val;
114
115 con0_val = FIELD_PREP(LGM_PWM_FAN_MODE_MSK, LGM_PWM_FAN_MODE_2WIRE);
116 pc->period = LGM_PWM_PERIOD_2WIRE_NS;
117 regmap_update_bits(regmap, LGM_PWM_FAN_CON1, LGM_PWM_FAN_MAX_RPM_MSK,
118 LGM_PWM_DEFAULT_RPM);
119 regmap_update_bits(regmap, LGM_PWM_FAN_CON0, LGM_PWM_FAN_MODE_MSK,
120 con0_val);
121 }
122
123 static const struct regmap_config lgm_pwm_regmap_config = {
124 .reg_bits = 32,
125 .reg_stride = 4,
126 .val_bits = 32,
127 };
128
lgm_clk_release(void * data)129 static void lgm_clk_release(void *data)
130 {
131 struct clk *clk = data;
132
133 clk_disable_unprepare(clk);
134 }
135
lgm_clk_enable(struct device * dev,struct clk * clk)136 static int lgm_clk_enable(struct device *dev, struct clk *clk)
137 {
138 int ret;
139
140 ret = clk_prepare_enable(clk);
141 if (ret)
142 return ret;
143
144 return devm_add_action_or_reset(dev, lgm_clk_release, clk);
145 }
146
lgm_reset_control_release(void * data)147 static void lgm_reset_control_release(void *data)
148 {
149 struct reset_control *rst = data;
150
151 reset_control_assert(rst);
152 }
153
lgm_reset_control_deassert(struct device * dev,struct reset_control * rst)154 static int lgm_reset_control_deassert(struct device *dev, struct reset_control *rst)
155 {
156 int ret;
157
158 ret = reset_control_deassert(rst);
159 if (ret)
160 return ret;
161
162 return devm_add_action_or_reset(dev, lgm_reset_control_release, rst);
163 }
164
lgm_pwm_probe(struct platform_device * pdev)165 static int lgm_pwm_probe(struct platform_device *pdev)
166 {
167 struct device *dev = &pdev->dev;
168 struct reset_control *rst;
169 struct pwm_chip *chip;
170 struct lgm_pwm_chip *pc;
171 void __iomem *io_base;
172 struct clk *clk;
173 int ret;
174
175 chip = devm_pwmchip_alloc(dev, 1, sizeof(*pc));
176 if (IS_ERR(chip))
177 return PTR_ERR(chip);
178 pc = to_lgm_pwm_chip(chip);
179
180 io_base = devm_platform_ioremap_resource(pdev, 0);
181 if (IS_ERR(io_base))
182 return PTR_ERR(io_base);
183
184 pc->regmap = devm_regmap_init_mmio(dev, io_base, &lgm_pwm_regmap_config);
185 if (IS_ERR(pc->regmap))
186 return dev_err_probe(dev, PTR_ERR(pc->regmap),
187 "failed to init register map\n");
188
189 clk = devm_clk_get(dev, NULL);
190 if (IS_ERR(clk))
191 return dev_err_probe(dev, PTR_ERR(clk), "failed to get clock\n");
192
193 ret = lgm_clk_enable(dev, clk);
194 if (ret)
195 return dev_err_probe(dev, ret, "failed to enable clock\n");
196
197 rst = devm_reset_control_get_exclusive(dev, NULL);
198 if (IS_ERR(rst))
199 return dev_err_probe(dev, PTR_ERR(rst),
200 "failed to get reset control\n");
201
202 ret = lgm_reset_control_deassert(dev, rst);
203 if (ret)
204 return dev_err_probe(dev, ret, "cannot deassert reset control\n");
205
206 chip->ops = &lgm_pwm_ops;
207
208 lgm_pwm_init(pc);
209
210 ret = devm_pwmchip_add(dev, chip);
211 if (ret < 0)
212 return dev_err_probe(dev, ret, "failed to add PWM chip\n");
213
214 return 0;
215 }
216
217 static const struct of_device_id lgm_pwm_of_match[] = {
218 { .compatible = "intel,lgm-pwm" },
219 { }
220 };
221 MODULE_DEVICE_TABLE(of, lgm_pwm_of_match);
222
223 static struct platform_driver lgm_pwm_driver = {
224 .driver = {
225 .name = "intel-pwm",
226 .of_match_table = lgm_pwm_of_match,
227 },
228 .probe = lgm_pwm_probe,
229 };
230 module_platform_driver(lgm_pwm_driver);
231
232 MODULE_DESCRIPTION("Intel LGM Pulse Width Modulator driver");
233 MODULE_LICENSE("GPL v2");
234