1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019 Realtek Corporation
3 */
4
5 #ifndef __RTK_MAIN_H_
6 #define __RTK_MAIN_H_
7
8 #include <net/mac80211.h>
9 #include <linux/vmalloc.h>
10 #include <linux/firmware.h>
11 #include <linux/average.h>
12 #include <linux/bitops.h>
13 #include <linux/bitfield.h>
14 #include <linux/iopoll.h>
15 #include <linux/interrupt.h>
16 #include <linux/workqueue.h>
17
18 #include "util.h"
19
20 #define RTW_MAX_MAC_ID_NUM 32
21 #define RTW_MAX_SEC_CAM_NUM 32
22 #define MAX_PG_CAM_BACKUP_NUM 8
23
24 #define RTW_SCAN_MAX_SSIDS 4
25
26 #define RTW_MAX_PATTERN_NUM 12
27 #define RTW_MAX_PATTERN_MASK_SIZE 16
28 #define RTW_MAX_PATTERN_SIZE 128
29
30 #define RTW_WATCH_DOG_DELAY_TIME round_jiffies_relative(HZ * 2)
31
32 #define RFREG_MASK 0xfffff
33 #define INV_RF_DATA 0xffffffff
34 #define TX_PAGE_SIZE_SHIFT 7
35 #define TX_PAGE_SIZE (1 << TX_PAGE_SIZE_SHIFT)
36
37 #define RTW_CHANNEL_WIDTH_MAX 3
38 #define RTW_RF_PATH_MAX 4
39 #define HW_FEATURE_LEN 13
40
41 #define RTW_TP_SHIFT 18 /* bytes/2s --> Mbps */
42
43 extern bool rtw_bf_support;
44 extern bool rtw_disable_lps_deep_mode;
45 extern unsigned int rtw_debug_mask;
46 extern bool rtw_edcca_enabled;
47 extern const struct ieee80211_ops rtw_ops;
48
49 #define RTW_MAX_CHANNEL_NUM_2G 14
50 #define RTW_MAX_CHANNEL_NUM_5G 49
51
52 struct rtw_dev;
53 struct rtw_debugfs;
54
55 enum rtw_hci_type {
56 RTW_HCI_TYPE_PCIE,
57 RTW_HCI_TYPE_USB,
58 RTW_HCI_TYPE_SDIO,
59
60 RTW_HCI_TYPE_UNDEFINE,
61 };
62
63 struct rtw_hci {
64 const struct rtw_hci_ops *ops;
65 enum rtw_hci_type type;
66
67 u32 rpwm_addr;
68 u32 cpwm_addr;
69
70 u8 bulkout_num;
71 };
72
73 #define IS_CH_5G_BAND_1(channel) ((channel) >= 36 && (channel <= 48))
74 #define IS_CH_5G_BAND_2(channel) ((channel) >= 52 && (channel <= 64))
75 #define IS_CH_5G_BAND_3(channel) ((channel) >= 100 && (channel <= 144))
76 #define IS_CH_5G_BAND_4(channel) ((channel) >= 149 && (channel <= 177))
77
78 #define IS_CH_5G_BAND_MID(channel) \
79 (IS_CH_5G_BAND_2(channel) || IS_CH_5G_BAND_3(channel))
80
81 #define IS_CH_2G_BAND(channel) ((channel) <= 14)
82 #define IS_CH_5G_BAND(channel) \
83 (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel) || \
84 IS_CH_5G_BAND_3(channel) || IS_CH_5G_BAND_4(channel))
85
86 enum rtw_supported_band {
87 RTW_BAND_2G = BIT(NL80211_BAND_2GHZ),
88 RTW_BAND_5G = BIT(NL80211_BAND_5GHZ),
89 RTW_BAND_60G = BIT(NL80211_BAND_60GHZ),
90 };
91
92 /* now, support up to 80M bw */
93 #define RTW_MAX_CHANNEL_WIDTH RTW_CHANNEL_WIDTH_80
94
95 enum rtw_bandwidth {
96 RTW_CHANNEL_WIDTH_20 = 0,
97 RTW_CHANNEL_WIDTH_40 = 1,
98 RTW_CHANNEL_WIDTH_80 = 2,
99 RTW_CHANNEL_WIDTH_160 = 3,
100 RTW_CHANNEL_WIDTH_80_80 = 4,
101 RTW_CHANNEL_WIDTH_5 = 5,
102 RTW_CHANNEL_WIDTH_10 = 6,
103 };
104
105 enum rtw_sc_offset {
106 RTW_SC_DONT_CARE = 0,
107 RTW_SC_20_UPPER = 1,
108 RTW_SC_20_LOWER = 2,
109 RTW_SC_20_UPMOST = 3,
110 RTW_SC_20_LOWEST = 4,
111 RTW_SC_40_UPPER = 9,
112 RTW_SC_40_LOWER = 10,
113 };
114
115 enum rtw_net_type {
116 RTW_NET_NO_LINK = 0,
117 RTW_NET_AD_HOC = 1,
118 RTW_NET_MGD_LINKED = 2,
119 RTW_NET_AP_MODE = 3,
120 };
121
122 enum rtw_rf_type {
123 RF_1T1R = 0,
124 RF_1T2R = 1,
125 RF_2T2R = 2,
126 RF_2T3R = 3,
127 RF_2T4R = 4,
128 RF_3T3R = 5,
129 RF_3T4R = 6,
130 RF_4T4R = 7,
131 RF_TYPE_MAX,
132 };
133
134 enum rtw_rf_path {
135 RF_PATH_A = 0,
136 RF_PATH_B = 1,
137 RF_PATH_C = 2,
138 RF_PATH_D = 3,
139 };
140
141 enum rtw_bb_path {
142 BB_PATH_A = BIT(0),
143 BB_PATH_B = BIT(1),
144 BB_PATH_C = BIT(2),
145 BB_PATH_D = BIT(3),
146
147 BB_PATH_AB = (BB_PATH_A | BB_PATH_B),
148 BB_PATH_AC = (BB_PATH_A | BB_PATH_C),
149 BB_PATH_AD = (BB_PATH_A | BB_PATH_D),
150 BB_PATH_BC = (BB_PATH_B | BB_PATH_C),
151 BB_PATH_BD = (BB_PATH_B | BB_PATH_D),
152 BB_PATH_CD = (BB_PATH_C | BB_PATH_D),
153
154 BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C),
155 BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D),
156 BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D),
157 BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D),
158
159 BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D),
160 };
161
162 enum rtw_rate_section {
163 RTW_RATE_SECTION_CCK = 0,
164 RTW_RATE_SECTION_OFDM,
165 RTW_RATE_SECTION_HT_1S,
166 RTW_RATE_SECTION_HT_2S,
167 RTW_RATE_SECTION_VHT_1S,
168 RTW_RATE_SECTION_VHT_2S,
169 __RTW_RATE_SECTION_2SS_MAX = RTW_RATE_SECTION_VHT_2S,
170 RTW_RATE_SECTION_HT_3S,
171 RTW_RATE_SECTION_HT_4S,
172 RTW_RATE_SECTION_VHT_3S,
173 RTW_RATE_SECTION_VHT_4S,
174
175 /* keep last */
176 RTW_RATE_SECTION_NUM,
177 };
178
179 enum rtw_wireless_set {
180 WIRELESS_CCK = 0x00000001,
181 WIRELESS_OFDM = 0x00000002,
182 WIRELESS_HT = 0x00000004,
183 WIRELESS_VHT = 0x00000008,
184 };
185
186 #define HT_STBC_EN BIT(0)
187 #define VHT_STBC_EN BIT(1)
188 #define HT_LDPC_EN BIT(0)
189 #define VHT_LDPC_EN BIT(1)
190
191 enum rtw_chip_type {
192 RTW_CHIP_TYPE_8822B,
193 RTW_CHIP_TYPE_8822C,
194 RTW_CHIP_TYPE_8723D,
195 RTW_CHIP_TYPE_8821C,
196 RTW_CHIP_TYPE_8703B,
197 RTW_CHIP_TYPE_8821A,
198 RTW_CHIP_TYPE_8812A,
199 RTW_CHIP_TYPE_8814A,
200 };
201
202 enum rtw_tx_queue_type {
203 /* the order of AC queues matters */
204 RTW_TX_QUEUE_BK = 0x0,
205 RTW_TX_QUEUE_BE = 0x1,
206 RTW_TX_QUEUE_VI = 0x2,
207 RTW_TX_QUEUE_VO = 0x3,
208
209 RTW_TX_QUEUE_BCN = 0x4,
210 RTW_TX_QUEUE_MGMT = 0x5,
211 RTW_TX_QUEUE_HI0 = 0x6,
212 RTW_TX_QUEUE_H2C = 0x7,
213 /* keep it last */
214 RTK_MAX_TX_QUEUE_NUM
215 };
216
217 enum rtw_rx_queue_type {
218 RTW_RX_QUEUE_MPDU = 0x0,
219 RTW_RX_QUEUE_C2H = 0x1,
220 /* keep it last */
221 RTK_MAX_RX_QUEUE_NUM
222 };
223
224 enum rtw_fw_type {
225 RTW_NORMAL_FW = 0x0,
226 RTW_WOWLAN_FW = 0x1,
227 };
228
229 enum rtw_rate_index {
230 RTW_RATEID_BGN_40M_2SS = 0,
231 RTW_RATEID_BGN_40M_1SS = 1,
232 RTW_RATEID_BGN_20M_2SS = 2,
233 RTW_RATEID_BGN_20M_1SS = 3,
234 RTW_RATEID_GN_N2SS = 4,
235 RTW_RATEID_GN_N1SS = 5,
236 RTW_RATEID_BG = 6,
237 RTW_RATEID_G = 7,
238 RTW_RATEID_B_20M = 8,
239 RTW_RATEID_ARFR0_AC_2SS = 9,
240 RTW_RATEID_ARFR1_AC_1SS = 10,
241 RTW_RATEID_ARFR2_AC_2G_1SS = 11,
242 RTW_RATEID_ARFR3_AC_2G_2SS = 12,
243 RTW_RATEID_ARFR4_AC_3SS = 13,
244 RTW_RATEID_ARFR5_N_3SS = 14,
245 RTW_RATEID_ARFR7_N_4SS = 15,
246 RTW_RATEID_ARFR6_AC_4SS = 16
247 };
248
249 enum rtw_trx_desc_rate {
250 DESC_RATE1M = 0x00,
251 DESC_RATE2M = 0x01,
252 DESC_RATE5_5M = 0x02,
253 DESC_RATE11M = 0x03,
254
255 DESC_RATE6M = 0x04,
256 DESC_RATE9M = 0x05,
257 DESC_RATE12M = 0x06,
258 DESC_RATE18M = 0x07,
259 DESC_RATE24M = 0x08,
260 DESC_RATE36M = 0x09,
261 DESC_RATE48M = 0x0a,
262 DESC_RATE54M = 0x0b,
263
264 DESC_RATEMCS0 = 0x0c,
265 DESC_RATEMCS1 = 0x0d,
266 DESC_RATEMCS2 = 0x0e,
267 DESC_RATEMCS3 = 0x0f,
268 DESC_RATEMCS4 = 0x10,
269 DESC_RATEMCS5 = 0x11,
270 DESC_RATEMCS6 = 0x12,
271 DESC_RATEMCS7 = 0x13,
272 DESC_RATEMCS8 = 0x14,
273 DESC_RATEMCS9 = 0x15,
274 DESC_RATEMCS10 = 0x16,
275 DESC_RATEMCS11 = 0x17,
276 DESC_RATEMCS12 = 0x18,
277 DESC_RATEMCS13 = 0x19,
278 DESC_RATEMCS14 = 0x1a,
279 DESC_RATEMCS15 = 0x1b,
280 DESC_RATEMCS16 = 0x1c,
281 DESC_RATEMCS17 = 0x1d,
282 DESC_RATEMCS18 = 0x1e,
283 DESC_RATEMCS19 = 0x1f,
284 DESC_RATEMCS20 = 0x20,
285 DESC_RATEMCS21 = 0x21,
286 DESC_RATEMCS22 = 0x22,
287 DESC_RATEMCS23 = 0x23,
288 DESC_RATEMCS24 = 0x24,
289 DESC_RATEMCS25 = 0x25,
290 DESC_RATEMCS26 = 0x26,
291 DESC_RATEMCS27 = 0x27,
292 DESC_RATEMCS28 = 0x28,
293 DESC_RATEMCS29 = 0x29,
294 DESC_RATEMCS30 = 0x2a,
295 DESC_RATEMCS31 = 0x2b,
296
297 DESC_RATEVHT1SS_MCS0 = 0x2c,
298 DESC_RATEVHT1SS_MCS1 = 0x2d,
299 DESC_RATEVHT1SS_MCS2 = 0x2e,
300 DESC_RATEVHT1SS_MCS3 = 0x2f,
301 DESC_RATEVHT1SS_MCS4 = 0x30,
302 DESC_RATEVHT1SS_MCS5 = 0x31,
303 DESC_RATEVHT1SS_MCS6 = 0x32,
304 DESC_RATEVHT1SS_MCS7 = 0x33,
305 DESC_RATEVHT1SS_MCS8 = 0x34,
306 DESC_RATEVHT1SS_MCS9 = 0x35,
307
308 DESC_RATEVHT2SS_MCS0 = 0x36,
309 DESC_RATEVHT2SS_MCS1 = 0x37,
310 DESC_RATEVHT2SS_MCS2 = 0x38,
311 DESC_RATEVHT2SS_MCS3 = 0x39,
312 DESC_RATEVHT2SS_MCS4 = 0x3a,
313 DESC_RATEVHT2SS_MCS5 = 0x3b,
314 DESC_RATEVHT2SS_MCS6 = 0x3c,
315 DESC_RATEVHT2SS_MCS7 = 0x3d,
316 DESC_RATEVHT2SS_MCS8 = 0x3e,
317 DESC_RATEVHT2SS_MCS9 = 0x3f,
318
319 DESC_RATEVHT3SS_MCS0 = 0x40,
320 DESC_RATEVHT3SS_MCS1 = 0x41,
321 DESC_RATEVHT3SS_MCS2 = 0x42,
322 DESC_RATEVHT3SS_MCS3 = 0x43,
323 DESC_RATEVHT3SS_MCS4 = 0x44,
324 DESC_RATEVHT3SS_MCS5 = 0x45,
325 DESC_RATEVHT3SS_MCS6 = 0x46,
326 DESC_RATEVHT3SS_MCS7 = 0x47,
327 DESC_RATEVHT3SS_MCS8 = 0x48,
328 DESC_RATEVHT3SS_MCS9 = 0x49,
329
330 DESC_RATEVHT4SS_MCS0 = 0x4a,
331 DESC_RATEVHT4SS_MCS1 = 0x4b,
332 DESC_RATEVHT4SS_MCS2 = 0x4c,
333 DESC_RATEVHT4SS_MCS3 = 0x4d,
334 DESC_RATEVHT4SS_MCS4 = 0x4e,
335 DESC_RATEVHT4SS_MCS5 = 0x4f,
336 DESC_RATEVHT4SS_MCS6 = 0x50,
337 DESC_RATEVHT4SS_MCS7 = 0x51,
338 DESC_RATEVHT4SS_MCS8 = 0x52,
339 DESC_RATEVHT4SS_MCS9 = 0x53,
340
341 DESC_RATE_MAX,
342 };
343
344 enum rtw_regulatory_domains {
345 RTW_REGD_FCC = 0,
346 RTW_REGD_MKK = 1,
347 RTW_REGD_ETSI = 2,
348 RTW_REGD_IC = 3,
349 RTW_REGD_KCC = 4,
350 RTW_REGD_ACMA = 5,
351 RTW_REGD_CHILE = 6,
352 RTW_REGD_UKRAINE = 7,
353 RTW_REGD_MEXICO = 8,
354 RTW_REGD_CN = 9,
355 RTW_REGD_QATAR = 10,
356 RTW_REGD_UK = 11,
357
358 RTW_REGD_WW,
359 RTW_REGD_MAX
360 };
361
362 enum rtw_txq_flags {
363 RTW_TXQ_AMPDU,
364 RTW_TXQ_BLOCK_BA,
365 };
366
367 enum rtw_flags {
368 RTW_FLAG_RUNNING,
369 RTW_FLAG_FW_RUNNING,
370 RTW_FLAG_SCANNING,
371 RTW_FLAG_POWERON,
372 RTW_FLAG_LEISURE_PS,
373 RTW_FLAG_LEISURE_PS_DEEP,
374 RTW_FLAG_DIG_DISABLE,
375 RTW_FLAG_BUSY_TRAFFIC,
376 RTW_FLAG_WOWLAN,
377 RTW_FLAG_RESTARTING,
378 RTW_FLAG_RESTART_TRIGGERING,
379 RTW_FLAG_FORCE_LOWEST_RATE,
380
381 NUM_OF_RTW_FLAGS,
382 };
383
384 enum rtw_evm {
385 RTW_EVM_OFDM = 0,
386 RTW_EVM_1SS,
387 RTW_EVM_2SS_A,
388 RTW_EVM_2SS_B,
389 RTW_EVM_3SS_A,
390 RTW_EVM_3SS_B,
391 RTW_EVM_3SS_C,
392 /* keep it last */
393 RTW_EVM_NUM
394 };
395
396 enum rtw_snr {
397 RTW_SNR_OFDM_A = 0,
398 RTW_SNR_OFDM_B,
399 RTW_SNR_OFDM_C,
400 RTW_SNR_OFDM_D,
401 RTW_SNR_1SS_A,
402 RTW_SNR_1SS_B,
403 RTW_SNR_1SS_C,
404 RTW_SNR_1SS_D,
405 RTW_SNR_2SS_A,
406 RTW_SNR_2SS_B,
407 RTW_SNR_2SS_C,
408 RTW_SNR_2SS_D,
409 RTW_SNR_3SS_A,
410 RTW_SNR_3SS_B,
411 RTW_SNR_3SS_C,
412 RTW_SNR_3SS_D,
413 /* keep it last */
414 RTW_SNR_NUM
415 };
416
417 enum rtw_port {
418 RTW_PORT_0 = 0,
419 RTW_PORT_1 = 1,
420 RTW_PORT_2 = 2,
421 RTW_PORT_3 = 3,
422 RTW_PORT_4 = 4,
423 RTW_PORT_NUM
424 };
425
426 enum rtw_wow_flags {
427 RTW_WOW_FLAG_EN_MAGIC_PKT,
428 RTW_WOW_FLAG_EN_REKEY_PKT,
429 RTW_WOW_FLAG_EN_DISCONNECT,
430
431 /* keep it last */
432 RTW_WOW_FLAG_MAX,
433 };
434
435 /* the power index is represented by differences, which cck-1s & ht40-1s are
436 * the base values, so for 1s's differences, there are only ht20 & ofdm
437 */
438 struct rtw_2g_1s_pwr_idx_diff {
439 #ifdef __LITTLE_ENDIAN
440 s8 ofdm:4;
441 s8 bw20:4;
442 #else
443 s8 bw20:4;
444 s8 ofdm:4;
445 #endif
446 } __packed;
447
448 struct rtw_2g_ns_pwr_idx_diff {
449 #ifdef __LITTLE_ENDIAN
450 s8 bw20:4;
451 s8 bw40:4;
452 s8 cck:4;
453 s8 ofdm:4;
454 #else
455 s8 ofdm:4;
456 s8 cck:4;
457 s8 bw40:4;
458 s8 bw20:4;
459 #endif
460 } __packed;
461
462 struct rtw_2g_txpwr_idx {
463 u8 cck_base[6];
464 u8 bw40_base[5];
465 struct rtw_2g_1s_pwr_idx_diff ht_1s_diff;
466 struct rtw_2g_ns_pwr_idx_diff ht_2s_diff;
467 struct rtw_2g_ns_pwr_idx_diff ht_3s_diff;
468 struct rtw_2g_ns_pwr_idx_diff ht_4s_diff;
469 };
470
471 struct rtw_5g_ht_1s_pwr_idx_diff {
472 #ifdef __LITTLE_ENDIAN
473 s8 ofdm:4;
474 s8 bw20:4;
475 #else
476 s8 bw20:4;
477 s8 ofdm:4;
478 #endif
479 } __packed;
480
481 struct rtw_5g_ht_ns_pwr_idx_diff {
482 #ifdef __LITTLE_ENDIAN
483 s8 bw20:4;
484 s8 bw40:4;
485 #else
486 s8 bw40:4;
487 s8 bw20:4;
488 #endif
489 } __packed;
490
491 struct rtw_5g_ofdm_ns_pwr_idx_diff {
492 #ifdef __LITTLE_ENDIAN
493 s8 ofdm_3s:4;
494 s8 ofdm_2s:4;
495 s8 ofdm_4s:4;
496 s8 res:4;
497 #else
498 s8 res:4;
499 s8 ofdm_4s:4;
500 s8 ofdm_2s:4;
501 s8 ofdm_3s:4;
502 #endif
503 } __packed;
504
505 struct rtw_5g_vht_ns_pwr_idx_diff {
506 #ifdef __LITTLE_ENDIAN
507 s8 bw160:4;
508 s8 bw80:4;
509 #else
510 s8 bw80:4;
511 s8 bw160:4;
512 #endif
513 } __packed;
514
515 struct rtw_5g_txpwr_idx {
516 u8 bw40_base[14];
517 struct rtw_5g_ht_1s_pwr_idx_diff ht_1s_diff;
518 struct rtw_5g_ht_ns_pwr_idx_diff ht_2s_diff;
519 struct rtw_5g_ht_ns_pwr_idx_diff ht_3s_diff;
520 struct rtw_5g_ht_ns_pwr_idx_diff ht_4s_diff;
521 struct rtw_5g_ofdm_ns_pwr_idx_diff ofdm_diff;
522 struct rtw_5g_vht_ns_pwr_idx_diff vht_1s_diff;
523 struct rtw_5g_vht_ns_pwr_idx_diff vht_2s_diff;
524 struct rtw_5g_vht_ns_pwr_idx_diff vht_3s_diff;
525 struct rtw_5g_vht_ns_pwr_idx_diff vht_4s_diff;
526 } __packed;
527
528 struct rtw_txpwr_idx {
529 struct rtw_2g_txpwr_idx pwr_idx_2g;
530 struct rtw_5g_txpwr_idx pwr_idx_5g;
531 } __packed;
532
533 struct rtw_channel_params {
534 u8 center_chan;
535 u8 primary_chan;
536 u8 bandwidth;
537 };
538
539 struct rtw_hw_reg {
540 u32 addr;
541 u32 mask;
542 };
543
544 struct rtw_hw_reg_desc {
545 u32 addr;
546 u32 mask;
547 const char *desc;
548 };
549
550 struct rtw_ltecoex_addr {
551 u32 ctrl;
552 u32 wdata;
553 u32 rdata;
554 };
555
556 struct rtw_reg_domain {
557 u32 addr;
558 u32 mask;
559 #define RTW_REG_DOMAIN_MAC32 0
560 #define RTW_REG_DOMAIN_MAC16 1
561 #define RTW_REG_DOMAIN_MAC8 2
562 #define RTW_REG_DOMAIN_RF_A 3
563 #define RTW_REG_DOMAIN_RF_B 4
564 #define RTW_REG_DOMAIN_NL 0xFF
565 u8 domain;
566 };
567
568 struct rtw_rf_sipi_addr {
569 u32 hssi_1;
570 u32 hssi_2;
571 u32 lssi_read;
572 u32 lssi_read_pi;
573 };
574
575 struct rtw_hw_reg_offset {
576 struct rtw_hw_reg hw_reg;
577 u8 offset;
578 };
579
580 struct rtw_backup_info {
581 u8 len;
582 u32 reg;
583 u32 val;
584 };
585
586 enum rtw_vif_port_set {
587 PORT_SET_MAC_ADDR = BIT(0),
588 PORT_SET_BSSID = BIT(1),
589 PORT_SET_NET_TYPE = BIT(2),
590 PORT_SET_AID = BIT(3),
591 PORT_SET_BCN_CTRL = BIT(4),
592 };
593
594 struct rtw_vif_port {
595 struct rtw_hw_reg mac_addr;
596 struct rtw_hw_reg bssid;
597 struct rtw_hw_reg net_type;
598 struct rtw_hw_reg aid;
599 struct rtw_hw_reg bcn_ctrl;
600 };
601
602 struct rtw_tx_pkt_info {
603 u32 tx_pkt_size;
604 u8 offset;
605 u8 pkt_offset;
606 u8 tim_offset;
607 u8 mac_id;
608 u8 rate_id;
609 u8 rate;
610 u8 qsel;
611 u8 bw;
612 u8 sec_type;
613 u8 sn;
614 bool ampdu_en;
615 u8 ampdu_factor;
616 u8 ampdu_density;
617 u16 seq;
618 bool stbc;
619 bool ldpc;
620 bool dis_rate_fallback;
621 bool bmc;
622 bool use_rate;
623 bool ls;
624 bool fs;
625 bool short_gi;
626 bool report;
627 bool rts;
628 bool dis_qselseq;
629 bool en_hwseq;
630 u8 hw_ssn_sel;
631 bool nav_use_hdr;
632 bool bt_null;
633 };
634
635 struct rtw_rx_pkt_stat {
636 bool phy_status;
637 bool icv_err;
638 bool crc_err;
639 bool decrypted;
640 bool is_c2h;
641 bool channel_invalid;
642
643 s32 signal_power;
644 u16 pkt_len;
645 u8 bw;
646 u8 drv_info_sz;
647 u8 shift;
648 u8 rate;
649 u8 mac_id;
650 u8 cam_id;
651 u8 ppdu_cnt;
652 u32 tsf_low;
653 s8 rx_power[RTW_RF_PATH_MAX];
654 u8 rssi;
655 u8 rxsc;
656 s8 rx_snr[RTW_RF_PATH_MAX];
657 u8 rx_evm[RTW_RF_PATH_MAX];
658 s8 cfo_tail[RTW_RF_PATH_MAX];
659 u16 freq;
660 u8 band;
661
662 struct rtw_sta_info *si;
663 struct ieee80211_vif *vif;
664 struct ieee80211_hdr *hdr;
665 };
666
667 DECLARE_EWMA(tp, 10, 2);
668
669 struct rtw_traffic_stats {
670 /* units in bytes */
671 u64 tx_unicast;
672 u64 rx_unicast;
673
674 /* count for packets */
675 u64 tx_cnt;
676 u64 rx_cnt;
677
678 /* units in Mbps */
679 u32 tx_throughput;
680 u32 rx_throughput;
681 struct ewma_tp tx_ewma_tp;
682 struct ewma_tp rx_ewma_tp;
683 };
684
685 enum rtw_lps_mode {
686 RTW_MODE_ACTIVE = 0,
687 RTW_MODE_LPS = 1,
688 RTW_MODE_WMM_PS = 2,
689 };
690
691 enum rtw_lps_deep_mode {
692 LPS_DEEP_MODE_NONE = 0,
693 LPS_DEEP_MODE_LCLK = 1,
694 LPS_DEEP_MODE_PG = 2,
695 };
696
697 enum rtw_pwr_state {
698 RTW_RF_OFF = 0x0,
699 RTW_RF_ON = 0x4,
700 RTW_ALL_ON = 0xc,
701 };
702
703 struct rtw_lps_conf {
704 enum rtw_lps_mode mode;
705 enum rtw_lps_deep_mode deep_mode;
706 enum rtw_lps_deep_mode wow_deep_mode;
707 enum rtw_pwr_state state;
708 u8 awake_interval;
709 u8 rlbm;
710 u8 smart_ps;
711 u8 port_id;
712 bool sec_cam_backup;
713 bool pattern_cam_backup;
714 };
715
716 enum rtw_hw_key_type {
717 RTW_CAM_NONE = 0,
718 RTW_CAM_WEP40 = 1,
719 RTW_CAM_TKIP = 2,
720 RTW_CAM_AES = 4,
721 RTW_CAM_WEP104 = 5,
722 };
723
724 struct rtw_cam_entry {
725 bool valid;
726 bool group;
727 u8 addr[ETH_ALEN];
728 u8 hw_key_type;
729 struct ieee80211_key_conf *key;
730 };
731
732 struct rtw_sec_desc {
733 /* search strategy */
734 bool default_key_search;
735
736 u32 total_cam_num;
737 struct rtw_cam_entry cam_table[RTW_MAX_SEC_CAM_NUM];
738 DECLARE_BITMAP(cam_map, RTW_MAX_SEC_CAM_NUM);
739 };
740
741 struct rtw_tx_report {
742 /* protect the tx report queue */
743 spinlock_t q_lock;
744 struct sk_buff_head queue;
745 atomic_t sn;
746 struct timer_list purge_timer;
747 };
748
749 struct rtw_ra_report {
750 struct rate_info txrate;
751 u32 bit_rate;
752 u8 desc_rate;
753 };
754
755 struct rtw_txq {
756 struct list_head list;
757 unsigned long flags;
758 };
759
760 DECLARE_EWMA(rssi, 10, 16);
761
762 struct rtw_sta_info {
763 struct rtw_dev *rtwdev;
764 struct ieee80211_sta *sta;
765 struct ieee80211_vif *vif;
766
767 struct ewma_rssi avg_rssi;
768 u8 rssi_level;
769
770 u8 mac_id;
771 u8 rate_id;
772 enum rtw_bandwidth bw_mode;
773 u8 stbc_en:2;
774 u8 ldpc_en:2;
775 bool sgi_enable;
776 bool vht_enable;
777 u8 init_ra_lv;
778 u64 ra_mask;
779
780 DECLARE_BITMAP(tid_ba, IEEE80211_NUM_TIDS);
781
782 struct rtw_ra_report ra_report;
783
784 bool use_cfg_mask;
785 struct cfg80211_bitrate_mask *mask;
786
787 struct work_struct rc_work;
788 };
789
790 enum rtw_bfee_role {
791 RTW_BFEE_NONE,
792 RTW_BFEE_SU,
793 RTW_BFEE_MU
794 };
795
796 struct rtw_bfee {
797 enum rtw_bfee_role role;
798
799 u16 p_aid;
800 u8 g_id;
801 u8 mac_addr[ETH_ALEN];
802 u8 sound_dim;
803
804 /* SU-MIMO */
805 u8 su_reg_index;
806
807 /* MU-MIMO */
808 u16 aid;
809 };
810
811 struct rtw_bf_info {
812 u8 bfer_mu_cnt;
813 u8 bfer_su_cnt;
814 DECLARE_BITMAP(bfer_su_reg_maping, 2);
815 u8 cur_csi_rpt_rate;
816 };
817
818 struct rtw_vif {
819 enum rtw_net_type net_type;
820 u16 aid;
821 u8 mac_id;
822 u8 mac_addr[ETH_ALEN];
823 u8 bssid[ETH_ALEN];
824 u8 port;
825 u8 bcn_ctrl;
826 struct list_head rsvd_page_list;
827 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS];
828 const struct rtw_vif_port *conf;
829 struct cfg80211_scan_request *scan_req;
830 struct ieee80211_scan_ies *scan_ies;
831
832 struct rtw_traffic_stats stats;
833
834 struct rtw_bfee bfee;
835 };
836
837 struct rtw_regulatory {
838 char alpha2[2] __nonstring;
839 u8 txpwr_regd_2g;
840 u8 txpwr_regd_5g;
841 };
842
843 enum rtw_regd_state {
844 RTW_REGD_STATE_WORLDWIDE,
845 RTW_REGD_STATE_PROGRAMMED,
846 RTW_REGD_STATE_SETTING,
847
848 RTW_REGD_STATE_NR,
849 };
850
851 struct rtw_regd {
852 enum rtw_regd_state state;
853 const struct rtw_regulatory *regulatory;
854 enum nl80211_dfs_regions dfs_region;
855 };
856
857 struct rtw_chip_ops {
858 int (*power_on)(struct rtw_dev *rtwdev);
859 void (*power_off)(struct rtw_dev *rtwdev);
860 int (*mac_init)(struct rtw_dev *rtwdev);
861 int (*mac_postinit)(struct rtw_dev *rtwdev);
862 int (*dump_fw_crash)(struct rtw_dev *rtwdev);
863 void (*shutdown)(struct rtw_dev *rtwdev);
864 int (*read_efuse)(struct rtw_dev *rtwdev, u8 *map);
865 void (*phy_set_param)(struct rtw_dev *rtwdev);
866 void (*set_channel)(struct rtw_dev *rtwdev, u8 channel,
867 u8 bandwidth, u8 primary_chan_idx);
868 void (*query_phy_status)(struct rtw_dev *rtwdev, u8 *phy_status,
869 struct rtw_rx_pkt_stat *pkt_stat);
870 u32 (*read_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
871 u32 addr, u32 mask);
872 bool (*write_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
873 u32 addr, u32 mask, u32 data);
874 void (*set_tx_power_index)(struct rtw_dev *rtwdev);
875 int (*rsvd_page_dump)(struct rtw_dev *rtwdev, u8 *buf, u32 offset,
876 u32 size);
877 int (*set_antenna)(struct rtw_dev *rtwdev, int radio_idx,
878 u32 antenna_tx,
879 u32 antenna_rx);
880 void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable);
881 void (*efuse_grant)(struct rtw_dev *rtwdev, bool enable);
882 void (*set_ampdu_factor)(struct rtw_dev *rtwdev, u8 factor);
883 void (*false_alarm_statistics)(struct rtw_dev *rtwdev);
884 void (*phy_calibration)(struct rtw_dev *rtwdev);
885 void (*dpk_track)(struct rtw_dev *rtwdev);
886 void (*cck_pd_set)(struct rtw_dev *rtwdev, u8 level);
887 void (*pwr_track)(struct rtw_dev *rtwdev);
888 void (*config_bfee)(struct rtw_dev *rtwdev, struct rtw_vif *vif,
889 struct rtw_bfee *bfee, bool enable);
890 void (*set_gid_table)(struct rtw_dev *rtwdev,
891 struct ieee80211_vif *vif,
892 struct ieee80211_bss_conf *conf);
893 void (*cfg_csi_rate)(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate,
894 u8 fixrate_en, u8 *new_rate);
895 void (*adaptivity_init)(struct rtw_dev *rtwdev);
896 void (*adaptivity)(struct rtw_dev *rtwdev);
897 void (*cfo_init)(struct rtw_dev *rtwdev);
898 void (*cfo_track)(struct rtw_dev *rtwdev);
899 void (*config_tx_path)(struct rtw_dev *rtwdev, u8 tx_path,
900 enum rtw_bb_path tx_path_1ss,
901 enum rtw_bb_path tx_path_cck,
902 bool is_tx2_path);
903 void (*config_txrx_mode)(struct rtw_dev *rtwdev, u8 tx_path,
904 u8 rx_path, bool is_tx2_path);
905 void (*led_set)(struct led_classdev *led, enum led_brightness brightness);
906 /* for USB/SDIO only */
907 void (*fill_txdesc_checksum)(struct rtw_dev *rtwdev,
908 struct rtw_tx_pkt_info *pkt_info,
909 u8 *txdesc);
910
911 /* for coex */
912 void (*coex_set_init)(struct rtw_dev *rtwdev);
913 void (*coex_set_ant_switch)(struct rtw_dev *rtwdev,
914 u8 ctrl_type, u8 pos_type);
915 void (*coex_set_gnt_fix)(struct rtw_dev *rtwdev);
916 void (*coex_set_gnt_debug)(struct rtw_dev *rtwdev);
917 void (*coex_set_rfe_type)(struct rtw_dev *rtwdev);
918 void (*coex_set_wl_tx_power)(struct rtw_dev *rtwdev, u8 wl_pwr);
919 void (*coex_set_wl_rx_gain)(struct rtw_dev *rtwdev, bool low_gain);
920 };
921
922 #define RTW_PWR_POLLING_CNT 20000
923
924 #define RTW_PWR_CMD_READ 0x00
925 #define RTW_PWR_CMD_WRITE 0x01
926 #define RTW_PWR_CMD_POLLING 0x02
927 #define RTW_PWR_CMD_DELAY 0x03
928 #define RTW_PWR_CMD_END 0x04
929
930 /* define the base address of each block */
931 #define RTW_PWR_ADDR_MAC 0x00
932 #define RTW_PWR_ADDR_USB 0x01
933 #define RTW_PWR_ADDR_PCIE 0x02
934 #define RTW_PWR_ADDR_SDIO 0x03
935
936 #define RTW_PWR_INTF_SDIO_MSK BIT(0)
937 #define RTW_PWR_INTF_USB_MSK BIT(1)
938 #define RTW_PWR_INTF_PCI_MSK BIT(2)
939 #define RTW_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
940
941 #define RTW_PWR_CUT_TEST_MSK BIT(0)
942 #define RTW_PWR_CUT_A_MSK BIT(1)
943 #define RTW_PWR_CUT_B_MSK BIT(2)
944 #define RTW_PWR_CUT_C_MSK BIT(3)
945 #define RTW_PWR_CUT_D_MSK BIT(4)
946 #define RTW_PWR_CUT_E_MSK BIT(5)
947 #define RTW_PWR_CUT_F_MSK BIT(6)
948 #define RTW_PWR_CUT_G_MSK BIT(7)
949 #define RTW_PWR_CUT_ALL_MSK 0xFF
950
951 enum rtw_pwr_seq_cmd_delay_unit {
952 RTW_PWR_DELAY_US,
953 RTW_PWR_DELAY_MS,
954 };
955
956 struct rtw_pwr_seq_cmd {
957 u16 offset;
958 u8 cut_mask;
959 u8 intf_mask;
960 u8 base:4;
961 u8 cmd:4;
962 u8 mask;
963 u8 value;
964 };
965
966 enum rtw_chip_ver {
967 RTW_CHIP_VER_CUT_A = 0x00,
968 RTW_CHIP_VER_CUT_B = 0x01,
969 RTW_CHIP_VER_CUT_C = 0x02,
970 RTW_CHIP_VER_CUT_D = 0x03,
971 RTW_CHIP_VER_CUT_E = 0x04,
972 RTW_CHIP_VER_CUT_F = 0x05,
973 RTW_CHIP_VER_CUT_G = 0x06,
974 };
975
976 #define RTW_INTF_PHY_PLATFORM_ALL 0
977
978 enum rtw_intf_phy_cut {
979 RTW_INTF_PHY_CUT_A = BIT(0),
980 RTW_INTF_PHY_CUT_B = BIT(1),
981 RTW_INTF_PHY_CUT_C = BIT(2),
982 RTW_INTF_PHY_CUT_D = BIT(3),
983 RTW_INTF_PHY_CUT_E = BIT(4),
984 RTW_INTF_PHY_CUT_F = BIT(5),
985 RTW_INTF_PHY_CUT_G = BIT(6),
986 RTW_INTF_PHY_CUT_ALL = 0xFFFF,
987 };
988
989 enum rtw_ip_sel {
990 RTW_IP_SEL_PHY = 0,
991 RTW_IP_SEL_MAC = 1,
992 RTW_IP_SEL_DBI = 2,
993
994 RTW_IP_SEL_UNDEF = 0xFFFF
995 };
996
997 enum rtw_pq_map_id {
998 RTW_PQ_MAP_VO = 0x0,
999 RTW_PQ_MAP_VI = 0x1,
1000 RTW_PQ_MAP_BE = 0x2,
1001 RTW_PQ_MAP_BK = 0x3,
1002 RTW_PQ_MAP_MG = 0x4,
1003 RTW_PQ_MAP_HI = 0x5,
1004 RTW_PQ_MAP_NUM = 0x6,
1005
1006 RTW_PQ_MAP_UNDEF,
1007 };
1008
1009 enum rtw_dma_mapping {
1010 RTW_DMA_MAPPING_EXTRA = 0,
1011 RTW_DMA_MAPPING_LOW = 1,
1012 RTW_DMA_MAPPING_NORMAL = 2,
1013 RTW_DMA_MAPPING_HIGH = 3,
1014
1015 RTW_DMA_MAPPING_MAX,
1016 RTW_DMA_MAPPING_UNDEF,
1017 };
1018
1019 struct rtw_rqpn {
1020 enum rtw_dma_mapping dma_map_vo;
1021 enum rtw_dma_mapping dma_map_vi;
1022 enum rtw_dma_mapping dma_map_be;
1023 enum rtw_dma_mapping dma_map_bk;
1024 enum rtw_dma_mapping dma_map_mg;
1025 enum rtw_dma_mapping dma_map_hi;
1026 };
1027
1028 struct rtw_prioq_addr {
1029 u32 rsvd;
1030 u32 avail;
1031 };
1032
1033 struct rtw_prioq_addrs {
1034 struct rtw_prioq_addr prio[RTW_DMA_MAPPING_MAX];
1035 bool wsize;
1036 };
1037
1038 struct rtw_page_table {
1039 u16 hq_num;
1040 u16 nq_num;
1041 u16 lq_num;
1042 u16 exq_num;
1043 u16 gapq_num;
1044 };
1045
1046 struct rtw_intf_phy_para {
1047 u16 offset;
1048 u16 value;
1049 u16 ip_sel;
1050 u16 cut_mask;
1051 u16 platform;
1052 };
1053
1054 struct rtw_wow_pattern {
1055 u16 crc;
1056 u8 type;
1057 u8 valid;
1058 u8 mask[RTW_MAX_PATTERN_MASK_SIZE];
1059 };
1060
1061 struct rtw_pno_request {
1062 bool inited;
1063 u32 match_set_cnt;
1064 struct cfg80211_match_set *match_sets;
1065 u8 channel_cnt;
1066 struct ieee80211_channel *channels;
1067 struct cfg80211_sched_scan_plan scan_plan;
1068 };
1069
1070 struct rtw_wow_param {
1071 struct ieee80211_vif *wow_vif;
1072 DECLARE_BITMAP(flags, RTW_WOW_FLAG_MAX);
1073 u8 txpause;
1074 u8 pattern_cnt;
1075 struct rtw_wow_pattern patterns[RTW_MAX_PATTERN_NUM];
1076
1077 bool ips_enabled;
1078 struct rtw_pno_request pno_req;
1079 };
1080
1081 struct rtw_intf_phy_para_table {
1082 const struct rtw_intf_phy_para *usb2_para;
1083 const struct rtw_intf_phy_para *usb3_para;
1084 const struct rtw_intf_phy_para *gen1_para;
1085 const struct rtw_intf_phy_para *gen2_para;
1086 u8 n_usb2_para;
1087 u8 n_usb3_para;
1088 u8 n_gen1_para;
1089 u8 n_gen2_para;
1090 };
1091
1092 struct rtw_table {
1093 const void *data;
1094 const u32 size;
1095 void (*parse)(struct rtw_dev *rtwdev, const struct rtw_table *tbl);
1096 void (*do_cfg)(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
1097 u32 addr, u32 data);
1098 enum rtw_rf_path rf_path;
1099 };
1100
rtw_load_table(struct rtw_dev * rtwdev,const struct rtw_table * tbl)1101 static inline void rtw_load_table(struct rtw_dev *rtwdev,
1102 const struct rtw_table *tbl)
1103 {
1104 (*tbl->parse)(rtwdev, tbl);
1105 }
1106
1107 enum rtw_rfe_fem {
1108 RTW_RFE_IFEM,
1109 RTW_RFE_EFEM,
1110 RTW_RFE_IFEM2G_EFEM5G,
1111 RTW_RFE_NUM,
1112 };
1113
1114 struct rtw_rfe_def {
1115 const struct rtw_table *phy_pg_tbl;
1116 const struct rtw_table *txpwr_lmt_tbl;
1117 const struct rtw_pwr_track_tbl *pwr_track_tbl;
1118 const struct rtw_table *agc_btg_tbl;
1119 };
1120
1121 #define RTW_DEF_RFE(chip, bb_pg, pwrlmt, track) { \
1122 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \
1123 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \
1124 .pwr_track_tbl = &rtw ## chip ## _pwr_track_type ## track ## _tbl, \
1125 }
1126
1127 #define RTW_DEF_RFE_EXT(chip, bb_pg, pwrlmt, track, btg) { \
1128 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \
1129 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \
1130 .pwr_track_tbl = &rtw ## chip ## _pwr_track_type ## track ## _tbl, \
1131 .agc_btg_tbl = &rtw ## chip ## _agc_btg_type ## btg ## _tbl, \
1132 }
1133
1134 #define RTW_PWR_TRK_5G_1 0
1135 #define RTW_PWR_TRK_5G_2 1
1136 #define RTW_PWR_TRK_5G_3 2
1137 #define RTW_PWR_TRK_5G_NUM 3
1138
1139 #define RTW_PWR_TRK_TBL_SZ 30
1140
1141 /* This table stores the values of TX power that will be adjusted by power
1142 * tracking.
1143 *
1144 * For 5G bands, there are 3 different settings.
1145 * For 2G there are cck rate and ofdm rate with different settings.
1146 */
1147 struct rtw_pwr_track_tbl {
1148 const u8 *pwrtrk_5gd_n[RTW_PWR_TRK_5G_NUM];
1149 const u8 *pwrtrk_5gd_p[RTW_PWR_TRK_5G_NUM];
1150 const u8 *pwrtrk_5gc_n[RTW_PWR_TRK_5G_NUM];
1151 const u8 *pwrtrk_5gc_p[RTW_PWR_TRK_5G_NUM];
1152 const u8 *pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM];
1153 const u8 *pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM];
1154 const u8 *pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM];
1155 const u8 *pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM];
1156 const u8 *pwrtrk_2gd_n;
1157 const u8 *pwrtrk_2gd_p;
1158 const u8 *pwrtrk_2gc_n;
1159 const u8 *pwrtrk_2gc_p;
1160 const u8 *pwrtrk_2gb_n;
1161 const u8 *pwrtrk_2gb_p;
1162 const u8 *pwrtrk_2ga_n;
1163 const u8 *pwrtrk_2ga_p;
1164 const u8 *pwrtrk_2g_cckd_n;
1165 const u8 *pwrtrk_2g_cckd_p;
1166 const u8 *pwrtrk_2g_cckc_n;
1167 const u8 *pwrtrk_2g_cckc_p;
1168 const u8 *pwrtrk_2g_cckb_n;
1169 const u8 *pwrtrk_2g_cckb_p;
1170 const u8 *pwrtrk_2g_ccka_n;
1171 const u8 *pwrtrk_2g_ccka_p;
1172 const s8 *pwrtrk_xtal_n;
1173 const s8 *pwrtrk_xtal_p;
1174 };
1175
1176 enum rtw_wlan_cpu {
1177 RTW_WCPU_3081,
1178 RTW_WCPU_8051,
1179 };
1180
1181 enum rtw_fw_fifo_sel {
1182 RTW_FW_FIFO_SEL_TX,
1183 RTW_FW_FIFO_SEL_RX,
1184 RTW_FW_FIFO_SEL_RSVD_PAGE,
1185 RTW_FW_FIFO_SEL_REPORT,
1186 RTW_FW_FIFO_SEL_LLT,
1187 RTW_FW_FIFO_SEL_RXBUF_FW,
1188
1189 RTW_FW_FIFO_MAX,
1190 };
1191
1192 enum rtw_fwcd_item {
1193 RTW_FWCD_TLV,
1194 RTW_FWCD_REG,
1195 RTW_FWCD_ROM,
1196 RTW_FWCD_IMEM,
1197 RTW_FWCD_DMEM,
1198 RTW_FWCD_EMEM,
1199 };
1200
1201 /* hardware configuration for each IC */
1202 struct rtw_chip_info {
1203 const struct rtw_chip_ops *ops;
1204 u8 id;
1205
1206 const char *fw_name;
1207 enum rtw_wlan_cpu wlan_cpu;
1208 u8 tx_pkt_desc_sz;
1209 u8 tx_buf_desc_sz;
1210 u8 rx_pkt_desc_sz;
1211 u8 rx_buf_desc_sz;
1212 u32 phy_efuse_size;
1213 u32 log_efuse_size;
1214 u32 ptct_efuse_size;
1215 u32 txff_size;
1216 u32 rxff_size;
1217 u32 fw_rxff_size;
1218 u16 rsvd_drv_pg_num;
1219 u8 band;
1220 u16 page_size;
1221 u8 csi_buf_pg_num;
1222 u8 dig_max;
1223 u8 dig_min;
1224 u8 txgi_factor;
1225 bool is_pwr_by_rate_dec;
1226 bool rx_ldpc;
1227 bool tx_stbc;
1228 u8 max_power_index;
1229 u8 ampdu_density;
1230
1231 u16 fw_fifo_addr[RTW_FW_FIFO_MAX];
1232 const struct rtw_fwcd_segs *fwcd_segs;
1233
1234 bool amsdu_in_ampdu;
1235 u8 usb_tx_agg_desc_num;
1236 bool hw_feature_report;
1237 u8 c2h_ra_report_size;
1238 bool old_datarate_fb_limit;
1239
1240 u8 default_1ss_tx_path;
1241
1242 bool path_div_supported;
1243 bool ht_supported;
1244 bool vht_supported;
1245 u8 lps_deep_mode_supported;
1246
1247 /* init values */
1248 u8 sys_func_en;
1249 const struct rtw_pwr_seq_cmd * const *pwr_on_seq;
1250 const struct rtw_pwr_seq_cmd * const *pwr_off_seq;
1251 const struct rtw_rqpn *rqpn_table;
1252 const struct rtw_prioq_addrs *prioq_addrs;
1253 const struct rtw_page_table *page_table;
1254 const struct rtw_intf_phy_para_table *intf_table;
1255
1256 const struct rtw_hw_reg *dig;
1257 const struct rtw_hw_reg *dig_cck;
1258 u32 rf_base_addr[RTW_RF_PATH_MAX];
1259 u32 rf_sipi_addr[RTW_RF_PATH_MAX];
1260 const struct rtw_rf_sipi_addr *rf_sipi_read_addr;
1261 u8 fix_rf_phy_num;
1262 const struct rtw_ltecoex_addr *ltecoex_addr;
1263
1264 const struct rtw_table *mac_tbl;
1265 const struct rtw_table *agc_tbl;
1266 const struct rtw_table *bb_tbl;
1267 const struct rtw_table *rf_tbl[RTW_RF_PATH_MAX];
1268 const struct rtw_table *rfk_init_tbl;
1269
1270 const struct rtw_rfe_def *rfe_defs;
1271 u32 rfe_defs_size;
1272
1273 bool en_dis_dpd;
1274 u16 dpd_ratemask;
1275 u8 iqk_threshold;
1276 u8 lck_threshold;
1277
1278 u8 bfer_su_max_num;
1279 u8 bfer_mu_max_num;
1280
1281 const struct rtw_hw_reg_offset *edcca_th;
1282 s8 l2h_th_ini_cs;
1283 s8 l2h_th_ini_ad;
1284
1285 const char *wow_fw_name;
1286 const struct wiphy_wowlan_support *wowlan_stub;
1287 const u8 max_sched_scan_ssids;
1288 const u16 max_scan_ie_len;
1289
1290 /* coex paras */
1291 u32 coex_para_ver;
1292 u8 bt_desired_ver;
1293 bool scbd_support;
1294 bool new_scbd10_def; /* true: fix 2M(8822c) */
1295 bool ble_hid_profile_support;
1296 bool wl_mimo_ps_support;
1297 u8 pstdma_type; /* 0: LPSoff, 1:LPSon */
1298 u8 bt_rssi_type;
1299 u8 ant_isolation;
1300 u8 rssi_tolerance;
1301 u8 table_sant_num;
1302 u8 table_nsant_num;
1303 u8 tdma_sant_num;
1304 u8 tdma_nsant_num;
1305 u8 bt_afh_span_bw20;
1306 u8 bt_afh_span_bw40;
1307 u8 afh_5g_num;
1308 u8 wl_rf_para_num;
1309 u8 coex_info_hw_regs_num;
1310 const u8 *bt_rssi_step;
1311 const u8 *wl_rssi_step;
1312 const struct coex_table_para *table_nsant;
1313 const struct coex_table_para *table_sant;
1314 const struct coex_tdma_para *tdma_sant;
1315 const struct coex_tdma_para *tdma_nsant;
1316 const struct coex_rf_para *wl_rf_para_tx;
1317 const struct coex_rf_para *wl_rf_para_rx;
1318 const struct coex_5g_afh_map *afh_5g;
1319 const struct rtw_hw_reg *btg_reg;
1320 const struct rtw_reg_domain *coex_info_hw_regs;
1321 u32 wl_fw_desired_ver;
1322 };
1323
1324 enum rtw_coex_bt_state_cnt {
1325 COEX_CNT_BT_RETRY,
1326 COEX_CNT_BT_REINIT,
1327 COEX_CNT_BT_REENABLE,
1328 COEX_CNT_BT_POPEVENT,
1329 COEX_CNT_BT_SETUPLINK,
1330 COEX_CNT_BT_IGNWLANACT,
1331 COEX_CNT_BT_INQ,
1332 COEX_CNT_BT_PAGE,
1333 COEX_CNT_BT_ROLESWITCH,
1334 COEX_CNT_BT_AFHUPDATE,
1335 COEX_CNT_BT_INFOUPDATE,
1336 COEX_CNT_BT_IQK,
1337 COEX_CNT_BT_IQKFAIL,
1338
1339 COEX_CNT_BT_MAX
1340 };
1341
1342 enum rtw_coex_wl_state_cnt {
1343 COEX_CNT_WL_SCANAP,
1344 COEX_CNT_WL_CONNPKT,
1345 COEX_CNT_WL_COEXRUN,
1346 COEX_CNT_WL_NOISY0,
1347 COEX_CNT_WL_NOISY1,
1348 COEX_CNT_WL_NOISY2,
1349 COEX_CNT_WL_5MS_NOEXTEND,
1350 COEX_CNT_WL_FW_NOTIFY,
1351
1352 COEX_CNT_WL_MAX
1353 };
1354
1355 struct rtw_coex_rfe {
1356 bool ant_switch_exist;
1357 bool ant_switch_diversity;
1358 bool ant_switch_with_bt;
1359 u8 rfe_module_type;
1360 u8 ant_switch_polarity;
1361
1362 /* true if WLG at BTG, else at WLAG */
1363 bool wlg_at_btg;
1364 };
1365
1366 #define COEX_WL_TDMA_PARA_LENGTH 5
1367
1368 struct rtw_coex_dm {
1369 bool cur_ps_tdma_on;
1370 bool cur_wl_rx_low_gain_en;
1371 bool ignore_wl_act;
1372
1373 u8 reason;
1374 u8 bt_rssi_state[4];
1375 u8 wl_rssi_state[4];
1376 u8 wl_ch_info[3];
1377 u8 cur_ps_tdma;
1378 u8 cur_table;
1379 u8 ps_tdma_para[5];
1380 u8 cur_bt_pwr_lvl;
1381 u8 cur_bt_lna_lvl;
1382 u8 cur_wl_pwr_lvl;
1383 u8 bt_status;
1384 u32 cur_ant_pos_type;
1385 u32 cur_switch_status;
1386 u32 setting_tdma;
1387 u8 fw_tdma_para[COEX_WL_TDMA_PARA_LENGTH];
1388 };
1389
1390 #define COEX_BTINFO_SRC_WL_FW 0x0
1391 #define COEX_BTINFO_SRC_BT_RSP 0x1
1392 #define COEX_BTINFO_SRC_BT_ACT 0x2
1393 #define COEX_BTINFO_SRC_BT_IQK 0x3
1394 #define COEX_BTINFO_SRC_BT_SCBD 0x4
1395 #define COEX_BTINFO_SRC_H2C60 0x5
1396 #define COEX_BTINFO_SRC_MAX 0x6
1397
1398 #define COEX_INFO_FTP BIT(7)
1399 #define COEX_INFO_A2DP BIT(6)
1400 #define COEX_INFO_HID BIT(5)
1401 #define COEX_INFO_SCO_BUSY BIT(4)
1402 #define COEX_INFO_ACL_BUSY BIT(3)
1403 #define COEX_INFO_INQ_PAGE BIT(2)
1404 #define COEX_INFO_SCO_ESCO BIT(1)
1405 #define COEX_INFO_CONNECTION BIT(0)
1406 #define COEX_BTINFO_LENGTH_MAX 10
1407 #define COEX_BTINFO_LENGTH 7
1408
1409 #define COEX_BT_HIDINFO_LIST 0x0
1410 #define COEX_BT_HIDINFO_A 0x1
1411 #define COEX_BT_HIDINFO_NAME 3
1412
1413 #define COEX_BT_HIDINFO_LENGTH 6
1414 #define COEX_BT_HIDINFO_HANDLE_NUM 4
1415 #define COEX_BT_HIDINFO_C2H_HANDLE 0
1416 #define COEX_BT_HIDINFO_C2H_VENDOR 1
1417 #define COEX_BT_BLE_HANDLE_THRS 0x10
1418 #define COEX_BT_HIDINFO_NOTCON 0xff
1419
1420 struct rtw_coex_hid {
1421 u8 hid_handle;
1422 u8 hid_vendor;
1423 u8 hid_name[COEX_BT_HIDINFO_NAME];
1424 bool hid_info_completed;
1425 bool is_game_hid;
1426 };
1427
1428 struct rtw_coex_hid_handle_list {
1429 u8 cmd_id;
1430 u8 len;
1431 u8 subid;
1432 u8 handle_cnt;
1433 u8 handle[COEX_BT_HIDINFO_HANDLE_NUM];
1434 } __packed;
1435
1436 struct rtw_coex_hid_info_a {
1437 u8 cmd_id;
1438 u8 len;
1439 u8 subid;
1440 u8 handle;
1441 u8 vendor;
1442 u8 name[COEX_BT_HIDINFO_NAME];
1443 } __packed;
1444
1445 struct rtw_coex_stat {
1446 bool bt_disabled;
1447 bool bt_disabled_pre;
1448 bool bt_link_exist;
1449 bool bt_whck_test;
1450 bool bt_inq_page;
1451 bool bt_inq_remain;
1452 bool bt_inq;
1453 bool bt_page;
1454 bool bt_ble_voice;
1455 bool bt_ble_exist;
1456 bool bt_hfp_exist;
1457 bool bt_a2dp_exist;
1458 bool bt_hid_exist;
1459 bool bt_pan_exist; /* PAN or OPP */
1460 bool bt_opp_exist; /* OPP only */
1461 bool bt_acl_busy;
1462 bool bt_fix_2M;
1463 bool bt_setup_link;
1464 bool bt_multi_link;
1465 bool bt_multi_link_pre;
1466 bool bt_multi_link_remain;
1467 bool bt_a2dp_sink;
1468 bool bt_a2dp_active;
1469 bool bt_reenable;
1470 bool bt_ble_scan_en;
1471 bool bt_init_scan;
1472 bool bt_slave;
1473 bool bt_418_hid_exist;
1474 bool bt_ble_hid_exist;
1475 bool bt_game_hid_exist;
1476 bool bt_hid_handle_cnt;
1477 bool bt_mailbox_reply;
1478
1479 bool wl_under_lps;
1480 bool wl_under_ips;
1481 bool wl_hi_pri_task1;
1482 bool wl_hi_pri_task2;
1483 bool wl_force_lps_ctrl;
1484 bool wl_gl_busy;
1485 bool wl_linkscan_proc;
1486 bool wl_ps_state_fail;
1487 bool wl_tx_limit_en;
1488 bool wl_ampdu_limit_en;
1489 bool wl_connected;
1490 bool wl_slot_extend;
1491 bool wl_cck_lock;
1492 bool wl_cck_lock_pre;
1493 bool wl_cck_lock_ever;
1494 bool wl_connecting;
1495 bool wl_slot_toggle;
1496 bool wl_slot_toggle_change; /* if toggle to no-toggle */
1497 bool wl_mimo_ps;
1498
1499 u32 bt_supported_version;
1500 u32 bt_supported_feature;
1501 u32 hi_pri_tx;
1502 u32 hi_pri_rx;
1503 u32 lo_pri_tx;
1504 u32 lo_pri_rx;
1505 u32 patch_ver;
1506 u16 bt_reg_vendor_ae;
1507 u16 bt_reg_vendor_ac;
1508 s8 bt_rssi;
1509 u8 kt_ver;
1510 u8 gnt_workaround_state;
1511 u8 tdma_timer_base;
1512 u8 bt_profile_num;
1513 u8 bt_info_c2h[COEX_BTINFO_SRC_MAX][COEX_BTINFO_LENGTH_MAX];
1514 u8 bt_info_lb2;
1515 u8 bt_info_lb3;
1516 u8 bt_info_hb0;
1517 u8 bt_info_hb1;
1518 u8 bt_info_hb2;
1519 u8 bt_info_hb3;
1520 u8 bt_ble_scan_type;
1521 u8 bt_hid_pair_num;
1522 u8 bt_hid_slot;
1523 u8 bt_a2dp_bitpool;
1524 u8 bt_iqk_state;
1525 u8 bt_disable_cnt;
1526
1527 u16 wl_beacon_interval;
1528 u8 wl_noisy_level;
1529 u8 wl_fw_dbg_info[10];
1530 u8 wl_fw_dbg_info_pre[10];
1531 u8 wl_rx_rate;
1532 u8 wl_tx_rate;
1533 u8 wl_rts_rx_rate;
1534 u8 wl_coex_mode;
1535 u8 wl_iot_peer;
1536 u8 ampdu_max_time;
1537 u8 wl_tput_dir;
1538
1539 u8 wl_toggle_para[6];
1540 u8 wl_toggle_interval;
1541
1542 u16 score_board;
1543 u16 retry_limit;
1544
1545 /* counters to record bt states */
1546 u32 cnt_bt[COEX_CNT_BT_MAX];
1547
1548 /* counters to record wifi states */
1549 u32 cnt_wl[COEX_CNT_WL_MAX];
1550
1551 /* counters to record bt c2h data */
1552 u32 cnt_bt_info_c2h[COEX_BTINFO_SRC_MAX];
1553
1554 u32 darfrc;
1555 u32 darfrch;
1556
1557 struct rtw_coex_hid hid_info[COEX_BT_HIDINFO_HANDLE_NUM];
1558 struct rtw_coex_hid_handle_list hid_handle_list;
1559 };
1560
1561 struct rtw_coex {
1562 struct sk_buff_head queue;
1563 wait_queue_head_t wait;
1564
1565 bool under_5g;
1566 bool stop_dm;
1567 bool freeze;
1568 bool freerun;
1569 bool wl_rf_off;
1570 bool manual_control;
1571
1572 struct rtw_coex_stat stat;
1573 struct rtw_coex_dm dm;
1574 struct rtw_coex_rfe rfe;
1575
1576 struct delayed_work bt_relink_work;
1577 struct delayed_work bt_reenable_work;
1578 struct delayed_work defreeze_work;
1579 struct delayed_work wl_remain_work;
1580 struct delayed_work bt_remain_work;
1581 struct delayed_work wl_connecting_work;
1582 struct delayed_work bt_multi_link_remain_work;
1583 struct delayed_work wl_ccklock_work;
1584
1585 };
1586
1587 #define DPK_RF_REG_NUM 7
1588 #define DPK_RF_PATH_NUM 2
1589 #define DPK_BB_REG_NUM 18
1590 #define DPK_CHANNEL_WIDTH_80 1
1591
1592 DECLARE_EWMA(thermal, 10, 4);
1593
1594 struct rtw_dpk_info {
1595 bool is_dpk_pwr_on;
1596 bool is_reload;
1597
1598 DECLARE_BITMAP(dpk_path_ok, DPK_RF_PATH_NUM);
1599
1600 u8 thermal_dpk[DPK_RF_PATH_NUM];
1601 struct ewma_thermal avg_thermal[DPK_RF_PATH_NUM];
1602
1603 u32 gnt_control;
1604 u32 gnt_value;
1605
1606 u8 result[RTW_RF_PATH_MAX];
1607 u8 dpk_txagc[RTW_RF_PATH_MAX];
1608 u32 coef[RTW_RF_PATH_MAX][20];
1609 u16 dpk_gs[RTW_RF_PATH_MAX];
1610 u8 thermal_dpk_delta[RTW_RF_PATH_MAX];
1611 u8 pre_pwsf[RTW_RF_PATH_MAX];
1612
1613 u8 dpk_band;
1614 u8 dpk_ch;
1615 u8 dpk_bw;
1616 };
1617
1618 struct rtw_phy_cck_pd_reg {
1619 u32 reg_pd;
1620 u32 mask_pd;
1621 u32 reg_cs;
1622 u32 mask_cs;
1623 };
1624
1625 #define DACK_MSBK_BACKUP_NUM 0xf
1626 #define DACK_DCK_BACKUP_NUM 0x2
1627
1628 struct rtw_swing_table {
1629 const u8 *p[RTW_RF_PATH_MAX];
1630 const u8 *n[RTW_RF_PATH_MAX];
1631 };
1632
1633 struct rtw_pkt_count {
1634 u16 num_bcn_pkt;
1635 u16 num_qry_pkt[DESC_RATE_MAX];
1636 };
1637
1638 DECLARE_EWMA(evm, 10, 4);
1639 DECLARE_EWMA(snr, 10, 4);
1640
1641 struct rtw_iqk_info {
1642 bool done;
1643 struct {
1644 u32 s1_x;
1645 u32 s1_y;
1646 u32 s0_x;
1647 u32 s0_y;
1648 } result;
1649 };
1650
1651 enum rtw_rf_band {
1652 RF_BAND_2G_CCK,
1653 RF_BAND_2G_OFDM,
1654 RF_BAND_5G_L,
1655 RF_BAND_5G_M,
1656 RF_BAND_5G_H,
1657 RF_BAND_MAX
1658 };
1659
1660 #define RF_GAIN_NUM 11
1661 #define RF_HW_OFFSET_NUM 10
1662
1663 struct rtw_gapk_info {
1664 u32 rf3f_bp[RF_BAND_MAX][RF_GAIN_NUM][RTW_RF_PATH_MAX];
1665 u32 rf3f_fs[RTW_RF_PATH_MAX][RF_GAIN_NUM];
1666 bool txgapk_bp_done;
1667 s8 offset[RF_GAIN_NUM][RTW_RF_PATH_MAX];
1668 s8 fianl_offset[RF_GAIN_NUM][RTW_RF_PATH_MAX];
1669 u8 read_txgain;
1670 u8 channel;
1671 };
1672
1673 #define EDCCA_TH_L2H_IDX 0
1674 #define EDCCA_TH_H2L_IDX 1
1675 #define EDCCA_TH_L2H_LB 48
1676 #define EDCCA_ADC_BACKOFF 12
1677 #define EDCCA_IGI_BASE 50
1678 #define EDCCA_IGI_L2H_DIFF 8
1679 #define EDCCA_L2H_H2L_DIFF 7
1680 #define EDCCA_L2H_H2L_DIFF_NORMAL 8
1681
1682 enum rtw_edcca_mode {
1683 RTW_EDCCA_NORMAL = 0,
1684 RTW_EDCCA_ADAPTIVITY = 1,
1685 };
1686
1687 struct rtw_cfo_track {
1688 bool is_adjust;
1689 u8 crystal_cap;
1690 s32 cfo_tail[RTW_RF_PATH_MAX];
1691 s32 cfo_cnt[RTW_RF_PATH_MAX];
1692 u32 packet_count;
1693 u32 packet_count_pre;
1694 };
1695
1696 #define RRSR_INIT_2G 0x15f
1697 #define RRSR_INIT_5G 0x150
1698
1699 enum rtw_dm_cap {
1700 RTW_DM_CAP_NA,
1701 RTW_DM_CAP_TXGAPK,
1702 RTW_DM_CAP_NUM
1703 };
1704
1705 struct rtw_dm_info {
1706 u32 cck_fa_cnt;
1707 u32 ofdm_fa_cnt;
1708 u32 total_fa_cnt;
1709 u32 cck_cca_cnt;
1710 u32 ofdm_cca_cnt;
1711 u32 total_cca_cnt;
1712
1713 u32 cck_ok_cnt;
1714 u32 cck_err_cnt;
1715 u32 ofdm_ok_cnt;
1716 u32 ofdm_err_cnt;
1717 u32 ht_ok_cnt;
1718 u32 ht_err_cnt;
1719 u32 vht_ok_cnt;
1720 u32 vht_err_cnt;
1721
1722 u8 min_rssi;
1723 u8 pre_min_rssi;
1724 u16 fa_history[4];
1725 u8 igi_history[4];
1726 u8 igi_bitmap;
1727 bool damping;
1728 u8 damping_cnt;
1729 u8 damping_rssi;
1730
1731 u8 cck_gi_u_bnd;
1732 u8 cck_gi_l_bnd;
1733
1734 u8 fix_rate;
1735 u8 tx_rate;
1736 u32 rrsr_val_init;
1737 u32 rrsr_mask_min;
1738 u8 thermal_avg[RTW_RF_PATH_MAX];
1739 u8 thermal_meter_k;
1740 u8 thermal_meter_lck;
1741 s8 delta_power_index[RTW_RF_PATH_MAX];
1742 s8 delta_power_index_last[RTW_RF_PATH_MAX];
1743 u8 default_ofdm_index;
1744 u8 default_cck_index;
1745 bool pwr_trk_triggered;
1746 bool pwr_trk_init_trigger;
1747 struct ewma_thermal avg_thermal[RTW_RF_PATH_MAX];
1748 s8 txagc_remnant_cck;
1749 s8 txagc_remnant_ofdm[RTW_RF_PATH_MAX];
1750 u8 rx_cck_agc_report_type;
1751
1752 /* backup dack results for each path and I/Q */
1753 u32 dack_adck[RTW_RF_PATH_MAX];
1754 u16 dack_msbk[RTW_RF_PATH_MAX][2][DACK_MSBK_BACKUP_NUM];
1755 u8 dack_dck[RTW_RF_PATH_MAX][2][DACK_DCK_BACKUP_NUM];
1756
1757 struct rtw_dpk_info dpk_info;
1758 struct rtw_cfo_track cfo_track;
1759
1760 /* [bandwidth 0:20M/1:40M][number of path] */
1761 u8 cck_pd_lv[2][RTW_RF_PATH_MAX];
1762 u32 cck_fa_avg;
1763 u8 cck_pd_default;
1764
1765 /* save the last rx phy status for debug */
1766 s8 rx_snr[RTW_RF_PATH_MAX];
1767 u8 rx_evm_dbm[RTW_RF_PATH_MAX];
1768 s16 cfo_tail[RTW_RF_PATH_MAX];
1769 u8 rssi[RTW_RF_PATH_MAX];
1770 u8 curr_rx_rate;
1771 struct rtw_pkt_count cur_pkt_count;
1772 struct rtw_pkt_count last_pkt_count;
1773 struct ewma_evm ewma_evm[RTW_EVM_NUM];
1774 struct ewma_snr ewma_snr[RTW_SNR_NUM];
1775
1776 u32 dm_flags; /* enum rtw_dm_cap */
1777 struct rtw_iqk_info iqk;
1778 struct rtw_gapk_info gapk;
1779 bool is_bt_iqk_timeout;
1780
1781 s8 l2h_th_ini;
1782 enum rtw_edcca_mode edcca_mode;
1783 u8 scan_density;
1784 };
1785
1786 struct rtw_efuse {
1787 u32 size;
1788 u32 physical_size;
1789 u32 logical_size;
1790 u32 protect_size;
1791
1792 u8 addr[ETH_ALEN];
1793 u8 channel_plan;
1794 u8 country_code[2];
1795 u8 rf_board_option;
1796 u8 rfe_option;
1797 u8 power_track_type;
1798 u8 thermal_meter[RTW_RF_PATH_MAX];
1799 u8 thermal_meter_k;
1800 u8 crystal_cap;
1801 u8 ant_div_cfg;
1802 u8 ant_div_type;
1803 u8 regd;
1804 u8 afe;
1805
1806 u8 lna_type_2g;
1807 u8 lna_type_5g;
1808 u8 glna_type;
1809 u8 alna_type;
1810 bool ext_lna_2g;
1811 bool ext_lna_5g;
1812 u8 pa_type_2g;
1813 u8 pa_type_5g;
1814 u8 gpa_type;
1815 u8 apa_type;
1816 bool ext_pa_2g;
1817 bool ext_pa_5g;
1818 u8 tx_bb_swing_setting_2g;
1819 u8 tx_bb_swing_setting_5g;
1820
1821 bool btcoex;
1822 /* bt share antenna with wifi */
1823 bool share_ant;
1824 u8 bt_setting;
1825
1826 u8 usb_mode_switch;
1827
1828 struct {
1829 u8 hci;
1830 u8 bw;
1831 u8 ptcl;
1832 u8 nss;
1833 u8 ant_num;
1834 } hw_cap;
1835
1836 struct rtw_txpwr_idx txpwr_idx_table[4];
1837 };
1838
1839 struct rtw_phy_cond {
1840 #ifdef __LITTLE_ENDIAN
1841 u32 rfe:8;
1842 u32 intf:4;
1843 u32 pkg:4;
1844 u32 plat:4;
1845 u32 intf_rsvd:4;
1846 u32 cut:4;
1847 u32 branch:2;
1848 u32 neg:1;
1849 u32 pos:1;
1850 #else
1851 u32 pos:1;
1852 u32 neg:1;
1853 u32 branch:2;
1854 u32 cut:4;
1855 u32 intf_rsvd:4;
1856 u32 plat:4;
1857 u32 pkg:4;
1858 u32 intf:4;
1859 u32 rfe:8;
1860 #endif
1861 /* for intf:4 */
1862 #define INTF_PCIE BIT(0)
1863 #define INTF_USB BIT(1)
1864 #define INTF_SDIO BIT(2)
1865 /* for branch:2 */
1866 #define BRANCH_IF 0
1867 #define BRANCH_ELIF 1
1868 #define BRANCH_ELSE 2
1869 #define BRANCH_ENDIF 3
1870 };
1871
1872 struct rtw_phy_cond2 {
1873 #ifdef __LITTLE_ENDIAN
1874 u8 type_glna;
1875 u8 type_gpa;
1876 u8 type_alna;
1877 u8 type_apa;
1878 #else
1879 u8 type_apa;
1880 u8 type_alna;
1881 u8 type_gpa;
1882 u8 type_glna;
1883 #endif
1884 };
1885
1886 struct rtw_fifo_conf {
1887 /* tx fifo information */
1888 u16 rsvd_boundary;
1889 u16 rsvd_pg_num;
1890 u16 rsvd_drv_pg_num;
1891 u16 txff_pg_num;
1892 u16 acq_pg_num;
1893 u16 rsvd_drv_addr;
1894 u16 rsvd_h2c_info_addr;
1895 u16 rsvd_h2c_sta_info_addr;
1896 u16 rsvd_h2cq_addr;
1897 u16 rsvd_cpu_instr_addr;
1898 u16 rsvd_fw_txbuf_addr;
1899 u16 rsvd_csibuf_addr;
1900 const struct rtw_rqpn *rqpn;
1901 };
1902
1903 struct rtw_fwcd_desc {
1904 u32 size;
1905 u8 *next;
1906 u8 *data;
1907 };
1908
1909 struct rtw_fwcd_segs {
1910 const u32 *segs;
1911 u8 num;
1912 };
1913
1914 #define FW_CD_TYPE 0xffff
1915 #define FW_CD_LEN 4
1916 #define FW_CD_VAL 0xaabbccdd
1917 struct rtw_fw_state {
1918 const struct firmware *firmware;
1919 struct rtw_dev *rtwdev;
1920 struct completion completion;
1921 struct rtw_fwcd_desc fwcd_desc;
1922 u16 version;
1923 u8 sub_version;
1924 u8 sub_index;
1925 u16 h2c_version;
1926 u32 feature;
1927 u32 feature_ext;
1928 enum rtw_fw_type type;
1929 };
1930
1931 enum rtw_sar_sources {
1932 RTW_SAR_SOURCE_NONE,
1933 RTW_SAR_SOURCE_COMMON,
1934 };
1935
1936 enum rtw_sar_bands {
1937 RTW_SAR_BAND_0,
1938 RTW_SAR_BAND_1,
1939 /* RTW_SAR_BAND_2, not used now */
1940 RTW_SAR_BAND_3,
1941 RTW_SAR_BAND_4,
1942
1943 RTW_SAR_BAND_NR,
1944 };
1945
1946 /* the union is reserved for other kinds of SAR sources
1947 * which might not re-use same format with array common.
1948 */
1949 union rtw_sar_cfg {
1950 s8 common[RTW_SAR_BAND_NR];
1951 };
1952
1953 struct rtw_sar {
1954 enum rtw_sar_sources src;
1955 union rtw_sar_cfg cfg[RTW_RF_PATH_MAX][RTW_RATE_SECTION_NUM];
1956 };
1957
1958 struct rtw_hal {
1959 u32 rcr;
1960
1961 u32 chip_version;
1962 u8 cut_version;
1963 u8 mp_chip;
1964 u8 oem_id;
1965 u8 pkg_type;
1966 struct rtw_phy_cond phy_cond;
1967 struct rtw_phy_cond2 phy_cond2;
1968 bool rfe_btg;
1969
1970 u8 ps_mode;
1971 u8 current_channel;
1972 u8 current_primary_channel_index;
1973 u8 current_band_width;
1974 u8 current_band_type;
1975 u8 primary_channel;
1976
1977 /* center channel for different available bandwidth,
1978 * val of (bw > current_band_width) is invalid
1979 */
1980 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1];
1981
1982 u8 sec_ch_offset;
1983 u8 rf_type;
1984 u8 rf_path_num;
1985 u8 rf_phy_num;
1986 u32 antenna_tx;
1987 u32 antenna_rx;
1988 u8 bfee_sts_cap;
1989 bool txrx_1ss;
1990 bool cck_high_power;
1991
1992 /* protect tx power section */
1993 struct mutex tx_power_mutex;
1994 s8 tx_pwr_by_rate_offset_2g[RTW_RF_PATH_MAX]
1995 [DESC_RATE_MAX];
1996 s8 tx_pwr_by_rate_offset_5g[RTW_RF_PATH_MAX]
1997 [DESC_RATE_MAX];
1998 s8 tx_pwr_by_rate_base_2g[RTW_RF_PATH_MAX]
1999 [RTW_RATE_SECTION_NUM];
2000 s8 tx_pwr_by_rate_base_5g[RTW_RF_PATH_MAX]
2001 [RTW_RATE_SECTION_NUM];
2002 s8 tx_pwr_limit_2g[RTW_REGD_MAX]
2003 [RTW_CHANNEL_WIDTH_MAX]
2004 [RTW_RATE_SECTION_NUM]
2005 [RTW_MAX_CHANNEL_NUM_2G];
2006 s8 tx_pwr_limit_5g[RTW_REGD_MAX]
2007 [RTW_CHANNEL_WIDTH_MAX]
2008 [RTW_RATE_SECTION_NUM]
2009 [RTW_MAX_CHANNEL_NUM_5G];
2010 s8 tx_pwr_tbl[RTW_RF_PATH_MAX]
2011 [DESC_RATE_MAX];
2012
2013 enum rtw_sar_bands sar_band;
2014 struct rtw_sar sar;
2015
2016 /* for 8821c set channel */
2017 u32 ch_param[3];
2018 };
2019
2020 struct rtw_path_div {
2021 enum rtw_bb_path current_tx_path;
2022 u32 path_a_sum;
2023 u32 path_b_sum;
2024 u16 path_a_cnt;
2025 u16 path_b_cnt;
2026 };
2027
2028 struct rtw_chan_info {
2029 int pri_ch_idx;
2030 int action_id;
2031 int bw;
2032 u8 extra_info;
2033 u8 channel;
2034 u16 timeout;
2035 };
2036
2037 struct rtw_chan_list {
2038 u32 buf_size;
2039 u32 ch_num;
2040 u32 size;
2041 u16 addr;
2042 };
2043
2044 struct rtw_hw_scan_info {
2045 struct ieee80211_vif *scanning_vif;
2046 u8 probe_pg_size;
2047 u8 op_pri_ch_idx;
2048 u8 op_pri_ch;
2049 u8 op_chan;
2050 u8 op_bw;
2051 };
2052
2053 struct rtw_dev {
2054 struct ieee80211_hw *hw;
2055 struct device *dev;
2056
2057 struct rtw_hci hci;
2058
2059 struct rtw_hw_scan_info scan_info;
2060 const struct rtw_chip_info *chip;
2061 struct rtw_hal hal;
2062 struct rtw_fifo_conf fifo;
2063 struct rtw_fw_state fw;
2064 struct rtw_efuse efuse;
2065 struct rtw_sec_desc sec;
2066 struct rtw_traffic_stats stats;
2067 struct rtw_regd regd;
2068 struct rtw_bf_info bf_info;
2069
2070 struct rtw_dm_info dm_info;
2071 struct rtw_coex coex;
2072
2073 /* ensures exclusive access from mac80211 callbacks */
2074 struct mutex mutex;
2075
2076 /* watch dog every 2 sec */
2077 struct delayed_work watch_dog_work;
2078 u32 watch_dog_cnt;
2079
2080 struct list_head rsvd_page_list;
2081
2082 /* c2h cmd queue & handler work */
2083 struct sk_buff_head c2h_queue;
2084 struct work_struct c2h_work;
2085 struct work_struct ips_work;
2086 struct work_struct fw_recovery_work;
2087 struct work_struct update_beacon_work;
2088
2089 /* used to protect txqs list */
2090 spinlock_t txq_lock;
2091 struct list_head txqs;
2092 struct workqueue_struct *tx_wq;
2093 struct work_struct tx_work;
2094 struct work_struct ba_work;
2095
2096 struct rtw_tx_report tx_report;
2097
2098 struct {
2099 /* indicate the mail box to use with fw */
2100 u8 last_box_num;
2101 u32 seq;
2102 } h2c;
2103
2104 /* lps power state & handler work */
2105 struct rtw_lps_conf lps_conf;
2106 bool ps_enabled;
2107 bool beacon_loss;
2108 struct completion lps_leave_check;
2109
2110 struct rtw_debugfs *debugfs;
2111
2112 u8 sta_cnt;
2113 u32 rts_threshold;
2114
2115 DECLARE_BITMAP(hw_port, RTW_PORT_NUM);
2116 DECLARE_BITMAP(mac_id_map, RTW_MAX_MAC_ID_NUM);
2117 DECLARE_BITMAP(flags, NUM_OF_RTW_FLAGS);
2118
2119 u8 mp_mode;
2120 struct rtw_path_div dm_path_div;
2121
2122 struct rtw_fw_state wow_fw;
2123 struct rtw_wow_param wow;
2124
2125 bool need_rfk;
2126 struct completion fw_scan_density;
2127 bool ap_active;
2128
2129 bool led_registered;
2130 char led_name[32];
2131 struct led_classdev led_cdev;
2132
2133 /* hci related data, must be last */
2134 u8 priv[] __aligned(sizeof(void *));
2135 };
2136
2137 #include "hci.h"
2138
rtw_is_assoc(struct rtw_dev * rtwdev)2139 static inline bool rtw_is_assoc(struct rtw_dev *rtwdev)
2140 {
2141 return !!rtwdev->sta_cnt;
2142 }
2143
rtwtxq_to_txq(struct rtw_txq * rtwtxq)2144 static inline struct ieee80211_txq *rtwtxq_to_txq(struct rtw_txq *rtwtxq)
2145 {
2146 void *p = rtwtxq;
2147
2148 return container_of(p, struct ieee80211_txq, drv_priv);
2149 }
2150
rtwvif_to_vif(struct rtw_vif * rtwvif)2151 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw_vif *rtwvif)
2152 {
2153 void *p = rtwvif;
2154
2155 return container_of(p, struct ieee80211_vif, drv_priv);
2156 }
2157
rtw_chip_efuse_grant_on(struct rtw_dev * rtwdev)2158 static inline void rtw_chip_efuse_grant_on(struct rtw_dev *rtwdev)
2159 {
2160 if (rtwdev->chip->ops->efuse_grant)
2161 rtwdev->chip->ops->efuse_grant(rtwdev, true);
2162 }
2163
rtw_chip_efuse_grant_off(struct rtw_dev * rtwdev)2164 static inline void rtw_chip_efuse_grant_off(struct rtw_dev *rtwdev)
2165 {
2166 if (rtwdev->chip->ops->efuse_grant)
2167 rtwdev->chip->ops->efuse_grant(rtwdev, false);
2168 }
2169
rtw_chip_wcpu_8051(struct rtw_dev * rtwdev)2170 static inline bool rtw_chip_wcpu_8051(struct rtw_dev *rtwdev)
2171 {
2172 return rtwdev->chip->wlan_cpu == RTW_WCPU_8051;
2173 }
2174
rtw_chip_wcpu_3081(struct rtw_dev * rtwdev)2175 static inline bool rtw_chip_wcpu_3081(struct rtw_dev *rtwdev)
2176 {
2177 return rtwdev->chip->wlan_cpu == RTW_WCPU_3081;
2178 }
2179
rtw_chip_has_rx_ldpc(struct rtw_dev * rtwdev)2180 static inline bool rtw_chip_has_rx_ldpc(struct rtw_dev *rtwdev)
2181 {
2182 return rtwdev->chip->rx_ldpc;
2183 }
2184
rtw_chip_has_tx_stbc(struct rtw_dev * rtwdev)2185 static inline bool rtw_chip_has_tx_stbc(struct rtw_dev *rtwdev)
2186 {
2187 return rtwdev->chip->tx_stbc;
2188 }
2189
rtw_acquire_macid(struct rtw_dev * rtwdev)2190 static inline u8 rtw_acquire_macid(struct rtw_dev *rtwdev)
2191 {
2192 unsigned long mac_id;
2193
2194 mac_id = find_first_zero_bit(rtwdev->mac_id_map, RTW_MAX_MAC_ID_NUM);
2195 if (mac_id < RTW_MAX_MAC_ID_NUM)
2196 set_bit(mac_id, rtwdev->mac_id_map);
2197
2198 return mac_id;
2199 }
2200
rtw_release_macid(struct rtw_dev * rtwdev,u8 mac_id)2201 static inline void rtw_release_macid(struct rtw_dev *rtwdev, u8 mac_id)
2202 {
2203 clear_bit(mac_id, rtwdev->mac_id_map);
2204 }
2205
rtw_chip_dump_fw_crash(struct rtw_dev * rtwdev)2206 static inline int rtw_chip_dump_fw_crash(struct rtw_dev *rtwdev)
2207 {
2208 if (rtwdev->chip->ops->dump_fw_crash)
2209 return rtwdev->chip->ops->dump_fw_crash(rtwdev);
2210
2211 return 0;
2212 }
2213
2214 static inline
rtw_hw_to_nl80211_band(enum rtw_supported_band hw_band)2215 enum nl80211_band rtw_hw_to_nl80211_band(enum rtw_supported_band hw_band)
2216 {
2217 switch (hw_band) {
2218 default:
2219 case RTW_BAND_2G:
2220 return NL80211_BAND_2GHZ;
2221 case RTW_BAND_5G:
2222 return NL80211_BAND_5GHZ;
2223 case RTW_BAND_60G:
2224 return NL80211_BAND_60GHZ;
2225 }
2226 }
2227
2228 void rtw_set_rx_freq_band(struct rtw_rx_pkt_stat *pkt_stat, u8 channel);
2229 void rtw_set_dtim_period(struct rtw_dev *rtwdev, int dtim_period);
2230 void rtw_get_channel_params(struct cfg80211_chan_def *chandef,
2231 struct rtw_channel_params *ch_param);
2232 bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target);
2233 bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val);
2234 bool ltecoex_reg_write(struct rtw_dev *rtwdev, u16 offset, u32 value);
2235 void rtw_restore_reg(struct rtw_dev *rtwdev,
2236 struct rtw_backup_info *bckp, u32 num);
2237 void rtw_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss);
2238 void rtw_set_channel(struct rtw_dev *rtwdev);
2239 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev);
2240 void rtw_vif_port_config(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif,
2241 u32 config);
2242 void rtw_tx_report_purge_timer(struct timer_list *t);
2243 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si,
2244 bool reset_ra_mask);
2245 void rtw_core_scan_start(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif,
2246 const u8 *mac_addr, bool hw_scan);
2247 void rtw_core_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
2248 bool hw_scan);
2249 int rtw_core_start(struct rtw_dev *rtwdev);
2250 void rtw_power_off(struct rtw_dev *rtwdev);
2251 void rtw_core_stop(struct rtw_dev *rtwdev);
2252 int rtw_chip_info_setup(struct rtw_dev *rtwdev);
2253 int rtw_core_init(struct rtw_dev *rtwdev);
2254 void rtw_core_deinit(struct rtw_dev *rtwdev);
2255 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw);
2256 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw);
2257 u16 rtw_desc_to_bitrate(u8 desc_rate);
2258 void rtw_vif_assoc_changed(struct rtw_vif *rtwvif,
2259 struct ieee80211_bss_conf *conf);
2260 int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
2261 struct ieee80211_vif *vif);
2262 void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
2263 bool fw_exist);
2264 void rtw_fw_recovery(struct rtw_dev *rtwdev);
2265 int rtw_wait_firmware_completion(struct rtw_dev *rtwdev);
2266 int rtw_power_on(struct rtw_dev *rtwdev);
2267 void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start);
2268 int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size,
2269 u32 fwcd_item);
2270 int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size);
2271 void rtw_set_txrx_1ss(struct rtw_dev *rtwdev, bool config_1ss);
2272 void rtw_update_channel(struct rtw_dev *rtwdev, u8 center_channel,
2273 u8 primary_channel, enum rtw_supported_band band,
2274 enum rtw_bandwidth bandwidth);
2275 void rtw_core_port_switch(struct rtw_dev *rtwdev, struct ieee80211_vif *vif);
2276 bool rtw_core_check_sta_active(struct rtw_dev *rtwdev);
2277 void rtw_core_enable_beacon(struct rtw_dev *rtwdev, bool enable);
2278 void rtw_set_ampdu_factor(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
2279 struct ieee80211_bss_conf *bss_conf);
2280 #endif
2281