1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Analog Devices AD4851 DAS driver
4 *
5 * Copyright 2024 Analog Devices Inc.
6 */
7
8 #include <linux/array_size.h>
9 #include <linux/bitfield.h>
10 #include <linux/bits.h>
11 #include <linux/delay.h>
12 #include <linux/device.h>
13 #include <linux/err.h>
14 #include <linux/minmax.h>
15 #include <linux/module.h>
16 #include <linux/mutex.h>
17 #include <linux/pwm.h>
18 #include <linux/regmap.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/spi/spi.h>
21 #include <linux/types.h>
22 #include <linux/unaligned.h>
23 #include <linux/units.h>
24
25 #include <linux/iio/backend.h>
26 #include <linux/iio/iio.h>
27
28 #define AD4851_REG_INTERFACE_CONFIG_A 0x00
29 #define AD4851_REG_INTERFACE_CONFIG_B 0x01
30 #define AD4851_REG_PRODUCT_ID_L 0x04
31 #define AD4851_REG_PRODUCT_ID_H 0x05
32 #define AD4851_REG_DEVICE_CTRL 0x25
33 #define AD4851_REG_PACKET 0x26
34 #define AD4851_REG_OVERSAMPLE 0x27
35
36 #define AD4851_REG_CH_CONFIG_BASE 0x2A
37 #define AD4851_REG_CHX_SOFTSPAN(ch) ((0x12 * (ch)) + AD4851_REG_CH_CONFIG_BASE)
38 #define AD4851_REG_CHX_OFFSET(ch) (AD4851_REG_CHX_SOFTSPAN(ch) + 0x01)
39 #define AD4851_REG_CHX_OFFSET_LSB(ch) AD4851_REG_CHX_OFFSET(ch)
40 #define AD4851_REG_CHX_OFFSET_MID(ch) (AD4851_REG_CHX_OFFSET_LSB(ch) + 0x01)
41 #define AD4851_REG_CHX_OFFSET_MSB(ch) (AD4851_REG_CHX_OFFSET_MID(ch) + 0x01)
42 #define AD4851_REG_CHX_GAIN(ch) (AD4851_REG_CHX_OFFSET(ch) + 0x03)
43 #define AD4851_REG_CHX_GAIN_LSB(ch) AD4851_REG_CHX_GAIN(ch)
44 #define AD4851_REG_CHX_GAIN_MSB(ch) (AD4851_REG_CHX_GAIN(ch) + 0x01)
45 #define AD4851_REG_CHX_PHASE(ch) (AD4851_REG_CHX_GAIN(ch) + 0x02)
46 #define AD4851_REG_CHX_PHASE_LSB(ch) AD4851_REG_CHX_PHASE(ch)
47 #define AD4851_REG_CHX_PHASE_MSB(ch) (AD4851_REG_CHX_PHASE_LSB(ch) + 0x01)
48
49 #define AD4851_REG_TESTPAT_0(c) (0x38 + (c) * 0x12)
50 #define AD4851_REG_TESTPAT_1(c) (0x39 + (c) * 0x12)
51 #define AD4851_REG_TESTPAT_2(c) (0x3A + (c) * 0x12)
52 #define AD4851_REG_TESTPAT_3(c) (0x3B + (c) * 0x12)
53
54 #define AD4851_SW_RESET (BIT(7) | BIT(0))
55 #define AD4851_SDO_ENABLE BIT(4)
56 #define AD4851_SINGLE_INSTRUCTION BIT(7)
57 #define AD4851_REFBUF BIT(2)
58 #define AD4851_REFSEL BIT(1)
59 #define AD4851_ECHO_CLOCK_MODE BIT(0)
60
61 #define AD4851_PACKET_FORMAT_0 0
62 #define AD4851_PACKET_FORMAT_1 1
63 #define AD4851_PACKET_FORMAT_MASK GENMASK(1, 0)
64
65 #define AD4851_OS_EN_MSK BIT(7)
66 #define AD4851_OS_RATIO_MSK GENMASK(3, 0)
67
68 #define AD4851_TEST_PAT BIT(2)
69
70 #define AD4858_PACKET_SIZE_20 0
71 #define AD4858_PACKET_SIZE_24 1
72 #define AD4858_PACKET_SIZE_32 2
73
74 #define AD4857_PACKET_SIZE_16 0
75 #define AD4857_PACKET_SIZE_24 1
76
77 #define AD4851_TESTPAT_0_DEFAULT 0x2A
78 #define AD4851_TESTPAT_1_DEFAULT 0x3C
79 #define AD4851_TESTPAT_2_DEFAULT 0xCE
80 #define AD4851_TESTPAT_3_DEFAULT(c) (0x0A + (0x10 * (c)))
81
82 #define AD4851_SOFTSPAN_0V_2V5 0
83 #define AD4851_SOFTSPAN_N2V5_2V5 1
84 #define AD4851_SOFTSPAN_0V_5V 2
85 #define AD4851_SOFTSPAN_N5V_5V 3
86 #define AD4851_SOFTSPAN_0V_6V25 4
87 #define AD4851_SOFTSPAN_N6V25_6V25 5
88 #define AD4851_SOFTSPAN_0V_10V 6
89 #define AD4851_SOFTSPAN_N10V_10V 7
90 #define AD4851_SOFTSPAN_0V_12V5 8
91 #define AD4851_SOFTSPAN_N12V5_12V5 9
92 #define AD4851_SOFTSPAN_0V_20V 10
93 #define AD4851_SOFTSPAN_N20V_20V 11
94 #define AD4851_SOFTSPAN_0V_25V 12
95 #define AD4851_SOFTSPAN_N25V_25V 13
96 #define AD4851_SOFTSPAN_0V_40V 14
97 #define AD4851_SOFTSPAN_N40V_40V 15
98
99 #define AD4851_MAX_LANES 8
100 #define AD4851_MAX_IODELAY 32
101
102 #define AD4851_T_CNVH_NS 40
103 #define AD4851_T_CNVH_NS_MARGIN 10
104
105 #define AD4841_MAX_SCALE_AVAIL 8
106
107 #define AD4851_MAX_CH_NR 8
108 #define AD4851_CH_START 0
109
110 struct ad4851_scale {
111 unsigned int scale_val;
112 u8 reg_val;
113 };
114
115 static const struct ad4851_scale ad4851_scale_table_unipolar[] = {
116 { 2500, 0x0 },
117 { 5000, 0x2 },
118 { 6250, 0x4 },
119 { 10000, 0x6 },
120 { 12500, 0x8 },
121 { 20000, 0xA },
122 { 25000, 0xC },
123 { 40000, 0xE },
124 };
125
126 static const struct ad4851_scale ad4851_scale_table_bipolar[] = {
127 { 5000, 0x1 },
128 { 10000, 0x3 },
129 { 12500, 0x5 },
130 { 20000, 0x7 },
131 { 25000, 0x9 },
132 { 40000, 0xB },
133 { 50000, 0xD },
134 { 80000, 0xF },
135 };
136
137 static const unsigned int ad4851_scale_avail_unipolar[] = {
138 2500,
139 5000,
140 6250,
141 10000,
142 12500,
143 20000,
144 25000,
145 40000,
146 };
147
148 static const unsigned int ad4851_scale_avail_bipolar[] = {
149 5000,
150 10000,
151 12500,
152 20000,
153 25000,
154 40000,
155 50000,
156 80000,
157 };
158
159 struct ad4851_chip_info {
160 const char *name;
161 unsigned int product_id;
162 int num_scales;
163 unsigned long max_sample_rate_hz;
164 unsigned int resolution;
165 unsigned int max_channels;
166 int (*parse_channels)(struct iio_dev *indio_dev);
167 };
168
169 enum {
170 AD4851_SCAN_TYPE_NORMAL,
171 AD4851_SCAN_TYPE_RESOLUTION_BOOST,
172 };
173
174 struct ad4851_state {
175 struct spi_device *spi;
176 struct pwm_device *cnv;
177 struct iio_backend *back;
178 /*
179 * Synchronize access to members the of driver state, and ensure
180 * atomicity of consecutive regmap operations.
181 */
182 struct mutex lock;
183 struct regmap *regmap;
184 const struct ad4851_chip_info *info;
185 struct gpio_desc *pd_gpio;
186 bool resolution_boost_enabled;
187 unsigned long cnv_trigger_rate_hz;
188 unsigned int osr;
189 bool vrefbuf_en;
190 bool vrefio_en;
191 bool bipolar_ch[AD4851_MAX_CH_NR];
192 unsigned int scales_unipolar[AD4841_MAX_SCALE_AVAIL][2];
193 unsigned int scales_bipolar[AD4841_MAX_SCALE_AVAIL][2];
194 };
195
ad4851_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)196 static int ad4851_reg_access(struct iio_dev *indio_dev,
197 unsigned int reg,
198 unsigned int writeval,
199 unsigned int *readval)
200 {
201 struct ad4851_state *st = iio_priv(indio_dev);
202
203 if (readval)
204 return regmap_read(st->regmap, reg, readval);
205
206 return regmap_write(st->regmap, reg, writeval);
207 }
208
ad4851_set_sampling_freq(struct ad4851_state * st,unsigned int freq)209 static int ad4851_set_sampling_freq(struct ad4851_state *st, unsigned int freq)
210 {
211 struct pwm_state cnv_state = {
212 .duty_cycle = AD4851_T_CNVH_NS + AD4851_T_CNVH_NS_MARGIN,
213 .enabled = true,
214 };
215 int ret;
216
217 freq = clamp(freq, 1, st->info->max_sample_rate_hz);
218
219 cnv_state.period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, freq);
220
221 ret = pwm_apply_might_sleep(st->cnv, &cnv_state);
222 if (ret)
223 return ret;
224
225 st->cnv_trigger_rate_hz = freq;
226
227 return 0;
228 }
229
230 static const int ad4851_oversampling_ratios[] = {
231 1, 2, 4, 8, 16, 32, 64, 128,
232 256, 512, 1024, 2048, 4096, 8192, 16384, 32768,
233 65536,
234 };
235
ad4851_osr_to_regval(unsigned int ratio)236 static int ad4851_osr_to_regval(unsigned int ratio)
237 {
238 int i;
239
240 for (i = 1; i < ARRAY_SIZE(ad4851_oversampling_ratios); i++)
241 if (ratio == ad4851_oversampling_ratios[i])
242 return i - 1;
243
244 return -EINVAL;
245 }
246
__ad4851_get_scale(struct iio_dev * indio_dev,int scale_tbl,unsigned int * val,unsigned int * val2)247 static int __ad4851_get_scale(struct iio_dev *indio_dev, int scale_tbl,
248 unsigned int *val, unsigned int *val2)
249 {
250 const struct iio_scan_type *scan_type;
251 unsigned int tmp;
252
253 scan_type = iio_get_current_scan_type(indio_dev, &indio_dev->channels[0]);
254 if (IS_ERR(scan_type))
255 return PTR_ERR(scan_type);
256
257 tmp = ((u64)scale_tbl * MICRO) >> scan_type->realbits;
258 *val = tmp / MICRO;
259 *val2 = tmp % MICRO;
260
261 return 0;
262 }
263
ad4851_scale_fill(struct iio_dev * indio_dev)264 static int ad4851_scale_fill(struct iio_dev *indio_dev)
265 {
266 struct ad4851_state *st = iio_priv(indio_dev);
267 unsigned int i, val1, val2;
268 int ret;
269
270 for (i = 0; i < ARRAY_SIZE(ad4851_scale_avail_unipolar); i++) {
271 ret = __ad4851_get_scale(indio_dev,
272 ad4851_scale_avail_unipolar[i],
273 &val1, &val2);
274 if (ret)
275 return ret;
276
277 st->scales_unipolar[i][0] = val1;
278 st->scales_unipolar[i][1] = val2;
279 }
280
281 for (i = 0; i < ARRAY_SIZE(ad4851_scale_avail_bipolar); i++) {
282 ret = __ad4851_get_scale(indio_dev,
283 ad4851_scale_avail_bipolar[i],
284 &val1, &val2);
285 if (ret)
286 return ret;
287
288 st->scales_bipolar[i][0] = val1;
289 st->scales_bipolar[i][1] = val2;
290 }
291
292 return 0;
293 }
294
ad4851_set_oversampling_ratio(struct iio_dev * indio_dev,unsigned int osr)295 static int ad4851_set_oversampling_ratio(struct iio_dev *indio_dev,
296 unsigned int osr)
297 {
298 struct ad4851_state *st = iio_priv(indio_dev);
299 int val, ret;
300
301 guard(mutex)(&st->lock);
302
303 if (osr == 1) {
304 ret = regmap_clear_bits(st->regmap, AD4851_REG_OVERSAMPLE,
305 AD4851_OS_EN_MSK);
306 if (ret)
307 return ret;
308 } else {
309 val = ad4851_osr_to_regval(osr);
310 if (val < 0)
311 return -EINVAL;
312
313 ret = regmap_update_bits(st->regmap, AD4851_REG_OVERSAMPLE,
314 AD4851_OS_EN_MSK |
315 AD4851_OS_RATIO_MSK,
316 FIELD_PREP(AD4851_OS_EN_MSK, 1) |
317 FIELD_PREP(AD4851_OS_RATIO_MSK, val));
318 if (ret)
319 return ret;
320 }
321
322 /* Channel is ignored by the backend being used here */
323 ret = iio_backend_oversampling_ratio_set(st->back, 0, osr);
324 if (ret)
325 return ret;
326
327 switch (st->info->resolution) {
328 case 20:
329 switch (osr) {
330 case 0:
331 return -EINVAL;
332 case 1:
333 val = 20;
334 break;
335 default:
336 val = 24;
337 break;
338 }
339 break;
340 case 16:
341 val = 16;
342 break;
343 default:
344 return -EINVAL;
345 }
346
347 ret = iio_backend_data_size_set(st->back, val);
348 if (ret)
349 return ret;
350
351 if (osr == 1 || st->info->resolution == 16) {
352 ret = regmap_clear_bits(st->regmap, AD4851_REG_PACKET,
353 AD4851_PACKET_FORMAT_MASK);
354 if (ret)
355 return ret;
356
357 st->resolution_boost_enabled = false;
358 } else {
359 ret = regmap_update_bits(st->regmap, AD4851_REG_PACKET,
360 AD4851_PACKET_FORMAT_MASK,
361 FIELD_PREP(AD4851_PACKET_FORMAT_MASK, 1));
362 if (ret)
363 return ret;
364
365 st->resolution_boost_enabled = true;
366 }
367
368 if (st->osr != osr) {
369 ret = ad4851_scale_fill(indio_dev);
370 if (ret)
371 return ret;
372
373 st->osr = osr;
374 }
375
376 return 0;
377 }
378
ad4851_get_oversampling_ratio(struct ad4851_state * st,unsigned int * val)379 static int ad4851_get_oversampling_ratio(struct ad4851_state *st, unsigned int *val)
380 {
381 unsigned int osr;
382 int ret;
383
384 guard(mutex)(&st->lock);
385
386 ret = regmap_read(st->regmap, AD4851_REG_OVERSAMPLE, &osr);
387 if (ret)
388 return ret;
389
390 if (!FIELD_GET(AD4851_OS_EN_MSK, osr))
391 *val = 1;
392 else
393 *val = ad4851_oversampling_ratios[FIELD_GET(AD4851_OS_RATIO_MSK, osr) + 1];
394
395 st->osr = *val;
396
397 return IIO_VAL_INT;
398 }
399
ad4851_pwm_disable(void * data)400 static void ad4851_pwm_disable(void *data)
401 {
402 pwm_disable(data);
403 }
404
ad4851_setup(struct ad4851_state * st)405 static int ad4851_setup(struct ad4851_state *st)
406 {
407 unsigned int product_id;
408 int ret;
409
410 if (st->pd_gpio) {
411 /* To initiate a global reset, bring the PD pin high twice */
412 gpiod_set_value(st->pd_gpio, 1);
413 fsleep(1);
414 gpiod_set_value(st->pd_gpio, 0);
415 fsleep(1);
416 gpiod_set_value(st->pd_gpio, 1);
417 fsleep(1);
418 gpiod_set_value(st->pd_gpio, 0);
419 fsleep(1000);
420 } else {
421 ret = regmap_set_bits(st->regmap, AD4851_REG_INTERFACE_CONFIG_A,
422 AD4851_SW_RESET);
423 if (ret)
424 return ret;
425 }
426
427 if (st->vrefbuf_en) {
428 ret = regmap_set_bits(st->regmap, AD4851_REG_DEVICE_CTRL,
429 AD4851_REFBUF);
430 if (ret)
431 return ret;
432 }
433
434 if (st->vrefio_en) {
435 ret = regmap_set_bits(st->regmap, AD4851_REG_DEVICE_CTRL,
436 AD4851_REFSEL);
437 if (ret)
438 return ret;
439 }
440
441 ret = regmap_write(st->regmap, AD4851_REG_INTERFACE_CONFIG_B,
442 AD4851_SINGLE_INSTRUCTION);
443 if (ret)
444 return ret;
445
446 if (!(st->spi->mode & SPI_3WIRE)) {
447 ret = regmap_write(st->regmap, AD4851_REG_INTERFACE_CONFIG_A,
448 AD4851_SDO_ENABLE);
449 if (ret)
450 return ret;
451 }
452
453 ret = regmap_read(st->regmap, AD4851_REG_PRODUCT_ID_L, &product_id);
454 if (ret)
455 return ret;
456
457 if (product_id != st->info->product_id)
458 dev_info(&st->spi->dev, "Unknown product ID: 0x%02X\n",
459 product_id);
460
461 ret = regmap_set_bits(st->regmap, AD4851_REG_DEVICE_CTRL,
462 AD4851_ECHO_CLOCK_MODE);
463 if (ret)
464 return ret;
465
466 return regmap_write(st->regmap, AD4851_REG_PACKET, 0);
467 }
468
469 /*
470 * Find the longest consecutive sequence of false values from field
471 * and return starting index.
472 */
ad4851_find_opt(const unsigned long * field,unsigned int start,unsigned int nbits,unsigned int * val)473 static int ad4851_find_opt(const unsigned long *field, unsigned int start,
474 unsigned int nbits, unsigned int *val)
475 {
476 unsigned int bit = start, end, start_cnt, cnt = 0;
477
478 for_each_clear_bitrange_from(bit, end, field, start + nbits) {
479 if (end - bit > cnt) {
480 cnt = end - bit;
481 start_cnt = bit - start;
482 }
483 }
484
485 if (!cnt)
486 return -ENOENT;
487
488 *val = start_cnt;
489
490 return cnt;
491 }
492
ad4851_calibrate(struct iio_dev * indio_dev)493 static int ad4851_calibrate(struct iio_dev *indio_dev)
494 {
495 struct ad4851_state *st = iio_priv(indio_dev);
496 unsigned int opt_delay, num_lanes, delay, i, s;
497 enum iio_backend_interface_type interface_type;
498 DECLARE_BITMAP(pn_status, AD4851_MAX_LANES * AD4851_MAX_IODELAY);
499 bool status;
500 int c, ret;
501
502 ret = iio_backend_interface_type_get(st->back, &interface_type);
503 if (ret)
504 return ret;
505
506 switch (interface_type) {
507 case IIO_BACKEND_INTERFACE_SERIAL_CMOS:
508 num_lanes = indio_dev->num_channels;
509 break;
510 case IIO_BACKEND_INTERFACE_SERIAL_LVDS:
511 num_lanes = 1;
512 break;
513 default:
514 return -EINVAL;
515 }
516
517 if (st->info->resolution == 16) {
518 ret = iio_backend_data_size_set(st->back, 24);
519 if (ret)
520 return ret;
521
522 ret = regmap_write(st->regmap, AD4851_REG_PACKET,
523 AD4851_TEST_PAT | AD4857_PACKET_SIZE_24);
524 if (ret)
525 return ret;
526 } else {
527 ret = iio_backend_data_size_set(st->back, 32);
528 if (ret)
529 return ret;
530
531 ret = regmap_write(st->regmap, AD4851_REG_PACKET,
532 AD4851_TEST_PAT | AD4858_PACKET_SIZE_32);
533 if (ret)
534 return ret;
535 }
536
537 for (i = 0; i < indio_dev->num_channels; i++) {
538 ret = regmap_write(st->regmap, AD4851_REG_TESTPAT_0(i),
539 AD4851_TESTPAT_0_DEFAULT);
540 if (ret)
541 return ret;
542
543 ret = regmap_write(st->regmap, AD4851_REG_TESTPAT_1(i),
544 AD4851_TESTPAT_1_DEFAULT);
545 if (ret)
546 return ret;
547
548 ret = regmap_write(st->regmap, AD4851_REG_TESTPAT_2(i),
549 AD4851_TESTPAT_2_DEFAULT);
550 if (ret)
551 return ret;
552
553 ret = regmap_write(st->regmap, AD4851_REG_TESTPAT_3(i),
554 AD4851_TESTPAT_3_DEFAULT(i));
555 if (ret)
556 return ret;
557
558 ret = iio_backend_chan_enable(st->back,
559 indio_dev->channels[i].channel);
560 if (ret)
561 return ret;
562 }
563
564 for (i = 0; i < num_lanes; i++) {
565 for (delay = 0; delay < AD4851_MAX_IODELAY; delay++) {
566 ret = iio_backend_iodelay_set(st->back, i, delay);
567 if (ret)
568 return ret;
569
570 ret = iio_backend_chan_status(st->back, i, &status);
571 if (ret)
572 return ret;
573
574 __assign_bit(i * AD4851_MAX_IODELAY + delay, pn_status,
575 status);
576 }
577 }
578
579 for (i = 0; i < num_lanes; i++) {
580 c = ad4851_find_opt(pn_status, i * AD4851_MAX_IODELAY,
581 AD4851_MAX_IODELAY, &s);
582 if (c < 0)
583 return c;
584
585 opt_delay = s + c / 2;
586 ret = iio_backend_iodelay_set(st->back, i, opt_delay);
587 if (ret)
588 return ret;
589 }
590
591 for (i = 0; i < indio_dev->num_channels; i++) {
592 ret = iio_backend_chan_disable(st->back, i);
593 if (ret)
594 return ret;
595 }
596
597 ret = iio_backend_data_size_set(st->back, 20);
598 if (ret)
599 return ret;
600
601 return regmap_write(st->regmap, AD4851_REG_PACKET, 0);
602 }
603
ad4851_get_calibscale(struct ad4851_state * st,int ch,int * val,int * val2)604 static int ad4851_get_calibscale(struct ad4851_state *st, int ch, int *val, int *val2)
605 {
606 unsigned int reg_val;
607 int gain;
608 int ret;
609
610 guard(mutex)(&st->lock);
611
612 ret = regmap_read(st->regmap, AD4851_REG_CHX_GAIN_MSB(ch), ®_val);
613 if (ret)
614 return ret;
615
616 gain = reg_val << 8;
617
618 ret = regmap_read(st->regmap, AD4851_REG_CHX_GAIN_LSB(ch), ®_val);
619 if (ret)
620 return ret;
621
622 gain |= reg_val;
623
624 *val = gain;
625 *val2 = 15;
626
627 return IIO_VAL_FRACTIONAL_LOG2;
628 }
629
ad4851_set_calibscale(struct ad4851_state * st,int ch,int val,int val2)630 static int ad4851_set_calibscale(struct ad4851_state *st, int ch, int val,
631 int val2)
632 {
633 u64 gain;
634 u8 buf[2];
635 int ret;
636
637 if (val < 0 || val2 < 0)
638 return -EINVAL;
639
640 gain = val * MICRO + val2;
641 gain = DIV_U64_ROUND_CLOSEST(gain * 32768, MICRO);
642
643 put_unaligned_be16(gain, buf);
644
645 guard(mutex)(&st->lock);
646
647 ret = regmap_write(st->regmap, AD4851_REG_CHX_GAIN_MSB(ch), buf[0]);
648 if (ret)
649 return ret;
650
651 return regmap_write(st->regmap, AD4851_REG_CHX_GAIN_LSB(ch), buf[1]);
652 }
653
ad4851_get_calibbias(struct ad4851_state * st,int ch,int * val)654 static int ad4851_get_calibbias(struct ad4851_state *st, int ch, int *val)
655 {
656 unsigned int lsb, mid, msb;
657 int ret;
658
659 guard(mutex)(&st->lock);
660 /*
661 * After testing, the bulk_write operations doesn't work as expected
662 * here since the cs needs to be raised after each byte transaction.
663 */
664 ret = regmap_read(st->regmap, AD4851_REG_CHX_OFFSET_MSB(ch), &msb);
665 if (ret)
666 return ret;
667
668 ret = regmap_read(st->regmap, AD4851_REG_CHX_OFFSET_MID(ch), &mid);
669 if (ret)
670 return ret;
671
672 ret = regmap_read(st->regmap, AD4851_REG_CHX_OFFSET_LSB(ch), &lsb);
673 if (ret)
674 return ret;
675
676 if (st->info->resolution == 16) {
677 *val = msb << 8;
678 *val |= mid;
679 *val = sign_extend32(*val, 15);
680 } else {
681 *val = msb << 12;
682 *val |= mid << 4;
683 *val |= lsb >> 4;
684 *val = sign_extend32(*val, 19);
685 }
686
687 return IIO_VAL_INT;
688 }
689
ad4851_set_calibbias(struct ad4851_state * st,int ch,int val)690 static int ad4851_set_calibbias(struct ad4851_state *st, int ch, int val)
691 {
692 u8 buf[3];
693 int ret;
694
695 if (val < 0)
696 return -EINVAL;
697
698 if (st->info->resolution == 16)
699 put_unaligned_be16(val, buf);
700 else
701 put_unaligned_be24(val << 4, buf);
702
703 guard(mutex)(&st->lock);
704 /*
705 * After testing, the bulk_write operations doesn't work as expected
706 * here since the cs needs to be raised after each byte transaction.
707 */
708 ret = regmap_write(st->regmap, AD4851_REG_CHX_OFFSET_LSB(ch), buf[2]);
709 if (ret)
710 return ret;
711
712 ret = regmap_write(st->regmap, AD4851_REG_CHX_OFFSET_MID(ch), buf[1]);
713 if (ret)
714 return ret;
715
716 return regmap_write(st->regmap, AD4851_REG_CHX_OFFSET_MSB(ch), buf[0]);
717 }
718
ad4851_set_scale(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int val,int val2)719 static int ad4851_set_scale(struct iio_dev *indio_dev,
720 const struct iio_chan_spec *chan, int val, int val2)
721 {
722 struct ad4851_state *st = iio_priv(indio_dev);
723 unsigned int scale_val[2];
724 unsigned int i;
725 const struct ad4851_scale *scale_table;
726 size_t table_size;
727 int ret;
728
729 if (st->bipolar_ch[chan->channel]) {
730 scale_table = ad4851_scale_table_bipolar;
731 table_size = ARRAY_SIZE(ad4851_scale_table_bipolar);
732 } else {
733 scale_table = ad4851_scale_table_unipolar;
734 table_size = ARRAY_SIZE(ad4851_scale_table_unipolar);
735 }
736
737 for (i = 0; i < table_size; i++) {
738 ret = __ad4851_get_scale(indio_dev, scale_table[i].scale_val,
739 &scale_val[0], &scale_val[1]);
740 if (ret)
741 return ret;
742
743 if (scale_val[0] != val || scale_val[1] != val2)
744 continue;
745
746 return regmap_write(st->regmap,
747 AD4851_REG_CHX_SOFTSPAN(chan->channel),
748 scale_table[i].reg_val);
749 }
750
751 return -EINVAL;
752 }
753
ad4851_get_scale(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int * val,int * val2)754 static int ad4851_get_scale(struct iio_dev *indio_dev,
755 const struct iio_chan_spec *chan, int *val,
756 int *val2)
757 {
758 struct ad4851_state *st = iio_priv(indio_dev);
759 const struct ad4851_scale *scale_table;
760 size_t table_size;
761 u32 softspan_val;
762 int i, ret;
763
764 if (st->bipolar_ch[chan->channel]) {
765 scale_table = ad4851_scale_table_bipolar;
766 table_size = ARRAY_SIZE(ad4851_scale_table_bipolar);
767 } else {
768 scale_table = ad4851_scale_table_unipolar;
769 table_size = ARRAY_SIZE(ad4851_scale_table_unipolar);
770 }
771
772 ret = regmap_read(st->regmap, AD4851_REG_CHX_SOFTSPAN(chan->channel),
773 &softspan_val);
774 if (ret)
775 return ret;
776
777 for (i = 0; i < table_size; i++) {
778 if (softspan_val == scale_table[i].reg_val)
779 break;
780 }
781
782 if (i == table_size)
783 return -EIO;
784
785 ret = __ad4851_get_scale(indio_dev, scale_table[i].scale_val, val,
786 val2);
787 if (ret)
788 return ret;
789
790 return IIO_VAL_INT_PLUS_MICRO;
791 }
792
ad4851_read_raw(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int * val,int * val2,long info)793 static int ad4851_read_raw(struct iio_dev *indio_dev,
794 const struct iio_chan_spec *chan,
795 int *val, int *val2, long info)
796 {
797 struct ad4851_state *st = iio_priv(indio_dev);
798
799 switch (info) {
800 case IIO_CHAN_INFO_SAMP_FREQ:
801 *val = st->cnv_trigger_rate_hz;
802 *val2 = st->osr;
803 return IIO_VAL_FRACTIONAL;
804 case IIO_CHAN_INFO_CALIBSCALE:
805 return ad4851_get_calibscale(st, chan->channel, val, val2);
806 case IIO_CHAN_INFO_SCALE:
807 return ad4851_get_scale(indio_dev, chan, val, val2);
808 case IIO_CHAN_INFO_CALIBBIAS:
809 return ad4851_get_calibbias(st, chan->channel, val);
810 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
811 return ad4851_get_oversampling_ratio(st, val);
812 default:
813 return -EINVAL;
814 }
815 }
816
ad4851_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)817 static int ad4851_write_raw(struct iio_dev *indio_dev,
818 struct iio_chan_spec const *chan,
819 int val, int val2, long info)
820 {
821 struct ad4851_state *st = iio_priv(indio_dev);
822
823 switch (info) {
824 case IIO_CHAN_INFO_SAMP_FREQ:
825 if (val < 0 || val2 < 0)
826 return -EINVAL;
827 return ad4851_set_sampling_freq(st, val * st->osr + val2 * st->osr / MICRO);
828 case IIO_CHAN_INFO_SCALE:
829 return ad4851_set_scale(indio_dev, chan, val, val2);
830 case IIO_CHAN_INFO_CALIBSCALE:
831 return ad4851_set_calibscale(st, chan->channel, val, val2);
832 case IIO_CHAN_INFO_CALIBBIAS:
833 return ad4851_set_calibbias(st, chan->channel, val);
834 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
835 return ad4851_set_oversampling_ratio(indio_dev, val);
836 default:
837 return -EINVAL;
838 }
839 }
840
ad4851_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * scan_mask)841 static int ad4851_update_scan_mode(struct iio_dev *indio_dev,
842 const unsigned long *scan_mask)
843 {
844 struct ad4851_state *st = iio_priv(indio_dev);
845 unsigned int c;
846 int ret;
847
848 for (c = 0; c < indio_dev->num_channels; c++) {
849 if (test_bit(c, scan_mask))
850 ret = iio_backend_chan_enable(st->back, c);
851 else
852 ret = iio_backend_chan_disable(st->back, c);
853 if (ret)
854 return ret;
855 }
856
857 return 0;
858 }
859
ad4851_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long mask)860 static int ad4851_read_avail(struct iio_dev *indio_dev,
861 struct iio_chan_spec const *chan,
862 const int **vals, int *type, int *length,
863 long mask)
864 {
865 struct ad4851_state *st = iio_priv(indio_dev);
866
867 switch (mask) {
868 case IIO_CHAN_INFO_SCALE:
869 if (st->bipolar_ch[chan->channel]) {
870 *vals = (const int *)st->scales_bipolar;
871 *type = IIO_VAL_INT_PLUS_MICRO;
872 /* Values are stored in a 2D matrix */
873 *length = ARRAY_SIZE(ad4851_scale_avail_bipolar) * 2;
874 } else {
875 *vals = (const int *)st->scales_unipolar;
876 *type = IIO_VAL_INT_PLUS_MICRO;
877 /* Values are stored in a 2D matrix */
878 *length = ARRAY_SIZE(ad4851_scale_avail_unipolar) * 2;
879 }
880 return IIO_AVAIL_LIST;
881 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
882 *vals = ad4851_oversampling_ratios;
883 *length = ARRAY_SIZE(ad4851_oversampling_ratios);
884 *type = IIO_VAL_INT;
885 return IIO_AVAIL_LIST;
886 default:
887 return -EINVAL;
888 }
889 }
890
891 static const struct iio_scan_type ad4851_scan_type_20_u[] = {
892 [AD4851_SCAN_TYPE_NORMAL] = {
893 .sign = 'u',
894 .realbits = 20,
895 .storagebits = 32,
896 },
897 [AD4851_SCAN_TYPE_RESOLUTION_BOOST] = {
898 .sign = 'u',
899 .realbits = 24,
900 .storagebits = 32,
901 },
902 };
903
904 static const struct iio_scan_type ad4851_scan_type_20_b[] = {
905 [AD4851_SCAN_TYPE_NORMAL] = {
906 .sign = 's',
907 .realbits = 20,
908 .storagebits = 32,
909 },
910 [AD4851_SCAN_TYPE_RESOLUTION_BOOST] = {
911 .sign = 's',
912 .realbits = 24,
913 .storagebits = 32,
914 },
915 };
916
ad4851_get_current_scan_type(const struct iio_dev * indio_dev,const struct iio_chan_spec * chan)917 static int ad4851_get_current_scan_type(const struct iio_dev *indio_dev,
918 const struct iio_chan_spec *chan)
919 {
920 struct ad4851_state *st = iio_priv(indio_dev);
921
922 return st->resolution_boost_enabled ? AD4851_SCAN_TYPE_RESOLUTION_BOOST
923 : AD4851_SCAN_TYPE_NORMAL;
924 }
925
926 #define AD4851_IIO_CHANNEL \
927 .type = IIO_VOLTAGE, \
928 .info_mask_separate = BIT(IIO_CHAN_INFO_CALIBSCALE) | \
929 BIT(IIO_CHAN_INFO_CALIBBIAS) | \
930 BIT(IIO_CHAN_INFO_SCALE), \
931 .info_mask_separate_available = BIT(IIO_CHAN_INFO_SCALE), \
932 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
933 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
934 .info_mask_shared_by_all_available = \
935 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
936 .indexed = 1
937
938 /*
939 * In case of AD4858_IIO_CHANNEL the scan_type is handled dynamically during the
940 * parse_channels function.
941 */
942 #define AD4858_IIO_CHANNEL \
943 { \
944 AD4851_IIO_CHANNEL \
945 }
946
947 #define AD4857_IIO_CHANNEL \
948 { \
949 AD4851_IIO_CHANNEL, \
950 .scan_type = { \
951 .sign = 'u', \
952 .realbits = 16, \
953 .storagebits = 16, \
954 }, \
955 }
956
ad4851_parse_channels_common(struct iio_dev * indio_dev,struct iio_chan_spec ** chans,const struct iio_chan_spec ad4851_chan)957 static int ad4851_parse_channels_common(struct iio_dev *indio_dev,
958 struct iio_chan_spec **chans,
959 const struct iio_chan_spec ad4851_chan)
960 {
961 struct ad4851_state *st = iio_priv(indio_dev);
962 struct device *dev = &st->spi->dev;
963 struct iio_chan_spec *channels, *chan_start;
964 unsigned int num_channels, reg;
965 unsigned int index = 0;
966 int ret;
967
968 num_channels = device_get_child_node_count(dev);
969 if (num_channels > AD4851_MAX_CH_NR)
970 return dev_err_probe(dev, -EINVAL, "Too many channels: %u\n",
971 num_channels);
972
973 channels = devm_kcalloc(dev, num_channels, sizeof(*channels), GFP_KERNEL);
974 if (!channels)
975 return -ENOMEM;
976
977 chan_start = channels;
978
979 device_for_each_child_node_scoped(dev, child) {
980 ret = fwnode_property_read_u32(child, "reg", ®);
981 if (ret)
982 return dev_err_probe(dev, ret,
983 "Missing channel number\n");
984 if (reg >= AD4851_MAX_CH_NR)
985 return dev_err_probe(dev, -EINVAL,
986 "Invalid channel number\n");
987 *channels = ad4851_chan;
988 channels->scan_index = index++;
989 channels->channel = reg;
990
991 if (fwnode_property_present(child, "diff-channels")) {
992 channels->channel2 = reg + st->info->max_channels;
993 channels->differential = 1;
994 }
995
996 st->bipolar_ch[reg] = fwnode_property_read_bool(child, "bipolar");
997
998 if (st->bipolar_ch[reg]) {
999 channels->scan_type.sign = 's';
1000 } else {
1001 ret = regmap_write(st->regmap, AD4851_REG_CHX_SOFTSPAN(reg),
1002 AD4851_SOFTSPAN_0V_40V);
1003 if (ret)
1004 return ret;
1005 }
1006
1007 channels++;
1008 }
1009
1010 *chans = chan_start;
1011
1012 return num_channels;
1013 }
1014
ad4857_parse_channels(struct iio_dev * indio_dev)1015 static int ad4857_parse_channels(struct iio_dev *indio_dev)
1016 {
1017 struct iio_chan_spec *ad4851_channels;
1018 const struct iio_chan_spec ad4851_chan = AD4857_IIO_CHANNEL;
1019 int ret;
1020
1021 ret = ad4851_parse_channels_common(indio_dev, &ad4851_channels,
1022 ad4851_chan);
1023 if (ret < 0)
1024 return ret;
1025
1026 indio_dev->channels = ad4851_channels;
1027 indio_dev->num_channels = ret;
1028
1029 return 0;
1030 }
1031
ad4858_parse_channels(struct iio_dev * indio_dev)1032 static int ad4858_parse_channels(struct iio_dev *indio_dev)
1033 {
1034 struct ad4851_state *st = iio_priv(indio_dev);
1035 struct device *dev = &st->spi->dev;
1036 struct iio_chan_spec *ad4851_channels;
1037 const struct iio_chan_spec ad4851_chan = AD4858_IIO_CHANNEL;
1038 int ret, i = 0;
1039
1040 ret = ad4851_parse_channels_common(indio_dev, &ad4851_channels,
1041 ad4851_chan);
1042 if (ret < 0)
1043 return ret;
1044
1045 device_for_each_child_node_scoped(dev, child) {
1046 ad4851_channels[i].has_ext_scan_type = 1;
1047 if (fwnode_property_read_bool(child, "bipolar")) {
1048 ad4851_channels[i].ext_scan_type = ad4851_scan_type_20_b;
1049 ad4851_channels[i].num_ext_scan_type = ARRAY_SIZE(ad4851_scan_type_20_b);
1050 } else {
1051 ad4851_channels[i].ext_scan_type = ad4851_scan_type_20_u;
1052 ad4851_channels[i].num_ext_scan_type = ARRAY_SIZE(ad4851_scan_type_20_u);
1053 }
1054 i++;
1055 }
1056
1057 indio_dev->channels = ad4851_channels;
1058 indio_dev->num_channels = ret;
1059
1060 return 0;
1061 }
1062
1063 /*
1064 * parse_channels() function handles the rest of the channel related attributes
1065 * that are usually are stored in the chip info structure.
1066 */
1067 static const struct ad4851_chip_info ad4851_info = {
1068 .name = "ad4851",
1069 .product_id = 0x67,
1070 .max_sample_rate_hz = 250 * KILO,
1071 .resolution = 16,
1072 .max_channels = AD4851_MAX_CH_NR,
1073 .parse_channels = ad4857_parse_channels,
1074 };
1075
1076 static const struct ad4851_chip_info ad4852_info = {
1077 .name = "ad4852",
1078 .product_id = 0x66,
1079 .max_sample_rate_hz = 250 * KILO,
1080 .resolution = 20,
1081 .max_channels = AD4851_MAX_CH_NR,
1082 .parse_channels = ad4858_parse_channels,
1083 };
1084
1085 static const struct ad4851_chip_info ad4853_info = {
1086 .name = "ad4853",
1087 .product_id = 0x65,
1088 .max_sample_rate_hz = 1 * MEGA,
1089 .resolution = 16,
1090 .max_channels = AD4851_MAX_CH_NR,
1091 .parse_channels = ad4857_parse_channels,
1092 };
1093
1094 static const struct ad4851_chip_info ad4854_info = {
1095 .name = "ad4854",
1096 .product_id = 0x64,
1097 .max_sample_rate_hz = 1 * MEGA,
1098 .resolution = 20,
1099 .max_channels = AD4851_MAX_CH_NR,
1100 .parse_channels = ad4858_parse_channels,
1101 };
1102
1103 static const struct ad4851_chip_info ad4855_info = {
1104 .name = "ad4855",
1105 .product_id = 0x63,
1106 .max_sample_rate_hz = 250 * KILO,
1107 .resolution = 16,
1108 .max_channels = AD4851_MAX_CH_NR,
1109 .parse_channels = ad4857_parse_channels,
1110 };
1111
1112 static const struct ad4851_chip_info ad4856_info = {
1113 .name = "ad4856",
1114 .product_id = 0x62,
1115 .max_sample_rate_hz = 250 * KILO,
1116 .resolution = 20,
1117 .max_channels = AD4851_MAX_CH_NR,
1118 .parse_channels = ad4858_parse_channels,
1119 };
1120
1121 static const struct ad4851_chip_info ad4857_info = {
1122 .name = "ad4857",
1123 .product_id = 0x61,
1124 .max_sample_rate_hz = 1 * MEGA,
1125 .resolution = 16,
1126 .max_channels = AD4851_MAX_CH_NR,
1127 .parse_channels = ad4857_parse_channels,
1128 };
1129
1130 static const struct ad4851_chip_info ad4858_info = {
1131 .name = "ad4858",
1132 .product_id = 0x60,
1133 .max_sample_rate_hz = 1 * MEGA,
1134 .resolution = 20,
1135 .max_channels = AD4851_MAX_CH_NR,
1136 .parse_channels = ad4858_parse_channels,
1137 };
1138
1139 static const struct ad4851_chip_info ad4858i_info = {
1140 .name = "ad4858i",
1141 .product_id = 0x6F,
1142 .max_sample_rate_hz = 1 * MEGA,
1143 .resolution = 20,
1144 .max_channels = AD4851_MAX_CH_NR,
1145 .parse_channels = ad4858_parse_channels,
1146 };
1147
1148 static const struct iio_info ad4851_iio_info = {
1149 .debugfs_reg_access = ad4851_reg_access,
1150 .read_raw = ad4851_read_raw,
1151 .write_raw = ad4851_write_raw,
1152 .update_scan_mode = ad4851_update_scan_mode,
1153 .get_current_scan_type = ad4851_get_current_scan_type,
1154 .read_avail = ad4851_read_avail,
1155 };
1156
1157 static const struct regmap_config regmap_config = {
1158 .reg_bits = 16,
1159 .val_bits = 8,
1160 .read_flag_mask = BIT(7),
1161 };
1162
1163 static const char * const ad4851_power_supplies[] = {
1164 "vcc", "vdd", "vee", "vio",
1165 };
1166
ad4851_probe(struct spi_device * spi)1167 static int ad4851_probe(struct spi_device *spi)
1168 {
1169 struct iio_dev *indio_dev;
1170 struct device *dev = &spi->dev;
1171 struct ad4851_state *st;
1172 int ret;
1173
1174 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1175 if (!indio_dev)
1176 return -ENOMEM;
1177
1178 st = iio_priv(indio_dev);
1179 st->spi = spi;
1180
1181 ret = devm_mutex_init(dev, &st->lock);
1182 if (ret)
1183 return ret;
1184
1185 ret = devm_regulator_bulk_get_enable(dev,
1186 ARRAY_SIZE(ad4851_power_supplies),
1187 ad4851_power_supplies);
1188 if (ret)
1189 return dev_err_probe(dev, ret,
1190 "failed to get and enable supplies\n");
1191
1192 ret = devm_regulator_get_enable_optional(dev, "vddh");
1193 if (ret < 0 && ret != -ENODEV)
1194 return dev_err_probe(dev, ret, "failed to enable vddh voltage\n");
1195
1196 ret = devm_regulator_get_enable_optional(dev, "vddl");
1197 if (ret < 0 && ret != -ENODEV)
1198 return dev_err_probe(dev, ret, "failed to enable vddl voltage\n");
1199
1200 ret = devm_regulator_get_enable_optional(dev, "vrefbuf");
1201 if (ret < 0 && ret != -ENODEV)
1202 return dev_err_probe(dev, ret, "failed to enable vrefbuf voltage\n");
1203
1204 st->vrefbuf_en = ret != -ENODEV;
1205
1206 ret = devm_regulator_get_enable_optional(dev, "vrefio");
1207 if (ret < 0 && ret != -ENODEV)
1208 return dev_err_probe(dev, ret, "failed to enable vrefio voltage\n");
1209
1210 st->vrefio_en = ret != -ENODEV;
1211
1212 st->pd_gpio = devm_gpiod_get_optional(dev, "pd", GPIOD_OUT_LOW);
1213 if (IS_ERR(st->pd_gpio))
1214 return dev_err_probe(dev, PTR_ERR(st->pd_gpio),
1215 "Error on requesting pd GPIO\n");
1216
1217 st->cnv = devm_pwm_get(dev, NULL);
1218 if (IS_ERR(st->cnv))
1219 return dev_err_probe(dev, PTR_ERR(st->cnv),
1220 "Error on requesting pwm\n");
1221
1222 st->info = spi_get_device_match_data(spi);
1223 if (!st->info)
1224 return -ENODEV;
1225
1226 st->regmap = devm_regmap_init_spi(spi, ®map_config);
1227 if (IS_ERR(st->regmap))
1228 return PTR_ERR(st->regmap);
1229
1230 ret = ad4851_set_sampling_freq(st, HZ_PER_MHZ);
1231 if (ret)
1232 return ret;
1233
1234 ret = devm_add_action_or_reset(&st->spi->dev, ad4851_pwm_disable,
1235 st->cnv);
1236 if (ret)
1237 return ret;
1238
1239 ret = ad4851_setup(st);
1240 if (ret)
1241 return ret;
1242
1243 indio_dev->name = st->info->name;
1244 indio_dev->info = &ad4851_iio_info;
1245 indio_dev->modes = INDIO_DIRECT_MODE;
1246
1247 ret = st->info->parse_channels(indio_dev);
1248 if (ret)
1249 return ret;
1250
1251 ret = ad4851_scale_fill(indio_dev);
1252 if (ret)
1253 return ret;
1254
1255 st->back = devm_iio_backend_get(dev, NULL);
1256 if (IS_ERR(st->back))
1257 return PTR_ERR(st->back);
1258
1259 ret = devm_iio_backend_request_buffer(dev, st->back, indio_dev);
1260 if (ret)
1261 return ret;
1262
1263 ret = devm_iio_backend_enable(dev, st->back);
1264 if (ret)
1265 return ret;
1266
1267 ret = ad4851_calibrate(indio_dev);
1268 if (ret)
1269 return ret;
1270
1271 return devm_iio_device_register(dev, indio_dev);
1272 }
1273
1274 static const struct of_device_id ad4851_of_match[] = {
1275 { .compatible = "adi,ad4851", .data = &ad4851_info, },
1276 { .compatible = "adi,ad4852", .data = &ad4852_info, },
1277 { .compatible = "adi,ad4853", .data = &ad4853_info, },
1278 { .compatible = "adi,ad4854", .data = &ad4854_info, },
1279 { .compatible = "adi,ad4855", .data = &ad4855_info, },
1280 { .compatible = "adi,ad4856", .data = &ad4856_info, },
1281 { .compatible = "adi,ad4857", .data = &ad4857_info, },
1282 { .compatible = "adi,ad4858", .data = &ad4858_info, },
1283 { .compatible = "adi,ad4858i", .data = &ad4858i_info, },
1284 { }
1285 };
1286
1287 static const struct spi_device_id ad4851_spi_id[] = {
1288 { "ad4851", (kernel_ulong_t)&ad4851_info },
1289 { "ad4852", (kernel_ulong_t)&ad4852_info },
1290 { "ad4853", (kernel_ulong_t)&ad4853_info },
1291 { "ad4854", (kernel_ulong_t)&ad4854_info },
1292 { "ad4855", (kernel_ulong_t)&ad4855_info },
1293 { "ad4856", (kernel_ulong_t)&ad4856_info },
1294 { "ad4857", (kernel_ulong_t)&ad4857_info },
1295 { "ad4858", (kernel_ulong_t)&ad4858_info },
1296 { "ad4858i", (kernel_ulong_t)&ad4858i_info },
1297 { }
1298 };
1299 MODULE_DEVICE_TABLE(spi, ad4851_spi_id);
1300
1301 static struct spi_driver ad4851_driver = {
1302 .probe = ad4851_probe,
1303 .driver = {
1304 .name = "ad4851",
1305 .of_match_table = ad4851_of_match,
1306 },
1307 .id_table = ad4851_spi_id,
1308 };
1309 module_spi_driver(ad4851_driver);
1310
1311 MODULE_AUTHOR("Sergiu Cuciurean <sergiu.cuciurean@analog.com>");
1312 MODULE_AUTHOR("Dragos Bogdan <dragos.bogdan@analog.com>");
1313 MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com>");
1314 MODULE_DESCRIPTION("Analog Devices AD4851 DAS driver");
1315 MODULE_LICENSE("GPL");
1316 MODULE_IMPORT_NS("IIO_BACKEND");
1317