1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 /* 82562G 10/100 Network Connection 5 * 82562G-2 10/100 Network Connection 6 * 82562GT 10/100 Network Connection 7 * 82562GT-2 10/100 Network Connection 8 * 82562V 10/100 Network Connection 9 * 82562V-2 10/100 Network Connection 10 * 82566DC-2 Gigabit Network Connection 11 * 82566DC Gigabit Network Connection 12 * 82566DM-2 Gigabit Network Connection 13 * 82566DM Gigabit Network Connection 14 * 82566MC Gigabit Network Connection 15 * 82566MM Gigabit Network Connection 16 * 82567LM Gigabit Network Connection 17 * 82567LF Gigabit Network Connection 18 * 82567V Gigabit Network Connection 19 * 82567LM-2 Gigabit Network Connection 20 * 82567LF-2 Gigabit Network Connection 21 * 82567V-2 Gigabit Network Connection 22 * 82567LF-3 Gigabit Network Connection 23 * 82567LM-3 Gigabit Network Connection 24 * 82567LM-4 Gigabit Network Connection 25 * 82577LM Gigabit Network Connection 26 * 82577LC Gigabit Network Connection 27 * 82578DM Gigabit Network Connection 28 * 82578DC Gigabit Network Connection 29 * 82579LM Gigabit Network Connection 30 * 82579V Gigabit Network Connection 31 * Ethernet Connection I217-LM 32 * Ethernet Connection I217-V 33 * Ethernet Connection I218-V 34 * Ethernet Connection I218-LM 35 * Ethernet Connection (2) I218-LM 36 * Ethernet Connection (2) I218-V 37 * Ethernet Connection (3) I218-LM 38 * Ethernet Connection (3) I218-V 39 */ 40 41 #include "e1000.h" 42 43 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ 44 /* Offset 04h HSFSTS */ 45 union ich8_hws_flash_status { 46 struct ich8_hsfsts { 47 u16 flcdone:1; /* bit 0 Flash Cycle Done */ 48 u16 flcerr:1; /* bit 1 Flash Cycle Error */ 49 u16 dael:1; /* bit 2 Direct Access error Log */ 50 u16 berasesz:2; /* bit 4:3 Sector Erase Size */ 51 u16 flcinprog:1; /* bit 5 flash cycle in Progress */ 52 u16 reserved1:2; /* bit 13:6 Reserved */ 53 u16 reserved2:6; /* bit 13:6 Reserved */ 54 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */ 55 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */ 56 } hsf_status; 57 u16 regval; 58 }; 59 60 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ 61 /* Offset 06h FLCTL */ 62 union ich8_hws_flash_ctrl { 63 struct ich8_hsflctl { 64 u16 flcgo:1; /* 0 Flash Cycle Go */ 65 u16 flcycle:2; /* 2:1 Flash Cycle */ 66 u16 reserved:5; /* 7:3 Reserved */ 67 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */ 68 u16 flockdn:6; /* 15:10 Reserved */ 69 } hsf_ctrl; 70 u16 regval; 71 }; 72 73 /* ICH Flash Region Access Permissions */ 74 union ich8_hws_flash_regacc { 75 struct ich8_flracc { 76 u32 grra:8; /* 0:7 GbE region Read Access */ 77 u32 grwa:8; /* 8:15 GbE region Write Access */ 78 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */ 79 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */ 80 } hsf_flregacc; 81 u16 regval; 82 }; 83 84 /* ICH Flash Protected Region */ 85 union ich8_flash_protected_range { 86 struct ich8_pr { 87 u32 base:13; /* 0:12 Protected Range Base */ 88 u32 reserved1:2; /* 13:14 Reserved */ 89 u32 rpe:1; /* 15 Read Protection Enable */ 90 u32 limit:13; /* 16:28 Protected Range Limit */ 91 u32 reserved2:2; /* 29:30 Reserved */ 92 u32 wpe:1; /* 31 Write Protection Enable */ 93 } range; 94 u32 regval; 95 }; 96 97 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); 98 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); 99 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); 100 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 101 u32 offset, u8 byte); 102 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 103 u8 *data); 104 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 105 u16 *data); 106 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 107 u8 size, u16 *data); 108 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 109 u32 *data); 110 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, 111 u32 offset, u32 *data); 112 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, 113 u32 offset, u32 data); 114 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw, 115 u32 offset, u32 dword); 116 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); 117 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); 118 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw); 119 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw); 120 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw); 121 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw); 122 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw); 123 static s32 e1000_led_on_pchlan(struct e1000_hw *hw); 124 static s32 e1000_led_off_pchlan(struct e1000_hw *hw); 125 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active); 126 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw); 127 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw); 128 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link); 129 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw); 130 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); 131 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw); 132 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index); 133 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index); 134 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw); 135 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw); 136 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate); 137 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force); 138 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw); 139 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state); 140 141 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg) 142 { 143 return readw(hw->flash_address + reg); 144 } 145 146 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg) 147 { 148 return readl(hw->flash_address + reg); 149 } 150 151 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val) 152 { 153 writew(val, hw->flash_address + reg); 154 } 155 156 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val) 157 { 158 writel(val, hw->flash_address + reg); 159 } 160 161 #define er16flash(reg) __er16flash(hw, (reg)) 162 #define er32flash(reg) __er32flash(hw, (reg)) 163 #define ew16flash(reg, val) __ew16flash(hw, (reg), (val)) 164 #define ew32flash(reg, val) __ew32flash(hw, (reg), (val)) 165 166 /** 167 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers 168 * @hw: pointer to the HW structure 169 * 170 * Test access to the PHY registers by reading the PHY ID registers. If 171 * the PHY ID is already known (e.g. resume path) compare it with known ID, 172 * otherwise assume the read PHY ID is correct if it is valid. 173 * 174 * Assumes the sw/fw/hw semaphore is already acquired. 175 **/ 176 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw) 177 { 178 u16 phy_reg = 0; 179 u32 phy_id = 0; 180 s32 ret_val = 0; 181 u16 retry_count; 182 u32 mac_reg = 0; 183 184 for (retry_count = 0; retry_count < 2; retry_count++) { 185 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg); 186 if (ret_val || (phy_reg == 0xFFFF)) 187 continue; 188 phy_id = (u32)(phy_reg << 16); 189 190 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg); 191 if (ret_val || (phy_reg == 0xFFFF)) { 192 phy_id = 0; 193 continue; 194 } 195 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK); 196 break; 197 } 198 199 if (hw->phy.id) { 200 if (hw->phy.id == phy_id) 201 goto out; 202 } else if (phy_id) { 203 hw->phy.id = phy_id; 204 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK); 205 goto out; 206 } 207 208 /* In case the PHY needs to be in mdio slow mode, 209 * set slow mode and try to get the PHY id again. 210 */ 211 if (hw->mac.type < e1000_pch_lpt) { 212 hw->phy.ops.release(hw); 213 ret_val = e1000_set_mdio_slow_mode_hv(hw); 214 if (!ret_val) 215 ret_val = e1000e_get_phy_id(hw); 216 hw->phy.ops.acquire(hw); 217 } 218 219 if (ret_val) 220 return false; 221 out: 222 if (hw->mac.type >= e1000_pch_lpt) { 223 /* Only unforce SMBus if ME is not active */ 224 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 225 /* Switching PHY interface always returns MDI error 226 * so disable retry mechanism to avoid wasting time 227 */ 228 e1000e_disable_phy_retry(hw); 229 230 /* Unforce SMBus mode in PHY */ 231 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg); 232 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 233 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg); 234 235 e1000e_enable_phy_retry(hw); 236 237 /* Unforce SMBus mode in MAC */ 238 mac_reg = er32(CTRL_EXT); 239 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 240 ew32(CTRL_EXT, mac_reg); 241 } 242 } 243 244 return true; 245 } 246 247 /** 248 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value 249 * @hw: pointer to the HW structure 250 * 251 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is 252 * used to reset the PHY to a quiescent state when necessary. 253 **/ 254 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw) 255 { 256 u32 mac_reg; 257 258 /* Set Phy Config Counter to 50msec */ 259 mac_reg = er32(FEXTNVM3); 260 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 261 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 262 ew32(FEXTNVM3, mac_reg); 263 264 /* Toggle LANPHYPC Value bit */ 265 mac_reg = er32(CTRL); 266 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE; 267 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE; 268 ew32(CTRL, mac_reg); 269 e1e_flush(); 270 usleep_range(10, 20); 271 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE; 272 ew32(CTRL, mac_reg); 273 e1e_flush(); 274 275 if (hw->mac.type < e1000_pch_lpt) { 276 msleep(50); 277 } else { 278 u16 count = 20; 279 280 do { 281 usleep_range(5000, 6000); 282 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--); 283 284 msleep(30); 285 } 286 } 287 288 /** 289 * e1000_reconfigure_k1_params - reconfigure Kumeran K1 parameters. 290 * @hw: pointer to the HW structure 291 * 292 * By default K1 is enabled after MAC reset, so this function only 293 * disables it. 294 * 295 * Context: PHY semaphore must be held by caller. 296 * Return: 0 on success, negative on failure 297 */ 298 static s32 e1000_reconfigure_k1_params(struct e1000_hw *hw) 299 { 300 u16 phy_timeout; 301 u32 fextnvm12; 302 s32 ret_val; 303 304 if (hw->mac.type < e1000_pch_mtp) { 305 if (hw->adapter->flags2 & FLAG2_DISABLE_K1) 306 return e1000_configure_k1_ich8lan(hw, false); 307 return 0; 308 } 309 310 /* Change Kumeran K1 power down state from P0s to P1 */ 311 fextnvm12 = er32(FEXTNVM12); 312 fextnvm12 &= ~E1000_FEXTNVM12_PHYPD_CTRL_MASK; 313 fextnvm12 |= E1000_FEXTNVM12_PHYPD_CTRL_P1; 314 ew32(FEXTNVM12, fextnvm12); 315 316 /* Wait for the interface the settle */ 317 usleep_range(1000, 1100); 318 if (hw->adapter->flags2 & FLAG2_DISABLE_K1) 319 return e1000_configure_k1_ich8lan(hw, false); 320 321 /* Change K1 exit timeout */ 322 ret_val = e1e_rphy_locked(hw, I217_PHY_TIMEOUTS_REG, 323 &phy_timeout); 324 if (ret_val) 325 return ret_val; 326 327 phy_timeout &= ~I217_PHY_TIMEOUTS_K1_EXIT_TO_MASK; 328 phy_timeout |= 0xF00; 329 330 return e1e_wphy_locked(hw, I217_PHY_TIMEOUTS_REG, 331 phy_timeout); 332 } 333 334 /** 335 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds 336 * @hw: pointer to the HW structure 337 * 338 * Workarounds/flow necessary for PHY initialization during driver load 339 * and resume paths. 340 **/ 341 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw) 342 { 343 struct e1000_adapter *adapter = hw->adapter; 344 u32 mac_reg, fwsm = er32(FWSM); 345 s32 ret_val; 346 347 /* Gate automatic PHY configuration by hardware on managed and 348 * non-managed 82579 and newer adapters. 349 */ 350 e1000_gate_hw_phy_config_ich8lan(hw, true); 351 352 /* It is not possible to be certain of the current state of ULP 353 * so forcibly disable it. 354 */ 355 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown; 356 ret_val = e1000_disable_ulp_lpt_lp(hw, true); 357 if (ret_val) 358 e_warn("Failed to disable ULP\n"); 359 360 ret_val = hw->phy.ops.acquire(hw); 361 if (ret_val) { 362 e_dbg("Failed to initialize PHY flow\n"); 363 goto out; 364 } 365 366 /* There is no guarantee that the PHY is accessible at this time 367 * so disable retry mechanism to avoid wasting time 368 */ 369 e1000e_disable_phy_retry(hw); 370 371 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is 372 * inaccessible and resetting the PHY is not blocked, toggle the 373 * LANPHYPC Value bit to force the interconnect to PCIe mode. 374 */ 375 switch (hw->mac.type) { 376 case e1000_pch_mtp: 377 case e1000_pch_lnp: 378 case e1000_pch_ptp: 379 case e1000_pch_nvp: 380 /* At this point the PHY might be inaccessible so don't 381 * propagate the failure 382 */ 383 if (e1000_reconfigure_k1_params(hw)) 384 e_dbg("Failed to reconfigure K1 parameters\n"); 385 386 fallthrough; 387 case e1000_pch_lpt: 388 case e1000_pch_spt: 389 case e1000_pch_cnp: 390 case e1000_pch_tgp: 391 case e1000_pch_adp: 392 if (e1000_phy_is_accessible_pchlan(hw)) 393 break; 394 395 /* Before toggling LANPHYPC, see if PHY is accessible by 396 * forcing MAC to SMBus mode first. 397 */ 398 mac_reg = er32(CTRL_EXT); 399 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 400 ew32(CTRL_EXT, mac_reg); 401 402 /* Wait 50 milliseconds for MAC to finish any retries 403 * that it might be trying to perform from previous 404 * attempts to acknowledge any phy read requests. 405 */ 406 msleep(50); 407 408 fallthrough; 409 case e1000_pch2lan: 410 if (e1000_phy_is_accessible_pchlan(hw)) 411 break; 412 413 fallthrough; 414 case e1000_pchlan: 415 if ((hw->mac.type == e1000_pchlan) && 416 (fwsm & E1000_ICH_FWSM_FW_VALID)) 417 break; 418 419 if (hw->phy.ops.check_reset_block(hw)) { 420 e_dbg("Required LANPHYPC toggle blocked by ME\n"); 421 ret_val = -E1000_ERR_PHY; 422 break; 423 } 424 425 /* Toggle LANPHYPC Value bit */ 426 e1000_toggle_lanphypc_pch_lpt(hw); 427 if (hw->mac.type >= e1000_pch_lpt) { 428 if (e1000_phy_is_accessible_pchlan(hw)) 429 break; 430 431 /* Toggling LANPHYPC brings the PHY out of SMBus mode 432 * so ensure that the MAC is also out of SMBus mode 433 */ 434 mac_reg = er32(CTRL_EXT); 435 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 436 ew32(CTRL_EXT, mac_reg); 437 438 if (e1000_phy_is_accessible_pchlan(hw)) 439 break; 440 441 ret_val = -E1000_ERR_PHY; 442 } 443 break; 444 default: 445 break; 446 } 447 448 e1000e_enable_phy_retry(hw); 449 450 hw->phy.ops.release(hw); 451 if (!ret_val) { 452 453 /* Check to see if able to reset PHY. Print error if not */ 454 if (hw->phy.ops.check_reset_block(hw)) { 455 e_err("Reset blocked by ME\n"); 456 goto out; 457 } 458 459 /* Reset the PHY before any access to it. Doing so, ensures 460 * that the PHY is in a known good state before we read/write 461 * PHY registers. The generic reset is sufficient here, 462 * because we haven't determined the PHY type yet. 463 */ 464 ret_val = e1000e_phy_hw_reset_generic(hw); 465 if (ret_val) 466 goto out; 467 468 /* On a successful reset, possibly need to wait for the PHY 469 * to quiesce to an accessible state before returning control 470 * to the calling function. If the PHY does not quiesce, then 471 * return E1000E_BLK_PHY_RESET, as this is the condition that 472 * the PHY is in. 473 */ 474 ret_val = hw->phy.ops.check_reset_block(hw); 475 if (ret_val) { 476 e_err("ME blocked access to PHY after reset\n"); 477 goto out; 478 } 479 480 if (hw->mac.type >= e1000_pch_mtp) { 481 ret_val = hw->phy.ops.acquire(hw); 482 if (ret_val) { 483 e_err("Failed to reconfigure K1 parameters\n"); 484 goto out; 485 } 486 ret_val = e1000_reconfigure_k1_params(hw); 487 hw->phy.ops.release(hw); 488 } 489 } 490 491 out: 492 /* Ungate automatic PHY configuration on non-managed 82579 */ 493 if ((hw->mac.type == e1000_pch2lan) && 494 !(fwsm & E1000_ICH_FWSM_FW_VALID)) { 495 usleep_range(10000, 11000); 496 e1000_gate_hw_phy_config_ich8lan(hw, false); 497 } 498 499 return ret_val; 500 } 501 502 /** 503 * e1000_init_phy_params_pchlan - Initialize PHY function pointers 504 * @hw: pointer to the HW structure 505 * 506 * Initialize family-specific PHY parameters and function pointers. 507 **/ 508 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) 509 { 510 struct e1000_phy_info *phy = &hw->phy; 511 s32 ret_val; 512 513 phy->addr = 1; 514 phy->reset_delay_us = 100; 515 516 phy->ops.set_page = e1000_set_page_igp; 517 phy->ops.read_reg = e1000_read_phy_reg_hv; 518 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked; 519 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv; 520 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan; 521 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan; 522 phy->ops.write_reg = e1000_write_phy_reg_hv; 523 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked; 524 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv; 525 phy->ops.power_up = e1000_power_up_phy_copper; 526 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 527 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 528 529 phy->id = e1000_phy_unknown; 530 531 if (hw->mac.type == e1000_pch_mtp || hw->mac.type == e1000_pch_ptp) { 532 phy->retry_count = 2; 533 e1000e_enable_phy_retry(hw); 534 } 535 536 ret_val = e1000_init_phy_workarounds_pchlan(hw); 537 if (ret_val) 538 return ret_val; 539 540 if (phy->id == e1000_phy_unknown) 541 switch (hw->mac.type) { 542 default: 543 ret_val = e1000e_get_phy_id(hw); 544 if (ret_val) 545 return ret_val; 546 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK)) 547 break; 548 fallthrough; 549 case e1000_pch2lan: 550 case e1000_pch_lpt: 551 case e1000_pch_spt: 552 case e1000_pch_cnp: 553 case e1000_pch_tgp: 554 case e1000_pch_adp: 555 case e1000_pch_mtp: 556 case e1000_pch_lnp: 557 case e1000_pch_ptp: 558 case e1000_pch_nvp: 559 /* In case the PHY needs to be in mdio slow mode, 560 * set slow mode and try to get the PHY id again. 561 */ 562 ret_val = e1000_set_mdio_slow_mode_hv(hw); 563 if (ret_val) 564 return ret_val; 565 ret_val = e1000e_get_phy_id(hw); 566 if (ret_val) 567 return ret_val; 568 break; 569 } 570 phy->type = e1000e_get_phy_type_from_id(phy->id); 571 572 switch (phy->type) { 573 case e1000_phy_82577: 574 case e1000_phy_82579: 575 case e1000_phy_i217: 576 phy->ops.check_polarity = e1000_check_polarity_82577; 577 phy->ops.force_speed_duplex = 578 e1000_phy_force_speed_duplex_82577; 579 phy->ops.get_cable_length = e1000_get_cable_length_82577; 580 phy->ops.get_info = e1000_get_phy_info_82577; 581 phy->ops.commit = e1000e_phy_sw_reset; 582 break; 583 case e1000_phy_82578: 584 phy->ops.check_polarity = e1000_check_polarity_m88; 585 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; 586 phy->ops.get_cable_length = e1000e_get_cable_length_m88; 587 phy->ops.get_info = e1000e_get_phy_info_m88; 588 break; 589 default: 590 ret_val = -E1000_ERR_PHY; 591 break; 592 } 593 594 return ret_val; 595 } 596 597 /** 598 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers 599 * @hw: pointer to the HW structure 600 * 601 * Initialize family-specific PHY parameters and function pointers. 602 **/ 603 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) 604 { 605 struct e1000_phy_info *phy = &hw->phy; 606 s32 ret_val; 607 u16 i = 0; 608 609 phy->addr = 1; 610 phy->reset_delay_us = 100; 611 612 phy->ops.power_up = e1000_power_up_phy_copper; 613 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 614 615 /* We may need to do this twice - once for IGP and if that fails, 616 * we'll set BM func pointers and try again 617 */ 618 ret_val = e1000e_determine_phy_address(hw); 619 if (ret_val) { 620 phy->ops.write_reg = e1000e_write_phy_reg_bm; 621 phy->ops.read_reg = e1000e_read_phy_reg_bm; 622 ret_val = e1000e_determine_phy_address(hw); 623 if (ret_val) { 624 e_dbg("Cannot determine PHY addr. Erroring out\n"); 625 return ret_val; 626 } 627 } 628 629 phy->id = 0; 630 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) && 631 (i++ < 100)) { 632 usleep_range(1000, 1100); 633 ret_val = e1000e_get_phy_id(hw); 634 if (ret_val) 635 return ret_val; 636 } 637 638 /* Verify phy id */ 639 switch (phy->id) { 640 case IGP03E1000_E_PHY_ID: 641 phy->type = e1000_phy_igp_3; 642 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 643 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked; 644 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked; 645 phy->ops.get_info = e1000e_get_phy_info_igp; 646 phy->ops.check_polarity = e1000_check_polarity_igp; 647 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp; 648 break; 649 case IFE_E_PHY_ID: 650 case IFE_PLUS_E_PHY_ID: 651 case IFE_C_E_PHY_ID: 652 phy->type = e1000_phy_ife; 653 phy->autoneg_mask = E1000_ALL_NOT_GIG; 654 phy->ops.get_info = e1000_get_phy_info_ife; 655 phy->ops.check_polarity = e1000_check_polarity_ife; 656 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; 657 break; 658 case BME1000_E_PHY_ID: 659 phy->type = e1000_phy_bm; 660 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 661 phy->ops.read_reg = e1000e_read_phy_reg_bm; 662 phy->ops.write_reg = e1000e_write_phy_reg_bm; 663 phy->ops.commit = e1000e_phy_sw_reset; 664 phy->ops.get_info = e1000e_get_phy_info_m88; 665 phy->ops.check_polarity = e1000_check_polarity_m88; 666 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; 667 break; 668 default: 669 return -E1000_ERR_PHY; 670 } 671 672 return 0; 673 } 674 675 /** 676 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers 677 * @hw: pointer to the HW structure 678 * 679 * Initialize family-specific NVM parameters and function 680 * pointers. 681 **/ 682 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) 683 { 684 struct e1000_nvm_info *nvm = &hw->nvm; 685 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 686 u32 gfpreg, sector_base_addr, sector_end_addr; 687 u16 i; 688 u32 nvm_size; 689 690 nvm->type = e1000_nvm_flash_sw; 691 692 if (hw->mac.type >= e1000_pch_spt) { 693 /* in SPT, gfpreg doesn't exist. NVM size is taken from the 694 * STRAP register. This is because in SPT the GbE Flash region 695 * is no longer accessed through the flash registers. Instead, 696 * the mechanism has changed, and the Flash region access 697 * registers are now implemented in GbE memory space. 698 */ 699 nvm->flash_base_addr = 0; 700 nvm_size = (((er32(STRAP) >> 1) & 0x1F) + 1) 701 * NVM_SIZE_MULTIPLIER; 702 nvm->flash_bank_size = nvm_size / 2; 703 /* Adjust to word count */ 704 nvm->flash_bank_size /= sizeof(u16); 705 /* Set the base address for flash register access */ 706 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR; 707 } else { 708 /* Can't read flash registers if register set isn't mapped. */ 709 if (!hw->flash_address) { 710 e_dbg("ERROR: Flash registers not mapped\n"); 711 return -E1000_ERR_CONFIG; 712 } 713 714 gfpreg = er32flash(ICH_FLASH_GFPREG); 715 716 /* sector_X_addr is a "sector"-aligned address (4096 bytes) 717 * Add 1 to sector_end_addr since this sector is included in 718 * the overall size. 719 */ 720 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; 721 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; 722 723 /* flash_base_addr is byte-aligned */ 724 nvm->flash_base_addr = sector_base_addr 725 << FLASH_SECTOR_ADDR_SHIFT; 726 727 /* find total size of the NVM, then cut in half since the total 728 * size represents two separate NVM banks. 729 */ 730 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr) 731 << FLASH_SECTOR_ADDR_SHIFT); 732 nvm->flash_bank_size /= 2; 733 /* Adjust to word count */ 734 nvm->flash_bank_size /= sizeof(u16); 735 } 736 737 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS; 738 739 /* Clear shadow ram */ 740 for (i = 0; i < nvm->word_size; i++) { 741 dev_spec->shadow_ram[i].modified = false; 742 dev_spec->shadow_ram[i].value = 0xFFFF; 743 } 744 745 return 0; 746 } 747 748 /** 749 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers 750 * @hw: pointer to the HW structure 751 * 752 * Initialize family-specific MAC parameters and function 753 * pointers. 754 **/ 755 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) 756 { 757 struct e1000_mac_info *mac = &hw->mac; 758 759 /* Set media type function pointer */ 760 hw->phy.media_type = e1000_media_type_copper; 761 762 /* Set mta register count */ 763 mac->mta_reg_count = 32; 764 /* Set rar entry count */ 765 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; 766 if (mac->type == e1000_ich8lan) 767 mac->rar_entry_count--; 768 /* FWSM register */ 769 mac->has_fwsm = true; 770 /* ARC subsystem not supported */ 771 mac->arc_subsystem_valid = false; 772 /* Adaptive IFS supported */ 773 mac->adaptive_ifs = true; 774 775 /* LED and other operations */ 776 switch (mac->type) { 777 case e1000_ich8lan: 778 case e1000_ich9lan: 779 case e1000_ich10lan: 780 /* check management mode */ 781 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan; 782 /* ID LED init */ 783 mac->ops.id_led_init = e1000e_id_led_init_generic; 784 /* blink LED */ 785 mac->ops.blink_led = e1000e_blink_led_generic; 786 /* setup LED */ 787 mac->ops.setup_led = e1000e_setup_led_generic; 788 /* cleanup LED */ 789 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; 790 /* turn on/off LED */ 791 mac->ops.led_on = e1000_led_on_ich8lan; 792 mac->ops.led_off = e1000_led_off_ich8lan; 793 break; 794 case e1000_pch2lan: 795 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES; 796 mac->ops.rar_set = e1000_rar_set_pch2lan; 797 fallthrough; 798 case e1000_pch_lpt: 799 case e1000_pch_spt: 800 case e1000_pch_cnp: 801 case e1000_pch_tgp: 802 case e1000_pch_adp: 803 case e1000_pch_mtp: 804 case e1000_pch_lnp: 805 case e1000_pch_ptp: 806 case e1000_pch_nvp: 807 case e1000_pchlan: 808 /* check management mode */ 809 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan; 810 /* ID LED init */ 811 mac->ops.id_led_init = e1000_id_led_init_pchlan; 812 /* setup LED */ 813 mac->ops.setup_led = e1000_setup_led_pchlan; 814 /* cleanup LED */ 815 mac->ops.cleanup_led = e1000_cleanup_led_pchlan; 816 /* turn on/off LED */ 817 mac->ops.led_on = e1000_led_on_pchlan; 818 mac->ops.led_off = e1000_led_off_pchlan; 819 break; 820 default: 821 break; 822 } 823 824 if (mac->type >= e1000_pch_lpt) { 825 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES; 826 mac->ops.rar_set = e1000_rar_set_pch_lpt; 827 mac->ops.setup_physical_interface = 828 e1000_setup_copper_link_pch_lpt; 829 mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt; 830 } 831 832 /* Enable PCS Lock-loss workaround for ICH8 */ 833 if (mac->type == e1000_ich8lan) 834 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true); 835 836 return 0; 837 } 838 839 /** 840 * __e1000_access_emi_reg_locked - Read/write EMI register 841 * @hw: pointer to the HW structure 842 * @address: EMI address to program 843 * @data: pointer to value to read/write from/to the EMI address 844 * @read: boolean flag to indicate read or write 845 * 846 * This helper function assumes the SW/FW/HW Semaphore is already acquired. 847 **/ 848 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address, 849 u16 *data, bool read) 850 { 851 s32 ret_val; 852 853 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address); 854 if (ret_val) 855 return ret_val; 856 857 if (read) 858 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data); 859 else 860 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data); 861 862 return ret_val; 863 } 864 865 /** 866 * e1000_read_emi_reg_locked - Read Extended Management Interface register 867 * @hw: pointer to the HW structure 868 * @addr: EMI address to program 869 * @data: value to be read from the EMI address 870 * 871 * Assumes the SW/FW/HW Semaphore is already acquired. 872 **/ 873 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data) 874 { 875 return __e1000_access_emi_reg_locked(hw, addr, data, true); 876 } 877 878 /** 879 * e1000_write_emi_reg_locked - Write Extended Management Interface register 880 * @hw: pointer to the HW structure 881 * @addr: EMI address to program 882 * @data: value to be written to the EMI address 883 * 884 * Assumes the SW/FW/HW Semaphore is already acquired. 885 **/ 886 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data) 887 { 888 return __e1000_access_emi_reg_locked(hw, addr, &data, false); 889 } 890 891 /** 892 * e1000_set_eee_pchlan - Enable/disable EEE support 893 * @hw: pointer to the HW structure 894 * 895 * Enable/disable EEE based on setting in dev_spec structure, the duplex of 896 * the link and the EEE capabilities of the link partner. The LPI Control 897 * register bits will remain set only if/when link is up. 898 * 899 * EEE LPI must not be asserted earlier than one second after link is up. 900 * On 82579, EEE LPI should not be enabled until such time otherwise there 901 * can be link issues with some switches. Other devices can have EEE LPI 902 * enabled immediately upon link up since they have a timer in hardware which 903 * prevents LPI from being asserted too early. 904 **/ 905 s32 e1000_set_eee_pchlan(struct e1000_hw *hw) 906 { 907 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 908 s32 ret_val; 909 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data; 910 911 switch (hw->phy.type) { 912 case e1000_phy_82579: 913 lpa = I82579_EEE_LP_ABILITY; 914 pcs_status = I82579_EEE_PCS_STATUS; 915 adv_addr = I82579_EEE_ADVERTISEMENT; 916 break; 917 case e1000_phy_i217: 918 lpa = I217_EEE_LP_ABILITY; 919 pcs_status = I217_EEE_PCS_STATUS; 920 adv_addr = I217_EEE_ADVERTISEMENT; 921 break; 922 default: 923 return 0; 924 } 925 926 ret_val = hw->phy.ops.acquire(hw); 927 if (ret_val) 928 return ret_val; 929 930 ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl); 931 if (ret_val) 932 goto release; 933 934 /* Clear bits that enable EEE in various speeds */ 935 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK; 936 937 /* Enable EEE if not disabled by user */ 938 if (!dev_spec->eee_disable) { 939 /* Save off link partner's EEE ability */ 940 ret_val = e1000_read_emi_reg_locked(hw, lpa, 941 &dev_spec->eee_lp_ability); 942 if (ret_val) 943 goto release; 944 945 /* Read EEE advertisement */ 946 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv); 947 if (ret_val) 948 goto release; 949 950 /* Enable EEE only for speeds in which the link partner is 951 * EEE capable and for which we advertise EEE. 952 */ 953 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED) 954 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE; 955 956 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) { 957 e1e_rphy_locked(hw, MII_LPA, &data); 958 if (data & LPA_100FULL) 959 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE; 960 else 961 /* EEE is not supported in 100Half, so ignore 962 * partner's EEE in 100 ability if full-duplex 963 * is not advertised. 964 */ 965 dev_spec->eee_lp_ability &= 966 ~I82579_EEE_100_SUPPORTED; 967 } 968 } 969 970 if (hw->phy.type == e1000_phy_82579) { 971 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, 972 &data); 973 if (ret_val) 974 goto release; 975 976 data &= ~I82579_LPI_100_PLL_SHUT; 977 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, 978 data); 979 } 980 981 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */ 982 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data); 983 if (ret_val) 984 goto release; 985 986 ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl); 987 release: 988 hw->phy.ops.release(hw); 989 990 return ret_val; 991 } 992 993 /** 994 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP 995 * @hw: pointer to the HW structure 996 * @link: link up bool flag 997 * 998 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications 999 * preventing further DMA write requests. Workaround the issue by disabling 1000 * the de-assertion of the clock request when in 1Gpbs mode. 1001 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link 1002 * speeds in order to avoid Tx hangs. 1003 **/ 1004 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link) 1005 { 1006 u32 fextnvm6 = er32(FEXTNVM6); 1007 u32 status = er32(STATUS); 1008 s32 ret_val = 0; 1009 u16 reg; 1010 1011 if (link && (status & E1000_STATUS_SPEED_1000)) { 1012 ret_val = hw->phy.ops.acquire(hw); 1013 if (ret_val) 1014 return ret_val; 1015 1016 ret_val = 1017 e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 1018 ®); 1019 if (ret_val) 1020 goto release; 1021 1022 ret_val = 1023 e1000e_write_kmrn_reg_locked(hw, 1024 E1000_KMRNCTRLSTA_K1_CONFIG, 1025 reg & 1026 ~E1000_KMRNCTRLSTA_K1_ENABLE); 1027 if (ret_val) 1028 goto release; 1029 1030 usleep_range(10, 20); 1031 1032 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK); 1033 1034 ret_val = 1035 e1000e_write_kmrn_reg_locked(hw, 1036 E1000_KMRNCTRLSTA_K1_CONFIG, 1037 reg); 1038 release: 1039 hw->phy.ops.release(hw); 1040 } else { 1041 /* clear FEXTNVM6 bit 8 on link down or 10/100 */ 1042 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK; 1043 1044 if ((hw->phy.revision > 5) || !link || 1045 ((status & E1000_STATUS_SPEED_100) && 1046 (status & E1000_STATUS_FD))) 1047 goto update_fextnvm6; 1048 1049 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, ®); 1050 if (ret_val) 1051 return ret_val; 1052 1053 /* Clear link status transmit timeout */ 1054 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK; 1055 1056 if (status & E1000_STATUS_SPEED_100) { 1057 /* Set inband Tx timeout to 5x10us for 100Half */ 1058 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 1059 1060 /* Do not extend the K1 entry latency for 100Half */ 1061 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 1062 } else { 1063 /* Set inband Tx timeout to 50x10us for 10Full/Half */ 1064 reg |= 50 << 1065 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 1066 1067 /* Extend the K1 entry latency for 10 Mbps */ 1068 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 1069 } 1070 1071 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg); 1072 if (ret_val) 1073 return ret_val; 1074 1075 update_fextnvm6: 1076 ew32(FEXTNVM6, fextnvm6); 1077 } 1078 1079 return ret_val; 1080 } 1081 1082 /** 1083 * e1000_platform_pm_pch_lpt - Set platform power management values 1084 * @hw: pointer to the HW structure 1085 * @link: bool indicating link status 1086 * 1087 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like" 1088 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed 1089 * when link is up (which must not exceed the maximum latency supported 1090 * by the platform), otherwise specify there is no LTR requirement. 1091 * Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop 1092 * latencies in the LTR Extended Capability Structure in the PCIe Extended 1093 * Capability register set, on this device LTR is set by writing the 1094 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and 1095 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB) 1096 * message to the PMC. 1097 **/ 1098 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link) 1099 { 1100 u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) | 1101 link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND; 1102 u32 max_ltr_enc_d = 0; /* maximum LTR decoded by platform */ 1103 u32 lat_enc_d = 0; /* latency decoded */ 1104 u16 lat_enc = 0; /* latency encoded */ 1105 1106 if (link) { 1107 u16 speed, duplex, scale = 0; 1108 u16 max_snoop, max_nosnoop; 1109 u16 max_ltr_enc; /* max LTR latency encoded */ 1110 u64 value; 1111 u32 rxa; 1112 1113 if (!hw->adapter->max_frame_size) { 1114 e_dbg("max_frame_size not set.\n"); 1115 return -E1000_ERR_CONFIG; 1116 } 1117 1118 hw->mac.ops.get_link_up_info(hw, &speed, &duplex); 1119 if (!speed) { 1120 e_dbg("Speed not set.\n"); 1121 return -E1000_ERR_CONFIG; 1122 } 1123 1124 /* Rx Packet Buffer Allocation size (KB) */ 1125 rxa = er32(PBA) & E1000_PBA_RXA_MASK; 1126 1127 /* Determine the maximum latency tolerated by the device. 1128 * 1129 * Per the PCIe spec, the tolerated latencies are encoded as 1130 * a 3-bit encoded scale (only 0-5 are valid) multiplied by 1131 * a 10-bit value (0-1023) to provide a range from 1 ns to 1132 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns, 1133 * 1=2^5ns, 2=2^10ns,...5=2^25ns. 1134 */ 1135 rxa *= 512; 1136 value = (rxa > hw->adapter->max_frame_size) ? 1137 (rxa - hw->adapter->max_frame_size) * (16000 / speed) : 1138 0; 1139 1140 while (value > PCI_LTR_VALUE_MASK) { 1141 scale++; 1142 value = DIV_ROUND_UP(value, BIT(5)); 1143 } 1144 if (scale > E1000_LTRV_SCALE_MAX) { 1145 e_dbg("Invalid LTR latency scale %d\n", scale); 1146 return -E1000_ERR_CONFIG; 1147 } 1148 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value); 1149 1150 /* Determine the maximum latency tolerated by the platform */ 1151 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT, 1152 &max_snoop); 1153 pci_read_config_word(hw->adapter->pdev, 1154 E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop); 1155 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop); 1156 1157 lat_enc_d = (lat_enc & E1000_LTRV_VALUE_MASK) * 1158 (1U << (E1000_LTRV_SCALE_FACTOR * 1159 FIELD_GET(E1000_LTRV_SCALE_MASK, lat_enc))); 1160 1161 max_ltr_enc_d = (max_ltr_enc & E1000_LTRV_VALUE_MASK) * 1162 (1U << (E1000_LTRV_SCALE_FACTOR * 1163 FIELD_GET(E1000_LTRV_SCALE_MASK, max_ltr_enc))); 1164 1165 if (lat_enc_d > max_ltr_enc_d) 1166 lat_enc = max_ltr_enc; 1167 } 1168 1169 /* Set Snoop and No-Snoop latencies the same */ 1170 reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT); 1171 ew32(LTRV, reg); 1172 1173 return 0; 1174 } 1175 1176 /** 1177 * e1000e_force_smbus - Force interfaces to transition to SMBUS mode. 1178 * @hw: pointer to the HW structure 1179 * 1180 * Force the MAC and the PHY to SMBUS mode. Assumes semaphore already 1181 * acquired. 1182 * 1183 * Return: 0 on success, negative errno on failure. 1184 **/ 1185 static s32 e1000e_force_smbus(struct e1000_hw *hw) 1186 { 1187 u16 smb_ctrl = 0; 1188 u32 ctrl_ext; 1189 s32 ret_val; 1190 1191 /* Switching PHY interface always returns MDI error 1192 * so disable retry mechanism to avoid wasting time 1193 */ 1194 e1000e_disable_phy_retry(hw); 1195 1196 /* Force SMBus mode in the PHY */ 1197 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &smb_ctrl); 1198 if (ret_val) { 1199 e1000e_enable_phy_retry(hw); 1200 return ret_val; 1201 } 1202 1203 smb_ctrl |= CV_SMB_CTRL_FORCE_SMBUS; 1204 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, smb_ctrl); 1205 1206 e1000e_enable_phy_retry(hw); 1207 1208 /* Force SMBus mode in the MAC */ 1209 ctrl_ext = er32(CTRL_EXT); 1210 ctrl_ext |= E1000_CTRL_EXT_FORCE_SMBUS; 1211 ew32(CTRL_EXT, ctrl_ext); 1212 1213 return 0; 1214 } 1215 1216 /** 1217 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP 1218 * @hw: pointer to the HW structure 1219 * @to_sx: boolean indicating a system power state transition to Sx 1220 * 1221 * When link is down, configure ULP mode to significantly reduce the power 1222 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the 1223 * ME firmware to start the ULP configuration. If not on an ME enabled 1224 * system, configure the ULP mode by software. 1225 */ 1226 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx) 1227 { 1228 u32 mac_reg; 1229 s32 ret_val = 0; 1230 u16 phy_reg; 1231 u16 oem_reg = 0; 1232 1233 if ((hw->mac.type < e1000_pch_lpt) || 1234 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) || 1235 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) || 1236 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) || 1237 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) || 1238 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on)) 1239 return 0; 1240 1241 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) { 1242 /* Request ME configure ULP mode in the PHY */ 1243 mac_reg = er32(H2ME); 1244 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS; 1245 ew32(H2ME, mac_reg); 1246 1247 goto out; 1248 } 1249 1250 if (!to_sx) { 1251 int i = 0; 1252 1253 /* Poll up to 5 seconds for Cable Disconnected indication */ 1254 while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) { 1255 /* Bail if link is re-acquired */ 1256 if (er32(STATUS) & E1000_STATUS_LU) 1257 return -E1000_ERR_PHY; 1258 1259 if (i++ == 100) 1260 break; 1261 1262 msleep(50); 1263 } 1264 e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n", 1265 (er32(FEXT) & 1266 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50); 1267 } 1268 1269 ret_val = hw->phy.ops.acquire(hw); 1270 if (ret_val) 1271 goto out; 1272 1273 ret_val = e1000e_force_smbus(hw); 1274 if (ret_val) { 1275 e_dbg("Failed to force SMBUS: %d\n", ret_val); 1276 goto release; 1277 } 1278 1279 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable 1280 * LPLU and disable Gig speed when entering ULP 1281 */ 1282 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) { 1283 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS, 1284 &oem_reg); 1285 if (ret_val) 1286 goto release; 1287 1288 phy_reg = oem_reg; 1289 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS; 1290 1291 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, 1292 phy_reg); 1293 1294 if (ret_val) 1295 goto release; 1296 } 1297 1298 /* Set Inband ULP Exit, Reset to SMBus mode and 1299 * Disable SMBus Release on PERST# in PHY 1300 */ 1301 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); 1302 if (ret_val) 1303 goto release; 1304 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS | 1305 I218_ULP_CONFIG1_DISABLE_SMB_PERST); 1306 if (to_sx) { 1307 if (er32(WUFC) & E1000_WUFC_LNKC) 1308 phy_reg |= I218_ULP_CONFIG1_WOL_HOST; 1309 else 1310 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST; 1311 1312 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP; 1313 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT; 1314 } else { 1315 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT; 1316 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP; 1317 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST; 1318 } 1319 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1320 1321 /* Set Disable SMBus Release on PERST# in MAC */ 1322 mac_reg = er32(FEXTNVM7); 1323 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST; 1324 ew32(FEXTNVM7, mac_reg); 1325 1326 /* Commit ULP changes in PHY by starting auto ULP configuration */ 1327 phy_reg |= I218_ULP_CONFIG1_START; 1328 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1329 1330 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) && 1331 to_sx && (er32(STATUS) & E1000_STATUS_LU)) { 1332 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, 1333 oem_reg); 1334 if (ret_val) 1335 goto release; 1336 } 1337 1338 release: 1339 hw->phy.ops.release(hw); 1340 out: 1341 if (ret_val) 1342 e_dbg("Error in ULP enable flow: %d\n", ret_val); 1343 else 1344 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on; 1345 1346 return ret_val; 1347 } 1348 1349 /** 1350 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP 1351 * @hw: pointer to the HW structure 1352 * @force: boolean indicating whether or not to force disabling ULP 1353 * 1354 * Un-configure ULP mode when link is up, the system is transitioned from 1355 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled 1356 * system, poll for an indication from ME that ULP has been un-configured. 1357 * If not on an ME enabled system, un-configure the ULP mode by software. 1358 * 1359 * During nominal operation, this function is called when link is acquired 1360 * to disable ULP mode (force=false); otherwise, for example when unloading 1361 * the driver or during Sx->S0 transitions, this is called with force=true 1362 * to forcibly disable ULP. 1363 */ 1364 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force) 1365 { 1366 s32 ret_val = 0; 1367 u32 mac_reg; 1368 u16 phy_reg; 1369 int i = 0; 1370 1371 if ((hw->mac.type < e1000_pch_lpt) || 1372 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) || 1373 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) || 1374 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) || 1375 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) || 1376 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off)) 1377 return 0; 1378 1379 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) { 1380 struct e1000_adapter *adapter = hw->adapter; 1381 bool firmware_bug = false; 1382 1383 if (force) { 1384 /* Request ME un-configure ULP mode in the PHY */ 1385 mac_reg = er32(H2ME); 1386 mac_reg &= ~E1000_H2ME_ULP; 1387 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS; 1388 ew32(H2ME, mac_reg); 1389 } 1390 1391 /* Poll up to 2.5 seconds for ME to clear ULP_CFG_DONE. 1392 * If this takes more than 1 second, show a warning indicating a 1393 * firmware bug 1394 */ 1395 while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) { 1396 if (i++ == 250) { 1397 ret_val = -E1000_ERR_PHY; 1398 goto out; 1399 } 1400 if (i > 100 && !firmware_bug) 1401 firmware_bug = true; 1402 1403 usleep_range(10000, 11000); 1404 } 1405 if (firmware_bug) 1406 e_warn("ULP_CONFIG_DONE took %d msec. This is a firmware bug\n", 1407 i * 10); 1408 else 1409 e_dbg("ULP_CONFIG_DONE cleared after %d msec\n", 1410 i * 10); 1411 1412 if (force) { 1413 mac_reg = er32(H2ME); 1414 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS; 1415 ew32(H2ME, mac_reg); 1416 } else { 1417 /* Clear H2ME.ULP after ME ULP configuration */ 1418 mac_reg = er32(H2ME); 1419 mac_reg &= ~E1000_H2ME_ULP; 1420 ew32(H2ME, mac_reg); 1421 } 1422 1423 goto out; 1424 } 1425 1426 ret_val = hw->phy.ops.acquire(hw); 1427 if (ret_val) 1428 goto out; 1429 1430 if (force) 1431 /* Toggle LANPHYPC Value bit */ 1432 e1000_toggle_lanphypc_pch_lpt(hw); 1433 1434 /* Switching PHY interface always returns MDI error 1435 * so disable retry mechanism to avoid wasting time 1436 */ 1437 e1000e_disable_phy_retry(hw); 1438 1439 /* Unforce SMBus mode in PHY */ 1440 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg); 1441 if (ret_val) { 1442 /* The MAC might be in PCIe mode, so temporarily force to 1443 * SMBus mode in order to access the PHY. 1444 */ 1445 mac_reg = er32(CTRL_EXT); 1446 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 1447 ew32(CTRL_EXT, mac_reg); 1448 1449 msleep(50); 1450 1451 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, 1452 &phy_reg); 1453 if (ret_val) 1454 goto release; 1455 } 1456 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 1457 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg); 1458 1459 e1000e_enable_phy_retry(hw); 1460 1461 /* Unforce SMBus mode in MAC */ 1462 mac_reg = er32(CTRL_EXT); 1463 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 1464 ew32(CTRL_EXT, mac_reg); 1465 1466 /* When ULP mode was previously entered, K1 was disabled by the 1467 * hardware. Re-Enable K1 in the PHY when exiting ULP. 1468 */ 1469 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg); 1470 if (ret_val) 1471 goto release; 1472 phy_reg |= HV_PM_CTRL_K1_ENABLE; 1473 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg); 1474 1475 /* Clear ULP enabled configuration */ 1476 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); 1477 if (ret_val) 1478 goto release; 1479 phy_reg &= ~(I218_ULP_CONFIG1_IND | 1480 I218_ULP_CONFIG1_STICKY_ULP | 1481 I218_ULP_CONFIG1_RESET_TO_SMBUS | 1482 I218_ULP_CONFIG1_WOL_HOST | 1483 I218_ULP_CONFIG1_INBAND_EXIT | 1484 I218_ULP_CONFIG1_EN_ULP_LANPHYPC | 1485 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST | 1486 I218_ULP_CONFIG1_DISABLE_SMB_PERST); 1487 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1488 1489 /* Commit ULP changes by starting auto ULP configuration */ 1490 phy_reg |= I218_ULP_CONFIG1_START; 1491 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1492 1493 /* Clear Disable SMBus Release on PERST# in MAC */ 1494 mac_reg = er32(FEXTNVM7); 1495 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST; 1496 ew32(FEXTNVM7, mac_reg); 1497 1498 release: 1499 hw->phy.ops.release(hw); 1500 if (force) { 1501 e1000_phy_hw_reset(hw); 1502 msleep(50); 1503 } 1504 out: 1505 if (ret_val) 1506 e_dbg("Error in ULP disable flow: %d\n", ret_val); 1507 else 1508 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off; 1509 1510 return ret_val; 1511 } 1512 1513 /** 1514 * e1000_check_for_copper_link_ich8lan - Check for link (Copper) 1515 * @hw: pointer to the HW structure 1516 * 1517 * Checks to see of the link status of the hardware has changed. If a 1518 * change in link status has been detected, then we read the PHY registers 1519 * to get the current speed/duplex if link exists. 1520 **/ 1521 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) 1522 { 1523 struct e1000_mac_info *mac = &hw->mac; 1524 s32 ret_val, tipg_reg = 0; 1525 u16 emi_addr, emi_val = 0; 1526 bool link; 1527 u16 phy_reg; 1528 1529 /* We only want to go out to the PHY registers to see if Auto-Neg 1530 * has completed and/or if our link status has changed. The 1531 * get_link_status flag is set upon receiving a Link Status 1532 * Change or Rx Sequence Error interrupt. 1533 */ 1534 if (!mac->get_link_status) 1535 return 0; 1536 mac->get_link_status = false; 1537 1538 /* First we want to see if the MII Status Register reports 1539 * link. If so, then we want to get the current speed/duplex 1540 * of the PHY. 1541 */ 1542 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 1543 if (ret_val) 1544 goto out; 1545 1546 if (hw->mac.type == e1000_pchlan) { 1547 ret_val = e1000_k1_gig_workaround_hv(hw, link); 1548 if (ret_val) 1549 goto out; 1550 } 1551 1552 /* When connected at 10Mbps half-duplex, some parts are excessively 1553 * aggressive resulting in many collisions. To avoid this, increase 1554 * the IPG and reduce Rx latency in the PHY. 1555 */ 1556 if ((hw->mac.type >= e1000_pch2lan) && link) { 1557 u16 speed, duplex; 1558 1559 e1000e_get_speed_and_duplex_copper(hw, &speed, &duplex); 1560 tipg_reg = er32(TIPG); 1561 tipg_reg &= ~E1000_TIPG_IPGT_MASK; 1562 1563 if (duplex == HALF_DUPLEX && speed == SPEED_10) { 1564 tipg_reg |= 0xFF; 1565 /* Reduce Rx latency in analog PHY */ 1566 emi_val = 0; 1567 } else if (hw->mac.type >= e1000_pch_spt && 1568 duplex == FULL_DUPLEX && speed != SPEED_1000) { 1569 tipg_reg |= 0xC; 1570 emi_val = 1; 1571 } else { 1572 1573 /* Roll back the default values */ 1574 tipg_reg |= 0x08; 1575 emi_val = 1; 1576 } 1577 1578 ew32(TIPG, tipg_reg); 1579 1580 ret_val = hw->phy.ops.acquire(hw); 1581 if (ret_val) 1582 goto out; 1583 1584 if (hw->mac.type == e1000_pch2lan) 1585 emi_addr = I82579_RX_CONFIG; 1586 else 1587 emi_addr = I217_RX_CONFIG; 1588 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val); 1589 1590 if (hw->mac.type >= e1000_pch_lpt) { 1591 u16 phy_reg; 1592 1593 e1e_rphy_locked(hw, I217_PLL_CLOCK_GATE_REG, &phy_reg); 1594 phy_reg &= ~I217_PLL_CLOCK_GATE_MASK; 1595 if (speed == SPEED_100 || speed == SPEED_10) 1596 phy_reg |= 0x3E8; 1597 else if (hw->mac.type == e1000_pch_mtp || 1598 hw->mac.type == e1000_pch_ptp) 1599 phy_reg |= 0x1D5; 1600 else 1601 phy_reg |= 0xFA; 1602 e1e_wphy_locked(hw, I217_PLL_CLOCK_GATE_REG, phy_reg); 1603 1604 if (speed == SPEED_1000) { 1605 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL, 1606 &phy_reg); 1607 1608 phy_reg |= HV_PM_CTRL_K1_CLK_REQ; 1609 1610 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL, 1611 phy_reg); 1612 } 1613 } 1614 hw->phy.ops.release(hw); 1615 1616 if (ret_val) 1617 goto out; 1618 1619 if (hw->mac.type >= e1000_pch_spt) { 1620 u16 data; 1621 u16 ptr_gap; 1622 1623 if (speed == SPEED_1000) { 1624 ret_val = hw->phy.ops.acquire(hw); 1625 if (ret_val) 1626 goto out; 1627 1628 ret_val = e1e_rphy_locked(hw, 1629 PHY_REG(776, 20), 1630 &data); 1631 if (ret_val) { 1632 hw->phy.ops.release(hw); 1633 goto out; 1634 } 1635 1636 ptr_gap = (data & (0x3FF << 2)) >> 2; 1637 if (ptr_gap < 0x18) { 1638 data &= ~(0x3FF << 2); 1639 data |= (0x18 << 2); 1640 ret_val = 1641 e1e_wphy_locked(hw, 1642 PHY_REG(776, 20), 1643 data); 1644 } 1645 hw->phy.ops.release(hw); 1646 if (ret_val) 1647 goto out; 1648 } else { 1649 ret_val = hw->phy.ops.acquire(hw); 1650 if (ret_val) 1651 goto out; 1652 1653 ret_val = e1e_wphy_locked(hw, 1654 PHY_REG(776, 20), 1655 0xC023); 1656 hw->phy.ops.release(hw); 1657 if (ret_val) 1658 goto out; 1659 1660 } 1661 } 1662 } 1663 1664 /* I217 Packet Loss issue: 1665 * ensure that FEXTNVM4 Beacon Duration is set correctly 1666 * on power up. 1667 * Set the Beacon Duration for I217 to 8 usec 1668 */ 1669 if (hw->mac.type >= e1000_pch_lpt) { 1670 u32 mac_reg; 1671 1672 mac_reg = er32(FEXTNVM4); 1673 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 1674 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC; 1675 ew32(FEXTNVM4, mac_reg); 1676 } 1677 1678 /* Work-around I218 hang issue */ 1679 if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 1680 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) || 1681 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) || 1682 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) { 1683 ret_val = e1000_k1_workaround_lpt_lp(hw, link); 1684 if (ret_val) 1685 goto out; 1686 } 1687 if (hw->mac.type >= e1000_pch_lpt) { 1688 /* Set platform power management values for 1689 * Latency Tolerance Reporting (LTR) 1690 */ 1691 ret_val = e1000_platform_pm_pch_lpt(hw, link); 1692 if (ret_val) 1693 goto out; 1694 } 1695 1696 /* Clear link partner's EEE ability */ 1697 hw->dev_spec.ich8lan.eee_lp_ability = 0; 1698 1699 if (hw->mac.type >= e1000_pch_lpt) { 1700 u32 fextnvm6 = er32(FEXTNVM6); 1701 1702 if (hw->mac.type == e1000_pch_spt) { 1703 /* FEXTNVM6 K1-off workaround - for SPT only */ 1704 u32 pcieanacfg = er32(PCIEANACFG); 1705 1706 if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE) 1707 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE; 1708 else 1709 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE; 1710 } 1711 1712 ew32(FEXTNVM6, fextnvm6); 1713 } 1714 1715 if (!link) 1716 goto out; 1717 1718 switch (hw->mac.type) { 1719 case e1000_pch2lan: 1720 ret_val = e1000_k1_workaround_lv(hw); 1721 if (ret_val) 1722 return ret_val; 1723 fallthrough; 1724 case e1000_pchlan: 1725 if (hw->phy.type == e1000_phy_82578) { 1726 ret_val = e1000_link_stall_workaround_hv(hw); 1727 if (ret_val) 1728 return ret_val; 1729 } 1730 1731 /* Workaround for PCHx parts in half-duplex: 1732 * Set the number of preambles removed from the packet 1733 * when it is passed from the PHY to the MAC to prevent 1734 * the MAC from misinterpreting the packet type. 1735 */ 1736 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg); 1737 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK; 1738 1739 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD) 1740 phy_reg |= BIT(HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT); 1741 1742 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg); 1743 break; 1744 default: 1745 break; 1746 } 1747 1748 /* Check if there was DownShift, must be checked 1749 * immediately after link-up 1750 */ 1751 e1000e_check_downshift(hw); 1752 1753 /* Enable/Disable EEE after link up */ 1754 if (hw->phy.type > e1000_phy_82579) { 1755 ret_val = e1000_set_eee_pchlan(hw); 1756 if (ret_val) 1757 return ret_val; 1758 } 1759 1760 /* If we are forcing speed/duplex, then we simply return since 1761 * we have already determined whether we have link or not. 1762 */ 1763 if (!mac->autoneg) 1764 return -E1000_ERR_CONFIG; 1765 1766 /* Auto-Neg is enabled. Auto Speed Detection takes care 1767 * of MAC speed/duplex configuration. So we only need to 1768 * configure Collision Distance in the MAC. 1769 */ 1770 mac->ops.config_collision_dist(hw); 1771 1772 /* Configure Flow Control now that Auto-Neg has completed. 1773 * First, we need to restore the desired flow control 1774 * settings because we may have had to re-autoneg with a 1775 * different link partner. 1776 */ 1777 ret_val = e1000e_config_fc_after_link_up(hw); 1778 if (ret_val) 1779 e_dbg("Error configuring flow control\n"); 1780 1781 return ret_val; 1782 1783 out: 1784 mac->get_link_status = true; 1785 return ret_val; 1786 } 1787 1788 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter) 1789 { 1790 struct e1000_hw *hw = &adapter->hw; 1791 s32 rc; 1792 1793 rc = e1000_init_mac_params_ich8lan(hw); 1794 if (rc) 1795 return rc; 1796 1797 rc = e1000_init_nvm_params_ich8lan(hw); 1798 if (rc) 1799 return rc; 1800 1801 switch (hw->mac.type) { 1802 case e1000_ich8lan: 1803 case e1000_ich9lan: 1804 case e1000_ich10lan: 1805 rc = e1000_init_phy_params_ich8lan(hw); 1806 break; 1807 case e1000_pchlan: 1808 case e1000_pch2lan: 1809 case e1000_pch_lpt: 1810 case e1000_pch_spt: 1811 case e1000_pch_cnp: 1812 case e1000_pch_tgp: 1813 case e1000_pch_adp: 1814 case e1000_pch_mtp: 1815 case e1000_pch_lnp: 1816 case e1000_pch_ptp: 1817 case e1000_pch_nvp: 1818 rc = e1000_init_phy_params_pchlan(hw); 1819 break; 1820 default: 1821 break; 1822 } 1823 if (rc) 1824 return rc; 1825 1826 /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or 1827 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT). 1828 */ 1829 if ((adapter->hw.phy.type == e1000_phy_ife) || 1830 ((adapter->hw.mac.type >= e1000_pch2lan) && 1831 (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) { 1832 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES; 1833 adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 1834 1835 hw->mac.ops.blink_led = NULL; 1836 } 1837 1838 if ((adapter->hw.mac.type == e1000_ich8lan) && 1839 (adapter->hw.phy.type != e1000_phy_ife)) 1840 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP; 1841 1842 /* Enable workaround for 82579 w/ ME enabled */ 1843 if ((adapter->hw.mac.type == e1000_pch2lan) && 1844 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 1845 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA; 1846 1847 return 0; 1848 } 1849 1850 static DEFINE_MUTEX(nvm_mutex); 1851 1852 /** 1853 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex 1854 * @hw: pointer to the HW structure 1855 * 1856 * Acquires the mutex for performing NVM operations. 1857 **/ 1858 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw) 1859 { 1860 mutex_lock(&nvm_mutex); 1861 1862 return 0; 1863 } 1864 1865 /** 1866 * e1000_release_nvm_ich8lan - Release NVM mutex 1867 * @hw: pointer to the HW structure 1868 * 1869 * Releases the mutex used while performing NVM operations. 1870 **/ 1871 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw) 1872 { 1873 mutex_unlock(&nvm_mutex); 1874 } 1875 1876 /** 1877 * e1000_acquire_swflag_ich8lan - Acquire software control flag 1878 * @hw: pointer to the HW structure 1879 * 1880 * Acquires the software control flag for performing PHY and select 1881 * MAC CSR accesses. 1882 **/ 1883 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) 1884 { 1885 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; 1886 s32 ret_val = 0; 1887 1888 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE, 1889 &hw->adapter->state)) { 1890 e_dbg("contention for Phy access\n"); 1891 return -E1000_ERR_PHY; 1892 } 1893 1894 while (timeout) { 1895 extcnf_ctrl = er32(EXTCNF_CTRL); 1896 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) 1897 break; 1898 1899 mdelay(1); 1900 timeout--; 1901 } 1902 1903 if (!timeout) { 1904 e_dbg("SW has already locked the resource.\n"); 1905 ret_val = -E1000_ERR_CONFIG; 1906 goto out; 1907 } 1908 1909 timeout = SW_FLAG_TIMEOUT; 1910 1911 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 1912 ew32(EXTCNF_CTRL, extcnf_ctrl); 1913 1914 while (timeout) { 1915 extcnf_ctrl = er32(EXTCNF_CTRL); 1916 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 1917 break; 1918 1919 mdelay(1); 1920 timeout--; 1921 } 1922 1923 if (!timeout) { 1924 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n", 1925 er32(FWSM), extcnf_ctrl); 1926 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 1927 ew32(EXTCNF_CTRL, extcnf_ctrl); 1928 ret_val = -E1000_ERR_CONFIG; 1929 goto out; 1930 } 1931 1932 out: 1933 if (ret_val) 1934 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 1935 1936 return ret_val; 1937 } 1938 1939 /** 1940 * e1000_release_swflag_ich8lan - Release software control flag 1941 * @hw: pointer to the HW structure 1942 * 1943 * Releases the software control flag for performing PHY and select 1944 * MAC CSR accesses. 1945 **/ 1946 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) 1947 { 1948 u32 extcnf_ctrl; 1949 1950 extcnf_ctrl = er32(EXTCNF_CTRL); 1951 1952 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) { 1953 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 1954 ew32(EXTCNF_CTRL, extcnf_ctrl); 1955 } else { 1956 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n"); 1957 } 1958 1959 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 1960 } 1961 1962 /** 1963 * e1000_check_mng_mode_ich8lan - Checks management mode 1964 * @hw: pointer to the HW structure 1965 * 1966 * This checks if the adapter has any manageability enabled. 1967 * This is a function pointer entry point only called by read/write 1968 * routines for the PHY and NVM parts. 1969 **/ 1970 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) 1971 { 1972 u32 fwsm; 1973 1974 fwsm = er32(FWSM); 1975 return (fwsm & E1000_ICH_FWSM_FW_VALID) && 1976 ((fwsm & E1000_FWSM_MODE_MASK) == 1977 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 1978 } 1979 1980 /** 1981 * e1000_check_mng_mode_pchlan - Checks management mode 1982 * @hw: pointer to the HW structure 1983 * 1984 * This checks if the adapter has iAMT enabled. 1985 * This is a function pointer entry point only called by read/write 1986 * routines for the PHY and NVM parts. 1987 **/ 1988 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw) 1989 { 1990 u32 fwsm; 1991 1992 fwsm = er32(FWSM); 1993 return (fwsm & E1000_ICH_FWSM_FW_VALID) && 1994 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 1995 } 1996 1997 /** 1998 * e1000_rar_set_pch2lan - Set receive address register 1999 * @hw: pointer to the HW structure 2000 * @addr: pointer to the receive address 2001 * @index: receive address array register 2002 * 2003 * Sets the receive address array register at index to the address passed 2004 * in by addr. For 82579, RAR[0] is the base address register that is to 2005 * contain the MAC address but RAR[1-6] are reserved for manageability (ME). 2006 * Use SHRA[0-3] in place of those reserved for ME. 2007 **/ 2008 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index) 2009 { 2010 u32 rar_low, rar_high; 2011 2012 /* HW expects these in little endian so we reverse the byte order 2013 * from network order (big endian) to little endian 2014 */ 2015 rar_low = ((u32)addr[0] | 2016 ((u32)addr[1] << 8) | 2017 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); 2018 2019 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); 2020 2021 /* If MAC address zero, no need to set the AV bit */ 2022 if (rar_low || rar_high) 2023 rar_high |= E1000_RAH_AV; 2024 2025 if (index == 0) { 2026 ew32(RAL(index), rar_low); 2027 e1e_flush(); 2028 ew32(RAH(index), rar_high); 2029 e1e_flush(); 2030 return 0; 2031 } 2032 2033 /* RAR[1-6] are owned by manageability. Skip those and program the 2034 * next address into the SHRA register array. 2035 */ 2036 if (index < (u32)(hw->mac.rar_entry_count)) { 2037 s32 ret_val; 2038 2039 ret_val = e1000_acquire_swflag_ich8lan(hw); 2040 if (ret_val) 2041 goto out; 2042 2043 ew32(SHRAL(index - 1), rar_low); 2044 e1e_flush(); 2045 ew32(SHRAH(index - 1), rar_high); 2046 e1e_flush(); 2047 2048 e1000_release_swflag_ich8lan(hw); 2049 2050 /* verify the register updates */ 2051 if ((er32(SHRAL(index - 1)) == rar_low) && 2052 (er32(SHRAH(index - 1)) == rar_high)) 2053 return 0; 2054 2055 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n", 2056 (index - 1), er32(FWSM)); 2057 } 2058 2059 out: 2060 e_dbg("Failed to write receive address at index %d\n", index); 2061 return -E1000_ERR_CONFIG; 2062 } 2063 2064 /** 2065 * e1000_rar_get_count_pch_lpt - Get the number of available SHRA 2066 * @hw: pointer to the HW structure 2067 * 2068 * Get the number of available receive registers that the Host can 2069 * program. SHRA[0-10] are the shared receive address registers 2070 * that are shared between the Host and manageability engine (ME). 2071 * ME can reserve any number of addresses and the host needs to be 2072 * able to tell how many available registers it has access to. 2073 **/ 2074 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw) 2075 { 2076 u32 wlock_mac; 2077 u32 num_entries; 2078 2079 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK; 2080 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT; 2081 2082 switch (wlock_mac) { 2083 case 0: 2084 /* All SHRA[0..10] and RAR[0] available */ 2085 num_entries = hw->mac.rar_entry_count; 2086 break; 2087 case 1: 2088 /* Only RAR[0] available */ 2089 num_entries = 1; 2090 break; 2091 default: 2092 /* SHRA[0..(wlock_mac - 1)] available + RAR[0] */ 2093 num_entries = wlock_mac + 1; 2094 break; 2095 } 2096 2097 return num_entries; 2098 } 2099 2100 /** 2101 * e1000_rar_set_pch_lpt - Set receive address registers 2102 * @hw: pointer to the HW structure 2103 * @addr: pointer to the receive address 2104 * @index: receive address array register 2105 * 2106 * Sets the receive address register array at index to the address passed 2107 * in by addr. For LPT, RAR[0] is the base address register that is to 2108 * contain the MAC address. SHRA[0-10] are the shared receive address 2109 * registers that are shared between the Host and manageability engine (ME). 2110 **/ 2111 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index) 2112 { 2113 u32 rar_low, rar_high; 2114 u32 wlock_mac; 2115 2116 /* HW expects these in little endian so we reverse the byte order 2117 * from network order (big endian) to little endian 2118 */ 2119 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) | 2120 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); 2121 2122 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); 2123 2124 /* If MAC address zero, no need to set the AV bit */ 2125 if (rar_low || rar_high) 2126 rar_high |= E1000_RAH_AV; 2127 2128 if (index == 0) { 2129 ew32(RAL(index), rar_low); 2130 e1e_flush(); 2131 ew32(RAH(index), rar_high); 2132 e1e_flush(); 2133 return 0; 2134 } 2135 2136 /* The manageability engine (ME) can lock certain SHRAR registers that 2137 * it is using - those registers are unavailable for use. 2138 */ 2139 if (index < hw->mac.rar_entry_count) { 2140 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK; 2141 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT; 2142 2143 /* Check if all SHRAR registers are locked */ 2144 if (wlock_mac == 1) 2145 goto out; 2146 2147 if ((wlock_mac == 0) || (index <= wlock_mac)) { 2148 s32 ret_val; 2149 2150 ret_val = e1000_acquire_swflag_ich8lan(hw); 2151 2152 if (ret_val) 2153 goto out; 2154 2155 ew32(SHRAL_PCH_LPT(index - 1), rar_low); 2156 e1e_flush(); 2157 ew32(SHRAH_PCH_LPT(index - 1), rar_high); 2158 e1e_flush(); 2159 2160 e1000_release_swflag_ich8lan(hw); 2161 2162 /* verify the register updates */ 2163 if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) && 2164 (er32(SHRAH_PCH_LPT(index - 1)) == rar_high)) 2165 return 0; 2166 } 2167 } 2168 2169 out: 2170 e_dbg("Failed to write receive address at index %d\n", index); 2171 return -E1000_ERR_CONFIG; 2172 } 2173 2174 /** 2175 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked 2176 * @hw: pointer to the HW structure 2177 * 2178 * Checks if firmware is blocking the reset of the PHY. 2179 * This is a function pointer entry point only called by 2180 * reset routines. 2181 **/ 2182 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) 2183 { 2184 bool blocked = false; 2185 int i = 0; 2186 2187 while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) && 2188 (i++ < 30)) 2189 usleep_range(10000, 11000); 2190 return blocked ? E1000_BLK_PHY_RESET : 0; 2191 } 2192 2193 /** 2194 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states 2195 * @hw: pointer to the HW structure 2196 * 2197 * Assumes semaphore already acquired. 2198 * 2199 **/ 2200 static s32 e1000_write_smbus_addr(struct e1000_hw *hw) 2201 { 2202 u16 phy_data; 2203 u32 strap = er32(STRAP); 2204 u32 freq = FIELD_GET(E1000_STRAP_SMT_FREQ_MASK, strap); 2205 s32 ret_val; 2206 2207 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK; 2208 2209 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data); 2210 if (ret_val) 2211 return ret_val; 2212 2213 phy_data &= ~HV_SMB_ADDR_MASK; 2214 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT); 2215 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID; 2216 2217 if (hw->phy.type == e1000_phy_i217) { 2218 /* Restore SMBus frequency */ 2219 if (freq--) { 2220 phy_data &= ~HV_SMB_ADDR_FREQ_MASK; 2221 phy_data |= (freq & BIT(0)) << 2222 HV_SMB_ADDR_FREQ_LOW_SHIFT; 2223 phy_data |= (freq & BIT(1)) << 2224 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1); 2225 } else { 2226 e_dbg("Unsupported SMB frequency in PHY\n"); 2227 } 2228 } 2229 2230 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data); 2231 } 2232 2233 /** 2234 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration 2235 * @hw: pointer to the HW structure 2236 * 2237 * SW should configure the LCD from the NVM extended configuration region 2238 * as a workaround for certain parts. 2239 **/ 2240 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) 2241 { 2242 struct e1000_phy_info *phy = &hw->phy; 2243 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask; 2244 s32 ret_val = 0; 2245 u16 word_addr, reg_data, reg_addr, phy_page = 0; 2246 2247 /* Initialize the PHY from the NVM on ICH platforms. This 2248 * is needed due to an issue where the NVM configuration is 2249 * not properly autoloaded after power transitions. 2250 * Therefore, after each PHY reset, we will load the 2251 * configuration data out of the NVM manually. 2252 */ 2253 switch (hw->mac.type) { 2254 case e1000_ich8lan: 2255 if (phy->type != e1000_phy_igp_3) 2256 return ret_val; 2257 2258 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) || 2259 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) { 2260 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; 2261 break; 2262 } 2263 fallthrough; 2264 case e1000_pchlan: 2265 case e1000_pch2lan: 2266 case e1000_pch_lpt: 2267 case e1000_pch_spt: 2268 case e1000_pch_cnp: 2269 case e1000_pch_tgp: 2270 case e1000_pch_adp: 2271 case e1000_pch_mtp: 2272 case e1000_pch_lnp: 2273 case e1000_pch_ptp: 2274 case e1000_pch_nvp: 2275 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; 2276 break; 2277 default: 2278 return ret_val; 2279 } 2280 2281 ret_val = hw->phy.ops.acquire(hw); 2282 if (ret_val) 2283 return ret_val; 2284 2285 data = er32(FEXTNVM); 2286 if (!(data & sw_cfg_mask)) 2287 goto release; 2288 2289 /* Make sure HW does not configure LCD from PHY 2290 * extended configuration before SW configuration 2291 */ 2292 data = er32(EXTCNF_CTRL); 2293 if ((hw->mac.type < e1000_pch2lan) && 2294 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)) 2295 goto release; 2296 2297 cnf_size = er32(EXTCNF_SIZE); 2298 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; 2299 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; 2300 if (!cnf_size) 2301 goto release; 2302 2303 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; 2304 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; 2305 2306 if (((hw->mac.type == e1000_pchlan) && 2307 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) || 2308 (hw->mac.type > e1000_pchlan)) { 2309 /* HW configures the SMBus address and LEDs when the 2310 * OEM and LCD Write Enable bits are set in the NVM. 2311 * When both NVM bits are cleared, SW will configure 2312 * them instead. 2313 */ 2314 ret_val = e1000_write_smbus_addr(hw); 2315 if (ret_val) 2316 goto release; 2317 2318 data = er32(LEDCTL); 2319 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG, 2320 (u16)data); 2321 if (ret_val) 2322 goto release; 2323 } 2324 2325 /* Configure LCD from extended configuration region. */ 2326 2327 /* cnf_base_addr is in DWORD */ 2328 word_addr = (u16)(cnf_base_addr << 1); 2329 2330 for (i = 0; i < cnf_size; i++) { 2331 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, ®_data); 2332 if (ret_val) 2333 goto release; 2334 2335 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1), 2336 1, ®_addr); 2337 if (ret_val) 2338 goto release; 2339 2340 /* Save off the PHY page for future writes. */ 2341 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { 2342 phy_page = reg_data; 2343 continue; 2344 } 2345 2346 reg_addr &= PHY_REG_MASK; 2347 reg_addr |= phy_page; 2348 2349 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data); 2350 if (ret_val) 2351 goto release; 2352 } 2353 2354 release: 2355 hw->phy.ops.release(hw); 2356 return ret_val; 2357 } 2358 2359 /** 2360 * e1000_k1_gig_workaround_hv - K1 Si workaround 2361 * @hw: pointer to the HW structure 2362 * @link: link up bool flag 2363 * 2364 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning 2365 * from a lower speed. This workaround disables K1 whenever link is at 1Gig 2366 * If link is down, the function will restore the default K1 setting located 2367 * in the NVM. 2368 **/ 2369 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) 2370 { 2371 s32 ret_val = 0; 2372 u16 status_reg = 0; 2373 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled; 2374 2375 if (hw->mac.type != e1000_pchlan) 2376 return 0; 2377 2378 /* Wrap the whole flow with the sw flag */ 2379 ret_val = hw->phy.ops.acquire(hw); 2380 if (ret_val) 2381 return ret_val; 2382 2383 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ 2384 if (link) { 2385 if (hw->phy.type == e1000_phy_82578) { 2386 ret_val = e1e_rphy_locked(hw, BM_CS_STATUS, 2387 &status_reg); 2388 if (ret_val) 2389 goto release; 2390 2391 status_reg &= (BM_CS_STATUS_LINK_UP | 2392 BM_CS_STATUS_RESOLVED | 2393 BM_CS_STATUS_SPEED_MASK); 2394 2395 if (status_reg == (BM_CS_STATUS_LINK_UP | 2396 BM_CS_STATUS_RESOLVED | 2397 BM_CS_STATUS_SPEED_1000)) 2398 k1_enable = false; 2399 } 2400 2401 if (hw->phy.type == e1000_phy_82577) { 2402 ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg); 2403 if (ret_val) 2404 goto release; 2405 2406 status_reg &= (HV_M_STATUS_LINK_UP | 2407 HV_M_STATUS_AUTONEG_COMPLETE | 2408 HV_M_STATUS_SPEED_MASK); 2409 2410 if (status_reg == (HV_M_STATUS_LINK_UP | 2411 HV_M_STATUS_AUTONEG_COMPLETE | 2412 HV_M_STATUS_SPEED_1000)) 2413 k1_enable = false; 2414 } 2415 2416 /* Link stall fix for link up */ 2417 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100); 2418 if (ret_val) 2419 goto release; 2420 2421 } else { 2422 /* Link stall fix for link down */ 2423 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100); 2424 if (ret_val) 2425 goto release; 2426 } 2427 2428 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable); 2429 2430 release: 2431 hw->phy.ops.release(hw); 2432 2433 return ret_val; 2434 } 2435 2436 /** 2437 * e1000_configure_k1_ich8lan - Configure K1 power state 2438 * @hw: pointer to the HW structure 2439 * @k1_enable: K1 state to configure 2440 * 2441 * Configure the K1 power state based on the provided parameter. 2442 * Assumes semaphore already acquired. 2443 * 2444 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2445 **/ 2446 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) 2447 { 2448 s32 ret_val; 2449 u32 ctrl_reg = 0; 2450 u32 ctrl_ext = 0; 2451 u32 reg = 0; 2452 u16 kmrn_reg = 0; 2453 2454 ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 2455 &kmrn_reg); 2456 if (ret_val) 2457 return ret_val; 2458 2459 if (k1_enable) 2460 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; 2461 else 2462 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE; 2463 2464 ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 2465 kmrn_reg); 2466 if (ret_val) 2467 return ret_val; 2468 2469 usleep_range(20, 40); 2470 ctrl_ext = er32(CTRL_EXT); 2471 ctrl_reg = er32(CTRL); 2472 2473 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 2474 reg |= E1000_CTRL_FRCSPD; 2475 ew32(CTRL, reg); 2476 2477 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); 2478 e1e_flush(); 2479 usleep_range(20, 40); 2480 ew32(CTRL, ctrl_reg); 2481 ew32(CTRL_EXT, ctrl_ext); 2482 e1e_flush(); 2483 usleep_range(20, 40); 2484 2485 return 0; 2486 } 2487 2488 /** 2489 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration 2490 * @hw: pointer to the HW structure 2491 * @d0_state: boolean if entering d0 or d3 device state 2492 * 2493 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are 2494 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit 2495 * in NVM determines whether HW should configure LPLU and Gbe Disable. 2496 **/ 2497 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) 2498 { 2499 s32 ret_val = 0; 2500 u32 mac_reg; 2501 u16 oem_reg; 2502 2503 if (hw->mac.type < e1000_pchlan) 2504 return ret_val; 2505 2506 ret_val = hw->phy.ops.acquire(hw); 2507 if (ret_val) 2508 return ret_val; 2509 2510 if (hw->mac.type == e1000_pchlan) { 2511 mac_reg = er32(EXTCNF_CTRL); 2512 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) 2513 goto release; 2514 } 2515 2516 mac_reg = er32(FEXTNVM); 2517 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M)) 2518 goto release; 2519 2520 mac_reg = er32(PHY_CTRL); 2521 2522 ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg); 2523 if (ret_val) 2524 goto release; 2525 2526 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); 2527 2528 if (d0_state) { 2529 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE) 2530 oem_reg |= HV_OEM_BITS_GBE_DIS; 2531 2532 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) 2533 oem_reg |= HV_OEM_BITS_LPLU; 2534 } else { 2535 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE | 2536 E1000_PHY_CTRL_NOND0A_GBE_DISABLE)) 2537 oem_reg |= HV_OEM_BITS_GBE_DIS; 2538 2539 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU | 2540 E1000_PHY_CTRL_NOND0A_LPLU)) 2541 oem_reg |= HV_OEM_BITS_LPLU; 2542 } 2543 2544 /* Set Restart auto-neg to activate the bits */ 2545 if ((d0_state || (hw->mac.type != e1000_pchlan)) && 2546 !hw->phy.ops.check_reset_block(hw)) 2547 oem_reg |= HV_OEM_BITS_RESTART_AN; 2548 2549 ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg); 2550 2551 release: 2552 hw->phy.ops.release(hw); 2553 2554 return ret_val; 2555 } 2556 2557 /** 2558 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode 2559 * @hw: pointer to the HW structure 2560 **/ 2561 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw) 2562 { 2563 s32 ret_val; 2564 u16 data; 2565 2566 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data); 2567 if (ret_val) 2568 return ret_val; 2569 2570 data |= HV_KMRN_MDIO_SLOW; 2571 2572 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data); 2573 2574 return ret_val; 2575 } 2576 2577 /** 2578 * e1000_hv_phy_workarounds_ich8lan - apply PHY workarounds 2579 * @hw: pointer to the HW structure 2580 * 2581 * A series of PHY workarounds to be done after every PHY reset. 2582 **/ 2583 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) 2584 { 2585 s32 ret_val = 0; 2586 u16 phy_data; 2587 2588 if (hw->mac.type != e1000_pchlan) 2589 return 0; 2590 2591 /* Set MDIO slow mode before any other MDIO access */ 2592 if (hw->phy.type == e1000_phy_82577) { 2593 ret_val = e1000_set_mdio_slow_mode_hv(hw); 2594 if (ret_val) 2595 return ret_val; 2596 } 2597 2598 if (((hw->phy.type == e1000_phy_82577) && 2599 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || 2600 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { 2601 /* Disable generation of early preamble */ 2602 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431); 2603 if (ret_val) 2604 return ret_val; 2605 2606 /* Preamble tuning for SSC */ 2607 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204); 2608 if (ret_val) 2609 return ret_val; 2610 } 2611 2612 if (hw->phy.type == e1000_phy_82578) { 2613 /* Return registers to default by doing a soft reset then 2614 * writing 0x3140 to the control register. 2615 */ 2616 if (hw->phy.revision < 2) { 2617 e1000e_phy_sw_reset(hw); 2618 ret_val = e1e_wphy(hw, MII_BMCR, 0x3140); 2619 if (ret_val) 2620 return ret_val; 2621 } 2622 } 2623 2624 /* Select page 0 */ 2625 ret_val = hw->phy.ops.acquire(hw); 2626 if (ret_val) 2627 return ret_val; 2628 2629 hw->phy.addr = 1; 2630 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); 2631 hw->phy.ops.release(hw); 2632 if (ret_val) 2633 return ret_val; 2634 2635 /* Configure the K1 Si workaround during phy reset assuming there is 2636 * link so that it disables K1 if link is in 1Gbps. 2637 */ 2638 ret_val = e1000_k1_gig_workaround_hv(hw, true); 2639 if (ret_val) 2640 return ret_val; 2641 2642 /* Workaround for link disconnects on a busy hub in half duplex */ 2643 ret_val = hw->phy.ops.acquire(hw); 2644 if (ret_val) 2645 return ret_val; 2646 ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data); 2647 if (ret_val) 2648 goto release; 2649 ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF); 2650 if (ret_val) 2651 goto release; 2652 2653 /* set MSE higher to enable link to stay up when noise is high */ 2654 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034); 2655 release: 2656 hw->phy.ops.release(hw); 2657 2658 return ret_val; 2659 } 2660 2661 /** 2662 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY 2663 * @hw: pointer to the HW structure 2664 **/ 2665 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw) 2666 { 2667 u32 mac_reg; 2668 u16 i, phy_reg = 0; 2669 s32 ret_val; 2670 2671 ret_val = hw->phy.ops.acquire(hw); 2672 if (ret_val) 2673 return; 2674 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2675 if (ret_val) 2676 goto release; 2677 2678 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */ 2679 for (i = 0; i < (hw->mac.rar_entry_count); i++) { 2680 mac_reg = er32(RAL(i)); 2681 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i), 2682 (u16)(mac_reg & 0xFFFF)); 2683 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i), 2684 (u16)((mac_reg >> 16) & 0xFFFF)); 2685 2686 mac_reg = er32(RAH(i)); 2687 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i), 2688 (u16)(mac_reg & 0xFFFF)); 2689 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i), 2690 (u16)((mac_reg & E1000_RAH_AV) >> 16)); 2691 } 2692 2693 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2694 2695 release: 2696 hw->phy.ops.release(hw); 2697 } 2698 2699 /** 2700 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation 2701 * with 82579 PHY 2702 * @hw: pointer to the HW structure 2703 * @enable: flag to enable/disable workaround when enabling/disabling jumbos 2704 **/ 2705 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) 2706 { 2707 s32 ret_val = 0; 2708 u16 phy_reg, data; 2709 u32 mac_reg; 2710 u16 i; 2711 2712 if (hw->mac.type < e1000_pch2lan) 2713 return 0; 2714 2715 /* disable Rx path while enabling/disabling workaround */ 2716 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg); 2717 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14)); 2718 if (ret_val) 2719 return ret_val; 2720 2721 if (enable) { 2722 /* Write Rx addresses (rar_entry_count for RAL/H, and 2723 * SHRAL/H) and initial CRC values to the MAC 2724 */ 2725 for (i = 0; i < hw->mac.rar_entry_count; i++) { 2726 u8 mac_addr[ETH_ALEN] = { 0 }; 2727 u32 addr_high, addr_low; 2728 2729 addr_high = er32(RAH(i)); 2730 if (!(addr_high & E1000_RAH_AV)) 2731 continue; 2732 addr_low = er32(RAL(i)); 2733 mac_addr[0] = (addr_low & 0xFF); 2734 mac_addr[1] = ((addr_low >> 8) & 0xFF); 2735 mac_addr[2] = ((addr_low >> 16) & 0xFF); 2736 mac_addr[3] = ((addr_low >> 24) & 0xFF); 2737 mac_addr[4] = (addr_high & 0xFF); 2738 mac_addr[5] = ((addr_high >> 8) & 0xFF); 2739 2740 ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr)); 2741 } 2742 2743 /* Write Rx addresses to the PHY */ 2744 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 2745 2746 /* Enable jumbo frame workaround in the MAC */ 2747 mac_reg = er32(FFLT_DBG); 2748 mac_reg &= ~BIT(14); 2749 mac_reg |= (7 << 15); 2750 ew32(FFLT_DBG, mac_reg); 2751 2752 mac_reg = er32(RCTL); 2753 mac_reg |= E1000_RCTL_SECRC; 2754 ew32(RCTL, mac_reg); 2755 2756 ret_val = e1000e_read_kmrn_reg(hw, 2757 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2758 &data); 2759 if (ret_val) 2760 return ret_val; 2761 ret_val = e1000e_write_kmrn_reg(hw, 2762 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2763 data | BIT(0)); 2764 if (ret_val) 2765 return ret_val; 2766 ret_val = e1000e_read_kmrn_reg(hw, 2767 E1000_KMRNCTRLSTA_HD_CTRL, 2768 &data); 2769 if (ret_val) 2770 return ret_val; 2771 data &= ~(0xF << 8); 2772 data |= (0xB << 8); 2773 ret_val = e1000e_write_kmrn_reg(hw, 2774 E1000_KMRNCTRLSTA_HD_CTRL, 2775 data); 2776 if (ret_val) 2777 return ret_val; 2778 2779 /* Enable jumbo frame workaround in the PHY */ 2780 e1e_rphy(hw, PHY_REG(769, 23), &data); 2781 data &= ~(0x7F << 5); 2782 data |= (0x37 << 5); 2783 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); 2784 if (ret_val) 2785 return ret_val; 2786 e1e_rphy(hw, PHY_REG(769, 16), &data); 2787 data &= ~BIT(13); 2788 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); 2789 if (ret_val) 2790 return ret_val; 2791 e1e_rphy(hw, PHY_REG(776, 20), &data); 2792 data &= ~(0x3FF << 2); 2793 data |= (E1000_TX_PTR_GAP << 2); 2794 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); 2795 if (ret_val) 2796 return ret_val; 2797 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100); 2798 if (ret_val) 2799 return ret_val; 2800 e1e_rphy(hw, HV_PM_CTRL, &data); 2801 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | BIT(10)); 2802 if (ret_val) 2803 return ret_val; 2804 } else { 2805 /* Write MAC register values back to h/w defaults */ 2806 mac_reg = er32(FFLT_DBG); 2807 mac_reg &= ~(0xF << 14); 2808 ew32(FFLT_DBG, mac_reg); 2809 2810 mac_reg = er32(RCTL); 2811 mac_reg &= ~E1000_RCTL_SECRC; 2812 ew32(RCTL, mac_reg); 2813 2814 ret_val = e1000e_read_kmrn_reg(hw, 2815 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2816 &data); 2817 if (ret_val) 2818 return ret_val; 2819 ret_val = e1000e_write_kmrn_reg(hw, 2820 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2821 data & ~BIT(0)); 2822 if (ret_val) 2823 return ret_val; 2824 ret_val = e1000e_read_kmrn_reg(hw, 2825 E1000_KMRNCTRLSTA_HD_CTRL, 2826 &data); 2827 if (ret_val) 2828 return ret_val; 2829 data &= ~(0xF << 8); 2830 data |= (0xB << 8); 2831 ret_val = e1000e_write_kmrn_reg(hw, 2832 E1000_KMRNCTRLSTA_HD_CTRL, 2833 data); 2834 if (ret_val) 2835 return ret_val; 2836 2837 /* Write PHY register values back to h/w defaults */ 2838 e1e_rphy(hw, PHY_REG(769, 23), &data); 2839 data &= ~(0x7F << 5); 2840 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); 2841 if (ret_val) 2842 return ret_val; 2843 e1e_rphy(hw, PHY_REG(769, 16), &data); 2844 data |= BIT(13); 2845 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); 2846 if (ret_val) 2847 return ret_val; 2848 e1e_rphy(hw, PHY_REG(776, 20), &data); 2849 data &= ~(0x3FF << 2); 2850 data |= (0x8 << 2); 2851 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); 2852 if (ret_val) 2853 return ret_val; 2854 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00); 2855 if (ret_val) 2856 return ret_val; 2857 e1e_rphy(hw, HV_PM_CTRL, &data); 2858 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~BIT(10)); 2859 if (ret_val) 2860 return ret_val; 2861 } 2862 2863 /* re-enable Rx path after enabling/disabling workaround */ 2864 return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~BIT(14)); 2865 } 2866 2867 /** 2868 * e1000_lv_phy_workarounds_ich8lan - apply ich8 specific workarounds 2869 * @hw: pointer to the HW structure 2870 * 2871 * A series of PHY workarounds to be done after every PHY reset. 2872 **/ 2873 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw) 2874 { 2875 s32 ret_val = 0; 2876 2877 if (hw->mac.type != e1000_pch2lan) 2878 return 0; 2879 2880 /* Set MDIO slow mode before any other MDIO access */ 2881 ret_val = e1000_set_mdio_slow_mode_hv(hw); 2882 if (ret_val) 2883 return ret_val; 2884 2885 ret_val = hw->phy.ops.acquire(hw); 2886 if (ret_val) 2887 return ret_val; 2888 /* set MSE higher to enable link to stay up when noise is high */ 2889 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034); 2890 if (ret_val) 2891 goto release; 2892 /* drop link after 5 times MSE threshold was reached */ 2893 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005); 2894 release: 2895 hw->phy.ops.release(hw); 2896 2897 return ret_val; 2898 } 2899 2900 /** 2901 * e1000_k1_workaround_lv - K1 Si workaround 2902 * @hw: pointer to the HW structure 2903 * 2904 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps 2905 * Disable K1 in 1000Mbps and 100Mbps 2906 **/ 2907 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw) 2908 { 2909 s32 ret_val = 0; 2910 u16 status_reg = 0; 2911 2912 if (hw->mac.type != e1000_pch2lan) 2913 return 0; 2914 2915 /* Set K1 beacon duration based on 10Mbs speed */ 2916 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg); 2917 if (ret_val) 2918 return ret_val; 2919 2920 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) 2921 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { 2922 if (status_reg & 2923 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) { 2924 u16 pm_phy_reg; 2925 2926 /* LV 1G/100 Packet drop issue wa */ 2927 ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg); 2928 if (ret_val) 2929 return ret_val; 2930 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE; 2931 ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg); 2932 if (ret_val) 2933 return ret_val; 2934 } else { 2935 u32 mac_reg; 2936 2937 mac_reg = er32(FEXTNVM4); 2938 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 2939 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC; 2940 ew32(FEXTNVM4, mac_reg); 2941 } 2942 } 2943 2944 return ret_val; 2945 } 2946 2947 /** 2948 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware 2949 * @hw: pointer to the HW structure 2950 * @gate: boolean set to true to gate, false to ungate 2951 * 2952 * Gate/ungate the automatic PHY configuration via hardware; perform 2953 * the configuration via software instead. 2954 **/ 2955 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate) 2956 { 2957 u32 extcnf_ctrl; 2958 2959 if (hw->mac.type < e1000_pch2lan) 2960 return; 2961 2962 extcnf_ctrl = er32(EXTCNF_CTRL); 2963 2964 if (gate) 2965 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 2966 else 2967 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG; 2968 2969 ew32(EXTCNF_CTRL, extcnf_ctrl); 2970 } 2971 2972 /** 2973 * e1000_lan_init_done_ich8lan - Check for PHY config completion 2974 * @hw: pointer to the HW structure 2975 * 2976 * Check the appropriate indication the MAC has finished configuring the 2977 * PHY after a software reset. 2978 **/ 2979 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) 2980 { 2981 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT; 2982 2983 /* Wait for basic configuration completes before proceeding */ 2984 do { 2985 data = er32(STATUS); 2986 data &= E1000_STATUS_LAN_INIT_DONE; 2987 usleep_range(100, 200); 2988 } while ((!data) && --loop); 2989 2990 /* If basic configuration is incomplete before the above loop 2991 * count reaches 0, loading the configuration from NVM will 2992 * leave the PHY in a bad state possibly resulting in no link. 2993 */ 2994 if (loop == 0) 2995 e_dbg("LAN_INIT_DONE not set, increase timeout\n"); 2996 2997 /* Clear the Init Done bit for the next init event */ 2998 data = er32(STATUS); 2999 data &= ~E1000_STATUS_LAN_INIT_DONE; 3000 ew32(STATUS, data); 3001 } 3002 3003 /** 3004 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset 3005 * @hw: pointer to the HW structure 3006 **/ 3007 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) 3008 { 3009 s32 ret_val = 0; 3010 u16 reg; 3011 3012 if (hw->phy.ops.check_reset_block(hw)) 3013 return 0; 3014 3015 /* Allow time for h/w to get to quiescent state after reset */ 3016 usleep_range(10000, 11000); 3017 3018 /* Perform any necessary post-reset workarounds */ 3019 switch (hw->mac.type) { 3020 case e1000_pchlan: 3021 ret_val = e1000_hv_phy_workarounds_ich8lan(hw); 3022 if (ret_val) 3023 return ret_val; 3024 break; 3025 case e1000_pch2lan: 3026 ret_val = e1000_lv_phy_workarounds_ich8lan(hw); 3027 if (ret_val) 3028 return ret_val; 3029 break; 3030 default: 3031 break; 3032 } 3033 3034 /* Clear the host wakeup bit after lcd reset */ 3035 if (hw->mac.type >= e1000_pchlan) { 3036 e1e_rphy(hw, BM_PORT_GEN_CFG, ®); 3037 reg &= ~BM_WUC_HOST_WU_BIT; 3038 e1e_wphy(hw, BM_PORT_GEN_CFG, reg); 3039 } 3040 3041 /* Configure the LCD with the extended configuration region in NVM */ 3042 ret_val = e1000_sw_lcd_config_ich8lan(hw); 3043 if (ret_val) 3044 return ret_val; 3045 3046 /* Configure the LCD with the OEM bits in NVM */ 3047 ret_val = e1000_oem_bits_config_ich8lan(hw, true); 3048 3049 if (hw->mac.type == e1000_pch2lan) { 3050 /* Ungate automatic PHY configuration on non-managed 82579 */ 3051 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 3052 usleep_range(10000, 11000); 3053 e1000_gate_hw_phy_config_ich8lan(hw, false); 3054 } 3055 3056 /* Set EEE LPI Update Timer to 200usec */ 3057 ret_val = hw->phy.ops.acquire(hw); 3058 if (ret_val) 3059 return ret_val; 3060 ret_val = e1000_write_emi_reg_locked(hw, 3061 I82579_LPI_UPDATE_TIMER, 3062 0x1387); 3063 hw->phy.ops.release(hw); 3064 } 3065 3066 return ret_val; 3067 } 3068 3069 /** 3070 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset 3071 * @hw: pointer to the HW structure 3072 * 3073 * Resets the PHY 3074 * This is a function pointer entry point called by drivers 3075 * or other shared routines. 3076 **/ 3077 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) 3078 { 3079 s32 ret_val = 0; 3080 3081 /* Gate automatic PHY configuration by hardware on non-managed 82579 */ 3082 if ((hw->mac.type == e1000_pch2lan) && 3083 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 3084 e1000_gate_hw_phy_config_ich8lan(hw, true); 3085 3086 ret_val = e1000e_phy_hw_reset_generic(hw); 3087 if (ret_val) 3088 return ret_val; 3089 3090 return e1000_post_phy_reset_ich8lan(hw); 3091 } 3092 3093 /** 3094 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state 3095 * @hw: pointer to the HW structure 3096 * @active: true to enable LPLU, false to disable 3097 * 3098 * Sets the LPLU state according to the active flag. For PCH, if OEM write 3099 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set 3100 * the phy speed. This function will manually set the LPLU bit and restart 3101 * auto-neg as hw would do. D3 and D0 LPLU will call the same function 3102 * since it configures the same bit. 3103 **/ 3104 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active) 3105 { 3106 s32 ret_val; 3107 u16 oem_reg; 3108 3109 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg); 3110 if (ret_val) 3111 return ret_val; 3112 3113 if (active) 3114 oem_reg |= HV_OEM_BITS_LPLU; 3115 else 3116 oem_reg &= ~HV_OEM_BITS_LPLU; 3117 3118 if (!hw->phy.ops.check_reset_block(hw)) 3119 oem_reg |= HV_OEM_BITS_RESTART_AN; 3120 3121 return e1e_wphy(hw, HV_OEM_BITS, oem_reg); 3122 } 3123 3124 /** 3125 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state 3126 * @hw: pointer to the HW structure 3127 * @active: true to enable LPLU, false to disable 3128 * 3129 * Sets the LPLU D0 state according to the active flag. When 3130 * activating LPLU this function also disables smart speed 3131 * and vice versa. LPLU will not be activated unless the 3132 * device autonegotiation advertisement meets standards of 3133 * either 10 or 10/100 or 10/100/1000 at all duplexes. 3134 * This is a function pointer entry point only called by 3135 * PHY setup routines. 3136 **/ 3137 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 3138 { 3139 struct e1000_phy_info *phy = &hw->phy; 3140 u32 phy_ctrl; 3141 s32 ret_val = 0; 3142 u16 data; 3143 3144 if (phy->type == e1000_phy_ife) 3145 return 0; 3146 3147 phy_ctrl = er32(PHY_CTRL); 3148 3149 if (active) { 3150 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 3151 ew32(PHY_CTRL, phy_ctrl); 3152 3153 if (phy->type != e1000_phy_igp_3) 3154 return 0; 3155 3156 /* Call gig speed drop workaround on LPLU before accessing 3157 * any PHY registers 3158 */ 3159 if (hw->mac.type == e1000_ich8lan) 3160 e1000e_gig_downshift_workaround_ich8lan(hw); 3161 3162 /* When LPLU is enabled, we should disable SmartSpeed */ 3163 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); 3164 if (ret_val) 3165 return ret_val; 3166 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3167 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); 3168 if (ret_val) 3169 return ret_val; 3170 } else { 3171 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 3172 ew32(PHY_CTRL, phy_ctrl); 3173 3174 if (phy->type != e1000_phy_igp_3) 3175 return 0; 3176 3177 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 3178 * during Dx states where the power conservation is most 3179 * important. During driver activity we should enable 3180 * SmartSpeed, so performance is maintained. 3181 */ 3182 if (phy->smart_speed == e1000_smart_speed_on) { 3183 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3184 &data); 3185 if (ret_val) 3186 return ret_val; 3187 3188 data |= IGP01E1000_PSCFR_SMART_SPEED; 3189 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3190 data); 3191 if (ret_val) 3192 return ret_val; 3193 } else if (phy->smart_speed == e1000_smart_speed_off) { 3194 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3195 &data); 3196 if (ret_val) 3197 return ret_val; 3198 3199 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3200 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3201 data); 3202 if (ret_val) 3203 return ret_val; 3204 } 3205 } 3206 3207 return 0; 3208 } 3209 3210 /** 3211 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state 3212 * @hw: pointer to the HW structure 3213 * @active: true to enable LPLU, false to disable 3214 * 3215 * Sets the LPLU D3 state according to the active flag. When 3216 * activating LPLU this function also disables smart speed 3217 * and vice versa. LPLU will not be activated unless the 3218 * device autonegotiation advertisement meets standards of 3219 * either 10 or 10/100 or 10/100/1000 at all duplexes. 3220 * This is a function pointer entry point only called by 3221 * PHY setup routines. 3222 **/ 3223 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 3224 { 3225 struct e1000_phy_info *phy = &hw->phy; 3226 u32 phy_ctrl; 3227 s32 ret_val = 0; 3228 u16 data; 3229 3230 phy_ctrl = er32(PHY_CTRL); 3231 3232 if (!active) { 3233 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 3234 ew32(PHY_CTRL, phy_ctrl); 3235 3236 if (phy->type != e1000_phy_igp_3) 3237 return 0; 3238 3239 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 3240 * during Dx states where the power conservation is most 3241 * important. During driver activity we should enable 3242 * SmartSpeed, so performance is maintained. 3243 */ 3244 if (phy->smart_speed == e1000_smart_speed_on) { 3245 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3246 &data); 3247 if (ret_val) 3248 return ret_val; 3249 3250 data |= IGP01E1000_PSCFR_SMART_SPEED; 3251 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3252 data); 3253 if (ret_val) 3254 return ret_val; 3255 } else if (phy->smart_speed == e1000_smart_speed_off) { 3256 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3257 &data); 3258 if (ret_val) 3259 return ret_val; 3260 3261 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3262 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3263 data); 3264 if (ret_val) 3265 return ret_val; 3266 } 3267 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 3268 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 3269 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 3270 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 3271 ew32(PHY_CTRL, phy_ctrl); 3272 3273 if (phy->type != e1000_phy_igp_3) 3274 return 0; 3275 3276 /* Call gig speed drop workaround on LPLU before accessing 3277 * any PHY registers 3278 */ 3279 if (hw->mac.type == e1000_ich8lan) 3280 e1000e_gig_downshift_workaround_ich8lan(hw); 3281 3282 /* When LPLU is enabled, we should disable SmartSpeed */ 3283 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); 3284 if (ret_val) 3285 return ret_val; 3286 3287 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3288 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); 3289 } 3290 3291 return ret_val; 3292 } 3293 3294 /** 3295 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 3296 * @hw: pointer to the HW structure 3297 * @bank: pointer to the variable that returns the active bank 3298 * 3299 * Reads signature byte from the NVM using the flash access registers. 3300 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. 3301 **/ 3302 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) 3303 { 3304 u32 eecd; 3305 struct e1000_nvm_info *nvm = &hw->nvm; 3306 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); 3307 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; 3308 u32 nvm_dword = 0; 3309 u8 sig_byte = 0; 3310 s32 ret_val; 3311 3312 switch (hw->mac.type) { 3313 case e1000_pch_spt: 3314 case e1000_pch_cnp: 3315 case e1000_pch_tgp: 3316 case e1000_pch_adp: 3317 case e1000_pch_mtp: 3318 case e1000_pch_lnp: 3319 case e1000_pch_ptp: 3320 case e1000_pch_nvp: 3321 bank1_offset = nvm->flash_bank_size; 3322 act_offset = E1000_ICH_NVM_SIG_WORD; 3323 3324 /* set bank to 0 in case flash read fails */ 3325 *bank = 0; 3326 3327 /* Check bank 0 */ 3328 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, 3329 &nvm_dword); 3330 if (ret_val) 3331 return ret_val; 3332 sig_byte = FIELD_GET(0xFF00, nvm_dword); 3333 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3334 E1000_ICH_NVM_SIG_VALUE) { 3335 *bank = 0; 3336 return 0; 3337 } 3338 3339 /* Check bank 1 */ 3340 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset + 3341 bank1_offset, 3342 &nvm_dword); 3343 if (ret_val) 3344 return ret_val; 3345 sig_byte = FIELD_GET(0xFF00, nvm_dword); 3346 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3347 E1000_ICH_NVM_SIG_VALUE) { 3348 *bank = 1; 3349 return 0; 3350 } 3351 3352 e_dbg("ERROR: No valid NVM bank present\n"); 3353 return -E1000_ERR_NVM; 3354 case e1000_ich8lan: 3355 case e1000_ich9lan: 3356 eecd = er32(EECD); 3357 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == 3358 E1000_EECD_SEC1VAL_VALID_MASK) { 3359 if (eecd & E1000_EECD_SEC1VAL) 3360 *bank = 1; 3361 else 3362 *bank = 0; 3363 3364 return 0; 3365 } 3366 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n"); 3367 fallthrough; 3368 default: 3369 /* set bank to 0 in case flash read fails */ 3370 *bank = 0; 3371 3372 /* Check bank 0 */ 3373 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset, 3374 &sig_byte); 3375 if (ret_val) 3376 return ret_val; 3377 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3378 E1000_ICH_NVM_SIG_VALUE) { 3379 *bank = 0; 3380 return 0; 3381 } 3382 3383 /* Check bank 1 */ 3384 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset + 3385 bank1_offset, 3386 &sig_byte); 3387 if (ret_val) 3388 return ret_val; 3389 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3390 E1000_ICH_NVM_SIG_VALUE) { 3391 *bank = 1; 3392 return 0; 3393 } 3394 3395 e_dbg("ERROR: No valid NVM bank present\n"); 3396 return -E1000_ERR_NVM; 3397 } 3398 } 3399 3400 /** 3401 * e1000_read_nvm_spt - NVM access for SPT 3402 * @hw: pointer to the HW structure 3403 * @offset: The offset (in bytes) of the word(s) to read. 3404 * @words: Size of data to read in words. 3405 * @data: pointer to the word(s) to read at offset. 3406 * 3407 * Reads a word(s) from the NVM 3408 **/ 3409 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words, 3410 u16 *data) 3411 { 3412 struct e1000_nvm_info *nvm = &hw->nvm; 3413 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3414 u32 act_offset; 3415 s32 ret_val = 0; 3416 u32 bank = 0; 3417 u32 dword = 0; 3418 u16 offset_to_read; 3419 u16 i; 3420 3421 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3422 (words == 0)) { 3423 e_dbg("nvm parameter(s) out of bounds\n"); 3424 ret_val = -E1000_ERR_NVM; 3425 goto out; 3426 } 3427 3428 nvm->ops.acquire(hw); 3429 3430 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3431 if (ret_val) { 3432 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3433 bank = 0; 3434 } 3435 3436 act_offset = (bank) ? nvm->flash_bank_size : 0; 3437 act_offset += offset; 3438 3439 ret_val = 0; 3440 3441 for (i = 0; i < words; i += 2) { 3442 if (words - i == 1) { 3443 if (dev_spec->shadow_ram[offset + i].modified) { 3444 data[i] = 3445 dev_spec->shadow_ram[offset + i].value; 3446 } else { 3447 offset_to_read = act_offset + i - 3448 ((act_offset + i) % 2); 3449 ret_val = 3450 e1000_read_flash_dword_ich8lan(hw, 3451 offset_to_read, 3452 &dword); 3453 if (ret_val) 3454 break; 3455 if ((act_offset + i) % 2 == 0) 3456 data[i] = (u16)(dword & 0xFFFF); 3457 else 3458 data[i] = (u16)((dword >> 16) & 0xFFFF); 3459 } 3460 } else { 3461 offset_to_read = act_offset + i; 3462 if (!(dev_spec->shadow_ram[offset + i].modified) || 3463 !(dev_spec->shadow_ram[offset + i + 1].modified)) { 3464 ret_val = 3465 e1000_read_flash_dword_ich8lan(hw, 3466 offset_to_read, 3467 &dword); 3468 if (ret_val) 3469 break; 3470 } 3471 if (dev_spec->shadow_ram[offset + i].modified) 3472 data[i] = 3473 dev_spec->shadow_ram[offset + i].value; 3474 else 3475 data[i] = (u16)(dword & 0xFFFF); 3476 if (dev_spec->shadow_ram[offset + i].modified) 3477 data[i + 1] = 3478 dev_spec->shadow_ram[offset + i + 1].value; 3479 else 3480 data[i + 1] = (u16)(dword >> 16 & 0xFFFF); 3481 } 3482 } 3483 3484 nvm->ops.release(hw); 3485 3486 out: 3487 if (ret_val) 3488 e_dbg("NVM read error: %d\n", ret_val); 3489 3490 return ret_val; 3491 } 3492 3493 /** 3494 * e1000_read_nvm_ich8lan - Read word(s) from the NVM 3495 * @hw: pointer to the HW structure 3496 * @offset: The offset (in bytes) of the word(s) to read. 3497 * @words: Size of data to read in words 3498 * @data: Pointer to the word(s) to read at offset. 3499 * 3500 * Reads a word(s) from the NVM using the flash access registers. 3501 **/ 3502 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 3503 u16 *data) 3504 { 3505 struct e1000_nvm_info *nvm = &hw->nvm; 3506 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3507 u32 act_offset; 3508 s32 ret_val = 0; 3509 u32 bank = 0; 3510 u16 i, word; 3511 3512 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3513 (words == 0)) { 3514 e_dbg("nvm parameter(s) out of bounds\n"); 3515 ret_val = -E1000_ERR_NVM; 3516 goto out; 3517 } 3518 3519 nvm->ops.acquire(hw); 3520 3521 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3522 if (ret_val) { 3523 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3524 bank = 0; 3525 } 3526 3527 act_offset = (bank) ? nvm->flash_bank_size : 0; 3528 act_offset += offset; 3529 3530 ret_val = 0; 3531 for (i = 0; i < words; i++) { 3532 if (dev_spec->shadow_ram[offset + i].modified) { 3533 data[i] = dev_spec->shadow_ram[offset + i].value; 3534 } else { 3535 ret_val = e1000_read_flash_word_ich8lan(hw, 3536 act_offset + i, 3537 &word); 3538 if (ret_val) 3539 break; 3540 data[i] = word; 3541 } 3542 } 3543 3544 nvm->ops.release(hw); 3545 3546 out: 3547 if (ret_val) 3548 e_dbg("NVM read error: %d\n", ret_val); 3549 3550 return ret_val; 3551 } 3552 3553 /** 3554 * e1000_flash_cycle_init_ich8lan - Initialize flash 3555 * @hw: pointer to the HW structure 3556 * 3557 * This function does initial flash setup so that a new read/write/erase cycle 3558 * can be started. 3559 **/ 3560 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) 3561 { 3562 union ich8_hws_flash_status hsfsts; 3563 s32 ret_val = -E1000_ERR_NVM; 3564 3565 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3566 3567 /* Check if the flash descriptor is valid */ 3568 if (!hsfsts.hsf_status.fldesvalid) { 3569 e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n"); 3570 return -E1000_ERR_NVM; 3571 } 3572 3573 /* Clear FCERR and DAEL in hw status by writing 1 */ 3574 hsfsts.hsf_status.flcerr = 1; 3575 hsfsts.hsf_status.dael = 1; 3576 if (hw->mac.type >= e1000_pch_spt) 3577 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF); 3578 else 3579 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 3580 3581 /* Either we should have a hardware SPI cycle in progress 3582 * bit to check against, in order to start a new cycle or 3583 * FDONE bit should be changed in the hardware so that it 3584 * is 1 after hardware reset, which can then be used as an 3585 * indication whether a cycle is in progress or has been 3586 * completed. 3587 */ 3588 3589 if (!hsfsts.hsf_status.flcinprog) { 3590 /* There is no cycle running at present, 3591 * so we can start a cycle. 3592 * Begin by setting Flash Cycle Done. 3593 */ 3594 hsfsts.hsf_status.flcdone = 1; 3595 if (hw->mac.type >= e1000_pch_spt) 3596 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF); 3597 else 3598 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 3599 ret_val = 0; 3600 } else { 3601 s32 i; 3602 3603 /* Otherwise poll for sometime so the current 3604 * cycle has a chance to end before giving up. 3605 */ 3606 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { 3607 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3608 if (!hsfsts.hsf_status.flcinprog) { 3609 ret_val = 0; 3610 break; 3611 } 3612 udelay(1); 3613 } 3614 if (!ret_val) { 3615 /* Successful in waiting for previous cycle to timeout, 3616 * now set the Flash Cycle Done. 3617 */ 3618 hsfsts.hsf_status.flcdone = 1; 3619 if (hw->mac.type >= e1000_pch_spt) 3620 ew32flash(ICH_FLASH_HSFSTS, 3621 hsfsts.regval & 0xFFFF); 3622 else 3623 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 3624 } else { 3625 e_dbg("Flash controller busy, cannot get access\n"); 3626 } 3627 } 3628 3629 return ret_val; 3630 } 3631 3632 /** 3633 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) 3634 * @hw: pointer to the HW structure 3635 * @timeout: maximum time to wait for completion 3636 * 3637 * This function starts a flash cycle and waits for its completion. 3638 **/ 3639 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) 3640 { 3641 union ich8_hws_flash_ctrl hsflctl; 3642 union ich8_hws_flash_status hsfsts; 3643 u32 i = 0; 3644 3645 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 3646 if (hw->mac.type >= e1000_pch_spt) 3647 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; 3648 else 3649 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 3650 hsflctl.hsf_ctrl.flcgo = 1; 3651 3652 if (hw->mac.type >= e1000_pch_spt) 3653 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); 3654 else 3655 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 3656 3657 /* wait till FDONE bit is set to 1 */ 3658 do { 3659 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3660 if (hsfsts.hsf_status.flcdone) 3661 break; 3662 udelay(1); 3663 } while (i++ < timeout); 3664 3665 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr) 3666 return 0; 3667 3668 return -E1000_ERR_NVM; 3669 } 3670 3671 /** 3672 * e1000_read_flash_dword_ich8lan - Read dword from flash 3673 * @hw: pointer to the HW structure 3674 * @offset: offset to data location 3675 * @data: pointer to the location for storing the data 3676 * 3677 * Reads the flash dword at offset into data. Offset is converted 3678 * to bytes before read. 3679 **/ 3680 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset, 3681 u32 *data) 3682 { 3683 /* Must convert word offset into bytes. */ 3684 offset <<= 1; 3685 return e1000_read_flash_data32_ich8lan(hw, offset, data); 3686 } 3687 3688 /** 3689 * e1000_read_flash_word_ich8lan - Read word from flash 3690 * @hw: pointer to the HW structure 3691 * @offset: offset to data location 3692 * @data: pointer to the location for storing the data 3693 * 3694 * Reads the flash word at offset into data. Offset is converted 3695 * to bytes before read. 3696 **/ 3697 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 3698 u16 *data) 3699 { 3700 /* Must convert offset into bytes. */ 3701 offset <<= 1; 3702 3703 return e1000_read_flash_data_ich8lan(hw, offset, 2, data); 3704 } 3705 3706 /** 3707 * e1000_read_flash_byte_ich8lan - Read byte from flash 3708 * @hw: pointer to the HW structure 3709 * @offset: The offset of the byte to read. 3710 * @data: Pointer to a byte to store the value read. 3711 * 3712 * Reads a single byte from the NVM using the flash access registers. 3713 **/ 3714 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 3715 u8 *data) 3716 { 3717 s32 ret_val; 3718 u16 word = 0; 3719 3720 /* In SPT, only 32 bits access is supported, 3721 * so this function should not be called. 3722 */ 3723 if (hw->mac.type >= e1000_pch_spt) 3724 return -E1000_ERR_NVM; 3725 else 3726 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); 3727 3728 if (ret_val) 3729 return ret_val; 3730 3731 *data = (u8)word; 3732 3733 return 0; 3734 } 3735 3736 /** 3737 * e1000_read_flash_data_ich8lan - Read byte or word from NVM 3738 * @hw: pointer to the HW structure 3739 * @offset: The offset (in bytes) of the byte or word to read. 3740 * @size: Size of data to read, 1=byte 2=word 3741 * @data: Pointer to the word to store the value read. 3742 * 3743 * Reads a byte or word from the NVM using the flash access registers. 3744 **/ 3745 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 3746 u8 size, u16 *data) 3747 { 3748 union ich8_hws_flash_status hsfsts; 3749 union ich8_hws_flash_ctrl hsflctl; 3750 u32 flash_linear_addr; 3751 u32 flash_data = 0; 3752 s32 ret_val = -E1000_ERR_NVM; 3753 u8 count = 0; 3754 3755 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 3756 return -E1000_ERR_NVM; 3757 3758 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 3759 hw->nvm.flash_base_addr); 3760 3761 do { 3762 udelay(1); 3763 /* Steps */ 3764 ret_val = e1000_flash_cycle_init_ich8lan(hw); 3765 if (ret_val) 3766 break; 3767 3768 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 3769 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 3770 hsflctl.hsf_ctrl.fldbcount = size - 1; 3771 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 3772 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 3773 3774 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 3775 3776 ret_val = 3777 e1000_flash_cycle_ich8lan(hw, 3778 ICH_FLASH_READ_COMMAND_TIMEOUT); 3779 3780 /* Check if FCERR is set to 1, if set to 1, clear it 3781 * and try the whole sequence a few more times, else 3782 * read in (shift in) the Flash Data0, the order is 3783 * least significant byte first msb to lsb 3784 */ 3785 if (!ret_val) { 3786 flash_data = er32flash(ICH_FLASH_FDATA0); 3787 if (size == 1) 3788 *data = (u8)(flash_data & 0x000000FF); 3789 else if (size == 2) 3790 *data = (u16)(flash_data & 0x0000FFFF); 3791 break; 3792 } else { 3793 /* If we've gotten here, then things are probably 3794 * completely hosed, but if the error condition is 3795 * detected, it won't hurt to give it another try... 3796 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 3797 */ 3798 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3799 if (hsfsts.hsf_status.flcerr) { 3800 /* Repeat for some time before giving up. */ 3801 continue; 3802 } else if (!hsfsts.hsf_status.flcdone) { 3803 e_dbg("Timeout error - flash cycle did not complete.\n"); 3804 break; 3805 } 3806 } 3807 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 3808 3809 return ret_val; 3810 } 3811 3812 /** 3813 * e1000_read_flash_data32_ich8lan - Read dword from NVM 3814 * @hw: pointer to the HW structure 3815 * @offset: The offset (in bytes) of the dword to read. 3816 * @data: Pointer to the dword to store the value read. 3817 * 3818 * Reads a byte or word from the NVM using the flash access registers. 3819 **/ 3820 3821 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 3822 u32 *data) 3823 { 3824 union ich8_hws_flash_status hsfsts; 3825 union ich8_hws_flash_ctrl hsflctl; 3826 u32 flash_linear_addr; 3827 s32 ret_val = -E1000_ERR_NVM; 3828 u8 count = 0; 3829 3830 if (offset > ICH_FLASH_LINEAR_ADDR_MASK || hw->mac.type < e1000_pch_spt) 3831 return -E1000_ERR_NVM; 3832 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 3833 hw->nvm.flash_base_addr); 3834 3835 do { 3836 udelay(1); 3837 /* Steps */ 3838 ret_val = e1000_flash_cycle_init_ich8lan(hw); 3839 if (ret_val) 3840 break; 3841 /* In SPT, This register is in Lan memory space, not flash. 3842 * Therefore, only 32 bit access is supported 3843 */ 3844 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; 3845 3846 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 3847 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; 3848 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 3849 /* In SPT, This register is in Lan memory space, not flash. 3850 * Therefore, only 32 bit access is supported 3851 */ 3852 ew32flash(ICH_FLASH_HSFSTS, (u32)hsflctl.regval << 16); 3853 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 3854 3855 ret_val = 3856 e1000_flash_cycle_ich8lan(hw, 3857 ICH_FLASH_READ_COMMAND_TIMEOUT); 3858 3859 /* Check if FCERR is set to 1, if set to 1, clear it 3860 * and try the whole sequence a few more times, else 3861 * read in (shift in) the Flash Data0, the order is 3862 * least significant byte first msb to lsb 3863 */ 3864 if (!ret_val) { 3865 *data = er32flash(ICH_FLASH_FDATA0); 3866 break; 3867 } else { 3868 /* If we've gotten here, then things are probably 3869 * completely hosed, but if the error condition is 3870 * detected, it won't hurt to give it another try... 3871 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 3872 */ 3873 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3874 if (hsfsts.hsf_status.flcerr) { 3875 /* Repeat for some time before giving up. */ 3876 continue; 3877 } else if (!hsfsts.hsf_status.flcdone) { 3878 e_dbg("Timeout error - flash cycle did not complete.\n"); 3879 break; 3880 } 3881 } 3882 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 3883 3884 return ret_val; 3885 } 3886 3887 /** 3888 * e1000_write_nvm_ich8lan - Write word(s) to the NVM 3889 * @hw: pointer to the HW structure 3890 * @offset: The offset (in bytes) of the word(s) to write. 3891 * @words: Size of data to write in words 3892 * @data: Pointer to the word(s) to write at offset. 3893 * 3894 * Writes a byte or word to the NVM using the flash access registers. 3895 **/ 3896 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 3897 u16 *data) 3898 { 3899 struct e1000_nvm_info *nvm = &hw->nvm; 3900 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3901 u16 i; 3902 3903 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3904 (words == 0)) { 3905 e_dbg("nvm parameter(s) out of bounds\n"); 3906 return -E1000_ERR_NVM; 3907 } 3908 3909 nvm->ops.acquire(hw); 3910 3911 for (i = 0; i < words; i++) { 3912 dev_spec->shadow_ram[offset + i].modified = true; 3913 dev_spec->shadow_ram[offset + i].value = data[i]; 3914 } 3915 3916 nvm->ops.release(hw); 3917 3918 return 0; 3919 } 3920 3921 /** 3922 * e1000_update_nvm_checksum_spt - Update the checksum for NVM 3923 * @hw: pointer to the HW structure 3924 * 3925 * The NVM checksum is updated by calling the generic update_nvm_checksum, 3926 * which writes the checksum to the shadow ram. The changes in the shadow 3927 * ram are then committed to the EEPROM by processing each bank at a time 3928 * checking for the modified bit and writing only the pending changes. 3929 * After a successful commit, the shadow ram is cleared and is ready for 3930 * future writes. 3931 **/ 3932 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw) 3933 { 3934 struct e1000_nvm_info *nvm = &hw->nvm; 3935 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3936 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 3937 s32 ret_val; 3938 u32 dword = 0; 3939 3940 ret_val = e1000e_update_nvm_checksum_generic(hw); 3941 if (ret_val) 3942 goto out; 3943 3944 if (nvm->type != e1000_nvm_flash_sw) 3945 goto out; 3946 3947 nvm->ops.acquire(hw); 3948 3949 /* We're writing to the opposite bank so if we're on bank 1, 3950 * write to bank 0 etc. We also need to erase the segment that 3951 * is going to be written 3952 */ 3953 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3954 if (ret_val) { 3955 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3956 bank = 0; 3957 } 3958 3959 if (bank == 0) { 3960 new_bank_offset = nvm->flash_bank_size; 3961 old_bank_offset = 0; 3962 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 3963 if (ret_val) 3964 goto release; 3965 } else { 3966 old_bank_offset = nvm->flash_bank_size; 3967 new_bank_offset = 0; 3968 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 3969 if (ret_val) 3970 goto release; 3971 } 3972 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i += 2) { 3973 /* Determine whether to write the value stored 3974 * in the other NVM bank or a modified value stored 3975 * in the shadow RAM 3976 */ 3977 ret_val = e1000_read_flash_dword_ich8lan(hw, 3978 i + old_bank_offset, 3979 &dword); 3980 3981 if (dev_spec->shadow_ram[i].modified) { 3982 dword &= 0xffff0000; 3983 dword |= (dev_spec->shadow_ram[i].value & 0xffff); 3984 } 3985 if (dev_spec->shadow_ram[i + 1].modified) { 3986 dword &= 0x0000ffff; 3987 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff) 3988 << 16); 3989 } 3990 if (ret_val) 3991 break; 3992 3993 /* If the word is 0x13, then make sure the signature bits 3994 * (15:14) are 11b until the commit has completed. 3995 * This will allow us to write 10b which indicates the 3996 * signature is valid. We want to do this after the write 3997 * has completed so that we don't mark the segment valid 3998 * while the write is still in progress 3999 */ 4000 if (i == E1000_ICH_NVM_SIG_WORD - 1) 4001 dword |= E1000_ICH_NVM_SIG_MASK << 16; 4002 4003 /* Convert offset to bytes. */ 4004 act_offset = (i + new_bank_offset) << 1; 4005 4006 usleep_range(100, 200); 4007 4008 /* Write the data to the new bank. Offset in words */ 4009 act_offset = i + new_bank_offset; 4010 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, 4011 dword); 4012 if (ret_val) 4013 break; 4014 } 4015 4016 /* Don't bother writing the segment valid bits if sector 4017 * programming failed. 4018 */ 4019 if (ret_val) { 4020 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ 4021 e_dbg("Flash commit failed.\n"); 4022 goto release; 4023 } 4024 4025 /* Finally validate the new segment by setting bit 15:14 4026 * to 10b in word 0x13 , this can be done without an 4027 * erase as well since these bits are 11 to start with 4028 * and we need to change bit 14 to 0b 4029 */ 4030 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 4031 4032 /*offset in words but we read dword */ 4033 --act_offset; 4034 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); 4035 4036 if (ret_val) 4037 goto release; 4038 4039 dword &= 0xBFFFFFFF; 4040 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); 4041 4042 if (ret_val) 4043 goto release; 4044 4045 /* offset in words but we read dword */ 4046 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1; 4047 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); 4048 4049 if (ret_val) 4050 goto release; 4051 4052 dword &= 0x00FFFFFF; 4053 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); 4054 4055 if (ret_val) 4056 goto release; 4057 4058 /* Great! Everything worked, we can now clear the cached entries. */ 4059 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 4060 dev_spec->shadow_ram[i].modified = false; 4061 dev_spec->shadow_ram[i].value = 0xFFFF; 4062 } 4063 4064 release: 4065 nvm->ops.release(hw); 4066 4067 /* Reload the EEPROM, or else modifications will not appear 4068 * until after the next adapter reset. 4069 */ 4070 if (!ret_val) { 4071 nvm->ops.reload(hw); 4072 usleep_range(10000, 11000); 4073 } 4074 4075 out: 4076 if (ret_val) 4077 e_dbg("NVM update error: %d\n", ret_val); 4078 4079 return ret_val; 4080 } 4081 4082 /** 4083 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM 4084 * @hw: pointer to the HW structure 4085 * 4086 * The NVM checksum is updated by calling the generic update_nvm_checksum, 4087 * which writes the checksum to the shadow ram. The changes in the shadow 4088 * ram are then committed to the EEPROM by processing each bank at a time 4089 * checking for the modified bit and writing only the pending changes. 4090 * After a successful commit, the shadow ram is cleared and is ready for 4091 * future writes. 4092 **/ 4093 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) 4094 { 4095 struct e1000_nvm_info *nvm = &hw->nvm; 4096 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 4097 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 4098 s32 ret_val; 4099 u16 data = 0; 4100 4101 ret_val = e1000e_update_nvm_checksum_generic(hw); 4102 if (ret_val) 4103 goto out; 4104 4105 if (nvm->type != e1000_nvm_flash_sw) 4106 goto out; 4107 4108 nvm->ops.acquire(hw); 4109 4110 /* We're writing to the opposite bank so if we're on bank 1, 4111 * write to bank 0 etc. We also need to erase the segment that 4112 * is going to be written 4113 */ 4114 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 4115 if (ret_val) { 4116 e_dbg("Could not detect valid bank, assuming bank 0\n"); 4117 bank = 0; 4118 } 4119 4120 if (bank == 0) { 4121 new_bank_offset = nvm->flash_bank_size; 4122 old_bank_offset = 0; 4123 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 4124 if (ret_val) 4125 goto release; 4126 } else { 4127 old_bank_offset = nvm->flash_bank_size; 4128 new_bank_offset = 0; 4129 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 4130 if (ret_val) 4131 goto release; 4132 } 4133 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 4134 if (dev_spec->shadow_ram[i].modified) { 4135 data = dev_spec->shadow_ram[i].value; 4136 } else { 4137 ret_val = e1000_read_flash_word_ich8lan(hw, i + 4138 old_bank_offset, 4139 &data); 4140 if (ret_val) 4141 break; 4142 } 4143 4144 /* If the word is 0x13, then make sure the signature bits 4145 * (15:14) are 11b until the commit has completed. 4146 * This will allow us to write 10b which indicates the 4147 * signature is valid. We want to do this after the write 4148 * has completed so that we don't mark the segment valid 4149 * while the write is still in progress 4150 */ 4151 if (i == E1000_ICH_NVM_SIG_WORD) 4152 data |= E1000_ICH_NVM_SIG_MASK; 4153 4154 /* Convert offset to bytes. */ 4155 act_offset = (i + new_bank_offset) << 1; 4156 4157 usleep_range(100, 200); 4158 /* Write the bytes to the new bank. */ 4159 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 4160 act_offset, 4161 (u8)data); 4162 if (ret_val) 4163 break; 4164 4165 usleep_range(100, 200); 4166 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 4167 act_offset + 1, 4168 (u8)(data >> 8)); 4169 if (ret_val) 4170 break; 4171 } 4172 4173 /* Don't bother writing the segment valid bits if sector 4174 * programming failed. 4175 */ 4176 if (ret_val) { 4177 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ 4178 e_dbg("Flash commit failed.\n"); 4179 goto release; 4180 } 4181 4182 /* Finally validate the new segment by setting bit 15:14 4183 * to 10b in word 0x13 , this can be done without an 4184 * erase as well since these bits are 11 to start with 4185 * and we need to change bit 14 to 0b 4186 */ 4187 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 4188 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); 4189 if (ret_val) 4190 goto release; 4191 4192 data &= 0xBFFF; 4193 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 4194 act_offset * 2 + 1, 4195 (u8)(data >> 8)); 4196 if (ret_val) 4197 goto release; 4198 4199 /* And invalidate the previously valid segment by setting 4200 * its signature word (0x13) high_byte to 0b. This can be 4201 * done without an erase because flash erase sets all bits 4202 * to 1's. We can write 1's to 0's without an erase 4203 */ 4204 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 4205 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); 4206 if (ret_val) 4207 goto release; 4208 4209 /* Great! Everything worked, we can now clear the cached entries. */ 4210 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 4211 dev_spec->shadow_ram[i].modified = false; 4212 dev_spec->shadow_ram[i].value = 0xFFFF; 4213 } 4214 4215 release: 4216 nvm->ops.release(hw); 4217 4218 /* Reload the EEPROM, or else modifications will not appear 4219 * until after the next adapter reset. 4220 */ 4221 if (!ret_val) { 4222 nvm->ops.reload(hw); 4223 usleep_range(10000, 11000); 4224 } 4225 4226 out: 4227 if (ret_val) 4228 e_dbg("NVM update error: %d\n", ret_val); 4229 4230 return ret_val; 4231 } 4232 4233 /** 4234 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum 4235 * @hw: pointer to the HW structure 4236 * 4237 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. 4238 * If the bit is 0, that the EEPROM had been modified, but the checksum was not 4239 * calculated, in which case we need to calculate the checksum and set bit 6. 4240 **/ 4241 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) 4242 { 4243 s32 ret_val; 4244 u16 data; 4245 u16 word; 4246 u16 valid_csum_mask; 4247 4248 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0, 4249 * the checksum needs to be fixed. This bit is an indication that 4250 * the NVM was prepared by OEM software and did not calculate 4251 * the checksum...a likely scenario. 4252 */ 4253 switch (hw->mac.type) { 4254 case e1000_pch_lpt: 4255 case e1000_pch_spt: 4256 case e1000_pch_cnp: 4257 case e1000_pch_tgp: 4258 case e1000_pch_adp: 4259 case e1000_pch_mtp: 4260 case e1000_pch_lnp: 4261 case e1000_pch_ptp: 4262 case e1000_pch_nvp: 4263 word = NVM_COMPAT; 4264 valid_csum_mask = NVM_COMPAT_VALID_CSUM; 4265 break; 4266 default: 4267 word = NVM_FUTURE_INIT_WORD1; 4268 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM; 4269 break; 4270 } 4271 4272 ret_val = e1000_read_nvm(hw, word, 1, &data); 4273 if (ret_val) 4274 return ret_val; 4275 4276 if (!(data & valid_csum_mask)) { 4277 e_dbg("NVM Checksum valid bit not set\n"); 4278 4279 if (hw->mac.type < e1000_pch_tgp) { 4280 data |= valid_csum_mask; 4281 ret_val = e1000_write_nvm(hw, word, 1, &data); 4282 if (ret_val) 4283 return ret_val; 4284 ret_val = e1000e_update_nvm_checksum(hw); 4285 if (ret_val) 4286 return ret_val; 4287 } else if (hw->mac.type == e1000_pch_tgp) { 4288 return 0; 4289 } 4290 } 4291 4292 return e1000e_validate_nvm_checksum_generic(hw); 4293 } 4294 4295 /** 4296 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only 4297 * @hw: pointer to the HW structure 4298 * 4299 * To prevent malicious write/erase of the NVM, set it to be read-only 4300 * so that the hardware ignores all write/erase cycles of the NVM via 4301 * the flash control registers. The shadow-ram copy of the NVM will 4302 * still be updated, however any updates to this copy will not stick 4303 * across driver reloads. 4304 **/ 4305 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw) 4306 { 4307 struct e1000_nvm_info *nvm = &hw->nvm; 4308 union ich8_flash_protected_range pr0; 4309 union ich8_hws_flash_status hsfsts; 4310 u32 gfpreg; 4311 4312 nvm->ops.acquire(hw); 4313 4314 gfpreg = er32flash(ICH_FLASH_GFPREG); 4315 4316 /* Write-protect GbE Sector of NVM */ 4317 pr0.regval = er32flash(ICH_FLASH_PR0); 4318 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK; 4319 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK); 4320 pr0.range.wpe = true; 4321 ew32flash(ICH_FLASH_PR0, pr0.regval); 4322 4323 /* Lock down a subset of GbE Flash Control Registers, e.g. 4324 * PR0 to prevent the write-protection from being lifted. 4325 * Once FLOCKDN is set, the registers protected by it cannot 4326 * be written until FLOCKDN is cleared by a hardware reset. 4327 */ 4328 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4329 hsfsts.hsf_status.flockdn = true; 4330 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval); 4331 4332 nvm->ops.release(hw); 4333 } 4334 4335 /** 4336 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM 4337 * @hw: pointer to the HW structure 4338 * @offset: The offset (in bytes) of the byte/word to read. 4339 * @size: Size of data to read, 1=byte 2=word 4340 * @data: The byte(s) to write to the NVM. 4341 * 4342 * Writes one/two bytes to the NVM using the flash access registers. 4343 **/ 4344 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 4345 u8 size, u16 data) 4346 { 4347 union ich8_hws_flash_status hsfsts; 4348 union ich8_hws_flash_ctrl hsflctl; 4349 u32 flash_linear_addr; 4350 u32 flash_data = 0; 4351 s32 ret_val; 4352 u8 count = 0; 4353 4354 if (hw->mac.type >= e1000_pch_spt) { 4355 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 4356 return -E1000_ERR_NVM; 4357 } else { 4358 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 4359 return -E1000_ERR_NVM; 4360 } 4361 4362 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 4363 hw->nvm.flash_base_addr); 4364 4365 do { 4366 udelay(1); 4367 /* Steps */ 4368 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4369 if (ret_val) 4370 break; 4371 /* In SPT, This register is in Lan memory space, not 4372 * flash. Therefore, only 32 bit access is supported 4373 */ 4374 if (hw->mac.type >= e1000_pch_spt) 4375 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; 4376 else 4377 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 4378 4379 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 4380 hsflctl.hsf_ctrl.fldbcount = size - 1; 4381 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 4382 /* In SPT, This register is in Lan memory space, 4383 * not flash. Therefore, only 32 bit access is 4384 * supported 4385 */ 4386 if (hw->mac.type >= e1000_pch_spt) 4387 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); 4388 else 4389 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 4390 4391 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 4392 4393 if (size == 1) 4394 flash_data = (u32)data & 0x00FF; 4395 else 4396 flash_data = (u32)data; 4397 4398 ew32flash(ICH_FLASH_FDATA0, flash_data); 4399 4400 /* check if FCERR is set to 1 , if set to 1, clear it 4401 * and try the whole sequence a few more times else done 4402 */ 4403 ret_val = 4404 e1000_flash_cycle_ich8lan(hw, 4405 ICH_FLASH_WRITE_COMMAND_TIMEOUT); 4406 if (!ret_val) 4407 break; 4408 4409 /* If we're here, then things are most likely 4410 * completely hosed, but if the error condition 4411 * is detected, it won't hurt to give it another 4412 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 4413 */ 4414 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4415 if (hsfsts.hsf_status.flcerr) 4416 /* Repeat for some time before giving up. */ 4417 continue; 4418 if (!hsfsts.hsf_status.flcdone) { 4419 e_dbg("Timeout error - flash cycle did not complete.\n"); 4420 break; 4421 } 4422 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 4423 4424 return ret_val; 4425 } 4426 4427 /** 4428 * e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM 4429 * @hw: pointer to the HW structure 4430 * @offset: The offset (in bytes) of the dwords to read. 4431 * @data: The 4 bytes to write to the NVM. 4432 * 4433 * Writes one/two/four bytes to the NVM using the flash access registers. 4434 **/ 4435 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 4436 u32 data) 4437 { 4438 union ich8_hws_flash_status hsfsts; 4439 union ich8_hws_flash_ctrl hsflctl; 4440 u32 flash_linear_addr; 4441 s32 ret_val; 4442 u8 count = 0; 4443 4444 if (hw->mac.type >= e1000_pch_spt) { 4445 if (offset > ICH_FLASH_LINEAR_ADDR_MASK) 4446 return -E1000_ERR_NVM; 4447 } 4448 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 4449 hw->nvm.flash_base_addr); 4450 do { 4451 udelay(1); 4452 /* Steps */ 4453 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4454 if (ret_val) 4455 break; 4456 4457 /* In SPT, This register is in Lan memory space, not 4458 * flash. Therefore, only 32 bit access is supported 4459 */ 4460 if (hw->mac.type >= e1000_pch_spt) 4461 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) 4462 >> 16; 4463 else 4464 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 4465 4466 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; 4467 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 4468 4469 /* In SPT, This register is in Lan memory space, 4470 * not flash. Therefore, only 32 bit access is 4471 * supported 4472 */ 4473 if (hw->mac.type >= e1000_pch_spt) 4474 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); 4475 else 4476 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 4477 4478 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 4479 4480 ew32flash(ICH_FLASH_FDATA0, data); 4481 4482 /* check if FCERR is set to 1 , if set to 1, clear it 4483 * and try the whole sequence a few more times else done 4484 */ 4485 ret_val = 4486 e1000_flash_cycle_ich8lan(hw, 4487 ICH_FLASH_WRITE_COMMAND_TIMEOUT); 4488 4489 if (!ret_val) 4490 break; 4491 4492 /* If we're here, then things are most likely 4493 * completely hosed, but if the error condition 4494 * is detected, it won't hurt to give it another 4495 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 4496 */ 4497 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4498 4499 if (hsfsts.hsf_status.flcerr) 4500 /* Repeat for some time before giving up. */ 4501 continue; 4502 if (!hsfsts.hsf_status.flcdone) { 4503 e_dbg("Timeout error - flash cycle did not complete.\n"); 4504 break; 4505 } 4506 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 4507 4508 return ret_val; 4509 } 4510 4511 /** 4512 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM 4513 * @hw: pointer to the HW structure 4514 * @offset: The index of the byte to read. 4515 * @data: The byte to write to the NVM. 4516 * 4517 * Writes a single byte to the NVM using the flash access registers. 4518 **/ 4519 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 4520 u8 data) 4521 { 4522 u16 word = (u16)data; 4523 4524 return e1000_write_flash_data_ich8lan(hw, offset, 1, word); 4525 } 4526 4527 /** 4528 * e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM 4529 * @hw: pointer to the HW structure 4530 * @offset: The offset of the word to write. 4531 * @dword: The dword to write to the NVM. 4532 * 4533 * Writes a single dword to the NVM using the flash access registers. 4534 * Goes through a retry algorithm before giving up. 4535 **/ 4536 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw, 4537 u32 offset, u32 dword) 4538 { 4539 s32 ret_val; 4540 u16 program_retries; 4541 4542 /* Must convert word offset into bytes. */ 4543 offset <<= 1; 4544 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); 4545 4546 if (!ret_val) 4547 return ret_val; 4548 for (program_retries = 0; program_retries < 100; program_retries++) { 4549 e_dbg("Retrying Byte %8.8X at offset %u\n", dword, offset); 4550 usleep_range(100, 200); 4551 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); 4552 if (!ret_val) 4553 break; 4554 } 4555 if (program_retries == 100) 4556 return -E1000_ERR_NVM; 4557 4558 return 0; 4559 } 4560 4561 /** 4562 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM 4563 * @hw: pointer to the HW structure 4564 * @offset: The offset of the byte to write. 4565 * @byte: The byte to write to the NVM. 4566 * 4567 * Writes a single byte to the NVM using the flash access registers. 4568 * Goes through a retry algorithm before giving up. 4569 **/ 4570 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 4571 u32 offset, u8 byte) 4572 { 4573 s32 ret_val; 4574 u16 program_retries; 4575 4576 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 4577 if (!ret_val) 4578 return ret_val; 4579 4580 for (program_retries = 0; program_retries < 100; program_retries++) { 4581 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset); 4582 usleep_range(100, 200); 4583 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 4584 if (!ret_val) 4585 break; 4586 } 4587 if (program_retries == 100) 4588 return -E1000_ERR_NVM; 4589 4590 return 0; 4591 } 4592 4593 /** 4594 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM 4595 * @hw: pointer to the HW structure 4596 * @bank: 0 for first bank, 1 for second bank, etc. 4597 * 4598 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. 4599 * bank N is 4096 * N + flash_reg_addr. 4600 **/ 4601 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) 4602 { 4603 struct e1000_nvm_info *nvm = &hw->nvm; 4604 union ich8_hws_flash_status hsfsts; 4605 union ich8_hws_flash_ctrl hsflctl; 4606 u32 flash_linear_addr; 4607 /* bank size is in 16bit words - adjust to bytes */ 4608 u32 flash_bank_size = nvm->flash_bank_size * 2; 4609 s32 ret_val; 4610 s32 count = 0; 4611 s32 j, iteration, sector_size; 4612 4613 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4614 4615 /* Determine HW Sector size: Read BERASE bits of hw flash status 4616 * register 4617 * 00: The Hw sector is 256 bytes, hence we need to erase 16 4618 * consecutive sectors. The start index for the nth Hw sector 4619 * can be calculated as = bank * 4096 + n * 256 4620 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. 4621 * The start index for the nth Hw sector can be calculated 4622 * as = bank * 4096 4623 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 4624 * (ich9 only, otherwise error condition) 4625 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 4626 */ 4627 switch (hsfsts.hsf_status.berasesz) { 4628 case 0: 4629 /* Hw sector size 256 */ 4630 sector_size = ICH_FLASH_SEG_SIZE_256; 4631 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; 4632 break; 4633 case 1: 4634 sector_size = ICH_FLASH_SEG_SIZE_4K; 4635 iteration = 1; 4636 break; 4637 case 2: 4638 sector_size = ICH_FLASH_SEG_SIZE_8K; 4639 iteration = 1; 4640 break; 4641 case 3: 4642 sector_size = ICH_FLASH_SEG_SIZE_64K; 4643 iteration = 1; 4644 break; 4645 default: 4646 return -E1000_ERR_NVM; 4647 } 4648 4649 /* Start with the base address, then add the sector offset. */ 4650 flash_linear_addr = hw->nvm.flash_base_addr; 4651 flash_linear_addr += (bank) ? flash_bank_size : 0; 4652 4653 for (j = 0; j < iteration; j++) { 4654 do { 4655 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT; 4656 4657 /* Steps */ 4658 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4659 if (ret_val) 4660 return ret_val; 4661 4662 /* Write a value 11 (block Erase) in Flash 4663 * Cycle field in hw flash control 4664 */ 4665 if (hw->mac.type >= e1000_pch_spt) 4666 hsflctl.regval = 4667 er32flash(ICH_FLASH_HSFSTS) >> 16; 4668 else 4669 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 4670 4671 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 4672 if (hw->mac.type >= e1000_pch_spt) 4673 ew32flash(ICH_FLASH_HSFSTS, 4674 hsflctl.regval << 16); 4675 else 4676 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 4677 4678 /* Write the last 24 bits of an index within the 4679 * block into Flash Linear address field in Flash 4680 * Address. 4681 */ 4682 flash_linear_addr += (j * sector_size); 4683 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 4684 4685 ret_val = e1000_flash_cycle_ich8lan(hw, timeout); 4686 if (!ret_val) 4687 break; 4688 4689 /* Check if FCERR is set to 1. If 1, 4690 * clear it and try the whole sequence 4691 * a few more times else Done 4692 */ 4693 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4694 if (hsfsts.hsf_status.flcerr) 4695 /* repeat for some time before giving up */ 4696 continue; 4697 else if (!hsfsts.hsf_status.flcdone) 4698 return ret_val; 4699 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); 4700 } 4701 4702 return 0; 4703 } 4704 4705 /** 4706 * e1000_valid_led_default_ich8lan - Set the default LED settings 4707 * @hw: pointer to the HW structure 4708 * @data: Pointer to the LED settings 4709 * 4710 * Reads the LED default settings from the NVM to data. If the NVM LED 4711 * settings is all 0's or F's, set the LED default to a valid LED default 4712 * setting. 4713 **/ 4714 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) 4715 { 4716 s32 ret_val; 4717 4718 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); 4719 if (ret_val) { 4720 e_dbg("NVM Read Error\n"); 4721 return ret_val; 4722 } 4723 4724 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 4725 *data = ID_LED_DEFAULT_ICH8LAN; 4726 4727 return 0; 4728 } 4729 4730 /** 4731 * e1000_id_led_init_pchlan - store LED configurations 4732 * @hw: pointer to the HW structure 4733 * 4734 * PCH does not control LEDs via the LEDCTL register, rather it uses 4735 * the PHY LED configuration register. 4736 * 4737 * PCH also does not have an "always on" or "always off" mode which 4738 * complicates the ID feature. Instead of using the "on" mode to indicate 4739 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()), 4740 * use "link_up" mode. The LEDs will still ID on request if there is no 4741 * link based on logic in e1000_led_[on|off]_pchlan(). 4742 **/ 4743 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) 4744 { 4745 struct e1000_mac_info *mac = &hw->mac; 4746 s32 ret_val; 4747 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP; 4748 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT; 4749 u16 data, i, temp, shift; 4750 4751 /* Get default ID LED modes */ 4752 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 4753 if (ret_val) 4754 return ret_val; 4755 4756 mac->ledctl_default = er32(LEDCTL); 4757 mac->ledctl_mode1 = mac->ledctl_default; 4758 mac->ledctl_mode2 = mac->ledctl_default; 4759 4760 for (i = 0; i < 4; i++) { 4761 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK; 4762 shift = (i * 5); 4763 switch (temp) { 4764 case ID_LED_ON1_DEF2: 4765 case ID_LED_ON1_ON2: 4766 case ID_LED_ON1_OFF2: 4767 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 4768 mac->ledctl_mode1 |= (ledctl_on << shift); 4769 break; 4770 case ID_LED_OFF1_DEF2: 4771 case ID_LED_OFF1_ON2: 4772 case ID_LED_OFF1_OFF2: 4773 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 4774 mac->ledctl_mode1 |= (ledctl_off << shift); 4775 break; 4776 default: 4777 /* Do nothing */ 4778 break; 4779 } 4780 switch (temp) { 4781 case ID_LED_DEF1_ON2: 4782 case ID_LED_ON1_ON2: 4783 case ID_LED_OFF1_ON2: 4784 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 4785 mac->ledctl_mode2 |= (ledctl_on << shift); 4786 break; 4787 case ID_LED_DEF1_OFF2: 4788 case ID_LED_ON1_OFF2: 4789 case ID_LED_OFF1_OFF2: 4790 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 4791 mac->ledctl_mode2 |= (ledctl_off << shift); 4792 break; 4793 default: 4794 /* Do nothing */ 4795 break; 4796 } 4797 } 4798 4799 return 0; 4800 } 4801 4802 /** 4803 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width 4804 * @hw: pointer to the HW structure 4805 * 4806 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability 4807 * register, so the bus width is hard coded. 4808 **/ 4809 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) 4810 { 4811 struct e1000_bus_info *bus = &hw->bus; 4812 s32 ret_val; 4813 4814 ret_val = e1000e_get_bus_info_pcie(hw); 4815 4816 /* ICH devices are "PCI Express"-ish. They have 4817 * a configuration space, but do not contain 4818 * PCI Express Capability registers, so bus width 4819 * must be hardcoded. 4820 */ 4821 if (bus->width == e1000_bus_width_unknown) 4822 bus->width = e1000_bus_width_pcie_x1; 4823 4824 return ret_val; 4825 } 4826 4827 /** 4828 * e1000_reset_hw_ich8lan - Reset the hardware 4829 * @hw: pointer to the HW structure 4830 * 4831 * Does a full reset of the hardware which includes a reset of the PHY and 4832 * MAC. 4833 **/ 4834 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) 4835 { 4836 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 4837 u16 kum_cfg; 4838 u32 ctrl, reg; 4839 s32 ret_val; 4840 4841 /* Prevent the PCI-E bus from sticking if there is no TLP connection 4842 * on the last TLP read/write transaction when MAC is reset. 4843 */ 4844 ret_val = e1000e_disable_pcie_master(hw); 4845 if (ret_val) 4846 e_dbg("PCI-E Master disable polling has failed.\n"); 4847 4848 e_dbg("Masking off all interrupts\n"); 4849 ew32(IMC, 0xffffffff); 4850 4851 /* Disable the Transmit and Receive units. Then delay to allow 4852 * any pending transactions to complete before we hit the MAC 4853 * with the global reset. 4854 */ 4855 ew32(RCTL, 0); 4856 ew32(TCTL, E1000_TCTL_PSP); 4857 e1e_flush(); 4858 4859 usleep_range(10000, 11000); 4860 4861 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 4862 if (hw->mac.type == e1000_ich8lan) { 4863 /* Set Tx and Rx buffer allocation to 8k apiece. */ 4864 ew32(PBA, E1000_PBA_8K); 4865 /* Set Packet Buffer Size to 16k. */ 4866 ew32(PBS, E1000_PBS_16K); 4867 } 4868 4869 if (hw->mac.type == e1000_pchlan) { 4870 /* Save the NVM K1 bit setting */ 4871 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg); 4872 if (ret_val) 4873 return ret_val; 4874 4875 if (kum_cfg & E1000_NVM_K1_ENABLE) 4876 dev_spec->nvm_k1_enabled = true; 4877 else 4878 dev_spec->nvm_k1_enabled = false; 4879 } 4880 4881 ctrl = er32(CTRL); 4882 4883 if (!hw->phy.ops.check_reset_block(hw)) { 4884 /* Full-chip reset requires MAC and PHY reset at the same 4885 * time to make sure the interface between MAC and the 4886 * external PHY is reset. 4887 */ 4888 ctrl |= E1000_CTRL_PHY_RST; 4889 4890 /* Gate automatic PHY configuration by hardware on 4891 * non-managed 82579 4892 */ 4893 if ((hw->mac.type == e1000_pch2lan) && 4894 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 4895 e1000_gate_hw_phy_config_ich8lan(hw, true); 4896 } 4897 ret_val = e1000_acquire_swflag_ich8lan(hw); 4898 e_dbg("Issuing a global reset to ich8lan\n"); 4899 ew32(CTRL, (ctrl | E1000_CTRL_RST)); 4900 /* cannot issue a flush here because it hangs the hardware */ 4901 msleep(20); 4902 4903 /* Set Phy Config Counter to 50msec */ 4904 if (hw->mac.type == e1000_pch2lan) { 4905 reg = er32(FEXTNVM3); 4906 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 4907 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 4908 ew32(FEXTNVM3, reg); 4909 } 4910 4911 if (!ret_val) 4912 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 4913 4914 if (ctrl & E1000_CTRL_PHY_RST) { 4915 ret_val = hw->phy.ops.get_cfg_done(hw); 4916 if (ret_val) 4917 return ret_val; 4918 4919 ret_val = e1000_post_phy_reset_ich8lan(hw); 4920 if (ret_val) 4921 return ret_val; 4922 } 4923 4924 /* For PCH, this write will make sure that any noise 4925 * will be detected as a CRC error and be dropped rather than show up 4926 * as a bad packet to the DMA engine. 4927 */ 4928 if (hw->mac.type == e1000_pchlan) 4929 ew32(CRC_OFFSET, 0x65656565); 4930 4931 ew32(IMC, 0xffffffff); 4932 er32(ICR); 4933 4934 reg = er32(KABGTXD); 4935 reg |= E1000_KABGTXD_BGSQLBIAS; 4936 ew32(KABGTXD, reg); 4937 4938 /* The hardware reset value of the DPG_EN bit is 1. 4939 * Clear DPG_EN to prevent unexpected autonomous power gating. 4940 */ 4941 if (hw->mac.type >= e1000_pch_ptp) { 4942 reg = er32(CTRL_EXT); 4943 reg &= ~E1000_CTRL_EXT_DPG_EN; 4944 ew32(CTRL_EXT, reg); 4945 } 4946 4947 return 0; 4948 } 4949 4950 /** 4951 * e1000_init_hw_ich8lan - Initialize the hardware 4952 * @hw: pointer to the HW structure 4953 * 4954 * Prepares the hardware for transmit and receive by doing the following: 4955 * - initialize hardware bits 4956 * - initialize LED identification 4957 * - setup receive address registers 4958 * - setup flow control 4959 * - setup transmit descriptors 4960 * - clear statistics 4961 **/ 4962 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) 4963 { 4964 struct e1000_mac_info *mac = &hw->mac; 4965 u32 ctrl_ext, txdctl, snoop, fflt_dbg; 4966 s32 ret_val; 4967 u16 i; 4968 4969 e1000_initialize_hw_bits_ich8lan(hw); 4970 ret_val = hw->phy.ops.acquire(hw); 4971 if (ret_val) 4972 return ret_val; 4973 4974 ret_val = e1000_reconfigure_k1_params(hw); 4975 hw->phy.ops.release(hw); 4976 if (ret_val) { 4977 e_dbg("Error failed to reconfigure K1 parameters\n"); 4978 return ret_val; 4979 } 4980 4981 /* Initialize identification LED */ 4982 ret_val = mac->ops.id_led_init(hw); 4983 /* An error is not fatal and we should not stop init due to this */ 4984 if (ret_val) 4985 e_dbg("Error initializing identification LED\n"); 4986 4987 /* Setup the receive address. */ 4988 e1000e_init_rx_addrs(hw, mac->rar_entry_count); 4989 4990 /* Zero out the Multicast HASH table */ 4991 e_dbg("Zeroing the MTA\n"); 4992 for (i = 0; i < mac->mta_reg_count; i++) 4993 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 4994 4995 /* The 82578 Rx buffer will stall if wakeup is enabled in host and 4996 * the ME. Disable wakeup by clearing the host wakeup bit. 4997 * Reset the phy after disabling host wakeup to reset the Rx buffer. 4998 */ 4999 if (hw->phy.type == e1000_phy_82578) { 5000 e1e_rphy(hw, BM_PORT_GEN_CFG, &i); 5001 i &= ~BM_WUC_HOST_WU_BIT; 5002 e1e_wphy(hw, BM_PORT_GEN_CFG, i); 5003 ret_val = e1000_phy_hw_reset_ich8lan(hw); 5004 if (ret_val) 5005 return ret_val; 5006 } 5007 5008 /* Setup link and flow control */ 5009 ret_val = mac->ops.setup_link(hw); 5010 5011 /* Set the transmit descriptor write-back policy for both queues */ 5012 txdctl = er32(TXDCTL(0)); 5013 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | 5014 E1000_TXDCTL_FULL_TX_DESC_WB); 5015 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | 5016 E1000_TXDCTL_MAX_TX_DESC_PREFETCH); 5017 ew32(TXDCTL(0), txdctl); 5018 txdctl = er32(TXDCTL(1)); 5019 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | 5020 E1000_TXDCTL_FULL_TX_DESC_WB); 5021 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | 5022 E1000_TXDCTL_MAX_TX_DESC_PREFETCH); 5023 ew32(TXDCTL(1), txdctl); 5024 5025 /* ICH8 has opposite polarity of no_snoop bits. 5026 * By default, we should use snoop behavior. 5027 */ 5028 if (mac->type == e1000_ich8lan) 5029 snoop = PCIE_ICH8_SNOOP_ALL; 5030 else 5031 snoop = (u32)~(PCIE_NO_SNOOP_ALL); 5032 e1000e_set_pcie_no_snoop(hw, snoop); 5033 5034 /* Enable workaround for packet loss issue on TGP PCH 5035 * Do not gate DMA clock from the modPHY block 5036 */ 5037 if (mac->type >= e1000_pch_tgp) { 5038 fflt_dbg = er32(FFLT_DBG); 5039 fflt_dbg |= E1000_FFLT_DBG_DONT_GATE_WAKE_DMA_CLK; 5040 ew32(FFLT_DBG, fflt_dbg); 5041 } 5042 5043 ctrl_ext = er32(CTRL_EXT); 5044 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 5045 ew32(CTRL_EXT, ctrl_ext); 5046 5047 /* Clear all of the statistics registers (clear on read). It is 5048 * important that we do this after we have tried to establish link 5049 * because the symbol error count will increment wildly if there 5050 * is no link. 5051 */ 5052 e1000_clear_hw_cntrs_ich8lan(hw); 5053 5054 return ret_val; 5055 } 5056 5057 /** 5058 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits 5059 * @hw: pointer to the HW structure 5060 * 5061 * Sets/Clears required hardware bits necessary for correctly setting up the 5062 * hardware for transmit and receive. 5063 **/ 5064 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) 5065 { 5066 u32 reg; 5067 5068 /* Extended Device Control */ 5069 reg = er32(CTRL_EXT); 5070 reg |= BIT(22); 5071 /* Enable PHY low-power state when MAC is at D3 w/o WoL */ 5072 if (hw->mac.type >= e1000_pchlan) 5073 reg |= E1000_CTRL_EXT_PHYPDEN; 5074 ew32(CTRL_EXT, reg); 5075 5076 /* Transmit Descriptor Control 0 */ 5077 reg = er32(TXDCTL(0)); 5078 reg |= BIT(22); 5079 ew32(TXDCTL(0), reg); 5080 5081 /* Transmit Descriptor Control 1 */ 5082 reg = er32(TXDCTL(1)); 5083 reg |= BIT(22); 5084 ew32(TXDCTL(1), reg); 5085 5086 /* Transmit Arbitration Control 0 */ 5087 reg = er32(TARC(0)); 5088 if (hw->mac.type == e1000_ich8lan) 5089 reg |= BIT(28) | BIT(29); 5090 reg |= BIT(23) | BIT(24) | BIT(26) | BIT(27); 5091 ew32(TARC(0), reg); 5092 5093 /* Transmit Arbitration Control 1 */ 5094 reg = er32(TARC(1)); 5095 if (er32(TCTL) & E1000_TCTL_MULR) 5096 reg &= ~BIT(28); 5097 else 5098 reg |= BIT(28); 5099 reg |= BIT(24) | BIT(26) | BIT(30); 5100 ew32(TARC(1), reg); 5101 5102 /* Device Status */ 5103 if (hw->mac.type == e1000_ich8lan) { 5104 reg = er32(STATUS); 5105 reg &= ~BIT(31); 5106 ew32(STATUS, reg); 5107 } 5108 5109 /* work-around descriptor data corruption issue during nfs v2 udp 5110 * traffic, just disable the nfs filtering capability 5111 */ 5112 reg = er32(RFCTL); 5113 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS); 5114 5115 /* Disable IPv6 extension header parsing because some malformed 5116 * IPv6 headers can hang the Rx. 5117 */ 5118 if (hw->mac.type == e1000_ich8lan) 5119 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); 5120 ew32(RFCTL, reg); 5121 5122 /* Enable ECC on Lynxpoint */ 5123 if (hw->mac.type >= e1000_pch_lpt) { 5124 reg = er32(PBECCSTS); 5125 reg |= E1000_PBECCSTS_ECC_ENABLE; 5126 ew32(PBECCSTS, reg); 5127 5128 reg = er32(CTRL); 5129 reg |= E1000_CTRL_MEHE; 5130 ew32(CTRL, reg); 5131 } 5132 } 5133 5134 /** 5135 * e1000_setup_link_ich8lan - Setup flow control and link settings 5136 * @hw: pointer to the HW structure 5137 * 5138 * Determines which flow control settings to use, then configures flow 5139 * control. Calls the appropriate media-specific link configuration 5140 * function. Assuming the adapter has a valid link partner, a valid link 5141 * should be established. Assumes the hardware has previously been reset 5142 * and the transmitter and receiver are not enabled. 5143 **/ 5144 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) 5145 { 5146 s32 ret_val; 5147 5148 if (hw->phy.ops.check_reset_block(hw)) 5149 return 0; 5150 5151 /* ICH parts do not have a word in the NVM to determine 5152 * the default flow control setting, so we explicitly 5153 * set it to full. 5154 */ 5155 if (hw->fc.requested_mode == e1000_fc_default) { 5156 /* Workaround h/w hang when Tx flow control enabled */ 5157 if (hw->mac.type == e1000_pchlan) 5158 hw->fc.requested_mode = e1000_fc_rx_pause; 5159 else 5160 hw->fc.requested_mode = e1000_fc_full; 5161 } 5162 5163 /* Save off the requested flow control mode for use later. Depending 5164 * on the link partner's capabilities, we may or may not use this mode. 5165 */ 5166 hw->fc.current_mode = hw->fc.requested_mode; 5167 5168 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode); 5169 5170 /* Continue to configure the copper link. */ 5171 ret_val = hw->mac.ops.setup_physical_interface(hw); 5172 if (ret_val) 5173 return ret_val; 5174 5175 ew32(FCTTV, hw->fc.pause_time); 5176 if ((hw->phy.type == e1000_phy_82578) || 5177 (hw->phy.type == e1000_phy_82579) || 5178 (hw->phy.type == e1000_phy_i217) || 5179 (hw->phy.type == e1000_phy_82577)) { 5180 ew32(FCRTV_PCH, hw->fc.refresh_time); 5181 5182 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27), 5183 hw->fc.pause_time); 5184 if (ret_val) 5185 return ret_val; 5186 } 5187 5188 return e1000e_set_fc_watermarks(hw); 5189 } 5190 5191 /** 5192 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface 5193 * @hw: pointer to the HW structure 5194 * 5195 * Configures the kumeran interface to the PHY to wait the appropriate time 5196 * when polling the PHY, then call the generic setup_copper_link to finish 5197 * configuring the copper link. 5198 **/ 5199 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) 5200 { 5201 u32 ctrl; 5202 s32 ret_val; 5203 u16 reg_data; 5204 5205 ctrl = er32(CTRL); 5206 ctrl |= E1000_CTRL_SLU; 5207 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 5208 ew32(CTRL, ctrl); 5209 5210 /* Set the mac to wait the maximum time between each iteration 5211 * and increase the max iterations when polling the phy; 5212 * this fixes erroneous timeouts at 10Mbps. 5213 */ 5214 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF); 5215 if (ret_val) 5216 return ret_val; 5217 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 5218 ®_data); 5219 if (ret_val) 5220 return ret_val; 5221 reg_data |= 0x3F; 5222 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 5223 reg_data); 5224 if (ret_val) 5225 return ret_val; 5226 5227 switch (hw->phy.type) { 5228 case e1000_phy_igp_3: 5229 ret_val = e1000e_copper_link_setup_igp(hw); 5230 if (ret_val) 5231 return ret_val; 5232 break; 5233 case e1000_phy_bm: 5234 case e1000_phy_82578: 5235 ret_val = e1000e_copper_link_setup_m88(hw); 5236 if (ret_val) 5237 return ret_val; 5238 break; 5239 case e1000_phy_82577: 5240 case e1000_phy_82579: 5241 ret_val = e1000_copper_link_setup_82577(hw); 5242 if (ret_val) 5243 return ret_val; 5244 break; 5245 case e1000_phy_ife: 5246 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, ®_data); 5247 if (ret_val) 5248 return ret_val; 5249 5250 reg_data &= ~IFE_PMC_AUTO_MDIX; 5251 5252 switch (hw->phy.mdix) { 5253 case 1: 5254 reg_data &= ~IFE_PMC_FORCE_MDIX; 5255 break; 5256 case 2: 5257 reg_data |= IFE_PMC_FORCE_MDIX; 5258 break; 5259 case 0: 5260 default: 5261 reg_data |= IFE_PMC_AUTO_MDIX; 5262 break; 5263 } 5264 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data); 5265 if (ret_val) 5266 return ret_val; 5267 break; 5268 default: 5269 break; 5270 } 5271 5272 return e1000e_setup_copper_link(hw); 5273 } 5274 5275 /** 5276 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface 5277 * @hw: pointer to the HW structure 5278 * 5279 * Calls the PHY specific link setup function and then calls the 5280 * generic setup_copper_link to finish configuring the link for 5281 * Lynxpoint PCH devices 5282 **/ 5283 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw) 5284 { 5285 u32 ctrl; 5286 s32 ret_val; 5287 5288 ctrl = er32(CTRL); 5289 ctrl |= E1000_CTRL_SLU; 5290 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 5291 ew32(CTRL, ctrl); 5292 5293 ret_val = e1000_copper_link_setup_82577(hw); 5294 if (ret_val) 5295 return ret_val; 5296 5297 return e1000e_setup_copper_link(hw); 5298 } 5299 5300 /** 5301 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex 5302 * @hw: pointer to the HW structure 5303 * @speed: pointer to store current link speed 5304 * @duplex: pointer to store the current link duplex 5305 * 5306 * Calls the generic get_speed_and_duplex to retrieve the current link 5307 * information and then calls the Kumeran lock loss workaround for links at 5308 * gigabit speeds. 5309 **/ 5310 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, 5311 u16 *duplex) 5312 { 5313 s32 ret_val; 5314 5315 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex); 5316 if (ret_val) 5317 return ret_val; 5318 5319 if ((hw->mac.type == e1000_ich8lan) && 5320 (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) { 5321 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); 5322 } 5323 5324 return ret_val; 5325 } 5326 5327 /** 5328 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround 5329 * @hw: pointer to the HW structure 5330 * 5331 * Work-around for 82566 Kumeran PCS lock loss: 5332 * On link status change (i.e. PCI reset, speed change) and link is up and 5333 * speed is gigabit- 5334 * 0) if workaround is optionally disabled do nothing 5335 * 1) wait 1ms for Kumeran link to come up 5336 * 2) check Kumeran Diagnostic register PCS lock loss bit 5337 * 3) if not set the link is locked (all is good), otherwise... 5338 * 4) reset the PHY 5339 * 5) repeat up to 10 times 5340 * Note: this is only called for IGP3 copper when speed is 1gb. 5341 **/ 5342 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) 5343 { 5344 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5345 u32 phy_ctrl; 5346 s32 ret_val; 5347 u16 i, data; 5348 bool link; 5349 5350 if (!dev_spec->kmrn_lock_loss_workaround_enabled) 5351 return 0; 5352 5353 /* Make sure link is up before proceeding. If not just return. 5354 * Attempting this while link is negotiating fouled up link 5355 * stability 5356 */ 5357 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 5358 if (!link) 5359 return 0; 5360 5361 for (i = 0; i < 10; i++) { 5362 /* read once to clear */ 5363 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); 5364 if (ret_val) 5365 return ret_val; 5366 /* and again to get new status */ 5367 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); 5368 if (ret_val) 5369 return ret_val; 5370 5371 /* check for PCS lock */ 5372 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) 5373 return 0; 5374 5375 /* Issue PHY reset */ 5376 e1000_phy_hw_reset(hw); 5377 mdelay(5); 5378 } 5379 /* Disable GigE link negotiation */ 5380 phy_ctrl = er32(PHY_CTRL); 5381 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | 5382 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5383 ew32(PHY_CTRL, phy_ctrl); 5384 5385 /* Call gig speed drop workaround on Gig disable before accessing 5386 * any PHY registers 5387 */ 5388 e1000e_gig_downshift_workaround_ich8lan(hw); 5389 5390 /* unable to acquire PCS lock */ 5391 return -E1000_ERR_PHY; 5392 } 5393 5394 /** 5395 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state 5396 * @hw: pointer to the HW structure 5397 * @state: boolean value used to set the current Kumeran workaround state 5398 * 5399 * If ICH8, set the current Kumeran workaround state (enabled - true 5400 * /disabled - false). 5401 **/ 5402 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 5403 bool state) 5404 { 5405 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5406 5407 if (hw->mac.type != e1000_ich8lan) { 5408 e_dbg("Workaround applies to ICH8 only.\n"); 5409 return; 5410 } 5411 5412 dev_spec->kmrn_lock_loss_workaround_enabled = state; 5413 } 5414 5415 /** 5416 * e1000e_igp3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 5417 * @hw: pointer to the HW structure 5418 * 5419 * Workaround for 82566 power-down on D3 entry: 5420 * 1) disable gigabit link 5421 * 2) write VR power-down enable 5422 * 3) read it back 5423 * Continue if successful, else issue LCD reset and repeat 5424 **/ 5425 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) 5426 { 5427 u32 reg; 5428 u16 data; 5429 u8 retry = 0; 5430 5431 if (hw->phy.type != e1000_phy_igp_3) 5432 return; 5433 5434 /* Try the workaround twice (if needed) */ 5435 do { 5436 /* Disable link */ 5437 reg = er32(PHY_CTRL); 5438 reg |= (E1000_PHY_CTRL_GBE_DISABLE | 5439 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5440 ew32(PHY_CTRL, reg); 5441 5442 /* Call gig speed drop workaround on Gig disable before 5443 * accessing any PHY registers 5444 */ 5445 if (hw->mac.type == e1000_ich8lan) 5446 e1000e_gig_downshift_workaround_ich8lan(hw); 5447 5448 /* Write VR power-down enable */ 5449 e1e_rphy(hw, IGP3_VR_CTRL, &data); 5450 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 5451 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN); 5452 5453 /* Read it back and test */ 5454 e1e_rphy(hw, IGP3_VR_CTRL, &data); 5455 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 5456 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) 5457 break; 5458 5459 /* Issue PHY reset and repeat at most one more time */ 5460 reg = er32(CTRL); 5461 ew32(CTRL, reg | E1000_CTRL_PHY_RST); 5462 retry++; 5463 } while (retry); 5464 } 5465 5466 /** 5467 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working 5468 * @hw: pointer to the HW structure 5469 * 5470 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), 5471 * LPLU, Gig disable, MDIC PHY reset): 5472 * 1) Set Kumeran Near-end loopback 5473 * 2) Clear Kumeran Near-end loopback 5474 * Should only be called for ICH8[m] devices with any 1G Phy. 5475 **/ 5476 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) 5477 { 5478 s32 ret_val; 5479 u16 reg_data; 5480 5481 if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife)) 5482 return; 5483 5484 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 5485 ®_data); 5486 if (ret_val) 5487 return; 5488 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; 5489 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 5490 reg_data); 5491 if (ret_val) 5492 return; 5493 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; 5494 e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data); 5495 } 5496 5497 /** 5498 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx 5499 * @hw: pointer to the HW structure 5500 * 5501 * During S0 to Sx transition, it is possible the link remains at gig 5502 * instead of negotiating to a lower speed. Before going to Sx, set 5503 * 'Gig Disable' to force link speed negotiation to a lower speed based on 5504 * the LPLU setting in the NVM or custom setting. For PCH and newer parts, 5505 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also 5506 * needs to be written. 5507 * Parts that support (and are linked to a partner which support) EEE in 5508 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power 5509 * than 10Mbps w/o EEE. 5510 **/ 5511 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw) 5512 { 5513 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5514 u32 phy_ctrl; 5515 s32 ret_val; 5516 5517 phy_ctrl = er32(PHY_CTRL); 5518 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE; 5519 5520 if (hw->phy.type == e1000_phy_i217) { 5521 u16 phy_reg, device_id = hw->adapter->pdev->device; 5522 5523 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 5524 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) || 5525 (device_id == E1000_DEV_ID_PCH_I218_LM3) || 5526 (device_id == E1000_DEV_ID_PCH_I218_V3) || 5527 (hw->mac.type >= e1000_pch_spt)) { 5528 u32 fextnvm6 = er32(FEXTNVM6); 5529 5530 ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK); 5531 } 5532 5533 ret_val = hw->phy.ops.acquire(hw); 5534 if (ret_val) 5535 goto out; 5536 5537 if (!dev_spec->eee_disable) { 5538 u16 eee_advert; 5539 5540 ret_val = 5541 e1000_read_emi_reg_locked(hw, 5542 I217_EEE_ADVERTISEMENT, 5543 &eee_advert); 5544 if (ret_val) 5545 goto release; 5546 5547 /* Disable LPLU if both link partners support 100BaseT 5548 * EEE and 100Full is advertised on both ends of the 5549 * link, and enable Auto Enable LPI since there will 5550 * be no driver to enable LPI while in Sx. 5551 */ 5552 if ((eee_advert & I82579_EEE_100_SUPPORTED) && 5553 (dev_spec->eee_lp_ability & 5554 I82579_EEE_100_SUPPORTED) && 5555 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) { 5556 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU | 5557 E1000_PHY_CTRL_NOND0A_LPLU); 5558 5559 /* Set Auto Enable LPI after link up */ 5560 e1e_rphy_locked(hw, 5561 I217_LPI_GPIO_CTRL, &phy_reg); 5562 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI; 5563 e1e_wphy_locked(hw, 5564 I217_LPI_GPIO_CTRL, phy_reg); 5565 } 5566 } 5567 5568 /* For i217 Intel Rapid Start Technology support, 5569 * when the system is going into Sx and no manageability engine 5570 * is present, the driver must configure proxy to reset only on 5571 * power good. LPI (Low Power Idle) state must also reset only 5572 * on power good, as well as the MTA (Multicast table array). 5573 * The SMBus release must also be disabled on LCD reset. 5574 */ 5575 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 5576 /* Enable proxy to reset only on power good. */ 5577 e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg); 5578 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE; 5579 e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg); 5580 5581 /* Set bit enable LPI (EEE) to reset only on 5582 * power good. 5583 */ 5584 e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg); 5585 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET; 5586 e1e_wphy_locked(hw, I217_SxCTRL, phy_reg); 5587 5588 /* Disable the SMB release on LCD reset. */ 5589 e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg); 5590 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE; 5591 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg); 5592 } 5593 5594 /* Enable MTA to reset for Intel Rapid Start Technology 5595 * Support 5596 */ 5597 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg); 5598 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET; 5599 e1e_wphy_locked(hw, I217_CGFREG, phy_reg); 5600 5601 release: 5602 hw->phy.ops.release(hw); 5603 } 5604 out: 5605 ew32(PHY_CTRL, phy_ctrl); 5606 5607 if (hw->mac.type == e1000_ich8lan) 5608 e1000e_gig_downshift_workaround_ich8lan(hw); 5609 5610 if (hw->mac.type >= e1000_pchlan) { 5611 e1000_oem_bits_config_ich8lan(hw, false); 5612 5613 /* Reset PHY to activate OEM bits on 82577/8 */ 5614 if (hw->mac.type == e1000_pchlan) 5615 e1000e_phy_hw_reset_generic(hw); 5616 5617 ret_val = hw->phy.ops.acquire(hw); 5618 if (ret_val) 5619 return; 5620 e1000_write_smbus_addr(hw); 5621 hw->phy.ops.release(hw); 5622 } 5623 } 5624 5625 /** 5626 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0 5627 * @hw: pointer to the HW structure 5628 * 5629 * During Sx to S0 transitions on non-managed devices or managed devices 5630 * on which PHY resets are not blocked, if the PHY registers cannot be 5631 * accessed properly by the s/w toggle the LANPHYPC value to power cycle 5632 * the PHY. 5633 * On i217, setup Intel Rapid Start Technology. 5634 **/ 5635 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw) 5636 { 5637 s32 ret_val; 5638 5639 if (hw->mac.type < e1000_pch2lan) 5640 return; 5641 5642 ret_val = e1000_init_phy_workarounds_pchlan(hw); 5643 if (ret_val) { 5644 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val); 5645 return; 5646 } 5647 5648 /* For i217 Intel Rapid Start Technology support when the system 5649 * is transitioning from Sx and no manageability engine is present 5650 * configure SMBus to restore on reset, disable proxy, and enable 5651 * the reset on MTA (Multicast table array). 5652 */ 5653 if (hw->phy.type == e1000_phy_i217) { 5654 u16 phy_reg; 5655 5656 ret_val = hw->phy.ops.acquire(hw); 5657 if (ret_val) { 5658 e_dbg("Failed to setup iRST\n"); 5659 return; 5660 } 5661 5662 /* Clear Auto Enable LPI after link up */ 5663 e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg); 5664 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI; 5665 e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, phy_reg); 5666 5667 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 5668 /* Restore clear on SMB if no manageability engine 5669 * is present 5670 */ 5671 ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg); 5672 if (ret_val) 5673 goto release; 5674 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE; 5675 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg); 5676 5677 /* Disable Proxy */ 5678 e1e_wphy_locked(hw, I217_PROXY_CTRL, 0); 5679 } 5680 /* Enable reset on MTA */ 5681 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg); 5682 if (ret_val) 5683 goto release; 5684 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET; 5685 e1e_wphy_locked(hw, I217_CGFREG, phy_reg); 5686 release: 5687 if (ret_val) 5688 e_dbg("Error %d in resume workarounds\n", ret_val); 5689 hw->phy.ops.release(hw); 5690 } 5691 } 5692 5693 /** 5694 * e1000_cleanup_led_ich8lan - Restore the default LED operation 5695 * @hw: pointer to the HW structure 5696 * 5697 * Return the LED back to the default configuration. 5698 **/ 5699 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) 5700 { 5701 if (hw->phy.type == e1000_phy_ife) 5702 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); 5703 5704 ew32(LEDCTL, hw->mac.ledctl_default); 5705 return 0; 5706 } 5707 5708 /** 5709 * e1000_led_on_ich8lan - Turn LEDs on 5710 * @hw: pointer to the HW structure 5711 * 5712 * Turn on the LEDs. 5713 **/ 5714 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) 5715 { 5716 if (hw->phy.type == e1000_phy_ife) 5717 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 5718 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); 5719 5720 ew32(LEDCTL, hw->mac.ledctl_mode2); 5721 return 0; 5722 } 5723 5724 /** 5725 * e1000_led_off_ich8lan - Turn LEDs off 5726 * @hw: pointer to the HW structure 5727 * 5728 * Turn off the LEDs. 5729 **/ 5730 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) 5731 { 5732 if (hw->phy.type == e1000_phy_ife) 5733 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 5734 (IFE_PSCL_PROBE_MODE | 5735 IFE_PSCL_PROBE_LEDS_OFF)); 5736 5737 ew32(LEDCTL, hw->mac.ledctl_mode1); 5738 return 0; 5739 } 5740 5741 /** 5742 * e1000_setup_led_pchlan - Configures SW controllable LED 5743 * @hw: pointer to the HW structure 5744 * 5745 * This prepares the SW controllable LED for use. 5746 **/ 5747 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw) 5748 { 5749 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1); 5750 } 5751 5752 /** 5753 * e1000_cleanup_led_pchlan - Restore the default LED operation 5754 * @hw: pointer to the HW structure 5755 * 5756 * Return the LED back to the default configuration. 5757 **/ 5758 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) 5759 { 5760 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default); 5761 } 5762 5763 /** 5764 * e1000_led_on_pchlan - Turn LEDs on 5765 * @hw: pointer to the HW structure 5766 * 5767 * Turn on the LEDs. 5768 **/ 5769 static s32 e1000_led_on_pchlan(struct e1000_hw *hw) 5770 { 5771 u16 data = (u16)hw->mac.ledctl_mode2; 5772 u32 i, led; 5773 5774 /* If no link, then turn LED on by setting the invert bit 5775 * for each LED that's mode is "link_up" in ledctl_mode2. 5776 */ 5777 if (!(er32(STATUS) & E1000_STATUS_LU)) { 5778 for (i = 0; i < 3; i++) { 5779 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 5780 if ((led & E1000_PHY_LED0_MODE_MASK) != 5781 E1000_LEDCTL_MODE_LINK_UP) 5782 continue; 5783 if (led & E1000_PHY_LED0_IVRT) 5784 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 5785 else 5786 data |= (E1000_PHY_LED0_IVRT << (i * 5)); 5787 } 5788 } 5789 5790 return e1e_wphy(hw, HV_LED_CONFIG, data); 5791 } 5792 5793 /** 5794 * e1000_led_off_pchlan - Turn LEDs off 5795 * @hw: pointer to the HW structure 5796 * 5797 * Turn off the LEDs. 5798 **/ 5799 static s32 e1000_led_off_pchlan(struct e1000_hw *hw) 5800 { 5801 u16 data = (u16)hw->mac.ledctl_mode1; 5802 u32 i, led; 5803 5804 /* If no link, then turn LED off by clearing the invert bit 5805 * for each LED that's mode is "link_up" in ledctl_mode1. 5806 */ 5807 if (!(er32(STATUS) & E1000_STATUS_LU)) { 5808 for (i = 0; i < 3; i++) { 5809 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 5810 if ((led & E1000_PHY_LED0_MODE_MASK) != 5811 E1000_LEDCTL_MODE_LINK_UP) 5812 continue; 5813 if (led & E1000_PHY_LED0_IVRT) 5814 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 5815 else 5816 data |= (E1000_PHY_LED0_IVRT << (i * 5)); 5817 } 5818 } 5819 5820 return e1e_wphy(hw, HV_LED_CONFIG, data); 5821 } 5822 5823 /** 5824 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset 5825 * @hw: pointer to the HW structure 5826 * 5827 * Read appropriate register for the config done bit for completion status 5828 * and configure the PHY through s/w for EEPROM-less parts. 5829 * 5830 * NOTE: some silicon which is EEPROM-less will fail trying to read the 5831 * config done bit, so only an error is logged and continues. If we were 5832 * to return with error, EEPROM-less silicon would not be able to be reset 5833 * or change link. 5834 **/ 5835 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) 5836 { 5837 s32 ret_val = 0; 5838 u32 bank = 0; 5839 u32 status; 5840 5841 e1000e_get_cfg_done_generic(hw); 5842 5843 /* Wait for indication from h/w that it has completed basic config */ 5844 if (hw->mac.type >= e1000_ich10lan) { 5845 e1000_lan_init_done_ich8lan(hw); 5846 } else { 5847 ret_val = e1000e_get_auto_rd_done(hw); 5848 if (ret_val) { 5849 /* When auto config read does not complete, do not 5850 * return with an error. This can happen in situations 5851 * where there is no eeprom and prevents getting link. 5852 */ 5853 e_dbg("Auto Read Done did not complete\n"); 5854 ret_val = 0; 5855 } 5856 } 5857 5858 /* Clear PHY Reset Asserted bit */ 5859 status = er32(STATUS); 5860 if (status & E1000_STATUS_PHYRA) 5861 ew32(STATUS, status & ~E1000_STATUS_PHYRA); 5862 else 5863 e_dbg("PHY Reset Asserted not set - needs delay\n"); 5864 5865 /* If EEPROM is not marked present, init the IGP 3 PHY manually */ 5866 if (hw->mac.type <= e1000_ich9lan) { 5867 if (!(er32(EECD) & E1000_EECD_PRES) && 5868 (hw->phy.type == e1000_phy_igp_3)) { 5869 e1000e_phy_init_script_igp3(hw); 5870 } 5871 } else { 5872 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { 5873 /* Maybe we should do a basic PHY config */ 5874 e_dbg("EEPROM not present\n"); 5875 ret_val = -E1000_ERR_CONFIG; 5876 } 5877 } 5878 5879 return ret_val; 5880 } 5881 5882 /** 5883 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down 5884 * @hw: pointer to the HW structure 5885 * 5886 * In the case of a PHY power down to save power, or to turn off link during a 5887 * driver unload, or wake on lan is not enabled, remove the link. 5888 **/ 5889 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw) 5890 { 5891 /* If the management interface is not enabled, then power down */ 5892 if (!(hw->mac.ops.check_mng_mode(hw) || 5893 hw->phy.ops.check_reset_block(hw))) 5894 e1000_power_down_phy_copper(hw); 5895 } 5896 5897 /** 5898 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters 5899 * @hw: pointer to the HW structure 5900 * 5901 * Clears hardware counters specific to the silicon family and calls 5902 * clear_hw_cntrs_generic to clear all general purpose counters. 5903 **/ 5904 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) 5905 { 5906 u16 phy_data; 5907 s32 ret_val; 5908 5909 e1000e_clear_hw_cntrs_base(hw); 5910 5911 er32(ALGNERRC); 5912 er32(RXERRC); 5913 er32(TNCRS); 5914 er32(CEXTERR); 5915 er32(TSCTC); 5916 er32(TSCTFC); 5917 5918 er32(MGTPRC); 5919 er32(MGTPDC); 5920 er32(MGTPTC); 5921 5922 er32(IAC); 5923 er32(ICRXOC); 5924 5925 /* Clear PHY statistics registers */ 5926 if ((hw->phy.type == e1000_phy_82578) || 5927 (hw->phy.type == e1000_phy_82579) || 5928 (hw->phy.type == e1000_phy_i217) || 5929 (hw->phy.type == e1000_phy_82577)) { 5930 ret_val = hw->phy.ops.acquire(hw); 5931 if (ret_val) 5932 return; 5933 ret_val = hw->phy.ops.set_page(hw, 5934 HV_STATS_PAGE << IGP_PAGE_SHIFT); 5935 if (ret_val) 5936 goto release; 5937 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); 5938 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); 5939 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); 5940 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); 5941 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); 5942 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); 5943 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); 5944 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); 5945 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); 5946 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); 5947 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); 5948 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); 5949 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); 5950 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); 5951 release: 5952 hw->phy.ops.release(hw); 5953 } 5954 } 5955 5956 static const struct e1000_mac_operations ich8_mac_ops = { 5957 /* check_mng_mode dependent on mac type */ 5958 .check_for_link = e1000_check_for_copper_link_ich8lan, 5959 /* cleanup_led dependent on mac type */ 5960 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan, 5961 .get_bus_info = e1000_get_bus_info_ich8lan, 5962 .set_lan_id = e1000_set_lan_id_single_port, 5963 .get_link_up_info = e1000_get_link_up_info_ich8lan, 5964 /* led_on dependent on mac type */ 5965 /* led_off dependent on mac type */ 5966 .update_mc_addr_list = e1000e_update_mc_addr_list_generic, 5967 .reset_hw = e1000_reset_hw_ich8lan, 5968 .init_hw = e1000_init_hw_ich8lan, 5969 .setup_link = e1000_setup_link_ich8lan, 5970 .setup_physical_interface = e1000_setup_copper_link_ich8lan, 5971 /* id_led_init dependent on mac type */ 5972 .config_collision_dist = e1000e_config_collision_dist_generic, 5973 .rar_set = e1000e_rar_set_generic, 5974 .rar_get_count = e1000e_rar_get_count_generic, 5975 }; 5976 5977 static const struct e1000_phy_operations ich8_phy_ops = { 5978 .acquire = e1000_acquire_swflag_ich8lan, 5979 .check_reset_block = e1000_check_reset_block_ich8lan, 5980 .commit = NULL, 5981 .get_cfg_done = e1000_get_cfg_done_ich8lan, 5982 .get_cable_length = e1000e_get_cable_length_igp_2, 5983 .read_reg = e1000e_read_phy_reg_igp, 5984 .release = e1000_release_swflag_ich8lan, 5985 .reset = e1000_phy_hw_reset_ich8lan, 5986 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan, 5987 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan, 5988 .write_reg = e1000e_write_phy_reg_igp, 5989 }; 5990 5991 static const struct e1000_nvm_operations ich8_nvm_ops = { 5992 .acquire = e1000_acquire_nvm_ich8lan, 5993 .read = e1000_read_nvm_ich8lan, 5994 .release = e1000_release_nvm_ich8lan, 5995 .reload = e1000e_reload_nvm_generic, 5996 .update = e1000_update_nvm_checksum_ich8lan, 5997 .valid_led_default = e1000_valid_led_default_ich8lan, 5998 .validate = e1000_validate_nvm_checksum_ich8lan, 5999 .write = e1000_write_nvm_ich8lan, 6000 }; 6001 6002 static const struct e1000_nvm_operations spt_nvm_ops = { 6003 .acquire = e1000_acquire_nvm_ich8lan, 6004 .release = e1000_release_nvm_ich8lan, 6005 .read = e1000_read_nvm_spt, 6006 .update = e1000_update_nvm_checksum_spt, 6007 .reload = e1000e_reload_nvm_generic, 6008 .valid_led_default = e1000_valid_led_default_ich8lan, 6009 .validate = e1000_validate_nvm_checksum_ich8lan, 6010 .write = e1000_write_nvm_ich8lan, 6011 }; 6012 6013 const struct e1000_info e1000_ich8_info = { 6014 .mac = e1000_ich8lan, 6015 .flags = FLAG_HAS_WOL 6016 | FLAG_IS_ICH 6017 | FLAG_HAS_CTRLEXT_ON_LOAD 6018 | FLAG_HAS_AMT 6019 | FLAG_HAS_FLASH 6020 | FLAG_APME_IN_WUC, 6021 .pba = 8, 6022 .max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN, 6023 .get_variants = e1000_get_variants_ich8lan, 6024 .mac_ops = &ich8_mac_ops, 6025 .phy_ops = &ich8_phy_ops, 6026 .nvm_ops = &ich8_nvm_ops, 6027 }; 6028 6029 const struct e1000_info e1000_ich9_info = { 6030 .mac = e1000_ich9lan, 6031 .flags = FLAG_HAS_JUMBO_FRAMES 6032 | FLAG_IS_ICH 6033 | FLAG_HAS_WOL 6034 | FLAG_HAS_CTRLEXT_ON_LOAD 6035 | FLAG_HAS_AMT 6036 | FLAG_HAS_FLASH 6037 | FLAG_APME_IN_WUC, 6038 .pba = 18, 6039 .max_hw_frame_size = DEFAULT_JUMBO, 6040 .get_variants = e1000_get_variants_ich8lan, 6041 .mac_ops = &ich8_mac_ops, 6042 .phy_ops = &ich8_phy_ops, 6043 .nvm_ops = &ich8_nvm_ops, 6044 }; 6045 6046 const struct e1000_info e1000_ich10_info = { 6047 .mac = e1000_ich10lan, 6048 .flags = FLAG_HAS_JUMBO_FRAMES 6049 | FLAG_IS_ICH 6050 | FLAG_HAS_WOL 6051 | FLAG_HAS_CTRLEXT_ON_LOAD 6052 | FLAG_HAS_AMT 6053 | FLAG_HAS_FLASH 6054 | FLAG_APME_IN_WUC, 6055 .pba = 18, 6056 .max_hw_frame_size = DEFAULT_JUMBO, 6057 .get_variants = e1000_get_variants_ich8lan, 6058 .mac_ops = &ich8_mac_ops, 6059 .phy_ops = &ich8_phy_ops, 6060 .nvm_ops = &ich8_nvm_ops, 6061 }; 6062 6063 const struct e1000_info e1000_pch_info = { 6064 .mac = e1000_pchlan, 6065 .flags = FLAG_IS_ICH 6066 | FLAG_HAS_WOL 6067 | FLAG_HAS_CTRLEXT_ON_LOAD 6068 | FLAG_HAS_AMT 6069 | FLAG_HAS_FLASH 6070 | FLAG_HAS_JUMBO_FRAMES 6071 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */ 6072 | FLAG_APME_IN_WUC, 6073 .flags2 = FLAG2_HAS_PHY_STATS, 6074 .pba = 26, 6075 .max_hw_frame_size = 4096, 6076 .get_variants = e1000_get_variants_ich8lan, 6077 .mac_ops = &ich8_mac_ops, 6078 .phy_ops = &ich8_phy_ops, 6079 .nvm_ops = &ich8_nvm_ops, 6080 }; 6081 6082 const struct e1000_info e1000_pch2_info = { 6083 .mac = e1000_pch2lan, 6084 .flags = FLAG_IS_ICH 6085 | FLAG_HAS_WOL 6086 | FLAG_HAS_HW_TIMESTAMP 6087 | FLAG_HAS_CTRLEXT_ON_LOAD 6088 | FLAG_HAS_AMT 6089 | FLAG_HAS_FLASH 6090 | FLAG_HAS_JUMBO_FRAMES 6091 | FLAG_APME_IN_WUC, 6092 .flags2 = FLAG2_HAS_PHY_STATS 6093 | FLAG2_HAS_EEE 6094 | FLAG2_CHECK_SYSTIM_OVERFLOW, 6095 .pba = 26, 6096 .max_hw_frame_size = 9022, 6097 .get_variants = e1000_get_variants_ich8lan, 6098 .mac_ops = &ich8_mac_ops, 6099 .phy_ops = &ich8_phy_ops, 6100 .nvm_ops = &ich8_nvm_ops, 6101 }; 6102 6103 const struct e1000_info e1000_pch_lpt_info = { 6104 .mac = e1000_pch_lpt, 6105 .flags = FLAG_IS_ICH 6106 | FLAG_HAS_WOL 6107 | FLAG_HAS_HW_TIMESTAMP 6108 | FLAG_HAS_CTRLEXT_ON_LOAD 6109 | FLAG_HAS_AMT 6110 | FLAG_HAS_FLASH 6111 | FLAG_HAS_JUMBO_FRAMES 6112 | FLAG_APME_IN_WUC, 6113 .flags2 = FLAG2_HAS_PHY_STATS 6114 | FLAG2_HAS_EEE 6115 | FLAG2_CHECK_SYSTIM_OVERFLOW, 6116 .pba = 26, 6117 .max_hw_frame_size = 9022, 6118 .get_variants = e1000_get_variants_ich8lan, 6119 .mac_ops = &ich8_mac_ops, 6120 .phy_ops = &ich8_phy_ops, 6121 .nvm_ops = &ich8_nvm_ops, 6122 }; 6123 6124 const struct e1000_info e1000_pch_spt_info = { 6125 .mac = e1000_pch_spt, 6126 .flags = FLAG_IS_ICH 6127 | FLAG_HAS_WOL 6128 | FLAG_HAS_HW_TIMESTAMP 6129 | FLAG_HAS_CTRLEXT_ON_LOAD 6130 | FLAG_HAS_AMT 6131 | FLAG_HAS_FLASH 6132 | FLAG_HAS_JUMBO_FRAMES 6133 | FLAG_APME_IN_WUC, 6134 .flags2 = FLAG2_HAS_PHY_STATS 6135 | FLAG2_HAS_EEE, 6136 .pba = 26, 6137 .max_hw_frame_size = 9022, 6138 .get_variants = e1000_get_variants_ich8lan, 6139 .mac_ops = &ich8_mac_ops, 6140 .phy_ops = &ich8_phy_ops, 6141 .nvm_ops = &spt_nvm_ops, 6142 }; 6143 6144 const struct e1000_info e1000_pch_cnp_info = { 6145 .mac = e1000_pch_cnp, 6146 .flags = FLAG_IS_ICH 6147 | FLAG_HAS_WOL 6148 | FLAG_HAS_HW_TIMESTAMP 6149 | FLAG_HAS_CTRLEXT_ON_LOAD 6150 | FLAG_HAS_AMT 6151 | FLAG_HAS_FLASH 6152 | FLAG_HAS_JUMBO_FRAMES 6153 | FLAG_APME_IN_WUC, 6154 .flags2 = FLAG2_HAS_PHY_STATS 6155 | FLAG2_HAS_EEE, 6156 .pba = 26, 6157 .max_hw_frame_size = 9022, 6158 .get_variants = e1000_get_variants_ich8lan, 6159 .mac_ops = &ich8_mac_ops, 6160 .phy_ops = &ich8_phy_ops, 6161 .nvm_ops = &spt_nvm_ops, 6162 }; 6163 6164 const struct e1000_info e1000_pch_tgp_info = { 6165 .mac = e1000_pch_tgp, 6166 .flags = FLAG_IS_ICH 6167 | FLAG_HAS_WOL 6168 | FLAG_HAS_HW_TIMESTAMP 6169 | FLAG_HAS_CTRLEXT_ON_LOAD 6170 | FLAG_HAS_AMT 6171 | FLAG_HAS_FLASH 6172 | FLAG_HAS_JUMBO_FRAMES 6173 | FLAG_APME_IN_WUC, 6174 .flags2 = FLAG2_HAS_PHY_STATS 6175 | FLAG2_HAS_EEE, 6176 .pba = 26, 6177 .max_hw_frame_size = 9022, 6178 .get_variants = e1000_get_variants_ich8lan, 6179 .mac_ops = &ich8_mac_ops, 6180 .phy_ops = &ich8_phy_ops, 6181 .nvm_ops = &spt_nvm_ops, 6182 }; 6183 6184 const struct e1000_info e1000_pch_adp_info = { 6185 .mac = e1000_pch_adp, 6186 .flags = FLAG_IS_ICH 6187 | FLAG_HAS_WOL 6188 | FLAG_HAS_HW_TIMESTAMP 6189 | FLAG_HAS_CTRLEXT_ON_LOAD 6190 | FLAG_HAS_AMT 6191 | FLAG_HAS_FLASH 6192 | FLAG_HAS_JUMBO_FRAMES 6193 | FLAG_APME_IN_WUC, 6194 .flags2 = FLAG2_HAS_PHY_STATS 6195 | FLAG2_HAS_EEE, 6196 .pba = 26, 6197 .max_hw_frame_size = 9022, 6198 .get_variants = e1000_get_variants_ich8lan, 6199 .mac_ops = &ich8_mac_ops, 6200 .phy_ops = &ich8_phy_ops, 6201 .nvm_ops = &spt_nvm_ops, 6202 }; 6203 6204 const struct e1000_info e1000_pch_mtp_info = { 6205 .mac = e1000_pch_mtp, 6206 .flags = FLAG_IS_ICH 6207 | FLAG_HAS_WOL 6208 | FLAG_HAS_HW_TIMESTAMP 6209 | FLAG_HAS_CTRLEXT_ON_LOAD 6210 | FLAG_HAS_AMT 6211 | FLAG_HAS_FLASH 6212 | FLAG_HAS_JUMBO_FRAMES 6213 | FLAG_APME_IN_WUC, 6214 .flags2 = FLAG2_HAS_PHY_STATS 6215 | FLAG2_HAS_EEE, 6216 .pba = 26, 6217 .max_hw_frame_size = 9022, 6218 .get_variants = e1000_get_variants_ich8lan, 6219 .mac_ops = &ich8_mac_ops, 6220 .phy_ops = &ich8_phy_ops, 6221 .nvm_ops = &spt_nvm_ops, 6222 }; 6223 6224 const struct e1000_info e1000_pch_ptp_info = { 6225 .mac = e1000_pch_ptp, 6226 .flags = FLAG_IS_ICH 6227 | FLAG_HAS_WOL 6228 | FLAG_HAS_HW_TIMESTAMP 6229 | FLAG_HAS_CTRLEXT_ON_LOAD 6230 | FLAG_HAS_AMT 6231 | FLAG_HAS_FLASH 6232 | FLAG_HAS_JUMBO_FRAMES 6233 | FLAG_APME_IN_WUC, 6234 .flags2 = FLAG2_HAS_PHY_STATS 6235 | FLAG2_HAS_EEE, 6236 .pba = 26, 6237 .max_hw_frame_size = 9022, 6238 .get_variants = e1000_get_variants_ich8lan, 6239 .mac_ops = &ich8_mac_ops, 6240 .phy_ops = &ich8_phy_ops, 6241 .nvm_ops = &spt_nvm_ops, 6242 }; 6243