1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
4 *
5 */
6
7 #include <linux/bitfield.h>
8 #include <linux/debugfs.h>
9 #include <linux/device.h>
10 #include <linux/dma-direction.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/idr.h>
13 #include <linux/interrupt.h>
14 #include <linux/list.h>
15 #include <linux/mhi.h>
16 #include <linux/module.h>
17 #include <linux/slab.h>
18 #include <linux/vmalloc.h>
19 #include <linux/wait.h>
20 #include "internal.h"
21
22 #define CREATE_TRACE_POINTS
23 #include "trace.h"
24
25 static DEFINE_IDA(mhi_controller_ida);
26
27 #undef mhi_ee
28 #undef mhi_ee_end
29
30 #define mhi_ee(a, b) [MHI_EE_##a] = b,
31 #define mhi_ee_end(a, b) [MHI_EE_##a] = b,
32
33 const char * const mhi_ee_str[MHI_EE_MAX] = {
34 MHI_EE_LIST
35 };
36
37 #undef dev_st_trans
38 #undef dev_st_trans_end
39
40 #define dev_st_trans(a, b) [DEV_ST_TRANSITION_##a] = b,
41 #define dev_st_trans_end(a, b) [DEV_ST_TRANSITION_##a] = b,
42
43 const char * const dev_state_tran_str[DEV_ST_TRANSITION_MAX] = {
44 DEV_ST_TRANSITION_LIST
45 };
46
47 #undef ch_state_type
48 #undef ch_state_type_end
49
50 #define ch_state_type(a, b) [MHI_CH_STATE_TYPE_##a] = b,
51 #define ch_state_type_end(a, b) [MHI_CH_STATE_TYPE_##a] = b,
52
53 const char * const mhi_ch_state_type_str[MHI_CH_STATE_TYPE_MAX] = {
54 MHI_CH_STATE_TYPE_LIST
55 };
56
57 #undef mhi_pm_state
58 #undef mhi_pm_state_end
59
60 #define mhi_pm_state(a, b) [MHI_PM_STATE_##a] = b,
61 #define mhi_pm_state_end(a, b) [MHI_PM_STATE_##a] = b,
62
63 static const char * const mhi_pm_state_str[] = {
64 MHI_PM_STATE_LIST
65 };
66
to_mhi_pm_state_str(u32 state)67 const char *to_mhi_pm_state_str(u32 state)
68 {
69 int index;
70
71 if (state)
72 index = __fls(state);
73
74 if (!state || index >= ARRAY_SIZE(mhi_pm_state_str))
75 return "Invalid State";
76
77 return mhi_pm_state_str[index];
78 }
79
serial_number_show(struct device * dev,struct device_attribute * attr,char * buf)80 static ssize_t serial_number_show(struct device *dev,
81 struct device_attribute *attr,
82 char *buf)
83 {
84 struct mhi_device *mhi_dev = to_mhi_device(dev);
85 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
86
87 return sysfs_emit(buf, "Serial Number: %u\n",
88 mhi_cntrl->serial_number);
89 }
90 static DEVICE_ATTR_RO(serial_number);
91
oem_pk_hash_show(struct device * dev,struct device_attribute * attr,char * buf)92 static ssize_t oem_pk_hash_show(struct device *dev,
93 struct device_attribute *attr,
94 char *buf)
95 {
96 struct mhi_device *mhi_dev = to_mhi_device(dev);
97 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
98 u32 hash_segment[MHI_MAX_OEM_PK_HASH_SEGMENTS];
99 int i, cnt = 0, ret;
100
101 for (i = 0; i < MHI_MAX_OEM_PK_HASH_SEGMENTS; i++) {
102 ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_OEMPKHASH(i), &hash_segment[i]);
103 if (ret) {
104 dev_err(dev, "Could not capture OEM PK HASH\n");
105 return ret;
106 }
107 }
108
109 for (i = 0; i < MHI_MAX_OEM_PK_HASH_SEGMENTS; i++)
110 cnt += sysfs_emit_at(buf, cnt, "OEMPKHASH[%d]: 0x%x\n", i, hash_segment[i]);
111
112 return cnt;
113 }
114 static DEVICE_ATTR_RO(oem_pk_hash);
115
soc_reset_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)116 static ssize_t soc_reset_store(struct device *dev,
117 struct device_attribute *attr,
118 const char *buf,
119 size_t count)
120 {
121 struct mhi_device *mhi_dev = to_mhi_device(dev);
122 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
123
124 mhi_soc_reset(mhi_cntrl);
125 return count;
126 }
127 static DEVICE_ATTR_WO(soc_reset);
128
trigger_edl_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)129 static ssize_t trigger_edl_store(struct device *dev,
130 struct device_attribute *attr,
131 const char *buf, size_t count)
132 {
133 struct mhi_device *mhi_dev = to_mhi_device(dev);
134 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
135 unsigned long val;
136 int ret;
137
138 ret = kstrtoul(buf, 10, &val);
139 if (ret < 0)
140 return ret;
141
142 if (!val)
143 return -EINVAL;
144
145 ret = mhi_cntrl->edl_trigger(mhi_cntrl);
146 if (ret)
147 return ret;
148
149 return count;
150 }
151 static DEVICE_ATTR_WO(trigger_edl);
152
153 static struct attribute *mhi_dev_attrs[] = {
154 &dev_attr_serial_number.attr,
155 &dev_attr_oem_pk_hash.attr,
156 &dev_attr_soc_reset.attr,
157 NULL,
158 };
159 ATTRIBUTE_GROUPS(mhi_dev);
160
161 /* MHI protocol requires the transfer ring to be aligned with ring length */
mhi_alloc_aligned_ring(struct mhi_controller * mhi_cntrl,struct mhi_ring * ring,u64 len)162 static int mhi_alloc_aligned_ring(struct mhi_controller *mhi_cntrl,
163 struct mhi_ring *ring,
164 u64 len)
165 {
166 ring->alloc_size = len + (len - 1);
167 ring->pre_aligned = dma_alloc_coherent(mhi_cntrl->cntrl_dev, ring->alloc_size,
168 &ring->dma_handle, GFP_KERNEL);
169 if (!ring->pre_aligned)
170 return -ENOMEM;
171
172 ring->iommu_base = (ring->dma_handle + (len - 1)) & ~(len - 1);
173 ring->base = ring->pre_aligned + (ring->iommu_base - ring->dma_handle);
174
175 return 0;
176 }
177
mhi_deinit_free_irq(struct mhi_controller * mhi_cntrl)178 static void mhi_deinit_free_irq(struct mhi_controller *mhi_cntrl)
179 {
180 int i;
181 struct mhi_event *mhi_event = mhi_cntrl->mhi_event;
182
183 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
184 if (mhi_event->offload_ev)
185 continue;
186
187 free_irq(mhi_cntrl->irq[mhi_event->irq], mhi_event);
188 }
189
190 free_irq(mhi_cntrl->irq[0], mhi_cntrl);
191 }
192
mhi_init_irq_setup(struct mhi_controller * mhi_cntrl)193 static int mhi_init_irq_setup(struct mhi_controller *mhi_cntrl)
194 {
195 struct mhi_event *mhi_event = mhi_cntrl->mhi_event;
196 unsigned long irq_flags = IRQF_SHARED | IRQF_NO_SUSPEND;
197 int i, ret;
198
199 /* if controller driver has set irq_flags, use it */
200 if (mhi_cntrl->irq_flags)
201 irq_flags = mhi_cntrl->irq_flags;
202
203 /* Setup BHI_INTVEC IRQ */
204 ret = request_threaded_irq(mhi_cntrl->irq[0], mhi_intvec_handler,
205 mhi_intvec_threaded_handler,
206 irq_flags,
207 "bhi", mhi_cntrl);
208 if (ret)
209 return ret;
210 /*
211 * IRQs should be enabled during mhi_async_power_up(), so disable them explicitly here.
212 * Due to the use of IRQF_SHARED flag as default while requesting IRQs, we assume that
213 * IRQ_NOAUTOEN is not applicable.
214 */
215 disable_irq(mhi_cntrl->irq[0]);
216
217 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
218 if (mhi_event->offload_ev)
219 continue;
220
221 if (mhi_event->irq >= mhi_cntrl->nr_irqs) {
222 dev_err(mhi_cntrl->cntrl_dev, "irq %d not available for event ring\n",
223 mhi_event->irq);
224 ret = -EINVAL;
225 goto error_request;
226 }
227
228 ret = request_irq(mhi_cntrl->irq[mhi_event->irq],
229 mhi_irq_handler,
230 irq_flags,
231 "mhi", mhi_event);
232 if (ret) {
233 dev_err(mhi_cntrl->cntrl_dev, "Error requesting irq:%d for ev:%d\n",
234 mhi_cntrl->irq[mhi_event->irq], i);
235 goto error_request;
236 }
237
238 disable_irq(mhi_cntrl->irq[mhi_event->irq]);
239 }
240
241 return 0;
242
243 error_request:
244 for (--i, --mhi_event; i >= 0; i--, mhi_event--) {
245 if (mhi_event->offload_ev)
246 continue;
247
248 free_irq(mhi_cntrl->irq[mhi_event->irq], mhi_event);
249 }
250 free_irq(mhi_cntrl->irq[0], mhi_cntrl);
251
252 return ret;
253 }
254
mhi_deinit_dev_ctxt(struct mhi_controller * mhi_cntrl)255 static void mhi_deinit_dev_ctxt(struct mhi_controller *mhi_cntrl)
256 {
257 int i;
258 struct mhi_ctxt *mhi_ctxt = mhi_cntrl->mhi_ctxt;
259 struct mhi_cmd *mhi_cmd;
260 struct mhi_event *mhi_event;
261 struct mhi_ring *ring;
262
263 mhi_cmd = mhi_cntrl->mhi_cmd;
264 for (i = 0; i < NR_OF_CMD_RINGS; i++, mhi_cmd++) {
265 ring = &mhi_cmd->ring;
266 dma_free_coherent(mhi_cntrl->cntrl_dev, ring->alloc_size,
267 ring->pre_aligned, ring->dma_handle);
268 ring->base = NULL;
269 ring->iommu_base = 0;
270 }
271
272 dma_free_coherent(mhi_cntrl->cntrl_dev,
273 sizeof(*mhi_ctxt->cmd_ctxt) * NR_OF_CMD_RINGS,
274 mhi_ctxt->cmd_ctxt, mhi_ctxt->cmd_ctxt_addr);
275
276 mhi_event = mhi_cntrl->mhi_event;
277 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
278 if (mhi_event->offload_ev)
279 continue;
280
281 ring = &mhi_event->ring;
282 dma_free_coherent(mhi_cntrl->cntrl_dev, ring->alloc_size,
283 ring->pre_aligned, ring->dma_handle);
284 ring->base = NULL;
285 ring->iommu_base = 0;
286 }
287
288 dma_free_coherent(mhi_cntrl->cntrl_dev, sizeof(*mhi_ctxt->er_ctxt) *
289 mhi_cntrl->total_ev_rings, mhi_ctxt->er_ctxt,
290 mhi_ctxt->er_ctxt_addr);
291
292 dma_free_coherent(mhi_cntrl->cntrl_dev, sizeof(*mhi_ctxt->chan_ctxt) *
293 mhi_cntrl->max_chan, mhi_ctxt->chan_ctxt,
294 mhi_ctxt->chan_ctxt_addr);
295
296 kfree(mhi_ctxt);
297 mhi_cntrl->mhi_ctxt = NULL;
298 }
299
mhi_init_dev_ctxt(struct mhi_controller * mhi_cntrl)300 static int mhi_init_dev_ctxt(struct mhi_controller *mhi_cntrl)
301 {
302 struct mhi_ctxt *mhi_ctxt;
303 struct mhi_chan_ctxt *chan_ctxt;
304 struct mhi_event_ctxt *er_ctxt;
305 struct mhi_cmd_ctxt *cmd_ctxt;
306 struct mhi_chan *mhi_chan;
307 struct mhi_event *mhi_event;
308 struct mhi_cmd *mhi_cmd;
309 u32 tmp;
310 int ret = -ENOMEM, i;
311
312 atomic_set(&mhi_cntrl->dev_wake, 0);
313 atomic_set(&mhi_cntrl->pending_pkts, 0);
314
315 mhi_ctxt = kzalloc_obj(*mhi_ctxt);
316 if (!mhi_ctxt)
317 return -ENOMEM;
318
319 /* Setup channel ctxt */
320 mhi_ctxt->chan_ctxt = dma_alloc_coherent(mhi_cntrl->cntrl_dev,
321 sizeof(*mhi_ctxt->chan_ctxt) *
322 mhi_cntrl->max_chan,
323 &mhi_ctxt->chan_ctxt_addr,
324 GFP_KERNEL);
325 if (!mhi_ctxt->chan_ctxt)
326 goto error_alloc_chan_ctxt;
327
328 mhi_chan = mhi_cntrl->mhi_chan;
329 chan_ctxt = mhi_ctxt->chan_ctxt;
330 for (i = 0; i < mhi_cntrl->max_chan; i++, chan_ctxt++, mhi_chan++) {
331 /* Skip if it is an offload channel */
332 if (mhi_chan->offload_ch)
333 continue;
334
335 tmp = le32_to_cpu(chan_ctxt->chcfg);
336 tmp &= ~CHAN_CTX_CHSTATE_MASK;
337 tmp |= FIELD_PREP(CHAN_CTX_CHSTATE_MASK, MHI_CH_STATE_DISABLED);
338 tmp &= ~CHAN_CTX_BRSTMODE_MASK;
339 tmp |= FIELD_PREP(CHAN_CTX_BRSTMODE_MASK, mhi_chan->db_cfg.brstmode);
340 tmp &= ~CHAN_CTX_POLLCFG_MASK;
341 tmp |= FIELD_PREP(CHAN_CTX_POLLCFG_MASK, mhi_chan->db_cfg.pollcfg);
342 chan_ctxt->chcfg = cpu_to_le32(tmp);
343
344 chan_ctxt->chtype = cpu_to_le32(mhi_chan->type);
345 chan_ctxt->erindex = cpu_to_le32(mhi_chan->er_index);
346
347 mhi_chan->ch_state = MHI_CH_STATE_DISABLED;
348 mhi_chan->tre_ring.db_addr = (void __iomem *)&chan_ctxt->wp;
349 }
350
351 /* Setup event context */
352 mhi_ctxt->er_ctxt = dma_alloc_coherent(mhi_cntrl->cntrl_dev,
353 sizeof(*mhi_ctxt->er_ctxt) *
354 mhi_cntrl->total_ev_rings,
355 &mhi_ctxt->er_ctxt_addr,
356 GFP_KERNEL);
357 if (!mhi_ctxt->er_ctxt)
358 goto error_alloc_er_ctxt;
359
360 er_ctxt = mhi_ctxt->er_ctxt;
361 mhi_event = mhi_cntrl->mhi_event;
362 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, er_ctxt++,
363 mhi_event++) {
364 struct mhi_ring *ring = &mhi_event->ring;
365
366 /* Skip if it is an offload event */
367 if (mhi_event->offload_ev)
368 continue;
369
370 tmp = le32_to_cpu(er_ctxt->intmod);
371 tmp &= ~EV_CTX_INTMODC_MASK;
372 tmp &= ~EV_CTX_INTMODT_MASK;
373 tmp |= FIELD_PREP(EV_CTX_INTMODT_MASK, mhi_event->intmod);
374 er_ctxt->intmod = cpu_to_le32(tmp);
375
376 er_ctxt->ertype = cpu_to_le32(MHI_ER_TYPE_VALID);
377 er_ctxt->msivec = cpu_to_le32(mhi_event->irq);
378 mhi_event->db_cfg.db_mode = true;
379
380 ring->el_size = sizeof(struct mhi_ring_element);
381 ring->len = ring->el_size * ring->elements;
382 ret = mhi_alloc_aligned_ring(mhi_cntrl, ring, ring->len);
383 if (ret)
384 goto error_alloc_er;
385
386 /*
387 * If the read pointer equals to the write pointer, then the
388 * ring is empty
389 */
390 ring->rp = ring->wp = ring->base;
391 er_ctxt->rbase = cpu_to_le64(ring->iommu_base);
392 er_ctxt->rp = er_ctxt->wp = er_ctxt->rbase;
393 er_ctxt->rlen = cpu_to_le64(ring->len);
394 ring->ctxt_wp = &er_ctxt->wp;
395 }
396
397 /* Setup cmd context */
398 ret = -ENOMEM;
399 mhi_ctxt->cmd_ctxt = dma_alloc_coherent(mhi_cntrl->cntrl_dev,
400 sizeof(*mhi_ctxt->cmd_ctxt) *
401 NR_OF_CMD_RINGS,
402 &mhi_ctxt->cmd_ctxt_addr,
403 GFP_KERNEL);
404 if (!mhi_ctxt->cmd_ctxt)
405 goto error_alloc_er;
406
407 mhi_cmd = mhi_cntrl->mhi_cmd;
408 cmd_ctxt = mhi_ctxt->cmd_ctxt;
409 for (i = 0; i < NR_OF_CMD_RINGS; i++, mhi_cmd++, cmd_ctxt++) {
410 struct mhi_ring *ring = &mhi_cmd->ring;
411
412 ring->el_size = sizeof(struct mhi_ring_element);
413 ring->elements = CMD_EL_PER_RING;
414 ring->len = ring->el_size * ring->elements;
415 ret = mhi_alloc_aligned_ring(mhi_cntrl, ring, ring->len);
416 if (ret)
417 goto error_alloc_cmd;
418
419 ring->rp = ring->wp = ring->base;
420 cmd_ctxt->rbase = cpu_to_le64(ring->iommu_base);
421 cmd_ctxt->rp = cmd_ctxt->wp = cmd_ctxt->rbase;
422 cmd_ctxt->rlen = cpu_to_le64(ring->len);
423 ring->ctxt_wp = &cmd_ctxt->wp;
424 }
425
426 mhi_cntrl->mhi_ctxt = mhi_ctxt;
427
428 return 0;
429
430 error_alloc_cmd:
431 for (--i, --mhi_cmd; i >= 0; i--, mhi_cmd--) {
432 struct mhi_ring *ring = &mhi_cmd->ring;
433
434 dma_free_coherent(mhi_cntrl->cntrl_dev, ring->alloc_size,
435 ring->pre_aligned, ring->dma_handle);
436 }
437 dma_free_coherent(mhi_cntrl->cntrl_dev,
438 sizeof(*mhi_ctxt->cmd_ctxt) * NR_OF_CMD_RINGS,
439 mhi_ctxt->cmd_ctxt, mhi_ctxt->cmd_ctxt_addr);
440 i = mhi_cntrl->total_ev_rings;
441 mhi_event = mhi_cntrl->mhi_event + i;
442
443 error_alloc_er:
444 for (--i, --mhi_event; i >= 0; i--, mhi_event--) {
445 struct mhi_ring *ring = &mhi_event->ring;
446
447 if (mhi_event->offload_ev)
448 continue;
449
450 dma_free_coherent(mhi_cntrl->cntrl_dev, ring->alloc_size,
451 ring->pre_aligned, ring->dma_handle);
452 }
453 dma_free_coherent(mhi_cntrl->cntrl_dev, sizeof(*mhi_ctxt->er_ctxt) *
454 mhi_cntrl->total_ev_rings, mhi_ctxt->er_ctxt,
455 mhi_ctxt->er_ctxt_addr);
456
457 error_alloc_er_ctxt:
458 dma_free_coherent(mhi_cntrl->cntrl_dev, sizeof(*mhi_ctxt->chan_ctxt) *
459 mhi_cntrl->max_chan, mhi_ctxt->chan_ctxt,
460 mhi_ctxt->chan_ctxt_addr);
461
462 error_alloc_chan_ctxt:
463 kfree(mhi_ctxt);
464
465 return ret;
466 }
467
mhi_init_mmio(struct mhi_controller * mhi_cntrl)468 int mhi_init_mmio(struct mhi_controller *mhi_cntrl)
469 {
470 u32 val;
471 int i, ret;
472 struct mhi_chan *mhi_chan;
473 struct mhi_event *mhi_event;
474 void __iomem *base = mhi_cntrl->regs;
475 struct device *dev = &mhi_cntrl->mhi_dev->dev;
476 struct {
477 u32 offset;
478 u32 val;
479 } reg_info[] = {
480 {
481 CCABAP_HIGHER,
482 upper_32_bits(mhi_cntrl->mhi_ctxt->chan_ctxt_addr),
483 },
484 {
485 CCABAP_LOWER,
486 lower_32_bits(mhi_cntrl->mhi_ctxt->chan_ctxt_addr),
487 },
488 {
489 ECABAP_HIGHER,
490 upper_32_bits(mhi_cntrl->mhi_ctxt->er_ctxt_addr),
491 },
492 {
493 ECABAP_LOWER,
494 lower_32_bits(mhi_cntrl->mhi_ctxt->er_ctxt_addr),
495 },
496 {
497 CRCBAP_HIGHER,
498 upper_32_bits(mhi_cntrl->mhi_ctxt->cmd_ctxt_addr),
499 },
500 {
501 CRCBAP_LOWER,
502 lower_32_bits(mhi_cntrl->mhi_ctxt->cmd_ctxt_addr),
503 },
504 {
505 MHICTRLBASE_HIGHER,
506 upper_32_bits(mhi_cntrl->iova_start),
507 },
508 {
509 MHICTRLBASE_LOWER,
510 lower_32_bits(mhi_cntrl->iova_start),
511 },
512 {
513 MHIDATABASE_HIGHER,
514 upper_32_bits(mhi_cntrl->iova_start),
515 },
516 {
517 MHIDATABASE_LOWER,
518 lower_32_bits(mhi_cntrl->iova_start),
519 },
520 {
521 MHICTRLLIMIT_HIGHER,
522 upper_32_bits(mhi_cntrl->iova_stop),
523 },
524 {
525 MHICTRLLIMIT_LOWER,
526 lower_32_bits(mhi_cntrl->iova_stop),
527 },
528 {
529 MHIDATALIMIT_HIGHER,
530 upper_32_bits(mhi_cntrl->iova_stop),
531 },
532 {
533 MHIDATALIMIT_LOWER,
534 lower_32_bits(mhi_cntrl->iova_stop),
535 },
536 {0, 0}
537 };
538
539 dev_dbg(dev, "Initializing MHI registers\n");
540
541 /* Read channel db offset */
542 ret = mhi_get_channel_doorbell_offset(mhi_cntrl, &val);
543 if (ret)
544 return ret;
545
546 if (val >= mhi_cntrl->reg_len - (8 * MHI_DEV_WAKE_DB)) {
547 dev_err(dev, "CHDB offset: 0x%x is out of range: 0x%zx\n",
548 val, mhi_cntrl->reg_len - (8 * MHI_DEV_WAKE_DB));
549 return -ERANGE;
550 }
551
552 /* Setup wake db */
553 mhi_cntrl->wake_db = base + val + (8 * MHI_DEV_WAKE_DB);
554 mhi_cntrl->wake_set = false;
555
556 /* Setup channel db address for each channel in tre_ring */
557 mhi_chan = mhi_cntrl->mhi_chan;
558 for (i = 0; i < mhi_cntrl->max_chan; i++, val += 8, mhi_chan++)
559 mhi_chan->tre_ring.db_addr = base + val;
560
561 /* Read event ring db offset */
562 ret = mhi_read_reg(mhi_cntrl, base, ERDBOFF, &val);
563 if (ret) {
564 dev_err(dev, "Unable to read ERDBOFF register\n");
565 return -EIO;
566 }
567
568 if (val >= mhi_cntrl->reg_len - (8 * mhi_cntrl->total_ev_rings)) {
569 dev_err(dev, "ERDB offset: 0x%x is out of range: 0x%zx\n",
570 val, mhi_cntrl->reg_len - (8 * mhi_cntrl->total_ev_rings));
571 return -ERANGE;
572 }
573
574 /* Setup event db address for each ev_ring */
575 mhi_event = mhi_cntrl->mhi_event;
576 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, val += 8, mhi_event++) {
577 if (mhi_event->offload_ev)
578 continue;
579
580 mhi_event->ring.db_addr = base + val;
581 }
582
583 /* Setup DB register for primary CMD rings */
584 mhi_cntrl->mhi_cmd[PRIMARY_CMD_RING].ring.db_addr = base + CRDB_LOWER;
585
586 /* Write to MMIO registers */
587 for (i = 0; reg_info[i].offset; i++)
588 mhi_write_reg(mhi_cntrl, base, reg_info[i].offset,
589 reg_info[i].val);
590
591 ret = mhi_write_reg_field(mhi_cntrl, base, MHICFG, MHICFG_NER_MASK,
592 mhi_cntrl->total_ev_rings);
593 if (ret) {
594 dev_err(dev, "Unable to write MHICFG register\n");
595 return ret;
596 }
597
598 ret = mhi_write_reg_field(mhi_cntrl, base, MHICFG, MHICFG_NHWER_MASK,
599 mhi_cntrl->hw_ev_rings);
600 if (ret) {
601 dev_err(dev, "Unable to write MHICFG register\n");
602 return ret;
603 }
604
605 return 0;
606 }
607
mhi_deinit_chan_ctxt(struct mhi_controller * mhi_cntrl,struct mhi_chan * mhi_chan)608 void mhi_deinit_chan_ctxt(struct mhi_controller *mhi_cntrl,
609 struct mhi_chan *mhi_chan)
610 {
611 struct mhi_ring *buf_ring;
612 struct mhi_ring *tre_ring;
613 struct mhi_chan_ctxt *chan_ctxt;
614 u32 tmp;
615
616 buf_ring = &mhi_chan->buf_ring;
617 tre_ring = &mhi_chan->tre_ring;
618 chan_ctxt = &mhi_cntrl->mhi_ctxt->chan_ctxt[mhi_chan->chan];
619
620 if (!chan_ctxt->rbase) /* Already uninitialized */
621 return;
622
623 dma_free_coherent(mhi_cntrl->cntrl_dev, tre_ring->alloc_size,
624 tre_ring->pre_aligned, tre_ring->dma_handle);
625 vfree(buf_ring->base);
626
627 buf_ring->base = tre_ring->base = NULL;
628 tre_ring->ctxt_wp = NULL;
629 chan_ctxt->rbase = 0;
630 chan_ctxt->rlen = 0;
631 chan_ctxt->rp = 0;
632 chan_ctxt->wp = 0;
633
634 tmp = le32_to_cpu(chan_ctxt->chcfg);
635 tmp &= ~CHAN_CTX_CHSTATE_MASK;
636 tmp |= FIELD_PREP(CHAN_CTX_CHSTATE_MASK, MHI_CH_STATE_DISABLED);
637 chan_ctxt->chcfg = cpu_to_le32(tmp);
638
639 /* Update to all cores */
640 smp_wmb();
641 }
642
mhi_init_chan_ctxt(struct mhi_controller * mhi_cntrl,struct mhi_chan * mhi_chan)643 int mhi_init_chan_ctxt(struct mhi_controller *mhi_cntrl,
644 struct mhi_chan *mhi_chan)
645 {
646 struct mhi_ring *buf_ring;
647 struct mhi_ring *tre_ring;
648 struct mhi_chan_ctxt *chan_ctxt;
649 u32 tmp;
650 int ret;
651
652 buf_ring = &mhi_chan->buf_ring;
653 tre_ring = &mhi_chan->tre_ring;
654 tre_ring->el_size = sizeof(struct mhi_ring_element);
655 tre_ring->len = tre_ring->el_size * tre_ring->elements;
656 chan_ctxt = &mhi_cntrl->mhi_ctxt->chan_ctxt[mhi_chan->chan];
657 ret = mhi_alloc_aligned_ring(mhi_cntrl, tre_ring, tre_ring->len);
658 if (ret)
659 return -ENOMEM;
660
661 buf_ring->el_size = sizeof(struct mhi_buf_info);
662 buf_ring->len = buf_ring->el_size * buf_ring->elements;
663 buf_ring->base = vzalloc(buf_ring->len);
664
665 if (!buf_ring->base) {
666 dma_free_coherent(mhi_cntrl->cntrl_dev, tre_ring->alloc_size,
667 tre_ring->pre_aligned, tre_ring->dma_handle);
668 return -ENOMEM;
669 }
670
671 tmp = le32_to_cpu(chan_ctxt->chcfg);
672 tmp &= ~CHAN_CTX_CHSTATE_MASK;
673 tmp |= FIELD_PREP(CHAN_CTX_CHSTATE_MASK, MHI_CH_STATE_ENABLED);
674 chan_ctxt->chcfg = cpu_to_le32(tmp);
675
676 chan_ctxt->rbase = cpu_to_le64(tre_ring->iommu_base);
677 chan_ctxt->rp = chan_ctxt->wp = chan_ctxt->rbase;
678 chan_ctxt->rlen = cpu_to_le64(tre_ring->len);
679 tre_ring->ctxt_wp = &chan_ctxt->wp;
680
681 tre_ring->rp = tre_ring->wp = tre_ring->base;
682 buf_ring->rp = buf_ring->wp = buf_ring->base;
683 mhi_chan->db_cfg.db_mode = 1;
684
685 /* Update to all cores */
686 smp_wmb();
687
688 return 0;
689 }
690
parse_ev_cfg(struct mhi_controller * mhi_cntrl,const struct mhi_controller_config * config)691 static int parse_ev_cfg(struct mhi_controller *mhi_cntrl,
692 const struct mhi_controller_config *config)
693 {
694 struct mhi_event *mhi_event;
695 const struct mhi_event_config *event_cfg;
696 struct device *dev = mhi_cntrl->cntrl_dev;
697 int i, num;
698
699 num = config->num_events;
700 mhi_cntrl->total_ev_rings = num;
701 mhi_cntrl->mhi_event = kzalloc_objs(*mhi_cntrl->mhi_event, num);
702 if (!mhi_cntrl->mhi_event)
703 return -ENOMEM;
704
705 /* Populate event ring */
706 mhi_event = mhi_cntrl->mhi_event;
707 for (i = 0; i < num; i++) {
708 event_cfg = &config->event_cfg[i];
709
710 mhi_event->er_index = i;
711 mhi_event->ring.elements = event_cfg->num_elements;
712 mhi_event->intmod = event_cfg->irq_moderation_ms;
713 mhi_event->irq = event_cfg->irq;
714
715 if (event_cfg->channel != U32_MAX) {
716 /* This event ring has a dedicated channel */
717 mhi_event->chan = event_cfg->channel;
718 if (mhi_event->chan >= mhi_cntrl->max_chan) {
719 dev_err(dev,
720 "Event Ring channel not available\n");
721 goto error_ev_cfg;
722 }
723
724 mhi_event->mhi_chan =
725 &mhi_cntrl->mhi_chan[mhi_event->chan];
726 }
727
728 /* Priority is fixed to 1 for now */
729 mhi_event->priority = 1;
730
731 mhi_event->db_cfg.brstmode = event_cfg->mode;
732 if (MHI_INVALID_BRSTMODE(mhi_event->db_cfg.brstmode))
733 goto error_ev_cfg;
734
735 if (mhi_event->db_cfg.brstmode == MHI_DB_BRST_ENABLE)
736 mhi_event->db_cfg.process_db = mhi_db_brstmode;
737 else
738 mhi_event->db_cfg.process_db = mhi_db_brstmode_disable;
739
740 mhi_event->data_type = event_cfg->data_type;
741
742 switch (mhi_event->data_type) {
743 case MHI_ER_DATA:
744 mhi_event->process_event = mhi_process_data_event_ring;
745 break;
746 case MHI_ER_CTRL:
747 mhi_event->process_event = mhi_process_ctrl_ev_ring;
748 break;
749 default:
750 dev_err(dev, "Event Ring type not supported\n");
751 goto error_ev_cfg;
752 }
753
754 mhi_event->hw_ring = event_cfg->hardware_event;
755 if (mhi_event->hw_ring)
756 mhi_cntrl->hw_ev_rings++;
757 else
758 mhi_cntrl->sw_ev_rings++;
759
760 mhi_event->cl_manage = event_cfg->client_managed;
761 mhi_event->offload_ev = event_cfg->offload_channel;
762 mhi_event++;
763 }
764
765 return 0;
766
767 error_ev_cfg:
768
769 kfree(mhi_cntrl->mhi_event);
770 return -EINVAL;
771 }
772
parse_ch_cfg(struct mhi_controller * mhi_cntrl,const struct mhi_controller_config * config)773 static int parse_ch_cfg(struct mhi_controller *mhi_cntrl,
774 const struct mhi_controller_config *config)
775 {
776 const struct mhi_channel_config *ch_cfg;
777 struct device *dev = mhi_cntrl->cntrl_dev;
778 int i;
779 u32 chan;
780
781 mhi_cntrl->max_chan = config->max_channels;
782
783 /*
784 * The allocation of MHI channels can exceed 32KB in some scenarios,
785 * so to avoid any memory possible allocation failures, vzalloc is
786 * used here
787 */
788 mhi_cntrl->mhi_chan = vcalloc(mhi_cntrl->max_chan,
789 sizeof(*mhi_cntrl->mhi_chan));
790 if (!mhi_cntrl->mhi_chan)
791 return -ENOMEM;
792
793 INIT_LIST_HEAD(&mhi_cntrl->lpm_chans);
794
795 /* Populate channel configurations */
796 for (i = 0; i < config->num_channels; i++) {
797 struct mhi_chan *mhi_chan;
798
799 ch_cfg = &config->ch_cfg[i];
800
801 chan = ch_cfg->num;
802 if (chan >= mhi_cntrl->max_chan) {
803 dev_err(dev, "Channel %d not available\n", chan);
804 goto error_chan_cfg;
805 }
806
807 mhi_chan = &mhi_cntrl->mhi_chan[chan];
808 mhi_chan->name = ch_cfg->name;
809 mhi_chan->chan = chan;
810
811 mhi_chan->tre_ring.elements = ch_cfg->num_elements;
812 if (!mhi_chan->tre_ring.elements)
813 goto error_chan_cfg;
814
815 /*
816 * For some channels, local ring length should be bigger than
817 * the transfer ring length due to internal logical channels
818 * in device. So host can queue much more buffers than transfer
819 * ring length. Example, RSC channels should have a larger local
820 * channel length than transfer ring length.
821 */
822 mhi_chan->buf_ring.elements = ch_cfg->local_elements;
823 if (!mhi_chan->buf_ring.elements)
824 mhi_chan->buf_ring.elements = mhi_chan->tre_ring.elements;
825 mhi_chan->er_index = ch_cfg->event_ring;
826 mhi_chan->dir = ch_cfg->dir;
827
828 /*
829 * For most channels, chtype is identical to channel directions.
830 * So, if it is not defined then assign channel direction to
831 * chtype
832 */
833 mhi_chan->type = ch_cfg->type;
834 if (!mhi_chan->type)
835 mhi_chan->type = (enum mhi_ch_type)mhi_chan->dir;
836
837 mhi_chan->ee_mask = ch_cfg->ee_mask;
838 mhi_chan->db_cfg.pollcfg = ch_cfg->pollcfg;
839 mhi_chan->lpm_notify = ch_cfg->lpm_notify;
840 mhi_chan->offload_ch = ch_cfg->offload_channel;
841 mhi_chan->db_cfg.reset_req = ch_cfg->doorbell_mode_switch;
842 mhi_chan->wake_capable = ch_cfg->wake_capable;
843
844 /*
845 * Bi-directional and direction less channel must be an
846 * offload channel
847 */
848 if ((mhi_chan->dir == DMA_BIDIRECTIONAL ||
849 mhi_chan->dir == DMA_NONE) && !mhi_chan->offload_ch) {
850 dev_err(dev, "Invalid channel configuration\n");
851 goto error_chan_cfg;
852 }
853
854 if (!mhi_chan->offload_ch) {
855 mhi_chan->db_cfg.brstmode = ch_cfg->doorbell;
856 if (MHI_INVALID_BRSTMODE(mhi_chan->db_cfg.brstmode)) {
857 dev_err(dev, "Invalid Door bell mode\n");
858 goto error_chan_cfg;
859 }
860 }
861
862 if (mhi_chan->db_cfg.brstmode == MHI_DB_BRST_ENABLE)
863 mhi_chan->db_cfg.process_db = mhi_db_brstmode;
864 else
865 mhi_chan->db_cfg.process_db = mhi_db_brstmode_disable;
866
867 mhi_chan->configured = true;
868
869 if (mhi_chan->lpm_notify)
870 list_add_tail(&mhi_chan->node, &mhi_cntrl->lpm_chans);
871 }
872
873 return 0;
874
875 error_chan_cfg:
876 vfree(mhi_cntrl->mhi_chan);
877
878 return -EINVAL;
879 }
880
parse_config(struct mhi_controller * mhi_cntrl,const struct mhi_controller_config * config)881 static int parse_config(struct mhi_controller *mhi_cntrl,
882 const struct mhi_controller_config *config)
883 {
884 int ret;
885
886 /* Parse MHI channel configuration */
887 ret = parse_ch_cfg(mhi_cntrl, config);
888 if (ret)
889 return ret;
890
891 /* Parse MHI event configuration */
892 ret = parse_ev_cfg(mhi_cntrl, config);
893 if (ret)
894 goto error_ev_cfg;
895
896 mhi_cntrl->timeout_ms = config->timeout_ms;
897 if (!mhi_cntrl->timeout_ms)
898 mhi_cntrl->timeout_ms = MHI_TIMEOUT_MS;
899
900 mhi_cntrl->ready_timeout_ms = config->ready_timeout_ms;
901 mhi_cntrl->bounce_buf = config->use_bounce_buf;
902 mhi_cntrl->buffer_len = config->buf_len;
903 if (!mhi_cntrl->buffer_len)
904 mhi_cntrl->buffer_len = MHI_MAX_MTU;
905
906 /* By default, host is allowed to ring DB in both M0 and M2 states */
907 mhi_cntrl->db_access = MHI_PM_M0 | MHI_PM_M2;
908 if (config->m2_no_db)
909 mhi_cntrl->db_access &= ~MHI_PM_M2;
910
911 return 0;
912
913 error_ev_cfg:
914 vfree(mhi_cntrl->mhi_chan);
915
916 return ret;
917 }
918
mhi_register_controller(struct mhi_controller * mhi_cntrl,const struct mhi_controller_config * config)919 int mhi_register_controller(struct mhi_controller *mhi_cntrl,
920 const struct mhi_controller_config *config)
921 {
922 struct mhi_event *mhi_event;
923 struct mhi_chan *mhi_chan;
924 struct mhi_cmd *mhi_cmd;
925 struct mhi_device *mhi_dev;
926 int ret, i;
927
928 if (!mhi_cntrl || !mhi_cntrl->cntrl_dev || !mhi_cntrl->regs ||
929 !mhi_cntrl->runtime_get || !mhi_cntrl->runtime_put ||
930 !mhi_cntrl->status_cb || !mhi_cntrl->read_reg ||
931 !mhi_cntrl->write_reg || !mhi_cntrl->nr_irqs ||
932 !mhi_cntrl->irq || !mhi_cntrl->reg_len)
933 return -EINVAL;
934
935 ret = parse_config(mhi_cntrl, config);
936 if (ret)
937 return -EINVAL;
938
939 mhi_cntrl->mhi_cmd = kzalloc_objs(*mhi_cntrl->mhi_cmd, NR_OF_CMD_RINGS);
940 if (!mhi_cntrl->mhi_cmd) {
941 ret = -ENOMEM;
942 goto err_free_event;
943 }
944
945 INIT_LIST_HEAD(&mhi_cntrl->transition_list);
946 mutex_init(&mhi_cntrl->pm_mutex);
947 rwlock_init(&mhi_cntrl->pm_lock);
948 spin_lock_init(&mhi_cntrl->transition_lock);
949 spin_lock_init(&mhi_cntrl->wlock);
950 INIT_WORK(&mhi_cntrl->st_worker, mhi_pm_st_worker);
951 init_waitqueue_head(&mhi_cntrl->state_event);
952
953 mhi_cntrl->hiprio_wq = alloc_ordered_workqueue("mhi_hiprio_wq", WQ_HIGHPRI);
954 if (!mhi_cntrl->hiprio_wq) {
955 dev_err(mhi_cntrl->cntrl_dev, "Failed to allocate workqueue\n");
956 ret = -ENOMEM;
957 goto err_free_cmd;
958 }
959
960 mhi_cmd = mhi_cntrl->mhi_cmd;
961 for (i = 0; i < NR_OF_CMD_RINGS; i++, mhi_cmd++)
962 spin_lock_init(&mhi_cmd->lock);
963
964 mhi_event = mhi_cntrl->mhi_event;
965 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
966 /* Skip for offload events */
967 if (mhi_event->offload_ev)
968 continue;
969
970 mhi_event->mhi_cntrl = mhi_cntrl;
971 spin_lock_init(&mhi_event->lock);
972 if (mhi_event->data_type == MHI_ER_CTRL)
973 tasklet_init(&mhi_event->task, mhi_ctrl_ev_task,
974 (ulong)mhi_event);
975 else
976 tasklet_init(&mhi_event->task, mhi_ev_task,
977 (ulong)mhi_event);
978 }
979
980 mhi_chan = mhi_cntrl->mhi_chan;
981 for (i = 0; i < mhi_cntrl->max_chan; i++, mhi_chan++) {
982 mutex_init(&mhi_chan->mutex);
983 init_completion(&mhi_chan->completion);
984 rwlock_init(&mhi_chan->lock);
985
986 /* used in setting bei field of TRE */
987 mhi_event = &mhi_cntrl->mhi_event[mhi_chan->er_index];
988 mhi_chan->intmod = mhi_event->intmod;
989 }
990
991 if (mhi_cntrl->bounce_buf) {
992 mhi_cntrl->map_single = mhi_map_single_use_bb;
993 mhi_cntrl->unmap_single = mhi_unmap_single_use_bb;
994 } else {
995 mhi_cntrl->map_single = mhi_map_single_no_bb;
996 mhi_cntrl->unmap_single = mhi_unmap_single_no_bb;
997 }
998
999 mhi_cntrl->index = ida_alloc(&mhi_controller_ida, GFP_KERNEL);
1000 if (mhi_cntrl->index < 0) {
1001 ret = mhi_cntrl->index;
1002 goto err_destroy_wq;
1003 }
1004
1005 ret = mhi_init_irq_setup(mhi_cntrl);
1006 if (ret)
1007 goto err_ida_free;
1008
1009 /* Register controller with MHI bus */
1010 mhi_dev = mhi_alloc_device(mhi_cntrl);
1011 if (IS_ERR(mhi_dev)) {
1012 dev_err(mhi_cntrl->cntrl_dev, "Failed to allocate MHI device\n");
1013 ret = PTR_ERR(mhi_dev);
1014 goto error_setup_irq;
1015 }
1016
1017 mhi_dev->dev_type = MHI_DEVICE_CONTROLLER;
1018 mhi_dev->mhi_cntrl = mhi_cntrl;
1019 dev_set_name(&mhi_dev->dev, "mhi%d", mhi_cntrl->index);
1020 mhi_dev->name = dev_name(&mhi_dev->dev);
1021
1022 /* Init wakeup source */
1023 device_init_wakeup(&mhi_dev->dev, true);
1024
1025 ret = device_add(&mhi_dev->dev);
1026 if (ret)
1027 goto err_release_dev;
1028
1029 if (mhi_cntrl->edl_trigger) {
1030 ret = sysfs_create_file(&mhi_dev->dev.kobj, &dev_attr_trigger_edl.attr);
1031 if (ret)
1032 goto err_del_dev;
1033 }
1034
1035 mhi_cntrl->mhi_dev = mhi_dev;
1036
1037 mhi_create_debugfs(mhi_cntrl);
1038
1039 return 0;
1040
1041 err_del_dev:
1042 device_del(&mhi_dev->dev);
1043 err_release_dev:
1044 put_device(&mhi_dev->dev);
1045 error_setup_irq:
1046 mhi_deinit_free_irq(mhi_cntrl);
1047 err_ida_free:
1048 ida_free(&mhi_controller_ida, mhi_cntrl->index);
1049 err_destroy_wq:
1050 destroy_workqueue(mhi_cntrl->hiprio_wq);
1051 err_free_cmd:
1052 kfree(mhi_cntrl->mhi_cmd);
1053 err_free_event:
1054 kfree(mhi_cntrl->mhi_event);
1055 vfree(mhi_cntrl->mhi_chan);
1056
1057 return ret;
1058 }
1059 EXPORT_SYMBOL_GPL(mhi_register_controller);
1060
mhi_unregister_controller(struct mhi_controller * mhi_cntrl)1061 void mhi_unregister_controller(struct mhi_controller *mhi_cntrl)
1062 {
1063 struct mhi_device *mhi_dev = mhi_cntrl->mhi_dev;
1064 struct mhi_chan *mhi_chan = mhi_cntrl->mhi_chan;
1065 unsigned int i;
1066
1067 mhi_deinit_free_irq(mhi_cntrl);
1068 mhi_destroy_debugfs(mhi_cntrl);
1069
1070 if (mhi_cntrl->edl_trigger)
1071 sysfs_remove_file(&mhi_dev->dev.kobj, &dev_attr_trigger_edl.attr);
1072
1073 destroy_workqueue(mhi_cntrl->hiprio_wq);
1074 kfree(mhi_cntrl->mhi_cmd);
1075 kfree(mhi_cntrl->mhi_event);
1076
1077 /* Drop the references to MHI devices created for channels */
1078 for (i = 0; i < mhi_cntrl->max_chan; i++, mhi_chan++) {
1079 if (!mhi_chan->mhi_dev)
1080 continue;
1081
1082 put_device(&mhi_chan->mhi_dev->dev);
1083 }
1084 vfree(mhi_cntrl->mhi_chan);
1085
1086 device_del(&mhi_dev->dev);
1087 put_device(&mhi_dev->dev);
1088
1089 ida_free(&mhi_controller_ida, mhi_cntrl->index);
1090 }
1091 EXPORT_SYMBOL_GPL(mhi_unregister_controller);
1092
mhi_alloc_controller(void)1093 struct mhi_controller *mhi_alloc_controller(void)
1094 {
1095 struct mhi_controller *mhi_cntrl;
1096
1097 mhi_cntrl = kzalloc_obj(*mhi_cntrl);
1098
1099 return mhi_cntrl;
1100 }
1101 EXPORT_SYMBOL_GPL(mhi_alloc_controller);
1102
mhi_free_controller(struct mhi_controller * mhi_cntrl)1103 void mhi_free_controller(struct mhi_controller *mhi_cntrl)
1104 {
1105 kfree(mhi_cntrl);
1106 }
1107 EXPORT_SYMBOL_GPL(mhi_free_controller);
1108
mhi_prepare_for_power_up(struct mhi_controller * mhi_cntrl)1109 int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl)
1110 {
1111 struct device *dev = &mhi_cntrl->mhi_dev->dev;
1112 u32 bhi_off, bhie_off;
1113 int ret;
1114
1115 mutex_lock(&mhi_cntrl->pm_mutex);
1116
1117 ret = mhi_init_dev_ctxt(mhi_cntrl);
1118 if (ret)
1119 goto error_dev_ctxt;
1120
1121 ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIOFF, &bhi_off);
1122 if (ret) {
1123 dev_err(dev, "Error getting BHI offset\n");
1124 goto error_reg_offset;
1125 }
1126
1127 if (bhi_off >= mhi_cntrl->reg_len) {
1128 dev_err(dev, "BHI offset: 0x%x is out of range: 0x%zx\n",
1129 bhi_off, mhi_cntrl->reg_len);
1130 ret = -ERANGE;
1131 goto error_reg_offset;
1132 }
1133 mhi_cntrl->bhi = mhi_cntrl->regs + bhi_off;
1134
1135 if (mhi_cntrl->fbc_download || mhi_cntrl->rddm_size || mhi_cntrl->seg_len) {
1136 ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIEOFF,
1137 &bhie_off);
1138 if (ret) {
1139 dev_err(dev, "Error getting BHIE offset\n");
1140 goto error_reg_offset;
1141 }
1142
1143 if (bhie_off >= mhi_cntrl->reg_len) {
1144 dev_err(dev,
1145 "BHIe offset: 0x%x is out of range: 0x%zx\n",
1146 bhie_off, mhi_cntrl->reg_len);
1147 ret = -ERANGE;
1148 goto error_reg_offset;
1149 }
1150 mhi_cntrl->bhie = mhi_cntrl->regs + bhie_off;
1151 }
1152
1153 if (mhi_cntrl->rddm_size) {
1154 /*
1155 * This controller supports RDDM, so we need to manually clear
1156 * BHIE RX registers since POR values are undefined.
1157 */
1158 memset_io(mhi_cntrl->bhie + BHIE_RXVECADDR_LOW_OFFS,
1159 0, BHIE_RXVECSTATUS_OFFS - BHIE_RXVECADDR_LOW_OFFS +
1160 4);
1161 /*
1162 * Allocate RDDM table for debugging purpose if specified
1163 */
1164 mhi_alloc_bhie_table(mhi_cntrl, &mhi_cntrl->rddm_image,
1165 mhi_cntrl->rddm_size);
1166 if (mhi_cntrl->rddm_image) {
1167 ret = mhi_rddm_prepare(mhi_cntrl,
1168 mhi_cntrl->rddm_image);
1169 if (ret) {
1170 mhi_free_bhie_table(mhi_cntrl,
1171 mhi_cntrl->rddm_image);
1172 goto error_reg_offset;
1173 }
1174 }
1175 }
1176
1177 mutex_unlock(&mhi_cntrl->pm_mutex);
1178
1179 return 0;
1180
1181 error_reg_offset:
1182 mhi_deinit_dev_ctxt(mhi_cntrl);
1183
1184 error_dev_ctxt:
1185 mutex_unlock(&mhi_cntrl->pm_mutex);
1186
1187 return ret;
1188 }
1189 EXPORT_SYMBOL_GPL(mhi_prepare_for_power_up);
1190
mhi_unprepare_after_power_down(struct mhi_controller * mhi_cntrl)1191 void mhi_unprepare_after_power_down(struct mhi_controller *mhi_cntrl)
1192 {
1193 if (mhi_cntrl->fbc_image) {
1194 mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->fbc_image);
1195 mhi_cntrl->fbc_image = NULL;
1196 }
1197
1198 if (mhi_cntrl->rddm_image) {
1199 mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->rddm_image);
1200 mhi_cntrl->rddm_image = NULL;
1201 }
1202
1203 mhi_cntrl->bhi = NULL;
1204 mhi_cntrl->bhie = NULL;
1205
1206 mhi_deinit_dev_ctxt(mhi_cntrl);
1207 }
1208 EXPORT_SYMBOL_GPL(mhi_unprepare_after_power_down);
1209
mhi_release_device(struct device * dev)1210 static void mhi_release_device(struct device *dev)
1211 {
1212 struct mhi_device *mhi_dev = to_mhi_device(dev);
1213
1214 /*
1215 * We need to set the mhi_chan->mhi_dev to NULL here since the MHI
1216 * devices for the channels will only get created if the mhi_dev
1217 * associated with it is NULL. This scenario will happen during the
1218 * controller suspend and resume.
1219 */
1220 if (mhi_dev->ul_chan)
1221 mhi_dev->ul_chan->mhi_dev = NULL;
1222
1223 if (mhi_dev->dl_chan)
1224 mhi_dev->dl_chan->mhi_dev = NULL;
1225
1226 kfree(mhi_dev);
1227 }
1228
mhi_alloc_device(struct mhi_controller * mhi_cntrl)1229 struct mhi_device *mhi_alloc_device(struct mhi_controller *mhi_cntrl)
1230 {
1231 struct mhi_device *mhi_dev;
1232 struct device *dev;
1233
1234 mhi_dev = kzalloc_obj(*mhi_dev);
1235 if (!mhi_dev)
1236 return ERR_PTR(-ENOMEM);
1237
1238 dev = &mhi_dev->dev;
1239 device_initialize(dev);
1240 dev->bus = &mhi_bus_type;
1241 dev->release = mhi_release_device;
1242
1243 if (mhi_cntrl->mhi_dev) {
1244 /* for MHI client devices, parent is the MHI controller device */
1245 dev->parent = &mhi_cntrl->mhi_dev->dev;
1246 } else {
1247 /* for MHI controller device, parent is the bus device (e.g. pci device) */
1248 dev->parent = mhi_cntrl->cntrl_dev;
1249 }
1250
1251 mhi_dev->mhi_cntrl = mhi_cntrl;
1252 mhi_dev->dev_wake = 0;
1253
1254 return mhi_dev;
1255 }
1256
mhi_probe(struct device * dev)1257 static int mhi_probe(struct device *dev)
1258 {
1259 struct mhi_device *mhi_dev = to_mhi_device(dev);
1260 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
1261 struct device_driver *drv = dev->driver;
1262 struct mhi_driver *mhi_drv = to_mhi_driver(drv);
1263 struct mhi_event *mhi_event;
1264 struct mhi_chan *ul_chan = mhi_dev->ul_chan;
1265 struct mhi_chan *dl_chan = mhi_dev->dl_chan;
1266 int ret;
1267
1268 /* Bring device out of LPM */
1269 ret = mhi_device_get_sync(mhi_dev);
1270 if (ret)
1271 return ret;
1272
1273 ret = -EINVAL;
1274
1275 if (ul_chan) {
1276 /*
1277 * If channel supports LPM notifications then status_cb should
1278 * be provided
1279 */
1280 if (ul_chan->lpm_notify && !mhi_drv->status_cb)
1281 goto exit_probe;
1282
1283 /* For non-offload channels then xfer_cb should be provided */
1284 if (!ul_chan->offload_ch && !mhi_drv->ul_xfer_cb)
1285 goto exit_probe;
1286
1287 ul_chan->xfer_cb = mhi_drv->ul_xfer_cb;
1288 }
1289
1290 ret = -EINVAL;
1291 if (dl_chan) {
1292 /*
1293 * If channel supports LPM notifications then status_cb should
1294 * be provided
1295 */
1296 if (dl_chan->lpm_notify && !mhi_drv->status_cb)
1297 goto exit_probe;
1298
1299 /* For non-offload channels then xfer_cb should be provided */
1300 if (!dl_chan->offload_ch && !mhi_drv->dl_xfer_cb)
1301 goto exit_probe;
1302
1303 mhi_event = &mhi_cntrl->mhi_event[dl_chan->er_index];
1304
1305 /*
1306 * If the channel event ring is managed by client, then
1307 * status_cb must be provided so that the framework can
1308 * notify pending data
1309 */
1310 if (mhi_event->cl_manage && !mhi_drv->status_cb)
1311 goto exit_probe;
1312
1313 dl_chan->xfer_cb = mhi_drv->dl_xfer_cb;
1314 }
1315
1316 /* Call the user provided probe function */
1317 ret = mhi_drv->probe(mhi_dev, mhi_dev->id);
1318 if (ret)
1319 goto exit_probe;
1320
1321 mhi_device_put(mhi_dev);
1322
1323 return ret;
1324
1325 exit_probe:
1326 mhi_unprepare_from_transfer(mhi_dev);
1327
1328 mhi_device_put(mhi_dev);
1329
1330 return ret;
1331 }
1332
mhi_remove(struct device * dev)1333 static void mhi_remove(struct device *dev)
1334 {
1335 struct mhi_device *mhi_dev = to_mhi_device(dev);
1336 struct mhi_driver *mhi_drv = to_mhi_driver(dev->driver);
1337 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
1338 struct mhi_chan *mhi_chan;
1339 enum mhi_ch_state ch_state[] = {
1340 MHI_CH_STATE_DISABLED,
1341 MHI_CH_STATE_DISABLED
1342 };
1343 int dir;
1344
1345 /* Skip if it is a controller device */
1346 if (mhi_dev->dev_type == MHI_DEVICE_CONTROLLER)
1347 return;
1348
1349 /* Reset both channels */
1350 for (dir = 0; dir < 2; dir++) {
1351 mhi_chan = dir ? mhi_dev->ul_chan : mhi_dev->dl_chan;
1352
1353 if (!mhi_chan)
1354 continue;
1355
1356 /* Wake all threads waiting for completion */
1357 write_lock_irq(&mhi_chan->lock);
1358 mhi_chan->ccs = MHI_EV_CC_INVALID;
1359 complete_all(&mhi_chan->completion);
1360 write_unlock_irq(&mhi_chan->lock);
1361
1362 /* Set the channel state to disabled */
1363 mutex_lock(&mhi_chan->mutex);
1364 write_lock_irq(&mhi_chan->lock);
1365 ch_state[dir] = mhi_chan->ch_state;
1366 mhi_chan->ch_state = MHI_CH_STATE_SUSPENDED;
1367 write_unlock_irq(&mhi_chan->lock);
1368
1369 /* Reset the non-offload channel */
1370 if (!mhi_chan->offload_ch)
1371 mhi_reset_chan(mhi_cntrl, mhi_chan);
1372
1373 mutex_unlock(&mhi_chan->mutex);
1374 }
1375
1376 mhi_drv->remove(mhi_dev);
1377
1378 /* De-init channel if it was enabled */
1379 for (dir = 0; dir < 2; dir++) {
1380 mhi_chan = dir ? mhi_dev->ul_chan : mhi_dev->dl_chan;
1381
1382 if (!mhi_chan)
1383 continue;
1384
1385 mutex_lock(&mhi_chan->mutex);
1386
1387 if ((ch_state[dir] == MHI_CH_STATE_ENABLED ||
1388 ch_state[dir] == MHI_CH_STATE_STOP) &&
1389 !mhi_chan->offload_ch)
1390 mhi_deinit_chan_ctxt(mhi_cntrl, mhi_chan);
1391
1392 mhi_chan->ch_state = MHI_CH_STATE_DISABLED;
1393
1394 mutex_unlock(&mhi_chan->mutex);
1395 }
1396
1397 while (mhi_dev->dev_wake)
1398 mhi_device_put(mhi_dev);
1399 }
1400
__mhi_driver_register(struct mhi_driver * mhi_drv,struct module * owner)1401 int __mhi_driver_register(struct mhi_driver *mhi_drv, struct module *owner)
1402 {
1403 struct device_driver *driver = &mhi_drv->driver;
1404
1405 if (!mhi_drv->probe || !mhi_drv->remove)
1406 return -EINVAL;
1407
1408 driver->bus = &mhi_bus_type;
1409 driver->owner = owner;
1410
1411 return driver_register(driver);
1412 }
1413 EXPORT_SYMBOL_GPL(__mhi_driver_register);
1414
mhi_driver_unregister(struct mhi_driver * mhi_drv)1415 void mhi_driver_unregister(struct mhi_driver *mhi_drv)
1416 {
1417 driver_unregister(&mhi_drv->driver);
1418 }
1419 EXPORT_SYMBOL_GPL(mhi_driver_unregister);
1420
mhi_uevent(const struct device * dev,struct kobj_uevent_env * env)1421 static int mhi_uevent(const struct device *dev, struct kobj_uevent_env *env)
1422 {
1423 const struct mhi_device *mhi_dev = to_mhi_device(dev);
1424
1425 return add_uevent_var(env, "MODALIAS=" MHI_DEVICE_MODALIAS_FMT,
1426 mhi_dev->name);
1427 }
1428
mhi_match(struct device * dev,const struct device_driver * drv)1429 static int mhi_match(struct device *dev, const struct device_driver *drv)
1430 {
1431 struct mhi_device *mhi_dev = to_mhi_device(dev);
1432 const struct mhi_driver *mhi_drv = to_mhi_driver(drv);
1433 const struct mhi_device_id *id;
1434
1435 /*
1436 * If the device is a controller type then there is no client driver
1437 * associated with it
1438 */
1439 if (mhi_dev->dev_type == MHI_DEVICE_CONTROLLER)
1440 return 0;
1441
1442 for (id = mhi_drv->id_table; id->chan[0]; id++)
1443 if (!strcmp(mhi_dev->name, id->chan)) {
1444 mhi_dev->id = id;
1445 return 1;
1446 }
1447
1448 return 0;
1449 };
1450
1451 const struct bus_type mhi_bus_type = {
1452 .name = "mhi",
1453 .dev_name = "mhi",
1454 .match = mhi_match,
1455 .uevent = mhi_uevent,
1456 .probe = mhi_probe,
1457 .remove = mhi_remove,
1458 .dev_groups = mhi_dev_groups,
1459 };
1460
mhi_init(void)1461 static int __init mhi_init(void)
1462 {
1463 mhi_debugfs_init();
1464 return bus_register(&mhi_bus_type);
1465 }
1466
mhi_exit(void)1467 static void __exit mhi_exit(void)
1468 {
1469 mhi_debugfs_exit();
1470 bus_unregister(&mhi_bus_type);
1471 }
1472
1473 postcore_initcall(mhi_init);
1474 module_exit(mhi_exit);
1475
1476 MODULE_LICENSE("GPL v2");
1477 MODULE_DESCRIPTION("Modem Host Interface");
1478