1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* Copyright 2017-2019 NXP */ 3 4 #include <linux/unaligned.h> 5 #include <linux/module.h> 6 #include <linux/of.h> 7 #include <linux/of_platform.h> 8 #include <linux/of_net.h> 9 #include <linux/pcs-lynx.h> 10 #include "enetc_ierb.h" 11 #include "enetc_pf_common.h" 12 13 #define ENETC_DRV_NAME_STR "ENETC PF driver" 14 15 static void enetc_pf_get_primary_mac_addr(struct enetc_hw *hw, int si, u8 *addr) 16 { 17 u32 upper = __raw_readl(hw->port + ENETC_PSIPMAR0(si)); 18 u16 lower = __raw_readw(hw->port + ENETC_PSIPMAR1(si)); 19 20 put_unaligned_le32(upper, addr); 21 put_unaligned_le16(lower, addr + 4); 22 } 23 24 static void enetc_pf_set_primary_mac_addr(struct enetc_hw *hw, int si, 25 const u8 *addr) 26 { 27 u32 upper = get_unaligned_le32(addr); 28 u16 lower = get_unaligned_le16(addr + 4); 29 30 __raw_writel(upper, hw->port + ENETC_PSIPMAR0(si)); 31 __raw_writew(lower, hw->port + ENETC_PSIPMAR1(si)); 32 } 33 34 static struct phylink_pcs *enetc_pf_create_pcs(struct enetc_pf *pf, 35 struct mii_bus *bus) 36 { 37 return lynx_pcs_create_mdiodev(bus, 0); 38 } 39 40 static void enetc_pf_destroy_pcs(struct phylink_pcs *pcs) 41 { 42 lynx_pcs_destroy(pcs); 43 } 44 45 static void enetc_set_isol_vlan(struct enetc_hw *hw, int si, u16 vlan, u8 qos) 46 { 47 u32 val = 0; 48 49 if (vlan) 50 val = ENETC_PSIVLAN_EN | ENETC_PSIVLAN_SET_QOS(qos) | vlan; 51 52 enetc_port_wr(hw, ENETC_PSIVLANR(si), val); 53 } 54 55 static void enetc_add_mac_addr_em_filter(struct enetc_mac_filter *filter, 56 const unsigned char *addr) 57 { 58 /* add exact match addr */ 59 ether_addr_copy(filter->mac_addr, addr); 60 filter->mac_addr_cnt++; 61 } 62 63 static void enetc_sync_mac_filters(struct enetc_si *si) 64 { 65 struct enetc_mac_filter *f = si->mac_filter; 66 int i, pos; 67 68 pos = EMETC_MAC_ADDR_FILT_RES; 69 70 for (i = 0; i < MADDR_TYPE; i++, f++) { 71 bool em = (f->mac_addr_cnt == 1) && (i == UC); 72 bool clear = !f->mac_addr_cnt; 73 u64 hash; 74 75 if (clear) { 76 if (i == UC) { 77 enetc_clear_mac_flt_entry(si, pos); 78 enetc_set_si_uc_hash_filter(si, 0, 0); 79 } else { 80 enetc_set_si_mc_hash_filter(si, 0, 0); 81 } 82 83 continue; 84 } 85 86 /* exact match filter */ 87 if (em) { 88 int err; 89 90 enetc_set_si_uc_hash_filter(si, 0, 0); 91 92 err = enetc_set_mac_flt_entry(si, pos, f->mac_addr, 93 BIT(0)); 94 if (!err) 95 continue; 96 97 /* fallback to HT filtering */ 98 dev_warn(&si->pdev->dev, "fallback to HT filt (%d)\n", 99 err); 100 } 101 102 bitmap_to_arr64(&hash, f->mac_hash_table, 103 ENETC_MADDR_HASH_TBL_SZ); 104 /* hash table filter, clear EM filter for UC entries */ 105 if (i == UC) { 106 enetc_clear_mac_flt_entry(si, pos); 107 enetc_set_si_uc_hash_filter(si, 0, hash); 108 } else { 109 enetc_set_si_mc_hash_filter(si, 0, hash); 110 } 111 } 112 } 113 114 static void enetc_pf_set_rx_mode(struct net_device *ndev) 115 { 116 struct enetc_ndev_priv *priv = netdev_priv(ndev); 117 bool uprom = false, mprom = false; 118 struct enetc_mac_filter *filter; 119 struct enetc_si *si = priv->si; 120 struct netdev_hw_addr *ha; 121 bool em; 122 123 if (ndev->flags & IFF_PROMISC) { 124 /* enable promisc mode for SI0 (PF) */ 125 uprom = true; 126 mprom = true; 127 } else if (ndev->flags & IFF_ALLMULTI) { 128 /* enable multi cast promisc mode for SI0 (PF) */ 129 mprom = true; 130 } 131 132 /* first 2 filter entries belong to PF */ 133 if (!uprom) { 134 /* Update unicast filters */ 135 filter = &si->mac_filter[UC]; 136 enetc_reset_mac_addr_filter(filter); 137 138 em = (netdev_uc_count(ndev) == 1); 139 netdev_for_each_uc_addr(ha, ndev) { 140 if (em) { 141 enetc_add_mac_addr_em_filter(filter, ha->addr); 142 break; 143 } 144 145 enetc_add_mac_addr_ht_filter(filter, ha->addr); 146 } 147 } 148 149 if (!mprom) { 150 /* Update multicast filters */ 151 filter = &si->mac_filter[MC]; 152 enetc_reset_mac_addr_filter(filter); 153 154 netdev_for_each_mc_addr(ha, ndev) { 155 if (!is_multicast_ether_addr(ha->addr)) 156 continue; 157 158 enetc_add_mac_addr_ht_filter(filter, ha->addr); 159 } 160 } 161 162 if (!uprom || !mprom) 163 /* update PF entries */ 164 enetc_sync_mac_filters(si); 165 166 enetc_set_si_uc_promisc(si, 0, uprom); 167 enetc_set_si_mc_promisc(si, 0, mprom); 168 } 169 170 static void enetc_set_loopback(struct net_device *ndev, bool en) 171 { 172 struct enetc_ndev_priv *priv = netdev_priv(ndev); 173 struct enetc_si *si = priv->si; 174 u32 reg; 175 176 reg = enetc_port_mac_rd(si, ENETC_PM0_IF_MODE); 177 if (reg & ENETC_PM0_IFM_RG) { 178 /* RGMII mode */ 179 reg = (reg & ~ENETC_PM0_IFM_RLP) | 180 (en ? ENETC_PM0_IFM_RLP : 0); 181 enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, reg); 182 } else { 183 /* assume SGMII mode */ 184 reg = enetc_port_mac_rd(si, ENETC_PM0_CMD_CFG); 185 reg = (reg & ~ENETC_PM0_CMD_XGLP) | 186 (en ? ENETC_PM0_CMD_XGLP : 0); 187 reg = (reg & ~ENETC_PM0_CMD_PHY_TX_EN) | 188 (en ? ENETC_PM0_CMD_PHY_TX_EN : 0); 189 enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, reg); 190 } 191 } 192 193 static int enetc_pf_set_vf_vlan(struct net_device *ndev, int vf, u16 vlan, 194 u8 qos, __be16 proto) 195 { 196 struct enetc_ndev_priv *priv = netdev_priv(ndev); 197 struct enetc_pf *pf = enetc_si_priv(priv->si); 198 struct enetc_vf_state *vf_state; 199 200 if (priv->si->errata & ENETC_ERR_VLAN_ISOL) 201 return -EOPNOTSUPP; 202 203 if (vf >= pf->total_vfs) 204 return -EINVAL; 205 206 if (proto != htons(ETH_P_8021Q)) 207 /* only C-tags supported for now */ 208 return -EPROTONOSUPPORT; 209 210 enetc_set_isol_vlan(&priv->si->hw, vf + 1, vlan, qos); 211 212 vf_state = &pf->vf_state[vf]; 213 mutex_lock(&vf_state->lock); 214 /* Currently only C-tags is supported, so tpid is always 0, 215 * which indicates ETH_P_8021Q. 216 */ 217 vf_state->tpid = 0; 218 vf_state->qos = qos; 219 vf_state->vid = vlan; 220 mutex_unlock(&vf_state->lock); 221 222 return 0; 223 } 224 225 static int enetc_pf_set_vf_spoofchk(struct net_device *ndev, int vf, bool en) 226 { 227 struct enetc_ndev_priv *priv = netdev_priv(ndev); 228 struct enetc_pf *pf = enetc_si_priv(priv->si); 229 struct enetc_vf_state *vf_state; 230 u32 cfgr; 231 232 if (vf >= pf->total_vfs) 233 return -EINVAL; 234 235 cfgr = enetc_port_rd(&priv->si->hw, ENETC_PSICFGR0(vf + 1)); 236 cfgr = (cfgr & ~ENETC_PSICFGR0_ASE) | (en ? ENETC_PSICFGR0_ASE : 0); 237 enetc_port_wr(&priv->si->hw, ENETC_PSICFGR0(vf + 1), cfgr); 238 239 vf_state = &pf->vf_state[vf]; 240 mutex_lock(&vf_state->lock); 241 242 if (en) 243 vf_state->flags |= ENETC_VF_FLAG_SPOOFCHK; 244 else 245 vf_state->flags &= ~ENETC_VF_FLAG_SPOOFCHK; 246 247 mutex_unlock(&vf_state->lock); 248 249 return 0; 250 } 251 252 static void enetc_port_assign_rfs_entries(struct enetc_si *si) 253 { 254 struct enetc_pf *pf = enetc_si_priv(si); 255 struct enetc_hw *hw = &si->hw; 256 int num_entries, vf_entries, i; 257 u32 val; 258 259 /* split RFS entries between functions */ 260 val = enetc_port_rd(hw, ENETC_PRFSCAPR); 261 num_entries = ENETC_PRFSCAPR_GET_NUM_RFS(val); 262 vf_entries = num_entries / (pf->total_vfs + 1); 263 264 for (i = 0; i < pf->total_vfs; i++) 265 enetc_port_wr(hw, ENETC_PSIRFSCFGR(i + 1), vf_entries); 266 enetc_port_wr(hw, ENETC_PSIRFSCFGR(0), 267 num_entries - vf_entries * pf->total_vfs); 268 269 /* enable RFS on port */ 270 enetc_port_wr(hw, ENETC_PRFSMR, ENETC_PRFSMR_RFSE); 271 } 272 273 static void enetc_port_get_caps(struct enetc_si *si) 274 { 275 struct enetc_hw *hw = &si->hw; 276 u32 val; 277 278 val = enetc_port_rd(hw, ENETC_PCAPR0); 279 280 if (val & ENETC_PCAPR0_QBV) 281 si->hw_features |= ENETC_SI_F_QBV; 282 283 if (val & ENETC_PCAPR0_QBU) 284 si->hw_features |= ENETC_SI_F_QBU; 285 286 if (val & ENETC_PCAPR0_PSFP) 287 si->hw_features |= ENETC_SI_F_PSFP; 288 } 289 290 static void enetc_port_si_configure(struct enetc_si *si) 291 { 292 struct enetc_pf *pf = enetc_si_priv(si); 293 struct enetc_hw *hw = &si->hw; 294 int num_rings, i; 295 u32 val; 296 297 enetc_port_get_caps(si); 298 299 val = enetc_port_rd(hw, ENETC_PCAPR0); 300 num_rings = min(ENETC_PCAPR0_RXBDR(val), ENETC_PCAPR0_TXBDR(val)); 301 302 val = ENETC_PSICFGR0_SET_TXBDR(ENETC_PF_NUM_RINGS); 303 val |= ENETC_PSICFGR0_SET_RXBDR(ENETC_PF_NUM_RINGS); 304 305 if (unlikely(num_rings < ENETC_PF_NUM_RINGS)) { 306 val = ENETC_PSICFGR0_SET_TXBDR(num_rings); 307 val |= ENETC_PSICFGR0_SET_RXBDR(num_rings); 308 309 dev_warn(&si->pdev->dev, "Found %d rings, expected %d!\n", 310 num_rings, ENETC_PF_NUM_RINGS); 311 312 num_rings = 0; 313 } 314 315 /* Add default one-time settings for SI0 (PF) */ 316 val |= ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S); 317 318 enetc_port_wr(hw, ENETC_PSICFGR0(0), val); 319 320 if (num_rings) 321 num_rings -= ENETC_PF_NUM_RINGS; 322 323 /* Configure the SIs for each available VF */ 324 val = ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S); 325 val |= ENETC_PSICFGR0_VTE | ENETC_PSICFGR0_SIVIE; 326 327 if (num_rings) { 328 num_rings /= pf->total_vfs; 329 val |= ENETC_PSICFGR0_SET_TXBDR(num_rings); 330 val |= ENETC_PSICFGR0_SET_RXBDR(num_rings); 331 } 332 333 for (i = 0; i < pf->total_vfs; i++) 334 enetc_port_wr(hw, ENETC_PSICFGR0(i + 1), val); 335 336 /* Port level VLAN settings */ 337 val = ENETC_PVCLCTR_OVTPIDL(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S); 338 enetc_port_wr(hw, ENETC_PVCLCTR, val); 339 /* use outer tag for VLAN filtering */ 340 enetc_port_wr(hw, ENETC_PSIVLANFMR, ENETC_PSIVLANFMR_VS); 341 } 342 343 void enetc_set_ptcmsdur(struct enetc_hw *hw, u32 *max_sdu) 344 { 345 int tc; 346 347 for (tc = 0; tc < 8; tc++) { 348 u32 val = ENETC_MAC_MAXFRM_SIZE; 349 350 if (max_sdu[tc]) 351 val = max_sdu[tc] + VLAN_ETH_HLEN; 352 353 enetc_port_wr(hw, ENETC_PTCMSDUR(tc), val); 354 } 355 } 356 357 void enetc_reset_ptcmsdur(struct enetc_hw *hw) 358 { 359 int tc; 360 361 for (tc = 0; tc < 8; tc++) 362 enetc_port_wr(hw, ENETC_PTCMSDUR(tc), ENETC_MAC_MAXFRM_SIZE); 363 } 364 365 static void enetc_configure_port_mac(struct enetc_si *si) 366 { 367 struct enetc_hw *hw = &si->hw; 368 369 enetc_port_mac_wr(si, ENETC_PM0_MAXFRM, 370 ENETC_SET_MAXFRM(ENETC_RX_MAXFRM_SIZE)); 371 372 enetc_reset_ptcmsdur(hw); 373 374 enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, ENETC_PM0_CMD_PHY_TX_EN | 375 ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC); 376 377 /* On LS1028A, the MAC RX FIFO defaults to 2, which is too high 378 * and may lead to RX lock-up under traffic. Set it to 1 instead, 379 * as recommended by the hardware team. 380 */ 381 enetc_port_mac_wr(si, ENETC_PM0_RX_FIFO, ENETC_PM0_RX_FIFO_VAL); 382 } 383 384 static void enetc_mac_config(struct enetc_si *si, phy_interface_t phy_mode) 385 { 386 u32 val; 387 388 if (phy_interface_mode_is_rgmii(phy_mode)) { 389 val = enetc_port_mac_rd(si, ENETC_PM0_IF_MODE); 390 val &= ~(ENETC_PM0_IFM_EN_AUTO | ENETC_PM0_IFM_IFMODE_MASK); 391 val |= ENETC_PM0_IFM_IFMODE_GMII | ENETC_PM0_IFM_RG; 392 enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, val); 393 } 394 395 if (phy_mode == PHY_INTERFACE_MODE_USXGMII) { 396 val = ENETC_PM0_IFM_FULL_DPX | ENETC_PM0_IFM_IFMODE_XGMII; 397 enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, val); 398 } 399 } 400 401 static void enetc_mac_enable(struct enetc_si *si, bool en) 402 { 403 u32 val = enetc_port_mac_rd(si, ENETC_PM0_CMD_CFG); 404 405 val &= ~(ENETC_PM0_TX_EN | ENETC_PM0_RX_EN); 406 val |= en ? (ENETC_PM0_TX_EN | ENETC_PM0_RX_EN) : 0; 407 408 enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, val); 409 } 410 411 static void enetc_configure_port(struct enetc_pf *pf) 412 { 413 struct enetc_hw *hw = &pf->si->hw; 414 415 enetc_configure_port_mac(pf->si); 416 417 enetc_port_si_configure(pf->si); 418 419 /* set up hash key */ 420 enetc_set_default_rss_key(pf); 421 422 /* split up RFS entries */ 423 enetc_port_assign_rfs_entries(pf->si); 424 /* enforce VLAN promisc mode for all SIs */ 425 for (int i = 0; i < pf->total_vfs + 1; i++) 426 enetc_set_si_vlan_promisc(pf->si, i, true); 427 428 enetc_port_wr(hw, ENETC_PSIPMMR, 0); 429 430 /* enable port */ 431 enetc_port_wr(hw, ENETC_PMR, ENETC_PMR_EN); 432 } 433 434 static int enetc_pf_set_features(struct net_device *ndev, 435 netdev_features_t features) 436 { 437 netdev_features_t changed = ndev->features ^ features; 438 struct enetc_ndev_priv *priv = netdev_priv(ndev); 439 int err; 440 441 if (changed & NETIF_F_HW_TC) { 442 err = enetc_set_psfp(ndev, !!(features & NETIF_F_HW_TC)); 443 if (err) 444 return err; 445 } 446 447 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) { 448 bool promisc = !(features & NETIF_F_HW_VLAN_CTAG_FILTER); 449 450 enetc_set_si_vlan_promisc(priv->si, 0, promisc); 451 } 452 453 if (changed & NETIF_F_LOOPBACK) 454 enetc_set_loopback(ndev, !!(features & NETIF_F_LOOPBACK)); 455 456 enetc_set_features(ndev, features); 457 458 return 0; 459 } 460 461 static int enetc_pf_setup_tc(struct net_device *ndev, enum tc_setup_type type, 462 void *type_data) 463 { 464 switch (type) { 465 case TC_QUERY_CAPS: 466 return enetc_qos_query_caps(ndev, type_data); 467 case TC_SETUP_QDISC_MQPRIO: 468 return enetc_setup_tc_mqprio(ndev, type_data); 469 case TC_SETUP_QDISC_TAPRIO: 470 return enetc_setup_tc_taprio(ndev, type_data); 471 case TC_SETUP_QDISC_CBS: 472 return enetc_setup_tc_cbs(ndev, type_data); 473 case TC_SETUP_QDISC_ETF: 474 return enetc_setup_tc_txtime(ndev, type_data); 475 case TC_SETUP_BLOCK: 476 return enetc_setup_tc_psfp(ndev, type_data); 477 default: 478 return -EOPNOTSUPP; 479 } 480 } 481 482 static const struct net_device_ops enetc_ndev_ops = { 483 .ndo_open = enetc_open, 484 .ndo_stop = enetc_close, 485 .ndo_start_xmit = enetc_xmit, 486 .ndo_get_stats = enetc_get_stats, 487 .ndo_set_mac_address = enetc_pf_set_mac_addr, 488 .ndo_set_rx_mode = enetc_pf_set_rx_mode, 489 .ndo_vlan_rx_add_vid = enetc_vlan_rx_add_vid, 490 .ndo_vlan_rx_kill_vid = enetc_vlan_rx_del_vid, 491 .ndo_set_vf_trust = enetc_pf_set_vf_trust, 492 .ndo_set_vf_mac = enetc_pf_set_vf_mac, 493 .ndo_set_vf_vlan = enetc_pf_set_vf_vlan, 494 .ndo_set_vf_spoofchk = enetc_pf_set_vf_spoofchk, 495 .ndo_set_features = enetc_pf_set_features, 496 .ndo_eth_ioctl = enetc_ioctl, 497 .ndo_setup_tc = enetc_pf_setup_tc, 498 .ndo_bpf = enetc_setup_bpf, 499 .ndo_xdp_xmit = enetc_xdp_xmit, 500 .ndo_hwtstamp_get = enetc_hwtstamp_get, 501 .ndo_hwtstamp_set = enetc_hwtstamp_set, 502 .ndo_get_vf_config = enetc_pf_get_vf_config, 503 }; 504 505 static struct phylink_pcs * 506 enetc_pl_mac_select_pcs(struct phylink_config *config, phy_interface_t iface) 507 { 508 struct enetc_pf *pf = phylink_to_enetc_pf(config); 509 510 return pf->pcs; 511 } 512 513 static void enetc_pl_mac_config(struct phylink_config *config, 514 unsigned int mode, 515 const struct phylink_link_state *state) 516 { 517 struct enetc_pf *pf = phylink_to_enetc_pf(config); 518 519 enetc_mac_config(pf->si, state->interface); 520 } 521 522 static void enetc_force_rgmii_mac(struct enetc_si *si, int speed, int duplex) 523 { 524 u32 old_val, val; 525 526 old_val = val = enetc_port_mac_rd(si, ENETC_PM0_IF_MODE); 527 528 if (speed == SPEED_1000) { 529 val &= ~ENETC_PM0_IFM_SSP_MASK; 530 val |= ENETC_PM0_IFM_SSP_1000; 531 } else if (speed == SPEED_100) { 532 val &= ~ENETC_PM0_IFM_SSP_MASK; 533 val |= ENETC_PM0_IFM_SSP_100; 534 } else if (speed == SPEED_10) { 535 val &= ~ENETC_PM0_IFM_SSP_MASK; 536 val |= ENETC_PM0_IFM_SSP_10; 537 } 538 539 if (duplex == DUPLEX_FULL) 540 val |= ENETC_PM0_IFM_FULL_DPX; 541 else 542 val &= ~ENETC_PM0_IFM_FULL_DPX; 543 544 if (val == old_val) 545 return; 546 547 enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, val); 548 } 549 550 static void enetc_pl_mac_link_up(struct phylink_config *config, 551 struct phy_device *phy, unsigned int mode, 552 phy_interface_t interface, int speed, 553 int duplex, bool tx_pause, bool rx_pause) 554 { 555 struct enetc_pf *pf = phylink_to_enetc_pf(config); 556 u32 pause_off_thresh = 0, pause_on_thresh = 0; 557 u32 init_quanta = 0, refresh_quanta = 0; 558 struct enetc_hw *hw = &pf->si->hw; 559 struct enetc_si *si = pf->si; 560 struct enetc_ndev_priv *priv; 561 u32 cmd_cfg; 562 563 priv = netdev_priv(pf->si->ndev); 564 565 if (pf->si->hw_features & ENETC_SI_F_QBV) 566 enetc_sched_speed_set(priv, speed); 567 568 if (!phylink_autoneg_inband(mode) && 569 phy_interface_mode_is_rgmii(interface)) 570 enetc_force_rgmii_mac(si, speed, duplex); 571 572 /* Flow control */ 573 enetc_set_congestion_mode(priv, tx_pause); 574 575 if (tx_pause) { 576 /* When the port first enters congestion, send a PAUSE request 577 * with the maximum number of quanta. When the port exits 578 * congestion, it will automatically send a PAUSE frame with 579 * zero quanta. 580 */ 581 init_quanta = 0xffff; 582 583 /* Also, set up the refresh timer to send follow-up PAUSE 584 * frames at half the quanta value, in case the congestion 585 * condition persists. 586 */ 587 refresh_quanta = 0xffff / 2; 588 589 /* Start emitting PAUSE frames when 3 large frames (or more 590 * smaller frames) have accumulated in the FIFO waiting to be 591 * DMAed to the RX ring. 592 */ 593 pause_on_thresh = 3 * ENETC_MAC_MAXFRM_SIZE; 594 pause_off_thresh = 1 * ENETC_MAC_MAXFRM_SIZE; 595 } 596 597 enetc_port_mac_wr(si, ENETC_PM0_PAUSE_QUANTA, init_quanta); 598 enetc_port_mac_wr(si, ENETC_PM0_PAUSE_THRESH, refresh_quanta); 599 enetc_port_wr(hw, ENETC_PPAUONTR, pause_on_thresh); 600 enetc_port_wr(hw, ENETC_PPAUOFFTR, pause_off_thresh); 601 602 cmd_cfg = enetc_port_mac_rd(si, ENETC_PM0_CMD_CFG); 603 604 if (rx_pause) 605 cmd_cfg &= ~ENETC_PM0_PAUSE_IGN; 606 else 607 cmd_cfg |= ENETC_PM0_PAUSE_IGN; 608 609 enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, cmd_cfg); 610 611 enetc_mac_enable(si, true); 612 613 if (si->hw_features & ENETC_SI_F_QBU) 614 enetc_mm_link_state_update(priv, true); 615 } 616 617 static void enetc_pl_mac_link_down(struct phylink_config *config, 618 unsigned int mode, 619 phy_interface_t interface) 620 { 621 struct enetc_pf *pf = phylink_to_enetc_pf(config); 622 struct enetc_si *si = pf->si; 623 struct enetc_ndev_priv *priv; 624 625 priv = netdev_priv(si->ndev); 626 627 if (si->hw_features & ENETC_SI_F_QBU) 628 enetc_mm_link_state_update(priv, false); 629 630 enetc_mac_enable(si, false); 631 } 632 633 static const struct phylink_mac_ops enetc_mac_phylink_ops = { 634 .mac_select_pcs = enetc_pl_mac_select_pcs, 635 .mac_config = enetc_pl_mac_config, 636 .mac_link_up = enetc_pl_mac_link_up, 637 .mac_link_down = enetc_pl_mac_link_down, 638 }; 639 640 /* Initialize the entire shared memory for the flow steering entries 641 * of this port (PF + VFs) 642 */ 643 static int enetc_init_port_rfs_memory(struct enetc_si *si) 644 { 645 struct enetc_cmd_rfse rfse = {0}; 646 struct enetc_hw *hw = &si->hw; 647 int num_rfs, i, err = 0; 648 u32 val; 649 650 val = enetc_port_rd(hw, ENETC_PRFSCAPR); 651 num_rfs = ENETC_PRFSCAPR_GET_NUM_RFS(val); 652 653 for (i = 0; i < num_rfs; i++) { 654 err = enetc_set_fs_entry(si, &rfse, i); 655 if (err) 656 break; 657 } 658 659 return err; 660 } 661 662 static int enetc_init_port_rss_memory(struct enetc_si *si) 663 { 664 struct enetc_hw *hw = &si->hw; 665 int num_rss, err; 666 int *rss_table; 667 u32 val; 668 669 val = enetc_port_rd(hw, ENETC_PRSSCAPR); 670 num_rss = ENETC_PRSSCAPR_GET_NUM_RSS(val); 671 if (!num_rss) 672 return 0; 673 674 rss_table = kzalloc_objs(*rss_table, num_rss); 675 if (!rss_table) 676 return -ENOMEM; 677 678 err = enetc_set_rss_table(si, rss_table, num_rss); 679 680 kfree(rss_table); 681 682 return err; 683 } 684 685 static int enetc_pf_register_with_ierb(struct pci_dev *pdev) 686 { 687 struct platform_device *ierb_pdev; 688 struct device_node *ierb_node; 689 int ret; 690 691 ierb_node = of_find_compatible_node(NULL, NULL, 692 "fsl,ls1028a-enetc-ierb"); 693 if (!ierb_node) 694 return -ENODEV; 695 696 if (!of_device_is_available(ierb_node)) { 697 of_node_put(ierb_node); 698 return -ENODEV; 699 } 700 701 ierb_pdev = of_find_device_by_node(ierb_node); 702 of_node_put(ierb_node); 703 704 if (!ierb_pdev) 705 return -EPROBE_DEFER; 706 707 ret = enetc_ierb_register_pf(ierb_pdev, pdev); 708 709 put_device(&ierb_pdev->dev); 710 711 return ret; 712 } 713 714 static const struct enetc_si_ops enetc_psi_ops = { 715 .get_rss_table = enetc_get_rss_table, 716 .set_rss_table = enetc_set_rss_table, 717 }; 718 719 static struct enetc_si *enetc_psi_create(struct pci_dev *pdev) 720 { 721 struct enetc_si *si; 722 int err; 723 724 err = enetc_pci_probe(pdev, KBUILD_MODNAME, sizeof(struct enetc_pf)); 725 if (err) { 726 dev_err_probe(&pdev->dev, err, "PCI probing failed\n"); 727 goto out; 728 } 729 730 si = pci_get_drvdata(pdev); 731 if (!si->hw.port || !si->hw.global) { 732 err = -ENODEV; 733 dev_err(&pdev->dev, "could not map PF space, probing a VF?\n"); 734 goto out_pci_remove; 735 } 736 737 si->revision = enetc_get_ip_revision(&si->hw); 738 si->ops = &enetc_psi_ops; 739 err = enetc_get_driver_data(si); 740 if (err) { 741 dev_err(&pdev->dev, "Could not get PF driver data\n"); 742 goto out_pci_remove; 743 } 744 745 err = enetc_setup_cbdr(si); 746 if (err) 747 goto out_pci_remove; 748 749 err = enetc_init_port_rfs_memory(si); 750 if (err) { 751 dev_err(&pdev->dev, "Failed to initialize RFS memory\n"); 752 goto out_teardown_cbdr; 753 } 754 755 err = enetc_init_port_rss_memory(si); 756 if (err) { 757 dev_err(&pdev->dev, "Failed to initialize RSS memory\n"); 758 goto out_teardown_cbdr; 759 } 760 761 return si; 762 763 out_teardown_cbdr: 764 enetc_teardown_cbdr(si); 765 out_pci_remove: 766 enetc_pci_remove(pdev); 767 out: 768 return ERR_PTR(err); 769 } 770 771 static void enetc_psi_destroy(struct pci_dev *pdev) 772 { 773 struct enetc_si *si = pci_get_drvdata(pdev); 774 775 enetc_teardown_cbdr(si); 776 enetc_pci_remove(pdev); 777 } 778 779 static const struct enetc_pf_ops enetc_pf_ops = { 780 .set_si_primary_mac = enetc_pf_set_primary_mac_addr, 781 .get_si_primary_mac = enetc_pf_get_primary_mac_addr, 782 .create_pcs = enetc_pf_create_pcs, 783 .destroy_pcs = enetc_pf_destroy_pcs, 784 .enable_psfp = enetc_psfp_enable, 785 }; 786 787 static int enetc_pf_probe(struct pci_dev *pdev, 788 const struct pci_device_id *ent) 789 { 790 struct device_node *node = pdev->dev.of_node; 791 struct enetc_ndev_priv *priv; 792 struct net_device *ndev; 793 struct enetc_si *si; 794 struct enetc_pf *pf; 795 int err; 796 797 err = enetc_pf_register_with_ierb(pdev); 798 if (err == -EPROBE_DEFER) 799 return err; 800 if (err) 801 dev_warn(&pdev->dev, 802 "Could not register with IERB driver: %pe, please update the device tree\n", 803 ERR_PTR(err)); 804 805 si = enetc_psi_create(pdev); 806 if (IS_ERR(si)) { 807 err = PTR_ERR(si); 808 goto err_psi_create; 809 } 810 811 pf = enetc_si_priv(si); 812 pf->si = si; 813 pf->ops = &enetc_pf_ops; 814 815 err = enetc_init_sriov_resources(pf); 816 if (err) 817 goto err_init_sriov_resources; 818 819 err = enetc_setup_mac_addresses(node, pf); 820 if (err) 821 goto err_setup_mac_addresses; 822 823 enetc_configure_port(pf); 824 825 enetc_get_si_caps(si); 826 827 ndev = alloc_etherdev_mq(sizeof(*priv), ENETC_MAX_NUM_TXQS); 828 if (!ndev) { 829 err = -ENOMEM; 830 dev_err(&pdev->dev, "netdev creation failed\n"); 831 goto err_alloc_netdev; 832 } 833 834 enetc_pf_netdev_setup(si, ndev, &enetc_ndev_ops); 835 836 priv = netdev_priv(ndev); 837 838 mutex_init(&priv->mm_lock); 839 840 enetc_init_si_rings_params(priv); 841 842 err = enetc_alloc_si_resources(priv); 843 if (err) { 844 dev_err(&pdev->dev, "SI resource alloc failed\n"); 845 goto err_alloc_si_res; 846 } 847 848 err = enetc_configure_si(priv); 849 if (err) { 850 dev_err(&pdev->dev, "Failed to configure SI\n"); 851 goto err_config_si; 852 } 853 854 err = enetc_alloc_msix(priv); 855 if (err) { 856 dev_err(&pdev->dev, "MSIX alloc failed\n"); 857 goto err_alloc_msix; 858 } 859 860 err = of_get_phy_mode(node, &pf->if_mode); 861 if (err) { 862 dev_err(&pdev->dev, "Failed to read PHY mode\n"); 863 goto err_phy_mode; 864 } 865 866 err = enetc_mdiobus_create(pf, node); 867 if (err) 868 goto err_mdiobus_create; 869 870 err = enetc_phylink_create(priv, node, &enetc_mac_phylink_ops); 871 if (err) 872 goto err_phylink_create; 873 874 err = register_netdev(ndev); 875 if (err) 876 goto err_reg_netdev; 877 878 return 0; 879 880 err_reg_netdev: 881 enetc_phylink_destroy(priv); 882 err_phylink_create: 883 enetc_mdiobus_destroy(pf); 884 err_mdiobus_create: 885 err_phy_mode: 886 enetc_free_msix(priv); 887 err_config_si: 888 err_alloc_msix: 889 enetc_free_si_resources(priv); 890 err_alloc_si_res: 891 si->ndev = NULL; 892 free_netdev(ndev); 893 err_alloc_netdev: 894 err_setup_mac_addresses: 895 err_init_sriov_resources: 896 enetc_psi_destroy(pdev); 897 err_psi_create: 898 return err; 899 } 900 901 static void enetc_pf_remove(struct pci_dev *pdev) 902 { 903 struct enetc_si *si = pci_get_drvdata(pdev); 904 struct enetc_pf *pf = enetc_si_priv(si); 905 struct enetc_ndev_priv *priv; 906 907 priv = netdev_priv(si->ndev); 908 909 if (pf->num_vfs) 910 enetc_sriov_configure(pdev, 0); 911 912 unregister_netdev(si->ndev); 913 914 enetc_phylink_destroy(priv); 915 enetc_mdiobus_destroy(pf); 916 917 enetc_free_msix(priv); 918 919 enetc_free_si_resources(priv); 920 921 free_netdev(si->ndev); 922 enetc_psi_destroy(pdev); 923 } 924 925 static void enetc_fixup_clear_rss_rfs(struct pci_dev *pdev) 926 { 927 struct device_node *node = pdev->dev.of_node; 928 struct enetc_si *si; 929 930 /* Only apply quirk for disabled functions. For the ones 931 * that are enabled, enetc_pf_probe() will apply it. 932 */ 933 if (node && of_device_is_available(node)) 934 return; 935 936 si = enetc_psi_create(pdev); 937 if (!IS_ERR(si)) 938 enetc_psi_destroy(pdev); 939 } 940 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID_PF, 941 enetc_fixup_clear_rss_rfs); 942 943 static const struct pci_device_id enetc_pf_id_table[] = { 944 { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID_PF) }, 945 { 0, } /* End of table. */ 946 }; 947 MODULE_DEVICE_TABLE(pci, enetc_pf_id_table); 948 949 static struct pci_driver enetc_pf_driver = { 950 .name = KBUILD_MODNAME, 951 .id_table = enetc_pf_id_table, 952 .probe = enetc_pf_probe, 953 .remove = enetc_pf_remove, 954 #ifdef CONFIG_PCI_IOV 955 .sriov_configure = enetc_sriov_configure, 956 #endif 957 }; 958 module_pci_driver(enetc_pf_driver); 959 960 MODULE_DESCRIPTION(ENETC_DRV_NAME_STR); 961 MODULE_LICENSE("Dual BSD/GPL"); 962