1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved. 4 */ 5 6/dts-v1/; 7#include <dt-bindings/clock/sophgo,sg2042-clkgen.h> 8#include <dt-bindings/clock/sophgo,sg2042-pll.h> 9#include <dt-bindings/clock/sophgo,sg2042-rpgate.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/pinctrl-sg2042.h> 12#include <dt-bindings/reset/sophgo,sg2042-reset.h> 13 14#include "sg2042-cpus.dtsi" 15 16/ { 17 compatible = "sophgo,sg2042"; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 dma-noncoherent; 21 22 distance-map { 23 compatible = "numa-distance-map-v1"; 24 distance-matrix = <0 0 10>, 25 <0 1 15>, 26 <0 2 25>, 27 <0 3 30>, 28 <1 0 15>, 29 <1 1 10>, 30 <1 2 30>, 31 <1 3 25>, 32 <2 0 25>, 33 <2 1 30>, 34 <2 2 10>, 35 <2 3 15>, 36 <3 0 30>, 37 <3 1 25>, 38 <3 2 15>, 39 <3 3 10>; 40 }; 41 42 aliases { 43 serial0 = &uart0; 44 }; 45 46 cgi_main: oscillator0 { 47 compatible = "fixed-clock"; 48 clock-output-names = "cgi_main"; 49 #clock-cells = <0>; 50 }; 51 52 cgi_dpll0: oscillator1 { 53 compatible = "fixed-clock"; 54 clock-output-names = "cgi_dpll0"; 55 #clock-cells = <0>; 56 }; 57 58 cgi_dpll1: oscillator2 { 59 compatible = "fixed-clock"; 60 clock-output-names = "cgi_dpll1"; 61 #clock-cells = <0>; 62 }; 63 64 soc: soc { 65 compatible = "simple-bus"; 66 #address-cells = <2>; 67 #size-cells = <2>; 68 interrupt-parent = <&intc>; 69 ranges; 70 71 spifmc0: spi@7000180000 { 72 compatible = "sophgo,sg2042-spifmc-nor"; 73 reg = <0x70 0x00180000 0x0 0x1000000>; 74 #address-cells = <1>; 75 #size-cells = <0>; 76 clocks = <&clkgen GATE_CLK_AHB_SF>; 77 interrupt-parent = <&intc>; 78 interrupts = <108 IRQ_TYPE_LEVEL_HIGH>; 79 resets = <&rstgen RST_SF0>; 80 status = "disabled"; 81 }; 82 83 spifmc1: spi@7002180000 { 84 compatible = "sophgo,sg2042-spifmc-nor"; 85 reg = <0x70 0x02180000 0x0 0x1000000>; 86 #address-cells = <1>; 87 #size-cells = <0>; 88 clocks = <&clkgen GATE_CLK_AHB_SF>; 89 interrupt-parent = <&intc>; 90 interrupts = <109 IRQ_TYPE_LEVEL_HIGH>; 91 resets = <&rstgen RST_SF1>; 92 status = "disabled"; 93 }; 94 95 i2c0: i2c@7030005000 { 96 compatible = "snps,designware-i2c"; 97 reg = <0x70 0x30005000 0x0 0x1000>; 98 #address-cells = <1>; 99 #size-cells = <0>; 100 clocks = <&clkgen GATE_CLK_APB_I2C>; 101 clock-names = "ref"; 102 clock-frequency = <100000>; 103 interrupts = <101 IRQ_TYPE_LEVEL_HIGH>; 104 resets = <&rstgen RST_I2C0>; 105 status = "disabled"; 106 }; 107 108 i2c1: i2c@7030006000 { 109 compatible = "snps,designware-i2c"; 110 reg = <0x70 0x30006000 0x0 0x1000>; 111 #address-cells = <1>; 112 #size-cells = <0>; 113 clocks = <&clkgen GATE_CLK_APB_I2C>; 114 clock-names = "ref"; 115 clock-frequency = <100000>; 116 interrupts = <102 IRQ_TYPE_LEVEL_HIGH>; 117 resets = <&rstgen RST_I2C1>; 118 status = "disabled"; 119 }; 120 121 i2c2: i2c@7030007000 { 122 compatible = "snps,designware-i2c"; 123 reg = <0x70 0x30007000 0x0 0x1000>; 124 #address-cells = <1>; 125 #size-cells = <0>; 126 clocks = <&clkgen GATE_CLK_APB_I2C>; 127 clock-names = "ref"; 128 clock-frequency = <100000>; 129 interrupts = <103 IRQ_TYPE_LEVEL_HIGH>; 130 resets = <&rstgen RST_I2C2>; 131 status = "disabled"; 132 }; 133 134 i2c3: i2c@7030008000 { 135 compatible = "snps,designware-i2c"; 136 reg = <0x70 0x30008000 0x0 0x1000>; 137 #address-cells = <1>; 138 #size-cells = <0>; 139 clocks = <&clkgen GATE_CLK_APB_I2C>; 140 clock-names = "ref"; 141 clock-frequency = <100000>; 142 interrupts = <104 IRQ_TYPE_LEVEL_HIGH>; 143 resets = <&rstgen RST_I2C3>; 144 status = "disabled"; 145 }; 146 147 gpio0: gpio@7030009000 { 148 compatible = "snps,dw-apb-gpio"; 149 reg = <0x70 0x30009000 0x0 0x400>; 150 #address-cells = <1>; 151 #size-cells = <0>; 152 clocks = <&clkgen GATE_CLK_APB_GPIO>, 153 <&clkgen GATE_CLK_GPIO_DB>; 154 clock-names = "bus", "db"; 155 156 port0a: gpio-controller@0 { 157 compatible = "snps,dw-apb-gpio-port"; 158 gpio-controller; 159 #gpio-cells = <2>; 160 ngpios = <32>; 161 reg = <0>; 162 interrupt-controller; 163 #interrupt-cells = <2>; 164 interrupt-parent = <&intc>; 165 interrupts = <96 IRQ_TYPE_LEVEL_HIGH>; 166 }; 167 }; 168 169 gpio1: gpio@703000a000 { 170 compatible = "snps,dw-apb-gpio"; 171 reg = <0x70 0x3000a000 0x0 0x400>; 172 #address-cells = <1>; 173 #size-cells = <0>; 174 clocks = <&clkgen GATE_CLK_APB_GPIO>, 175 <&clkgen GATE_CLK_GPIO_DB>; 176 clock-names = "bus", "db"; 177 178 port1a: gpio-controller@0 { 179 compatible = "snps,dw-apb-gpio-port"; 180 gpio-controller; 181 #gpio-cells = <2>; 182 ngpios = <32>; 183 reg = <0>; 184 interrupt-controller; 185 #interrupt-cells = <2>; 186 interrupt-parent = <&intc>; 187 interrupts = <97 IRQ_TYPE_LEVEL_HIGH>; 188 }; 189 }; 190 191 gpio2: gpio@703000b000 { 192 compatible = "snps,dw-apb-gpio"; 193 reg = <0x70 0x3000b000 0x0 0x400>; 194 #address-cells = <1>; 195 #size-cells = <0>; 196 clocks = <&clkgen GATE_CLK_APB_GPIO>, 197 <&clkgen GATE_CLK_GPIO_DB>; 198 clock-names = "bus", "db"; 199 200 port2a: gpio-controller@0 { 201 compatible = "snps,dw-apb-gpio-port"; 202 gpio-controller; 203 #gpio-cells = <2>; 204 ngpios = <32>; 205 reg = <0>; 206 interrupt-controller; 207 #interrupt-cells = <2>; 208 interrupt-parent = <&intc>; 209 interrupts = <98 IRQ_TYPE_LEVEL_HIGH>; 210 }; 211 }; 212 213 pwm: pwm@703000c000 { 214 compatible = "sophgo,sg2042-pwm"; 215 reg = <0x70 0x3000c000 0x0 0x20>; 216 #pwm-cells = <3>; 217 clocks = <&clkgen GATE_CLK_APB_PWM>; 218 clock-names = "apb"; 219 resets = <&rstgen RST_PWM>; 220 }; 221 222 pllclk: clock-controller@70300100c0 { 223 compatible = "sophgo,sg2042-pll"; 224 reg = <0x70 0x300100c0 0x0 0x40>; 225 clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>; 226 clock-names = "cgi_main", "cgi_dpll0", "cgi_dpll1"; 227 #clock-cells = <1>; 228 }; 229 230 msi: msi-controller@7030010304 { 231 compatible = "sophgo,sg2042-msi"; 232 reg = <0x70 0x30010304 0x0 0x4>, 233 <0x70 0x30010300 0x0 0x4>; 234 reg-names = "clr", "doorbell"; 235 msi-controller; 236 #msi-cells = <0>; 237 msi-ranges = <&intc 64 IRQ_TYPE_EDGE_RISING 32>; 238 }; 239 240 rpgate: clock-controller@7030010368 { 241 compatible = "sophgo,sg2042-rpgate"; 242 reg = <0x70 0x30010368 0x0 0x98>; 243 clocks = <&clkgen GATE_CLK_RP_CPU_NORMAL>; 244 clock-names = "rpgate"; 245 #clock-cells = <1>; 246 }; 247 248 pinctrl: pinctrl@7030011000 { 249 compatible = "sophgo,sg2042-pinctrl"; 250 reg = <0x70 0x30011000 0x0 0x1000>; 251 }; 252 253 clkgen: clock-controller@7030012000 { 254 compatible = "sophgo,sg2042-clkgen"; 255 reg = <0x70 0x30012000 0x0 0x1000>; 256 clocks = <&pllclk MPLL_CLK>, 257 <&pllclk FPLL_CLK>, 258 <&pllclk DPLL0_CLK>, 259 <&pllclk DPLL1_CLK>; 260 clock-names = "mpll", 261 "fpll", 262 "dpll0", 263 "dpll1"; 264 #clock-cells = <1>; 265 }; 266 267 pcie_rc0: pcie@7060000000 { 268 compatible = "sophgo,sg2042-pcie-host"; 269 device_type = "pci"; 270 reg = <0x70 0x60000000 0x0 0x00800000>, 271 <0x40 0x00000000 0x0 0x00001000>; 272 reg-names = "reg", "cfg"; 273 linux,pci-domain = <0>; 274 #address-cells = <3>; 275 #size-cells = <2>; 276 ranges = <0x01000000 0x0 0x00000000 0x40 0xc0000000 0x0 0x00400000>, 277 <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>, 278 <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>, 279 <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, 280 <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; 281 bus-range = <0x0 0xff>; 282 vendor-id = <0x1f1c>; 283 device-id = <0x2042>; 284 cdns,no-bar-match-nbits = <48>; 285 msi-parent = <&msi>; 286 status = "disabled"; 287 }; 288 289 pcie_rc1: pcie@7060800000 { 290 compatible = "sophgo,sg2042-pcie-host"; 291 device_type = "pci"; 292 reg = <0x70 0x60800000 0x0 0x00800000>, 293 <0x44 0x00000000 0x0 0x00001000>; 294 reg-names = "reg", "cfg"; 295 linux,pci-domain = <1>; 296 #address-cells = <3>; 297 #size-cells = <2>; 298 ranges = <0x01000000 0x0 0x00000000 0x44 0xc0400000 0x0 0x00400000>, 299 <0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>, 300 <0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>, 301 <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>, 302 <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>; 303 bus-range = <0x0 0xff>; 304 vendor-id = <0x1f1c>; 305 device-id = <0x2042>; 306 cdns,no-bar-match-nbits = <48>; 307 msi-parent = <&msi>; 308 status = "disabled"; 309 }; 310 311 pcie_rc2: pcie@7062000000 { 312 compatible = "sophgo,sg2042-pcie-host"; 313 device_type = "pci"; 314 reg = <0x70 0x62000000 0x0 0x00800000>, 315 <0x48 0x00000000 0x0 0x00001000>; 316 reg-names = "reg", "cfg"; 317 linux,pci-domain = <2>; 318 #address-cells = <3>; 319 #size-cells = <2>; 320 ranges = <0x01000000 0x0 0x00000000 0x48 0xc0800000 0x0 0x00400000>, 321 <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>, 322 <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>, 323 <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>, 324 <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>; 325 bus-range = <0x0 0xff>; 326 vendor-id = <0x1f1c>; 327 device-id = <0x2042>; 328 cdns,no-bar-match-nbits = <48>; 329 msi-parent = <&msi>; 330 status = "disabled"; 331 }; 332 333 pcie_rc3: pcie@7062800000 { 334 compatible = "sophgo,sg2042-pcie-host"; 335 device_type = "pci"; 336 reg = <0x70 0x62800000 0x0 0x00800000>, 337 <0x4c 0x00000000 0x0 0x00001000>; 338 reg-names = "reg", "cfg"; 339 linux,pci-domain = <3>; 340 #address-cells = <3>; 341 #size-cells = <2>; 342 ranges = <0x01000000 0x0 0x00000000 0x4c 0xc0c00000 0x0 0x00400000>, 343 <0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>, 344 <0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>, 345 <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>, 346 <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>; 347 bus-range = <0x0 0xff>; 348 vendor-id = <0x1f1c>; 349 device-id = <0x2042>; 350 cdns,no-bar-match-nbits = <48>; 351 msi-parent = <&msi>; 352 status = "disabled"; 353 }; 354 355 clint_mswi: interrupt-controller@7094000000 { 356 compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi"; 357 reg = <0x00000070 0x94000000 0x00000000 0x00004000>; 358 interrupts-extended = <&cpu0_intc 3>, 359 <&cpu1_intc 3>, 360 <&cpu2_intc 3>, 361 <&cpu3_intc 3>, 362 <&cpu4_intc 3>, 363 <&cpu5_intc 3>, 364 <&cpu6_intc 3>, 365 <&cpu7_intc 3>, 366 <&cpu8_intc 3>, 367 <&cpu9_intc 3>, 368 <&cpu10_intc 3>, 369 <&cpu11_intc 3>, 370 <&cpu12_intc 3>, 371 <&cpu13_intc 3>, 372 <&cpu14_intc 3>, 373 <&cpu15_intc 3>, 374 <&cpu16_intc 3>, 375 <&cpu17_intc 3>, 376 <&cpu18_intc 3>, 377 <&cpu19_intc 3>, 378 <&cpu20_intc 3>, 379 <&cpu21_intc 3>, 380 <&cpu22_intc 3>, 381 <&cpu23_intc 3>, 382 <&cpu24_intc 3>, 383 <&cpu25_intc 3>, 384 <&cpu26_intc 3>, 385 <&cpu27_intc 3>, 386 <&cpu28_intc 3>, 387 <&cpu29_intc 3>, 388 <&cpu30_intc 3>, 389 <&cpu31_intc 3>, 390 <&cpu32_intc 3>, 391 <&cpu33_intc 3>, 392 <&cpu34_intc 3>, 393 <&cpu35_intc 3>, 394 <&cpu36_intc 3>, 395 <&cpu37_intc 3>, 396 <&cpu38_intc 3>, 397 <&cpu39_intc 3>, 398 <&cpu40_intc 3>, 399 <&cpu41_intc 3>, 400 <&cpu42_intc 3>, 401 <&cpu43_intc 3>, 402 <&cpu44_intc 3>, 403 <&cpu45_intc 3>, 404 <&cpu46_intc 3>, 405 <&cpu47_intc 3>, 406 <&cpu48_intc 3>, 407 <&cpu49_intc 3>, 408 <&cpu50_intc 3>, 409 <&cpu51_intc 3>, 410 <&cpu52_intc 3>, 411 <&cpu53_intc 3>, 412 <&cpu54_intc 3>, 413 <&cpu55_intc 3>, 414 <&cpu56_intc 3>, 415 <&cpu57_intc 3>, 416 <&cpu58_intc 3>, 417 <&cpu59_intc 3>, 418 <&cpu60_intc 3>, 419 <&cpu61_intc 3>, 420 <&cpu62_intc 3>, 421 <&cpu63_intc 3>; 422 }; 423 424 clint_mtimer0: timer@70ac004000 { 425 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 426 reg = <0x00000070 0xac004000 0x00000000 0x0000c000>; 427 reg-names = "mtimecmp"; 428 interrupts-extended = <&cpu0_intc 7>, 429 <&cpu1_intc 7>, 430 <&cpu2_intc 7>, 431 <&cpu3_intc 7>; 432 }; 433 434 clint_mtimer1: timer@70ac014000 { 435 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 436 reg = <0x00000070 0xac014000 0x00000000 0x0000c000>; 437 reg-names = "mtimecmp"; 438 interrupts-extended = <&cpu4_intc 7>, 439 <&cpu5_intc 7>, 440 <&cpu6_intc 7>, 441 <&cpu7_intc 7>; 442 }; 443 444 clint_mtimer2: timer@70ac024000 { 445 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 446 reg = <0x00000070 0xac024000 0x00000000 0x0000c000>; 447 reg-names = "mtimecmp"; 448 interrupts-extended = <&cpu8_intc 7>, 449 <&cpu9_intc 7>, 450 <&cpu10_intc 7>, 451 <&cpu11_intc 7>; 452 }; 453 454 clint_mtimer3: timer@70ac034000 { 455 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 456 reg = <0x00000070 0xac034000 0x00000000 0x0000c000>; 457 reg-names = "mtimecmp"; 458 interrupts-extended = <&cpu12_intc 7>, 459 <&cpu13_intc 7>, 460 <&cpu14_intc 7>, 461 <&cpu15_intc 7>; 462 }; 463 464 clint_mtimer4: timer@70ac044000 { 465 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 466 reg = <0x00000070 0xac044000 0x00000000 0x0000c000>; 467 reg-names = "mtimecmp"; 468 interrupts-extended = <&cpu16_intc 7>, 469 <&cpu17_intc 7>, 470 <&cpu18_intc 7>, 471 <&cpu19_intc 7>; 472 }; 473 474 clint_mtimer5: timer@70ac054000 { 475 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 476 reg = <0x00000070 0xac054000 0x00000000 0x0000c000>; 477 reg-names = "mtimecmp"; 478 interrupts-extended = <&cpu20_intc 7>, 479 <&cpu21_intc 7>, 480 <&cpu22_intc 7>, 481 <&cpu23_intc 7>; 482 }; 483 484 clint_mtimer6: timer@70ac064000 { 485 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 486 reg = <0x00000070 0xac064000 0x00000000 0x0000c000>; 487 reg-names = "mtimecmp"; 488 interrupts-extended = <&cpu24_intc 7>, 489 <&cpu25_intc 7>, 490 <&cpu26_intc 7>, 491 <&cpu27_intc 7>; 492 }; 493 494 clint_mtimer7: timer@70ac074000 { 495 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 496 reg = <0x00000070 0xac074000 0x00000000 0x0000c000>; 497 reg-names = "mtimecmp"; 498 interrupts-extended = <&cpu28_intc 7>, 499 <&cpu29_intc 7>, 500 <&cpu30_intc 7>, 501 <&cpu31_intc 7>; 502 }; 503 504 clint_mtimer8: timer@70ac084000 { 505 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 506 reg = <0x00000070 0xac084000 0x00000000 0x0000c000>; 507 reg-names = "mtimecmp"; 508 interrupts-extended = <&cpu32_intc 7>, 509 <&cpu33_intc 7>, 510 <&cpu34_intc 7>, 511 <&cpu35_intc 7>; 512 }; 513 514 clint_mtimer9: timer@70ac094000 { 515 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 516 reg = <0x00000070 0xac094000 0x00000000 0x0000c000>; 517 reg-names = "mtimecmp"; 518 interrupts-extended = <&cpu36_intc 7>, 519 <&cpu37_intc 7>, 520 <&cpu38_intc 7>, 521 <&cpu39_intc 7>; 522 }; 523 524 clint_mtimer10: timer@70ac0a4000 { 525 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 526 reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>; 527 reg-names = "mtimecmp"; 528 interrupts-extended = <&cpu40_intc 7>, 529 <&cpu41_intc 7>, 530 <&cpu42_intc 7>, 531 <&cpu43_intc 7>; 532 }; 533 534 clint_mtimer11: timer@70ac0b4000 { 535 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 536 reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>; 537 reg-names = "mtimecmp"; 538 interrupts-extended = <&cpu44_intc 7>, 539 <&cpu45_intc 7>, 540 <&cpu46_intc 7>, 541 <&cpu47_intc 7>; 542 }; 543 544 clint_mtimer12: timer@70ac0c4000 { 545 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 546 reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>; 547 reg-names = "mtimecmp"; 548 interrupts-extended = <&cpu48_intc 7>, 549 <&cpu49_intc 7>, 550 <&cpu50_intc 7>, 551 <&cpu51_intc 7>; 552 }; 553 554 clint_mtimer13: timer@70ac0d4000 { 555 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 556 reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>; 557 reg-names = "mtimecmp"; 558 interrupts-extended = <&cpu52_intc 7>, 559 <&cpu53_intc 7>, 560 <&cpu54_intc 7>, 561 <&cpu55_intc 7>; 562 }; 563 564 clint_mtimer14: timer@70ac0e4000 { 565 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 566 reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>; 567 reg-names = "mtimecmp"; 568 interrupts-extended = <&cpu56_intc 7>, 569 <&cpu57_intc 7>, 570 <&cpu58_intc 7>, 571 <&cpu59_intc 7>; 572 }; 573 574 clint_mtimer15: timer@70ac0f4000 { 575 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 576 reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>; 577 reg-names = "mtimecmp"; 578 interrupts-extended = <&cpu60_intc 7>, 579 <&cpu61_intc 7>, 580 <&cpu62_intc 7>, 581 <&cpu63_intc 7>; 582 }; 583 584 intc: interrupt-controller@7090000000 { 585 compatible = "sophgo,sg2042-plic", "thead,c900-plic"; 586 #address-cells = <0>; 587 #interrupt-cells = <2>; 588 reg = <0x00000070 0x90000000 0x00000000 0x04000000>; 589 interrupt-controller; 590 interrupts-extended = 591 <&cpu0_intc 11>, <&cpu0_intc 9>, 592 <&cpu1_intc 11>, <&cpu1_intc 9>, 593 <&cpu2_intc 11>, <&cpu2_intc 9>, 594 <&cpu3_intc 11>, <&cpu3_intc 9>, 595 <&cpu4_intc 11>, <&cpu4_intc 9>, 596 <&cpu5_intc 11>, <&cpu5_intc 9>, 597 <&cpu6_intc 11>, <&cpu6_intc 9>, 598 <&cpu7_intc 11>, <&cpu7_intc 9>, 599 <&cpu8_intc 11>, <&cpu8_intc 9>, 600 <&cpu9_intc 11>, <&cpu9_intc 9>, 601 <&cpu10_intc 11>, <&cpu10_intc 9>, 602 <&cpu11_intc 11>, <&cpu11_intc 9>, 603 <&cpu12_intc 11>, <&cpu12_intc 9>, 604 <&cpu13_intc 11>, <&cpu13_intc 9>, 605 <&cpu14_intc 11>, <&cpu14_intc 9>, 606 <&cpu15_intc 11>, <&cpu15_intc 9>, 607 <&cpu16_intc 11>, <&cpu16_intc 9>, 608 <&cpu17_intc 11>, <&cpu17_intc 9>, 609 <&cpu18_intc 11>, <&cpu18_intc 9>, 610 <&cpu19_intc 11>, <&cpu19_intc 9>, 611 <&cpu20_intc 11>, <&cpu20_intc 9>, 612 <&cpu21_intc 11>, <&cpu21_intc 9>, 613 <&cpu22_intc 11>, <&cpu22_intc 9>, 614 <&cpu23_intc 11>, <&cpu23_intc 9>, 615 <&cpu24_intc 11>, <&cpu24_intc 9>, 616 <&cpu25_intc 11>, <&cpu25_intc 9>, 617 <&cpu26_intc 11>, <&cpu26_intc 9>, 618 <&cpu27_intc 11>, <&cpu27_intc 9>, 619 <&cpu28_intc 11>, <&cpu28_intc 9>, 620 <&cpu29_intc 11>, <&cpu29_intc 9>, 621 <&cpu30_intc 11>, <&cpu30_intc 9>, 622 <&cpu31_intc 11>, <&cpu31_intc 9>, 623 <&cpu32_intc 11>, <&cpu32_intc 9>, 624 <&cpu33_intc 11>, <&cpu33_intc 9>, 625 <&cpu34_intc 11>, <&cpu34_intc 9>, 626 <&cpu35_intc 11>, <&cpu35_intc 9>, 627 <&cpu36_intc 11>, <&cpu36_intc 9>, 628 <&cpu37_intc 11>, <&cpu37_intc 9>, 629 <&cpu38_intc 11>, <&cpu38_intc 9>, 630 <&cpu39_intc 11>, <&cpu39_intc 9>, 631 <&cpu40_intc 11>, <&cpu40_intc 9>, 632 <&cpu41_intc 11>, <&cpu41_intc 9>, 633 <&cpu42_intc 11>, <&cpu42_intc 9>, 634 <&cpu43_intc 11>, <&cpu43_intc 9>, 635 <&cpu44_intc 11>, <&cpu44_intc 9>, 636 <&cpu45_intc 11>, <&cpu45_intc 9>, 637 <&cpu46_intc 11>, <&cpu46_intc 9>, 638 <&cpu47_intc 11>, <&cpu47_intc 9>, 639 <&cpu48_intc 11>, <&cpu48_intc 9>, 640 <&cpu49_intc 11>, <&cpu49_intc 9>, 641 <&cpu50_intc 11>, <&cpu50_intc 9>, 642 <&cpu51_intc 11>, <&cpu51_intc 9>, 643 <&cpu52_intc 11>, <&cpu52_intc 9>, 644 <&cpu53_intc 11>, <&cpu53_intc 9>, 645 <&cpu54_intc 11>, <&cpu54_intc 9>, 646 <&cpu55_intc 11>, <&cpu55_intc 9>, 647 <&cpu56_intc 11>, <&cpu56_intc 9>, 648 <&cpu57_intc 11>, <&cpu57_intc 9>, 649 <&cpu58_intc 11>, <&cpu58_intc 9>, 650 <&cpu59_intc 11>, <&cpu59_intc 9>, 651 <&cpu60_intc 11>, <&cpu60_intc 9>, 652 <&cpu61_intc 11>, <&cpu61_intc 9>, 653 <&cpu62_intc 11>, <&cpu62_intc 9>, 654 <&cpu63_intc 11>, <&cpu63_intc 9>; 655 riscv,ndev = <224>; 656 }; 657 658 rstgen: reset-controller@7030013000 { 659 compatible = "sophgo,sg2042-reset"; 660 reg = <0x00000070 0x30013000 0x00000000 0x0000000c>; 661 #reset-cells = <1>; 662 }; 663 664 uart0: serial@7040000000 { 665 compatible = "snps,dw-apb-uart"; 666 reg = <0x00000070 0x40000000 0x00000000 0x00001000>; 667 interrupts = <112 IRQ_TYPE_LEVEL_HIGH>; 668 clock-frequency = <500000000>; 669 clocks = <&clkgen GATE_CLK_UART_500M>, 670 <&clkgen GATE_CLK_APB_UART>; 671 clock-names = "baudclk", "apb_pclk"; 672 reg-shift = <2>; 673 reg-io-width = <4>; 674 resets = <&rstgen RST_UART0>; 675 status = "disabled"; 676 }; 677 678 spi0: spi@7040004000 { 679 compatible = "sophgo,sg2042-spi", "snps,dw-apb-ssi"; 680 reg = <0x70 0x40004000 0x00 0x1000>; 681 clocks = <&clkgen GATE_CLK_APB_SPI>; 682 interrupt-parent = <&intc>; 683 interrupts = <110 IRQ_TYPE_LEVEL_HIGH>; 684 #address-cells = <1>; 685 #size-cells = <0>; 686 num-cs = <2>; 687 resets = <&rstgen RST_SPI0>; 688 status = "disabled"; 689 }; 690 691 spi1: spi@7040005000 { 692 compatible = "sophgo,sg2042-spi", "snps,dw-apb-ssi"; 693 reg = <0x70 0x40005000 0x00 0x1000>; 694 clocks = <&clkgen GATE_CLK_APB_SPI>; 695 interrupt-parent = <&intc>; 696 interrupts = <111 IRQ_TYPE_LEVEL_HIGH>; 697 #address-cells = <1>; 698 #size-cells = <0>; 699 num-cs = <2>; 700 resets = <&rstgen RST_SPI1>; 701 status = "disabled"; 702 }; 703 704 gmac0: ethernet@7040026000 { 705 compatible = "sophgo,sg2042-dwmac", "snps,dwmac-5.00a"; 706 reg = <0x70 0x40026000 0x0 0x4000>; 707 clocks = <&clkgen GATE_CLK_AXI_ETH0>, 708 <&clkgen GATE_CLK_PTP_REF_I_ETH0>, 709 <&clkgen GATE_CLK_TX_ETH0>; 710 clock-names = "stmmaceth", "ptp_ref", "tx"; 711 dma-noncoherent; 712 interrupt-parent = <&intc>; 713 interrupts = <132 IRQ_TYPE_LEVEL_HIGH>; 714 interrupt-names = "macirq"; 715 resets = <&rstgen RST_ETH0>; 716 reset-names = "stmmaceth"; 717 snps,multicast-filter-bins = <0>; 718 snps,perfect-filter-entries = <1>; 719 snps,aal; 720 snps,tso; 721 snps,txpbl = <32>; 722 snps,rxpbl = <32>; 723 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; 724 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; 725 snps,axi-config = <&gmac0_stmmac_axi_setup>; 726 status = "disabled"; 727 728 mdio { 729 compatible = "snps,dwmac-mdio"; 730 #address-cells = <1>; 731 #size-cells = <0>; 732 }; 733 734 gmac0_mtl_rx_setup: rx-queues-config { 735 snps,rx-queues-to-use = <8>; 736 queue0 {}; 737 queue1 {}; 738 queue2 {}; 739 queue3 {}; 740 queue4 {}; 741 queue5 {}; 742 queue6 {}; 743 queue7 {}; 744 }; 745 746 gmac0_mtl_tx_setup: tx-queues-config { 747 snps,tx-queues-to-use = <8>; 748 queue0 {}; 749 queue1 {}; 750 queue2 {}; 751 queue3 {}; 752 queue4 {}; 753 queue5 {}; 754 queue6 {}; 755 queue7 {}; 756 }; 757 758 gmac0_stmmac_axi_setup: stmmac-axi-config { 759 snps,blen = <16 8 4 0 0 0 0>; 760 snps,wr_osr_lmt = <1>; 761 snps,rd_osr_lmt = <2>; 762 }; 763 }; 764 765 emmc: mmc@704002a000 { 766 compatible = "sophgo,sg2042-dwcmshc"; 767 reg = <0x70 0x4002a000 0x0 0x1000>; 768 interrupt-parent = <&intc>; 769 interrupts = <134 IRQ_TYPE_LEVEL_HIGH>; 770 clocks = <&clkgen GATE_CLK_EMMC_100M>, 771 <&clkgen GATE_CLK_AXI_EMMC>, 772 <&clkgen GATE_CLK_100K_EMMC>; 773 clock-names = "core", 774 "bus", 775 "timer"; 776 status = "disabled"; 777 }; 778 779 sd: mmc@704002b000 { 780 compatible = "sophgo,sg2042-dwcmshc"; 781 reg = <0x70 0x4002b000 0x0 0x1000>; 782 interrupt-parent = <&intc>; 783 interrupts = <136 IRQ_TYPE_LEVEL_HIGH>; 784 clocks = <&clkgen GATE_CLK_SD_100M>, 785 <&clkgen GATE_CLK_AXI_SD>, 786 <&clkgen GATE_CLK_100K_SD>; 787 clock-names = "core", 788 "bus", 789 "timer"; 790 status = "disabled"; 791 }; 792 }; 793}; 794