1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Clk driver for NXP LPC18xx/LPC43xx Clock Generation Unit (CGU)
4 *
5 * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
6 */
7
8 #include <linux/clk-provider.h>
9 #include <linux/delay.h>
10 #include <linux/io.h>
11 #include <linux/kernel.h>
12 #include <linux/of.h>
13 #include <linux/of_address.h>
14
15 #include <dt-bindings/clock/lpc18xx-cgu.h>
16
17 /* Clock Generation Unit (CGU) registers */
18 #define LPC18XX_CGU_XTAL_OSC_CTRL 0x018
19 #define LPC18XX_CGU_PLL0USB_STAT 0x01c
20 #define LPC18XX_CGU_PLL0USB_CTRL 0x020
21 #define LPC18XX_CGU_PLL0USB_MDIV 0x024
22 #define LPC18XX_CGU_PLL0USB_NP_DIV 0x028
23 #define LPC18XX_CGU_PLL0AUDIO_STAT 0x02c
24 #define LPC18XX_CGU_PLL0AUDIO_CTRL 0x030
25 #define LPC18XX_CGU_PLL0AUDIO_MDIV 0x034
26 #define LPC18XX_CGU_PLL0AUDIO_NP_DIV 0x038
27 #define LPC18XX_CGU_PLL0AUDIO_FRAC 0x03c
28 #define LPC18XX_CGU_PLL1_STAT 0x040
29 #define LPC18XX_CGU_PLL1_CTRL 0x044
30 #define LPC18XX_PLL1_CTRL_FBSEL BIT(6)
31 #define LPC18XX_PLL1_CTRL_DIRECT BIT(7)
32 #define LPC18XX_CGU_IDIV_CTRL(n) (0x048 + (n) * sizeof(u32))
33 #define LPC18XX_CGU_BASE_CLK(id) (0x05c + (id) * sizeof(u32))
34 #define LPC18XX_CGU_PLL_CTRL_OFFSET 0x4
35
36 /* PLL0 bits common to both audio and USB PLL */
37 #define LPC18XX_PLL0_STAT_LOCK BIT(0)
38 #define LPC18XX_PLL0_CTRL_PD BIT(0)
39 #define LPC18XX_PLL0_CTRL_BYPASS BIT(1)
40 #define LPC18XX_PLL0_CTRL_DIRECTI BIT(2)
41 #define LPC18XX_PLL0_CTRL_DIRECTO BIT(3)
42 #define LPC18XX_PLL0_CTRL_CLKEN BIT(4)
43 #define LPC18XX_PLL0_MDIV_MDEC_MASK 0x1ffff
44 #define LPC18XX_PLL0_MDIV_SELP_SHIFT 17
45 #define LPC18XX_PLL0_MDIV_SELI_SHIFT 22
46 #define LPC18XX_PLL0_MSEL_MAX BIT(15)
47
48 /* Register value that gives PLL0 post/pre dividers equal to 1 */
49 #define LPC18XX_PLL0_NP_DIVS_1 0x00302062
50
51 enum {
52 CLK_SRC_OSC32,
53 CLK_SRC_IRC,
54 CLK_SRC_ENET_RX_CLK,
55 CLK_SRC_ENET_TX_CLK,
56 CLK_SRC_GP_CLKIN,
57 CLK_SRC_RESERVED1,
58 CLK_SRC_OSC,
59 CLK_SRC_PLL0USB,
60 CLK_SRC_PLL0AUDIO,
61 CLK_SRC_PLL1,
62 CLK_SRC_RESERVED2,
63 CLK_SRC_RESERVED3,
64 CLK_SRC_IDIVA,
65 CLK_SRC_IDIVB,
66 CLK_SRC_IDIVC,
67 CLK_SRC_IDIVD,
68 CLK_SRC_IDIVE,
69 CLK_SRC_MAX
70 };
71
72 static const char *clk_src_names[CLK_SRC_MAX] = {
73 [CLK_SRC_OSC32] = "osc32",
74 [CLK_SRC_IRC] = "irc",
75 [CLK_SRC_ENET_RX_CLK] = "enet_rx_clk",
76 [CLK_SRC_ENET_TX_CLK] = "enet_tx_clk",
77 [CLK_SRC_GP_CLKIN] = "gp_clkin",
78 [CLK_SRC_OSC] = "osc",
79 [CLK_SRC_PLL0USB] = "pll0usb",
80 [CLK_SRC_PLL0AUDIO] = "pll0audio",
81 [CLK_SRC_PLL1] = "pll1",
82 [CLK_SRC_IDIVA] = "idiva",
83 [CLK_SRC_IDIVB] = "idivb",
84 [CLK_SRC_IDIVC] = "idivc",
85 [CLK_SRC_IDIVD] = "idivd",
86 [CLK_SRC_IDIVE] = "idive",
87 };
88
89 static const char *clk_base_names[BASE_CLK_MAX] = {
90 [BASE_SAFE_CLK] = "base_safe_clk",
91 [BASE_USB0_CLK] = "base_usb0_clk",
92 [BASE_PERIPH_CLK] = "base_periph_clk",
93 [BASE_USB1_CLK] = "base_usb1_clk",
94 [BASE_CPU_CLK] = "base_cpu_clk",
95 [BASE_SPIFI_CLK] = "base_spifi_clk",
96 [BASE_SPI_CLK] = "base_spi_clk",
97 [BASE_PHY_RX_CLK] = "base_phy_rx_clk",
98 [BASE_PHY_TX_CLK] = "base_phy_tx_clk",
99 [BASE_APB1_CLK] = "base_apb1_clk",
100 [BASE_APB3_CLK] = "base_apb3_clk",
101 [BASE_LCD_CLK] = "base_lcd_clk",
102 [BASE_ADCHS_CLK] = "base_adchs_clk",
103 [BASE_SDIO_CLK] = "base_sdio_clk",
104 [BASE_SSP0_CLK] = "base_ssp0_clk",
105 [BASE_SSP1_CLK] = "base_ssp1_clk",
106 [BASE_UART0_CLK] = "base_uart0_clk",
107 [BASE_UART1_CLK] = "base_uart1_clk",
108 [BASE_UART2_CLK] = "base_uart2_clk",
109 [BASE_UART3_CLK] = "base_uart3_clk",
110 [BASE_OUT_CLK] = "base_out_clk",
111 [BASE_AUDIO_CLK] = "base_audio_clk",
112 [BASE_CGU_OUT0_CLK] = "base_cgu_out0_clk",
113 [BASE_CGU_OUT1_CLK] = "base_cgu_out1_clk",
114 };
115
116 static u32 lpc18xx_cgu_pll0_src_ids[] = {
117 CLK_SRC_OSC32, CLK_SRC_IRC, CLK_SRC_ENET_RX_CLK,
118 CLK_SRC_ENET_TX_CLK, CLK_SRC_GP_CLKIN, CLK_SRC_OSC,
119 CLK_SRC_PLL1, CLK_SRC_IDIVA, CLK_SRC_IDIVB, CLK_SRC_IDIVC,
120 CLK_SRC_IDIVD, CLK_SRC_IDIVE,
121 };
122
123 static u32 lpc18xx_cgu_pll1_src_ids[] = {
124 CLK_SRC_OSC32, CLK_SRC_IRC, CLK_SRC_ENET_RX_CLK,
125 CLK_SRC_ENET_TX_CLK, CLK_SRC_GP_CLKIN, CLK_SRC_OSC,
126 CLK_SRC_PLL0USB, CLK_SRC_PLL0AUDIO, CLK_SRC_IDIVA,
127 CLK_SRC_IDIVB, CLK_SRC_IDIVC, CLK_SRC_IDIVD, CLK_SRC_IDIVE,
128 };
129
130 static u32 lpc18xx_cgu_idiva_src_ids[] = {
131 CLK_SRC_OSC32, CLK_SRC_IRC, CLK_SRC_ENET_RX_CLK,
132 CLK_SRC_ENET_TX_CLK, CLK_SRC_GP_CLKIN, CLK_SRC_OSC,
133 CLK_SRC_PLL0USB, CLK_SRC_PLL0AUDIO, CLK_SRC_PLL1
134 };
135
136 static u32 lpc18xx_cgu_idivbcde_src_ids[] = {
137 CLK_SRC_OSC32, CLK_SRC_IRC, CLK_SRC_ENET_RX_CLK,
138 CLK_SRC_ENET_TX_CLK, CLK_SRC_GP_CLKIN, CLK_SRC_OSC,
139 CLK_SRC_PLL0AUDIO, CLK_SRC_PLL1, CLK_SRC_IDIVA,
140 };
141
142 static u32 lpc18xx_cgu_base_irc_src_ids[] = {CLK_SRC_IRC};
143
144 static u32 lpc18xx_cgu_base_usb0_src_ids[] = {CLK_SRC_PLL0USB};
145
146 static u32 lpc18xx_cgu_base_common_src_ids[] = {
147 CLK_SRC_OSC32, CLK_SRC_IRC, CLK_SRC_ENET_RX_CLK,
148 CLK_SRC_ENET_TX_CLK, CLK_SRC_GP_CLKIN, CLK_SRC_OSC,
149 CLK_SRC_PLL0AUDIO, CLK_SRC_PLL1, CLK_SRC_IDIVA,
150 CLK_SRC_IDIVB, CLK_SRC_IDIVC, CLK_SRC_IDIVD, CLK_SRC_IDIVE,
151 };
152
153 static u32 lpc18xx_cgu_base_all_src_ids[] = {
154 CLK_SRC_OSC32, CLK_SRC_IRC, CLK_SRC_ENET_RX_CLK,
155 CLK_SRC_ENET_TX_CLK, CLK_SRC_GP_CLKIN, CLK_SRC_OSC,
156 CLK_SRC_PLL0USB, CLK_SRC_PLL0AUDIO, CLK_SRC_PLL1,
157 CLK_SRC_IDIVA, CLK_SRC_IDIVB, CLK_SRC_IDIVC,
158 CLK_SRC_IDIVD, CLK_SRC_IDIVE,
159 };
160
161 struct lpc18xx_cgu_src_clk_div {
162 u8 clk_id;
163 u8 n_parents;
164 struct clk_divider div;
165 struct clk_mux mux;
166 struct clk_gate gate;
167 };
168
169 #define LPC1XX_CGU_SRC_CLK_DIV(_id, _width, _table) \
170 { \
171 .clk_id = CLK_SRC_ ##_id, \
172 .n_parents = ARRAY_SIZE(lpc18xx_cgu_ ##_table), \
173 .div = { \
174 .shift = 2, \
175 .width = _width, \
176 }, \
177 .mux = { \
178 .mask = 0x1f, \
179 .shift = 24, \
180 .table = lpc18xx_cgu_ ##_table, \
181 }, \
182 .gate = { \
183 .bit_idx = 0, \
184 .flags = CLK_GATE_SET_TO_DISABLE, \
185 }, \
186 }
187
188 static struct lpc18xx_cgu_src_clk_div lpc18xx_cgu_src_clk_divs[] = {
189 LPC1XX_CGU_SRC_CLK_DIV(IDIVA, 2, idiva_src_ids),
190 LPC1XX_CGU_SRC_CLK_DIV(IDIVB, 4, idivbcde_src_ids),
191 LPC1XX_CGU_SRC_CLK_DIV(IDIVC, 4, idivbcde_src_ids),
192 LPC1XX_CGU_SRC_CLK_DIV(IDIVD, 4, idivbcde_src_ids),
193 LPC1XX_CGU_SRC_CLK_DIV(IDIVE, 8, idivbcde_src_ids),
194 };
195
196 struct lpc18xx_cgu_base_clk {
197 u8 clk_id;
198 u8 n_parents;
199 struct clk_mux mux;
200 struct clk_gate gate;
201 };
202
203 #define LPC1XX_CGU_BASE_CLK(_id, _table, _flags) \
204 { \
205 .clk_id = BASE_ ##_id ##_CLK, \
206 .n_parents = ARRAY_SIZE(lpc18xx_cgu_ ##_table), \
207 .mux = { \
208 .mask = 0x1f, \
209 .shift = 24, \
210 .table = lpc18xx_cgu_ ##_table, \
211 .flags = _flags, \
212 }, \
213 .gate = { \
214 .bit_idx = 0, \
215 .flags = CLK_GATE_SET_TO_DISABLE, \
216 }, \
217 }
218
219 static struct lpc18xx_cgu_base_clk lpc18xx_cgu_base_clks[] = {
220 LPC1XX_CGU_BASE_CLK(SAFE, base_irc_src_ids, CLK_MUX_READ_ONLY),
221 LPC1XX_CGU_BASE_CLK(USB0, base_usb0_src_ids, 0),
222 LPC1XX_CGU_BASE_CLK(PERIPH, base_common_src_ids, 0),
223 LPC1XX_CGU_BASE_CLK(USB1, base_all_src_ids, 0),
224 LPC1XX_CGU_BASE_CLK(CPU, base_common_src_ids, 0),
225 LPC1XX_CGU_BASE_CLK(SPIFI, base_common_src_ids, 0),
226 LPC1XX_CGU_BASE_CLK(SPI, base_common_src_ids, 0),
227 LPC1XX_CGU_BASE_CLK(PHY_RX, base_common_src_ids, 0),
228 LPC1XX_CGU_BASE_CLK(PHY_TX, base_common_src_ids, 0),
229 LPC1XX_CGU_BASE_CLK(APB1, base_common_src_ids, 0),
230 LPC1XX_CGU_BASE_CLK(APB3, base_common_src_ids, 0),
231 LPC1XX_CGU_BASE_CLK(LCD, base_common_src_ids, 0),
232 LPC1XX_CGU_BASE_CLK(ADCHS, base_common_src_ids, 0),
233 LPC1XX_CGU_BASE_CLK(SDIO, base_common_src_ids, 0),
234 LPC1XX_CGU_BASE_CLK(SSP0, base_common_src_ids, 0),
235 LPC1XX_CGU_BASE_CLK(SSP1, base_common_src_ids, 0),
236 LPC1XX_CGU_BASE_CLK(UART0, base_common_src_ids, 0),
237 LPC1XX_CGU_BASE_CLK(UART1, base_common_src_ids, 0),
238 LPC1XX_CGU_BASE_CLK(UART2, base_common_src_ids, 0),
239 LPC1XX_CGU_BASE_CLK(UART3, base_common_src_ids, 0),
240 LPC1XX_CGU_BASE_CLK(OUT, base_all_src_ids, 0),
241 { /* 21 reserved */ },
242 { /* 22 reserved */ },
243 { /* 23 reserved */ },
244 { /* 24 reserved */ },
245 LPC1XX_CGU_BASE_CLK(AUDIO, base_common_src_ids, 0),
246 LPC1XX_CGU_BASE_CLK(CGU_OUT0, base_all_src_ids, 0),
247 LPC1XX_CGU_BASE_CLK(CGU_OUT1, base_all_src_ids, 0),
248 };
249
250 struct lpc18xx_pll {
251 struct clk_hw hw;
252 void __iomem *reg;
253 u8 flags;
254 };
255
256 #define to_lpc_pll(hw) container_of(hw, struct lpc18xx_pll, hw)
257
258 struct lpc18xx_cgu_pll_clk {
259 u8 clk_id;
260 u8 n_parents;
261 u8 reg_offset;
262 struct clk_mux mux;
263 struct clk_gate gate;
264 struct lpc18xx_pll pll;
265 const struct clk_ops *pll_ops;
266 };
267
268 #define LPC1XX_CGU_CLK_PLL(_id, _table, _pll_ops) \
269 { \
270 .clk_id = CLK_SRC_ ##_id, \
271 .n_parents = ARRAY_SIZE(lpc18xx_cgu_ ##_table), \
272 .reg_offset = LPC18XX_CGU_ ##_id ##_STAT, \
273 .mux = { \
274 .mask = 0x1f, \
275 .shift = 24, \
276 .table = lpc18xx_cgu_ ##_table, \
277 }, \
278 .gate = { \
279 .bit_idx = 0, \
280 .flags = CLK_GATE_SET_TO_DISABLE, \
281 }, \
282 .pll_ops = &lpc18xx_ ##_pll_ops, \
283 }
284
285 /*
286 * PLL0 uses a special register value encoding. The compute functions below
287 * are taken or derived from the LPC1850 user manual (section 12.6.3.3).
288 */
289
290 /* Compute PLL0 multiplier from decoded version */
lpc18xx_pll0_mdec2msel(u32 x)291 static u32 lpc18xx_pll0_mdec2msel(u32 x)
292 {
293 int i;
294
295 switch (x) {
296 case 0x18003: return 1;
297 case 0x10003: return 2;
298 default:
299 for (i = LPC18XX_PLL0_MSEL_MAX + 1; x != 0x4000 && i > 0; i--)
300 x = ((x ^ x >> 14) & 1) | (x << 1 & 0x7fff);
301 return i;
302 }
303 }
304 /* Compute PLL0 decoded multiplier from binary version */
lpc18xx_pll0_msel2mdec(u32 msel)305 static u32 lpc18xx_pll0_msel2mdec(u32 msel)
306 {
307 u32 i, x = 0x4000;
308
309 switch (msel) {
310 case 0: return 0;
311 case 1: return 0x18003;
312 case 2: return 0x10003;
313 default:
314 for (i = msel; i <= LPC18XX_PLL0_MSEL_MAX; i++)
315 x = ((x ^ x >> 1) & 1) << 14 | (x >> 1 & 0xffff);
316 return x;
317 }
318 }
319
320 /* Compute PLL0 bandwidth SELI reg from multiplier */
lpc18xx_pll0_msel2seli(u32 msel)321 static u32 lpc18xx_pll0_msel2seli(u32 msel)
322 {
323 u32 tmp;
324
325 if (msel > 16384) return 1;
326 if (msel > 8192) return 2;
327 if (msel > 2048) return 4;
328 if (msel >= 501) return 8;
329 if (msel >= 60) {
330 tmp = 1024 / (msel + 9);
331 return ((1024 == (tmp * (msel + 9))) == 0) ? tmp * 4 : (tmp + 1) * 4;
332 }
333
334 return (msel & 0x3c) + 4;
335 }
336
337 /* Compute PLL0 bandwidth SELP reg from multiplier */
lpc18xx_pll0_msel2selp(u32 msel)338 static u32 lpc18xx_pll0_msel2selp(u32 msel)
339 {
340 if (msel < 60)
341 return (msel >> 1) + 1;
342
343 return 31;
344 }
345
lpc18xx_pll0_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)346 static unsigned long lpc18xx_pll0_recalc_rate(struct clk_hw *hw,
347 unsigned long parent_rate)
348 {
349 struct lpc18xx_pll *pll = to_lpc_pll(hw);
350 u32 ctrl, mdiv, msel, npdiv;
351
352 ctrl = readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
353 mdiv = readl(pll->reg + LPC18XX_CGU_PLL0USB_MDIV);
354 npdiv = readl(pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV);
355
356 if (ctrl & LPC18XX_PLL0_CTRL_BYPASS)
357 return parent_rate;
358
359 if (npdiv != LPC18XX_PLL0_NP_DIVS_1) {
360 pr_warn("%s: pre/post dividers not supported\n", __func__);
361 return 0;
362 }
363
364 msel = lpc18xx_pll0_mdec2msel(mdiv & LPC18XX_PLL0_MDIV_MDEC_MASK);
365 if (msel)
366 return 2 * msel * parent_rate;
367
368 pr_warn("%s: unable to calculate rate\n", __func__);
369
370 return 0;
371 }
372
lpc18xx_pll0_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)373 static int lpc18xx_pll0_determine_rate(struct clk_hw *hw,
374 struct clk_rate_request *req)
375 {
376 unsigned long m;
377
378 if (req->best_parent_rate < req->rate) {
379 pr_warn("%s: pll dividers not supported\n", __func__);
380 return -EINVAL;
381 }
382
383 m = DIV_ROUND_UP_ULL(req->best_parent_rate, req->rate * 2);
384 if (m == 0 || m > LPC18XX_PLL0_MSEL_MAX) {
385 pr_warn("%s: unable to support rate %lu\n", __func__, req->rate);
386 return -EINVAL;
387 }
388
389 req->rate = 2 * req->best_parent_rate * m;
390
391 return 0;
392 }
393
lpc18xx_pll0_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)394 static int lpc18xx_pll0_set_rate(struct clk_hw *hw, unsigned long rate,
395 unsigned long parent_rate)
396 {
397 struct lpc18xx_pll *pll = to_lpc_pll(hw);
398 u32 ctrl, stat, m;
399 int retry = 3;
400
401 if (parent_rate < rate) {
402 pr_warn("%s: pll dividers not supported\n", __func__);
403 return -EINVAL;
404 }
405
406 m = DIV_ROUND_UP_ULL(parent_rate, rate * 2);
407 if (m == 0 || m > LPC18XX_PLL0_MSEL_MAX) {
408 pr_warn("%s: unable to support rate %lu\n", __func__, rate);
409 return -EINVAL;
410 }
411
412 m = lpc18xx_pll0_msel2mdec(m);
413 m |= lpc18xx_pll0_msel2selp(m) << LPC18XX_PLL0_MDIV_SELP_SHIFT;
414 m |= lpc18xx_pll0_msel2seli(m) << LPC18XX_PLL0_MDIV_SELI_SHIFT;
415
416 /* Power down PLL, disable clk output and dividers */
417 ctrl = readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
418 ctrl |= LPC18XX_PLL0_CTRL_PD;
419 ctrl &= ~(LPC18XX_PLL0_CTRL_BYPASS | LPC18XX_PLL0_CTRL_DIRECTI |
420 LPC18XX_PLL0_CTRL_DIRECTO | LPC18XX_PLL0_CTRL_CLKEN);
421 writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
422
423 /* Configure new PLL settings */
424 writel(m, pll->reg + LPC18XX_CGU_PLL0USB_MDIV);
425 writel(LPC18XX_PLL0_NP_DIVS_1, pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV);
426
427 /* Power up PLL and wait for lock */
428 ctrl &= ~LPC18XX_PLL0_CTRL_PD;
429 writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
430 do {
431 udelay(10);
432 stat = readl(pll->reg + LPC18XX_CGU_PLL0USB_STAT);
433 if (stat & LPC18XX_PLL0_STAT_LOCK) {
434 ctrl |= LPC18XX_PLL0_CTRL_CLKEN;
435 writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
436
437 return 0;
438 }
439 } while (retry--);
440
441 pr_warn("%s: unable to lock pll\n", __func__);
442
443 return -EINVAL;
444 }
445
446 static const struct clk_ops lpc18xx_pll0_ops = {
447 .recalc_rate = lpc18xx_pll0_recalc_rate,
448 .determine_rate = lpc18xx_pll0_determine_rate,
449 .set_rate = lpc18xx_pll0_set_rate,
450 };
451
lpc18xx_pll1_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)452 static unsigned long lpc18xx_pll1_recalc_rate(struct clk_hw *hw,
453 unsigned long parent_rate)
454 {
455 struct lpc18xx_pll *pll = to_lpc_pll(hw);
456 u16 msel, nsel, psel;
457 bool direct, fbsel;
458 u32 ctrl;
459
460 ctrl = readl(pll->reg + LPC18XX_CGU_PLL1_CTRL);
461
462 direct = (ctrl & LPC18XX_PLL1_CTRL_DIRECT) ? true : false;
463 fbsel = (ctrl & LPC18XX_PLL1_CTRL_FBSEL) ? true : false;
464
465 msel = ((ctrl >> 16) & 0xff) + 1;
466 nsel = ((ctrl >> 12) & 0x3) + 1;
467
468 if (direct || fbsel)
469 return msel * (parent_rate / nsel);
470
471 psel = (ctrl >> 8) & 0x3;
472 psel = 1 << psel;
473
474 return (msel / (2 * psel)) * (parent_rate / nsel);
475 }
476
477 static const struct clk_ops lpc18xx_pll1_ops = {
478 .recalc_rate = lpc18xx_pll1_recalc_rate,
479 };
480
lpc18xx_cgu_gate_enable(struct clk_hw * hw)481 static int lpc18xx_cgu_gate_enable(struct clk_hw *hw)
482 {
483 return clk_gate_ops.enable(hw);
484 }
485
lpc18xx_cgu_gate_disable(struct clk_hw * hw)486 static void lpc18xx_cgu_gate_disable(struct clk_hw *hw)
487 {
488 clk_gate_ops.disable(hw);
489 }
490
lpc18xx_cgu_gate_is_enabled(struct clk_hw * hw)491 static int lpc18xx_cgu_gate_is_enabled(struct clk_hw *hw)
492 {
493 const struct clk_hw *parent;
494
495 /*
496 * The consumer of base clocks needs know if the
497 * base clock is really enabled before it can be
498 * accessed. It is therefore necessary to verify
499 * this all the way up.
500 */
501 parent = clk_hw_get_parent(hw);
502 if (!parent)
503 return 0;
504
505 if (!clk_hw_is_enabled(parent))
506 return 0;
507
508 return clk_gate_ops.is_enabled(hw);
509 }
510
511 static const struct clk_ops lpc18xx_gate_ops = {
512 .enable = lpc18xx_cgu_gate_enable,
513 .disable = lpc18xx_cgu_gate_disable,
514 .is_enabled = lpc18xx_cgu_gate_is_enabled,
515 };
516
517 static struct lpc18xx_cgu_pll_clk lpc18xx_cgu_src_clk_plls[] = {
518 LPC1XX_CGU_CLK_PLL(PLL0USB, pll0_src_ids, pll0_ops),
519 LPC1XX_CGU_CLK_PLL(PLL0AUDIO, pll0_src_ids, pll0_ops),
520 LPC1XX_CGU_CLK_PLL(PLL1, pll1_src_ids, pll1_ops),
521 };
522
lpc18xx_fill_parent_names(const char ** parent,const u32 * id,int size)523 static void lpc18xx_fill_parent_names(const char **parent, const u32 *id, int size)
524 {
525 int i;
526
527 for (i = 0; i < size; i++)
528 parent[i] = clk_src_names[id[i]];
529 }
530
lpc18xx_cgu_register_div(struct lpc18xx_cgu_src_clk_div * clk,void __iomem * base,int n)531 static struct clk *lpc18xx_cgu_register_div(struct lpc18xx_cgu_src_clk_div *clk,
532 void __iomem *base, int n)
533 {
534 void __iomem *reg = base + LPC18XX_CGU_IDIV_CTRL(n);
535 const char *name = clk_src_names[clk->clk_id];
536 const char *parents[CLK_SRC_MAX];
537
538 clk->div.reg = reg;
539 clk->mux.reg = reg;
540 clk->gate.reg = reg;
541
542 lpc18xx_fill_parent_names(parents, clk->mux.table, clk->n_parents);
543
544 return clk_register_composite(NULL, name, parents, clk->n_parents,
545 &clk->mux.hw, &clk_mux_ops,
546 &clk->div.hw, &clk_divider_ops,
547 &clk->gate.hw, &lpc18xx_gate_ops, 0);
548 }
549
550
lpc18xx_register_base_clk(struct lpc18xx_cgu_base_clk * clk,void __iomem * reg_base,int n)551 static struct clk *lpc18xx_register_base_clk(struct lpc18xx_cgu_base_clk *clk,
552 void __iomem *reg_base, int n)
553 {
554 void __iomem *reg = reg_base + LPC18XX_CGU_BASE_CLK(n);
555 const char *name = clk_base_names[clk->clk_id];
556 const char *parents[CLK_SRC_MAX];
557
558 if (clk->n_parents == 0)
559 return ERR_PTR(-ENOENT);
560
561 clk->mux.reg = reg;
562 clk->gate.reg = reg;
563
564 lpc18xx_fill_parent_names(parents, clk->mux.table, clk->n_parents);
565
566 /* SAFE_CLK can not be turned off */
567 if (n == BASE_SAFE_CLK)
568 return clk_register_composite(NULL, name, parents, clk->n_parents,
569 &clk->mux.hw, &clk_mux_ops,
570 NULL, NULL, NULL, NULL, 0);
571
572 return clk_register_composite(NULL, name, parents, clk->n_parents,
573 &clk->mux.hw, &clk_mux_ops,
574 NULL, NULL,
575 &clk->gate.hw, &lpc18xx_gate_ops, 0);
576 }
577
578
lpc18xx_cgu_register_pll(struct lpc18xx_cgu_pll_clk * clk,void __iomem * base)579 static struct clk *lpc18xx_cgu_register_pll(struct lpc18xx_cgu_pll_clk *clk,
580 void __iomem *base)
581 {
582 const char *name = clk_src_names[clk->clk_id];
583 const char *parents[CLK_SRC_MAX];
584
585 clk->pll.reg = base;
586 clk->mux.reg = base + clk->reg_offset + LPC18XX_CGU_PLL_CTRL_OFFSET;
587 clk->gate.reg = base + clk->reg_offset + LPC18XX_CGU_PLL_CTRL_OFFSET;
588
589 lpc18xx_fill_parent_names(parents, clk->mux.table, clk->n_parents);
590
591 return clk_register_composite(NULL, name, parents, clk->n_parents,
592 &clk->mux.hw, &clk_mux_ops,
593 &clk->pll.hw, clk->pll_ops,
594 &clk->gate.hw, &lpc18xx_gate_ops, 0);
595 }
596
lpc18xx_cgu_register_source_clks(struct device_node * np,void __iomem * base)597 static void __init lpc18xx_cgu_register_source_clks(struct device_node *np,
598 void __iomem *base)
599 {
600 const char *parents[CLK_SRC_MAX];
601 struct clk *clk;
602 int i;
603
604 /* Register the internal 12 MHz RC oscillator (IRC) */
605 clk = clk_register_fixed_rate(NULL, clk_src_names[CLK_SRC_IRC],
606 NULL, 0, 12000000);
607 if (IS_ERR(clk))
608 pr_warn("%s: failed to register irc clk\n", __func__);
609
610 /* Register crystal oscillator controller */
611 parents[0] = of_clk_get_parent_name(np, 0);
612 clk = clk_register_gate(NULL, clk_src_names[CLK_SRC_OSC], parents[0],
613 0, base + LPC18XX_CGU_XTAL_OSC_CTRL,
614 0, CLK_GATE_SET_TO_DISABLE, NULL);
615 if (IS_ERR(clk))
616 pr_warn("%s: failed to register osc clk\n", __func__);
617
618 /* Register all PLLs */
619 for (i = 0; i < ARRAY_SIZE(lpc18xx_cgu_src_clk_plls); i++) {
620 clk = lpc18xx_cgu_register_pll(&lpc18xx_cgu_src_clk_plls[i],
621 base);
622 if (IS_ERR(clk))
623 pr_warn("%s: failed to register pll (%d)\n", __func__, i);
624 }
625
626 /* Register all clock dividers A-E */
627 for (i = 0; i < ARRAY_SIZE(lpc18xx_cgu_src_clk_divs); i++) {
628 clk = lpc18xx_cgu_register_div(&lpc18xx_cgu_src_clk_divs[i],
629 base, i);
630 if (IS_ERR(clk))
631 pr_warn("%s: failed to register div %d\n", __func__, i);
632 }
633 }
634
635 static struct clk *clk_base[BASE_CLK_MAX];
636 static struct clk_onecell_data clk_base_data = {
637 .clks = clk_base,
638 .clk_num = BASE_CLK_MAX,
639 };
640
lpc18xx_cgu_register_base_clks(void __iomem * reg_base)641 static void __init lpc18xx_cgu_register_base_clks(void __iomem *reg_base)
642 {
643 int i;
644
645 for (i = BASE_SAFE_CLK; i < BASE_CLK_MAX; i++) {
646 clk_base[i] = lpc18xx_register_base_clk(&lpc18xx_cgu_base_clks[i],
647 reg_base, i);
648 if (IS_ERR(clk_base[i]) && PTR_ERR(clk_base[i]) != -ENOENT)
649 pr_warn("%s: register base clk %d failed\n", __func__, i);
650 }
651 }
652
lpc18xx_cgu_init(struct device_node * np)653 static void __init lpc18xx_cgu_init(struct device_node *np)
654 {
655 void __iomem *reg_base;
656
657 reg_base = of_iomap(np, 0);
658 if (!reg_base) {
659 pr_warn("%s: failed to map address range\n", __func__);
660 return;
661 }
662
663 lpc18xx_cgu_register_source_clks(np, reg_base);
664 lpc18xx_cgu_register_base_clks(reg_base);
665
666 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_base_data);
667 }
668 CLK_OF_DECLARE(lpc18xx_cgu, "nxp,lpc1850-cgu", lpc18xx_cgu_init);
669