1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
4 * Copyright (c) 2024 Yao Zi <ziyao@disroot.org>
5 * Author: Joseph Chen <chenjh@rock-chips.com>
6 */
7
8 #include <linux/clk-provider.h>
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/minmax.h>
15 #include <linux/slab.h>
16
17 #include <dt-bindings/clock/rockchip,rk3528-cru.h>
18
19 #include "clk.h"
20
21 #define RK3528_GRF_SOC_STATUS0 0x1a0
22
23 enum rk3528_plls {
24 apll, cpll, gpll, ppll, dpll,
25 };
26
27 static struct rockchip_pll_rate_table rk3528_pll_rates[] = {
28 RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
29 RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
30 RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
31 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
32 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
33 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
34 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
35 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
36 RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0), /* GPLL */
37 RK3036_PLL_RATE(1092000000, 2, 91, 1, 1, 1, 0),
38 RK3036_PLL_RATE(1008000000, 1, 42, 1, 1, 1, 0),
39 RK3036_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0), /* PPLL */
40 RK3036_PLL_RATE(996000000, 2, 83, 1, 1, 1, 0), /* CPLL */
41 RK3036_PLL_RATE(960000000, 1, 40, 1, 1, 1, 0),
42 RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
43 RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
44 RK3036_PLL_RATE(600000000, 1, 50, 2, 1, 1, 0),
45 RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0),
46 RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
47 RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
48 RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
49 RK3036_PLL_RATE(96000000, 1, 24, 3, 2, 1, 0),
50 { /* sentinel */ },
51 };
52
53 #define RK3528_DIV_ACLK_M_CORE_MASK 0x1f
54 #define RK3528_DIV_ACLK_M_CORE_SHIFT 11
55 #define RK3528_DIV_PCLK_DBG_MASK 0x1f
56 #define RK3528_DIV_PCLK_DBG_SHIFT 1
57
58 #define RK3528_CLKSEL39(_aclk_m_core) \
59 { \
60 .reg = RK3528_CLKSEL_CON(39), \
61 .val = HIWORD_UPDATE(_aclk_m_core, RK3528_DIV_ACLK_M_CORE_MASK, \
62 RK3528_DIV_ACLK_M_CORE_SHIFT), \
63 }
64
65 #define RK3528_CLKSEL40(_pclk_dbg) \
66 { \
67 .reg = RK3528_CLKSEL_CON(40), \
68 .val = HIWORD_UPDATE(_pclk_dbg, RK3528_DIV_PCLK_DBG_MASK, \
69 RK3528_DIV_PCLK_DBG_SHIFT), \
70 }
71
72 #define RK3528_CPUCLK_RATE(_prate, _aclk_m_core, _pclk_dbg) \
73 { \
74 .prate = _prate, \
75 .divs = { \
76 RK3528_CLKSEL39(_aclk_m_core), \
77 RK3528_CLKSEL40(_pclk_dbg), \
78 }, \
79 }
80
81 static struct rockchip_cpuclk_rate_table rk3528_cpuclk_rates[] __initdata = {
82 RK3528_CPUCLK_RATE(1896000000, 1, 13),
83 RK3528_CPUCLK_RATE(1800000000, 1, 12),
84 RK3528_CPUCLK_RATE(1704000000, 1, 11),
85 RK3528_CPUCLK_RATE(1608000000, 1, 11),
86 RK3528_CPUCLK_RATE(1512000000, 1, 11),
87 RK3528_CPUCLK_RATE(1416000000, 1, 9),
88 RK3528_CPUCLK_RATE(1296000000, 1, 8),
89 RK3528_CPUCLK_RATE(1200000000, 1, 8),
90 RK3528_CPUCLK_RATE(1188000000, 1, 8),
91 RK3528_CPUCLK_RATE(1092000000, 1, 7),
92 RK3528_CPUCLK_RATE(1008000000, 1, 6),
93 RK3528_CPUCLK_RATE(1000000000, 1, 6),
94 RK3528_CPUCLK_RATE(996000000, 1, 6),
95 RK3528_CPUCLK_RATE(960000000, 1, 6),
96 RK3528_CPUCLK_RATE(912000000, 1, 6),
97 RK3528_CPUCLK_RATE(816000000, 1, 5),
98 RK3528_CPUCLK_RATE(600000000, 1, 3),
99 RK3528_CPUCLK_RATE(594000000, 1, 3),
100 RK3528_CPUCLK_RATE(408000000, 1, 2),
101 RK3528_CPUCLK_RATE(312000000, 1, 2),
102 RK3528_CPUCLK_RATE(216000000, 1, 1),
103 RK3528_CPUCLK_RATE(96000000, 1, 0),
104 };
105
106 static const struct rockchip_cpuclk_reg_data rk3528_cpuclk_data = {
107 .core_reg[0] = RK3528_CLKSEL_CON(39),
108 .div_core_shift[0] = 5,
109 .div_core_mask[0] = 0x1f,
110 .num_cores = 1,
111 .mux_core_alt = 1,
112 .mux_core_main = 0,
113 .mux_core_shift = 10,
114 .mux_core_mask = 0x1,
115 };
116
117 PNAME(mux_pll_p) = { "xin24m" };
118 PNAME(mux_armclk) = { "apll", "gpll" };
119 PNAME(mux_24m_32k_p) = { "xin24m", "clk_32k" };
120 PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
121 PNAME(mux_gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" };
122 PNAME(mux_100m_50m_24m_p) = { "clk_100m_src", "clk_50m_src",
123 "xin24m" };
124 PNAME(mux_150m_100m_24m_p) = { "clk_150m_src", "clk_100m_src",
125 "xin24m" };
126 PNAME(mux_200m_100m_24m_p) = { "clk_200m_src", "clk_100m_src",
127 "xin24m" };
128 PNAME(mux_200m_100m_50m_24m_p) = { "clk_200m_src", "clk_100m_src",
129 "clk_50m_src", "xin24m" };
130 PNAME(mux_300m_200m_100m_24m_p) = { "clk_300m_src", "clk_200m_src",
131 "clk_100m_src", "xin24m" };
132 PNAME(mux_339m_200m_100m_24m_p) = { "clk_339m_src", "clk_200m_src",
133 "clk_100m_src", "xin24m" };
134 PNAME(mux_500m_200m_100m_24m_p) = { "clk_500m_src", "clk_200m_src",
135 "clk_100m_src", "xin24m" };
136 PNAME(mux_500m_300m_100m_24m_p) = { "clk_500m_src", "clk_300m_src",
137 "clk_100m_src", "xin24m" };
138 PNAME(mux_600m_300m_200m_24m_p) = { "clk_600m_src", "clk_300m_src",
139 "clk_200m_src", "xin24m" };
140 PNAME(aclk_gpu_p) = { "aclk_gpu_root",
141 "clk_gpu_pvtpll_src" };
142 PNAME(aclk_rkvdec_pvtmux_root_p) = { "aclk_rkvdec_root",
143 "clk_rkvdec_pvtpll_src" };
144 PNAME(clk_i2c2_p) = { "clk_200m_src", "clk_100m_src",
145 "xin24m", "clk_32k" };
146 PNAME(clk_ref_pcie_inner_phy_p) = { "clk_ppll_100m_src", "xin24m" };
147 PNAME(dclk_vop0_p) = { "dclk_vop_src0",
148 "clk_hdmiphy_pixel_io" };
149 PNAME(mclk_i2s0_2ch_sai_src_p) = { "clk_i2s0_2ch_src",
150 "clk_i2s0_2ch_frac", "xin12m" };
151 PNAME(mclk_i2s1_8ch_sai_src_p) = { "clk_i2s1_8ch_src",
152 "clk_i2s1_8ch_frac", "xin12m" };
153 PNAME(mclk_i2s2_2ch_sai_src_p) = { "clk_i2s2_2ch_src",
154 "clk_i2s2_2ch_frac", "xin12m" };
155 PNAME(mclk_i2s3_8ch_sai_src_p) = { "clk_i2s3_8ch_src",
156 "clk_i2s3_8ch_frac", "xin12m" };
157 PNAME(mclk_sai_i2s0_p) = { "mclk_i2s0_2ch_sai_src",
158 "i2s0_mclkin" };
159 PNAME(mclk_sai_i2s1_p) = { "mclk_i2s1_8ch_sai_src",
160 "i2s1_mclkin" };
161 PNAME(mclk_spdif_src_p) = { "clk_spdif_src", "clk_spdif_frac",
162 "xin12m" };
163 PNAME(sclk_uart0_src_p) = { "clk_uart0_src", "clk_uart0_frac",
164 "xin24m" };
165 PNAME(sclk_uart1_src_p) = { "clk_uart1_src", "clk_uart1_frac",
166 "xin24m" };
167 PNAME(sclk_uart2_src_p) = { "clk_uart2_src", "clk_uart2_frac",
168 "xin24m" };
169 PNAME(sclk_uart3_src_p) = { "clk_uart3_src", "clk_uart3_frac",
170 "xin24m" };
171 PNAME(sclk_uart4_src_p) = { "clk_uart4_src", "clk_uart4_frac",
172 "xin24m" };
173 PNAME(sclk_uart5_src_p) = { "clk_uart5_src", "clk_uart5_frac",
174 "xin24m" };
175 PNAME(sclk_uart6_src_p) = { "clk_uart6_src", "clk_uart6_frac",
176 "xin24m" };
177 PNAME(sclk_uart7_src_p) = { "clk_uart7_src", "clk_uart7_frac",
178 "xin24m" };
179 PNAME(clk_32k_p) = { "xin_osc0_div", "clk_pvtm_32k" };
180
181 static struct rockchip_pll_clock rk3528_pll_clks[] __initdata = {
182 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
183 CLK_IS_CRITICAL, RK3528_PLL_CON(0),
184 RK3528_MODE_CON, 0, 0, 0, rk3528_pll_rates),
185
186 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
187 CLK_IS_CRITICAL, RK3528_PLL_CON(8),
188 RK3528_MODE_CON, 2, 0, 0, rk3528_pll_rates),
189
190 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
191 CLK_IS_CRITICAL, RK3528_PLL_CON(24),
192 RK3528_MODE_CON, 4, 0, 0, rk3528_pll_rates),
193
194 [ppll] = PLL(pll_rk3328, PLL_PPLL, "ppll", mux_pll_p,
195 CLK_IS_CRITICAL, RK3528_PCIE_PLL_CON(32),
196 RK3528_MODE_CON, 6, 0, ROCKCHIP_PLL_FIXED_MODE, rk3528_pll_rates),
197
198 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
199 CLK_IGNORE_UNUSED, RK3528_DDRPHY_PLL_CON(16),
200 RK3528_DDRPHY_MODE_CON, 0, 0, 0, rk3528_pll_rates),
201 };
202
203 #define MFLAGS CLK_MUX_HIWORD_MASK
204 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
205 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
206
207 static struct rockchip_clk_branch rk3528_uart0_fracmux __initdata =
208 MUX(CLK_UART0, "clk_uart0", sclk_uart0_src_p, CLK_SET_RATE_PARENT,
209 RK3528_CLKSEL_CON(6), 0, 2, MFLAGS);
210
211 static struct rockchip_clk_branch rk3528_uart1_fracmux __initdata =
212 MUX(CLK_UART1, "clk_uart1", sclk_uart1_src_p, CLK_SET_RATE_PARENT,
213 RK3528_CLKSEL_CON(8), 0, 2, MFLAGS);
214
215 static struct rockchip_clk_branch rk3528_uart2_fracmux __initdata =
216 MUX(CLK_UART2, "clk_uart2", sclk_uart2_src_p, CLK_SET_RATE_PARENT,
217 RK3528_CLKSEL_CON(10), 0, 2, MFLAGS);
218
219 static struct rockchip_clk_branch rk3528_uart3_fracmux __initdata =
220 MUX(CLK_UART3, "clk_uart3", sclk_uart3_src_p, CLK_SET_RATE_PARENT,
221 RK3528_CLKSEL_CON(12), 0, 2, MFLAGS);
222
223 static struct rockchip_clk_branch rk3528_uart4_fracmux __initdata =
224 MUX(CLK_UART4, "clk_uart4", sclk_uart4_src_p, CLK_SET_RATE_PARENT,
225 RK3528_CLKSEL_CON(14), 0, 2, MFLAGS);
226
227 static struct rockchip_clk_branch rk3528_uart5_fracmux __initdata =
228 MUX(CLK_UART5, "clk_uart5", sclk_uart5_src_p, CLK_SET_RATE_PARENT,
229 RK3528_CLKSEL_CON(16), 0, 2, MFLAGS);
230
231 static struct rockchip_clk_branch rk3528_uart6_fracmux __initdata =
232 MUX(CLK_UART6, "clk_uart6", sclk_uart6_src_p, CLK_SET_RATE_PARENT,
233 RK3528_CLKSEL_CON(18), 0, 2, MFLAGS);
234
235 static struct rockchip_clk_branch rk3528_uart7_fracmux __initdata =
236 MUX(CLK_UART7, "clk_uart7", sclk_uart7_src_p, CLK_SET_RATE_PARENT,
237 RK3528_CLKSEL_CON(20), 0, 2, MFLAGS);
238
239 static struct rockchip_clk_branch mclk_i2s0_2ch_sai_src_fracmux __initdata =
240 MUX(MCLK_I2S0_2CH_SAI_SRC_PRE, "mclk_i2s0_2ch_sai_src_pre", mclk_i2s0_2ch_sai_src_p, CLK_SET_RATE_PARENT,
241 RK3528_CLKSEL_CON(22), 0, 2, MFLAGS);
242
243 static struct rockchip_clk_branch mclk_i2s1_8ch_sai_src_fracmux __initdata =
244 MUX(MCLK_I2S1_8CH_SAI_SRC_PRE, "mclk_i2s1_8ch_sai_src_pre", mclk_i2s1_8ch_sai_src_p, CLK_SET_RATE_PARENT,
245 RK3528_CLKSEL_CON(26), 0, 2, MFLAGS);
246
247 static struct rockchip_clk_branch mclk_i2s2_2ch_sai_src_fracmux __initdata =
248 MUX(MCLK_I2S2_2CH_SAI_SRC_PRE, "mclk_i2s2_2ch_sai_src_pre", mclk_i2s2_2ch_sai_src_p, CLK_SET_RATE_PARENT,
249 RK3528_CLKSEL_CON(28), 0, 2, MFLAGS);
250
251 static struct rockchip_clk_branch mclk_i2s3_8ch_sai_src_fracmux __initdata =
252 MUX(MCLK_I2S3_8CH_SAI_SRC_PRE, "mclk_i2s3_8ch_sai_src_pre", mclk_i2s3_8ch_sai_src_p, CLK_SET_RATE_PARENT,
253 RK3528_CLKSEL_CON(24), 0, 2, MFLAGS);
254
255 static struct rockchip_clk_branch mclk_spdif_src_fracmux __initdata =
256 MUX(MCLK_SDPDIF_SRC_PRE, "mclk_spdif_src_pre", mclk_spdif_src_p, CLK_SET_RATE_PARENT,
257 RK3528_CLKSEL_CON(32), 0, 2, MFLAGS);
258
259 static struct rockchip_clk_branch rk3528_clk_branches[] __initdata = {
260 /* top */
261 FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
262
263 COMPOSITE(CLK_MATRIX_250M_SRC, "clk_250m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
264 RK3528_CLKSEL_CON(1), 15, 1, MFLAGS, 10, 5, DFLAGS,
265 RK3528_CLKGATE_CON(0), 5, GFLAGS),
266 COMPOSITE(CLK_MATRIX_500M_SRC, "clk_500m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
267 RK3528_CLKSEL_CON(3), 11, 1, MFLAGS, 6, 5, DFLAGS,
268 RK3528_CLKGATE_CON(0), 10, GFLAGS),
269 COMPOSITE_NOMUX(CLK_MATRIX_50M_SRC, "clk_50m_src", "cpll", CLK_IS_CRITICAL,
270 RK3528_CLKSEL_CON(0), 2, 5, DFLAGS,
271 RK3528_CLKGATE_CON(0), 1, GFLAGS),
272 COMPOSITE_NOMUX(CLK_MATRIX_100M_SRC, "clk_100m_src", "cpll", CLK_IS_CRITICAL,
273 RK3528_CLKSEL_CON(0), 7, 5, DFLAGS,
274 RK3528_CLKGATE_CON(0), 2, GFLAGS),
275 COMPOSITE_NOMUX(CLK_MATRIX_150M_SRC, "clk_150m_src", "gpll", CLK_IS_CRITICAL,
276 RK3528_CLKSEL_CON(1), 0, 5, DFLAGS,
277 RK3528_CLKGATE_CON(0), 3, GFLAGS),
278 COMPOSITE_NOMUX(CLK_MATRIX_200M_SRC, "clk_200m_src", "gpll", CLK_IS_CRITICAL,
279 RK3528_CLKSEL_CON(1), 5, 5, DFLAGS,
280 RK3528_CLKGATE_CON(0), 4, GFLAGS),
281 COMPOSITE_NOMUX(CLK_MATRIX_300M_SRC, "clk_300m_src", "gpll", CLK_IS_CRITICAL,
282 RK3528_CLKSEL_CON(2), 0, 5, DFLAGS,
283 RK3528_CLKGATE_CON(0), 6, GFLAGS),
284 COMPOSITE_NOMUX_HALFDIV(CLK_MATRIX_339M_SRC, "clk_339m_src", "gpll", CLK_IS_CRITICAL,
285 RK3528_CLKSEL_CON(2), 5, 5, DFLAGS,
286 RK3528_CLKGATE_CON(0), 7, GFLAGS),
287 COMPOSITE_NOMUX(CLK_MATRIX_400M_SRC, "clk_400m_src", "gpll", CLK_IS_CRITICAL,
288 RK3528_CLKSEL_CON(2), 10, 5, DFLAGS,
289 RK3528_CLKGATE_CON(0), 8, GFLAGS),
290 COMPOSITE_NOMUX(CLK_MATRIX_600M_SRC, "clk_600m_src", "gpll", CLK_IS_CRITICAL,
291 RK3528_CLKSEL_CON(4), 0, 5, DFLAGS,
292 RK3528_CLKGATE_CON(0), 11, GFLAGS),
293 COMPOSITE(DCLK_VOP_SRC0, "dclk_vop_src0", mux_gpll_cpll_p, 0,
294 RK3528_CLKSEL_CON(32), 10, 1, MFLAGS, 2, 8, DFLAGS,
295 RK3528_CLKGATE_CON(3), 7, GFLAGS),
296 COMPOSITE(DCLK_VOP_SRC1, "dclk_vop_src1", mux_gpll_cpll_p, 0,
297 RK3528_CLKSEL_CON(33), 8, 1, MFLAGS, 0, 8, DFLAGS,
298 RK3528_CLKGATE_CON(3), 8, GFLAGS),
299 COMPOSITE_NOMUX(CLK_HSM, "clk_hsm", "xin24m", 0,
300 RK3528_CLKSEL_CON(36), 5, 5, DFLAGS,
301 RK3528_CLKGATE_CON(3), 13, GFLAGS),
302
303 COMPOSITE_NOMUX(CLK_UART0_SRC, "clk_uart0_src", "gpll", 0,
304 RK3528_CLKSEL_CON(4), 5, 5, DFLAGS,
305 RK3528_CLKGATE_CON(0), 12, GFLAGS),
306 COMPOSITE_FRACMUX(CLK_UART0_FRAC, "clk_uart0_frac", "clk_uart0_src", CLK_SET_RATE_PARENT,
307 RK3528_CLKSEL_CON(5), 0,
308 RK3528_CLKGATE_CON(0), 13, GFLAGS,
309 &rk3528_uart0_fracmux),
310 GATE(SCLK_UART0, "sclk_uart0", "clk_uart0", 0,
311 RK3528_CLKGATE_CON(0), 14, GFLAGS),
312
313 COMPOSITE_NOMUX(CLK_UART1_SRC, "clk_uart1_src", "gpll", 0,
314 RK3528_CLKSEL_CON(6), 2, 5, DFLAGS,
315 RK3528_CLKGATE_CON(0), 15, GFLAGS),
316 COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
317 RK3528_CLKSEL_CON(7), 0,
318 RK3528_CLKGATE_CON(1), 0, GFLAGS,
319 &rk3528_uart1_fracmux),
320 GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0,
321 RK3528_CLKGATE_CON(1), 1, GFLAGS),
322
323 COMPOSITE_NOMUX(CLK_UART2_SRC, "clk_uart2_src", "gpll", 0,
324 RK3528_CLKSEL_CON(8), 2, 5, DFLAGS,
325 RK3528_CLKGATE_CON(1), 2, GFLAGS),
326 COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
327 RK3528_CLKSEL_CON(9), 0,
328 RK3528_CLKGATE_CON(1), 3, GFLAGS,
329 &rk3528_uart2_fracmux),
330 GATE(SCLK_UART2, "sclk_uart2", "clk_uart2", 0,
331 RK3528_CLKGATE_CON(1), 4, GFLAGS),
332
333 COMPOSITE_NOMUX(CLK_UART3_SRC, "clk_uart3_src", "gpll", 0,
334 RK3528_CLKSEL_CON(10), 2, 5, DFLAGS,
335 RK3528_CLKGATE_CON(1), 5, GFLAGS),
336 COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
337 RK3528_CLKSEL_CON(11), 0,
338 RK3528_CLKGATE_CON(1), 6, GFLAGS,
339 &rk3528_uart3_fracmux),
340 GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0,
341 RK3528_CLKGATE_CON(1), 7, GFLAGS),
342
343 COMPOSITE_NOMUX(CLK_UART4_SRC, "clk_uart4_src", "gpll", 0,
344 RK3528_CLKSEL_CON(12), 2, 5, DFLAGS,
345 RK3528_CLKGATE_CON(1), 8, GFLAGS),
346 COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
347 RK3528_CLKSEL_CON(13), 0,
348 RK3528_CLKGATE_CON(1), 9, GFLAGS,
349 &rk3528_uart4_fracmux),
350 GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0,
351 RK3528_CLKGATE_CON(1), 10, GFLAGS),
352
353 COMPOSITE_NOMUX(CLK_UART5_SRC, "clk_uart5_src", "gpll", 0,
354 RK3528_CLKSEL_CON(14), 2, 5, DFLAGS,
355 RK3528_CLKGATE_CON(1), 11, GFLAGS),
356 COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT,
357 RK3528_CLKSEL_CON(15), 0,
358 RK3528_CLKGATE_CON(1), 12, GFLAGS,
359 &rk3528_uart5_fracmux),
360 GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0,
361 RK3528_CLKGATE_CON(1), 13, GFLAGS),
362
363 COMPOSITE_NOMUX(CLK_UART6_SRC, "clk_uart6_src", "gpll", 0,
364 RK3528_CLKSEL_CON(16), 2, 5, DFLAGS,
365 RK3528_CLKGATE_CON(1), 14, GFLAGS),
366 COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT,
367 RK3528_CLKSEL_CON(17), 0,
368 RK3528_CLKGATE_CON(1), 15, GFLAGS,
369 &rk3528_uart6_fracmux),
370 GATE(SCLK_UART6, "sclk_uart6", "clk_uart6", 0,
371 RK3528_CLKGATE_CON(2), 0, GFLAGS),
372
373 COMPOSITE_NOMUX(CLK_UART7_SRC, "clk_uart7_src", "gpll", 0,
374 RK3528_CLKSEL_CON(18), 2, 5, DFLAGS,
375 RK3528_CLKGATE_CON(2), 1, GFLAGS),
376 COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT,
377 RK3528_CLKSEL_CON(19), 0,
378 RK3528_CLKGATE_CON(2), 2, GFLAGS,
379 &rk3528_uart7_fracmux),
380 GATE(SCLK_UART7, "sclk_uart7", "clk_uart7", 0,
381 RK3528_CLKGATE_CON(2), 3, GFLAGS),
382
383 COMPOSITE_NOMUX(CLK_I2S0_2CH_SRC, "clk_i2s0_2ch_src", "gpll", 0,
384 RK3528_CLKSEL_CON(20), 8, 5, DFLAGS,
385 RK3528_CLKGATE_CON(2), 5, GFLAGS),
386 COMPOSITE_FRACMUX(CLK_I2S0_2CH_FRAC, "clk_i2s0_2ch_frac", "clk_i2s0_2ch_src", CLK_SET_RATE_PARENT,
387 RK3528_CLKSEL_CON(21), 0,
388 RK3528_CLKGATE_CON(2), 6, GFLAGS,
389 &mclk_i2s0_2ch_sai_src_fracmux),
390 GATE(MCLK_I2S0_2CH_SAI_SRC, "mclk_i2s0_2ch_sai_src", "mclk_i2s0_2ch_sai_src_pre", 0,
391 RK3528_CLKGATE_CON(2), 7, GFLAGS),
392
393 COMPOSITE_NOMUX(CLK_I2S1_8CH_SRC, "clk_i2s1_8ch_src", "gpll", 0,
394 RK3528_CLKSEL_CON(24), 3, 5, DFLAGS,
395 RK3528_CLKGATE_CON(2), 11, GFLAGS),
396 COMPOSITE_FRACMUX(CLK_I2S1_8CH_FRAC, "clk_i2s1_8ch_frac", "clk_i2s1_8ch_src", CLK_SET_RATE_PARENT,
397 RK3528_CLKSEL_CON(25), 0,
398 RK3528_CLKGATE_CON(2), 12, GFLAGS,
399 &mclk_i2s1_8ch_sai_src_fracmux),
400 GATE(MCLK_I2S1_8CH_SAI_SRC, "mclk_i2s1_8ch_sai_src", "mclk_i2s1_8ch_sai_src_pre", 0,
401 RK3528_CLKGATE_CON(2), 13, GFLAGS),
402
403 COMPOSITE_NOMUX(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", "gpll", 0,
404 RK3528_CLKSEL_CON(26), 3, 5, DFLAGS,
405 RK3528_CLKGATE_CON(2), 14, GFLAGS),
406 COMPOSITE_FRACMUX(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_src", CLK_SET_RATE_PARENT,
407 RK3528_CLKSEL_CON(27), 0,
408 RK3528_CLKGATE_CON(2), 15, GFLAGS,
409 &mclk_i2s2_2ch_sai_src_fracmux),
410 GATE(MCLK_I2S2_2CH_SAI_SRC, "mclk_i2s2_2ch_sai_src", "mclk_i2s2_2ch_sai_src_pre", 0,
411 RK3528_CLKGATE_CON(3), 0, GFLAGS),
412
413 COMPOSITE_NOMUX(CLK_I2S3_8CH_SRC, "clk_i2s3_8ch_src", "gpll", 0,
414 RK3528_CLKSEL_CON(22), 3, 5, DFLAGS,
415 RK3528_CLKGATE_CON(2), 8, GFLAGS),
416 COMPOSITE_FRACMUX(CLK_I2S3_8CH_FRAC, "clk_i2s3_8ch_frac", "clk_i2s3_8ch_src", CLK_SET_RATE_PARENT,
417 RK3528_CLKSEL_CON(23), 0,
418 RK3528_CLKGATE_CON(2), 9, GFLAGS,
419 &mclk_i2s3_8ch_sai_src_fracmux),
420 GATE(MCLK_I2S3_8CH_SAI_SRC, "mclk_i2s3_8ch_sai_src", "mclk_i2s3_8ch_sai_src_pre", 0,
421 RK3528_CLKGATE_CON(2), 10, GFLAGS),
422
423 COMPOSITE_NOMUX(CLK_SPDIF_SRC, "clk_spdif_src", "gpll", 0,
424 RK3528_CLKSEL_CON(30), 2, 5, DFLAGS,
425 RK3528_CLKGATE_CON(3), 4, GFLAGS),
426 COMPOSITE_FRACMUX(CLK_SPDIF_FRAC, "clk_spdif_frac", "clk_spdif_src", CLK_SET_RATE_PARENT,
427 RK3528_CLKSEL_CON(31), 0,
428 RK3528_CLKGATE_CON(3), 5, GFLAGS,
429 &mclk_spdif_src_fracmux),
430 GATE(MCLK_SPDIF_SRC, "mclk_spdif_src", "mclk_spdif_src_pre", 0,
431 RK3528_CLKGATE_CON(3), 6, GFLAGS),
432
433 /* bus */
434 COMPOSITE_NODIV(ACLK_BUS_M_ROOT, "aclk_bus_m_root", mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL,
435 RK3528_CLKSEL_CON(43), 12, 2, MFLAGS,
436 RK3528_CLKGATE_CON(8), 7, GFLAGS),
437 GATE(ACLK_GIC, "aclk_gic", "aclk_bus_m_root", CLK_IS_CRITICAL,
438 RK3528_CLKGATE_CON(9), 1, GFLAGS),
439
440 COMPOSITE_NODIV(ACLK_BUS_ROOT, "aclk_bus_root", mux_200m_100m_24m_p, CLK_IS_CRITICAL,
441 RK3528_CLKSEL_CON(43), 6, 2, MFLAGS,
442 RK3528_CLKGATE_CON(8), 4, GFLAGS),
443 GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_bus_root", 0,
444 RK3528_CLKGATE_CON(9), 2, GFLAGS),
445 GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_root", 0,
446 RK3528_CLKGATE_CON(9), 4, GFLAGS),
447 GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_root", 0,
448 RK3528_CLKGATE_CON(11), 11, GFLAGS),
449 COMPOSITE(ACLK_BUS_VOPGL_ROOT, "aclk_bus_vopgl_root", mux_gpll_cpll_p, CLK_IS_CRITICAL,
450 RK3528_CLKSEL_CON(43), 3, 1, MFLAGS, 0, 3, DFLAGS,
451 RK3528_CLKGATE_CON(8), 0, GFLAGS),
452 COMPOSITE_NODIV(ACLK_BUS_H_ROOT, "aclk_bus_h_root", mux_500m_200m_100m_24m_p, CLK_IS_CRITICAL,
453 RK3528_CLKSEL_CON(43), 4, 2, MFLAGS,
454 RK3528_CLKGATE_CON(8), 2, GFLAGS),
455 GATE(ACLK_DMA2DDR, "aclk_dma2ddr", "aclk_bus_h_root", 0,
456 RK3528_CLKGATE_CON(10), 14, GFLAGS),
457
458 COMPOSITE_NODIV(HCLK_BUS_ROOT, "hclk_bus_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
459 RK3528_CLKSEL_CON(43), 8, 2, MFLAGS,
460 RK3528_CLKGATE_CON(8), 5, GFLAGS),
461
462 COMPOSITE_NODIV(PCLK_BUS_ROOT, "pclk_bus_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
463 RK3528_CLKSEL_CON(43), 10, 2, MFLAGS,
464 RK3528_CLKGATE_CON(8), 6, GFLAGS),
465 GATE(PCLK_DFT2APB, "pclk_dft2apb", "pclk_bus_root", 0,
466 RK3528_CLKGATE_CON(8), 13, GFLAGS),
467 GATE(PCLK_BUS_GRF, "pclk_bus_grf", "pclk_bus_root", CLK_IS_CRITICAL,
468 RK3528_CLKGATE_CON(8), 15, GFLAGS),
469 GATE(PCLK_TIMER, "pclk_timer", "pclk_bus_root", 0,
470 RK3528_CLKGATE_CON(9), 5, GFLAGS),
471 GATE(PCLK_JDBCK_DAP, "pclk_jdbck_dap", "pclk_bus_root", 0,
472 RK3528_CLKGATE_CON(9), 12, GFLAGS),
473 GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus_root", 0,
474 RK3528_CLKGATE_CON(9), 15, GFLAGS),
475 GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_root", 0,
476 RK3528_CLKGATE_CON(10), 7, GFLAGS),
477 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus_root", 0,
478 RK3528_CLKGATE_CON(11), 4, GFLAGS),
479 GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus_root", 0,
480 RK3528_CLKGATE_CON(11), 7, GFLAGS),
481 GATE(PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_bus_root", 0,
482 RK3528_CLKGATE_CON(10), 13, GFLAGS),
483 GATE(PCLK_SCR, "pclk_scr", "pclk_bus_root", 0,
484 RK3528_CLKGATE_CON(11), 10, GFLAGS),
485 GATE(PCLK_INTMUX, "pclk_intmux", "pclk_bus_root", CLK_IGNORE_UNUSED,
486 RK3528_CLKGATE_CON(11), 12, GFLAGS),
487
488 COMPOSITE_NODIV(CLK_PWM0, "clk_pwm0", mux_100m_50m_24m_p, 0,
489 RK3528_CLKSEL_CON(44), 6, 2, MFLAGS,
490 RK3528_CLKGATE_CON(11), 5, GFLAGS),
491 COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", mux_100m_50m_24m_p, 0,
492 RK3528_CLKSEL_CON(44), 8, 2, MFLAGS,
493 RK3528_CLKGATE_CON(11), 8, GFLAGS),
494
495 GATE(CLK_CAPTURE_PWM1, "clk_capture_pwm1", "xin24m", 0,
496 RK3528_CLKGATE_CON(11), 9, GFLAGS),
497 GATE(CLK_CAPTURE_PWM0, "clk_capture_pwm0", "xin24m", 0,
498 RK3528_CLKGATE_CON(11), 6, GFLAGS),
499 GATE(CLK_JDBCK_DAP, "clk_jdbck_dap", "xin24m", 0,
500 RK3528_CLKGATE_CON(9), 13, GFLAGS),
501 GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 0,
502 RK3528_CLKGATE_CON(10), 0, GFLAGS),
503
504 GATE(CLK_TIMER_ROOT, "clk_timer_root", "xin24m", 0,
505 RK3528_CLKGATE_CON(8), 9, GFLAGS),
506 GATE(CLK_TIMER0, "clk_timer0", "clk_timer_root", 0,
507 RK3528_CLKGATE_CON(9), 6, GFLAGS),
508 GATE(CLK_TIMER1, "clk_timer1", "clk_timer_root", 0,
509 RK3528_CLKGATE_CON(9), 7, GFLAGS),
510 GATE(CLK_TIMER2, "clk_timer2", "clk_timer_root", 0,
511 RK3528_CLKGATE_CON(9), 8, GFLAGS),
512 GATE(CLK_TIMER3, "clk_timer3", "clk_timer_root", 0,
513 RK3528_CLKGATE_CON(9), 9, GFLAGS),
514 GATE(CLK_TIMER4, "clk_timer4", "clk_timer_root", 0,
515 RK3528_CLKGATE_CON(9), 10, GFLAGS),
516 GATE(CLK_TIMER5, "clk_timer5", "clk_timer_root", 0,
517 RK3528_CLKGATE_CON(9), 11, GFLAGS),
518
519 /* pmu */
520 GATE(HCLK_PMU_ROOT, "hclk_pmu_root", "clk_100m_src", CLK_IGNORE_UNUSED,
521 RK3528_PMU_CLKGATE_CON(0), 1, GFLAGS),
522 GATE(PCLK_PMU_ROOT, "pclk_pmu_root", "clk_100m_src", CLK_IGNORE_UNUSED,
523 RK3528_PMU_CLKGATE_CON(0), 0, GFLAGS),
524
525 GATE(FCLK_MCU, "fclk_mcu", "hclk_pmu_root", 0,
526 RK3528_PMU_CLKGATE_CON(0), 7, GFLAGS),
527 GATE(HCLK_PMU_SRAM, "hclk_pmu_sram", "hclk_pmu_root", CLK_IS_CRITICAL,
528 RK3528_PMU_CLKGATE_CON(5), 4, GFLAGS),
529
530 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_pmu_root", 0,
531 RK3528_PMU_CLKGATE_CON(0), 2, GFLAGS),
532 GATE(PCLK_PMU_HP_TIMER, "pclk_pmu_hp_timer", "pclk_pmu_root", 0,
533 RK3528_PMU_CLKGATE_CON(1), 2, GFLAGS),
534 GATE(PCLK_PMU_IOC, "pclk_pmu_ioc", "pclk_pmu_root", CLK_IS_CRITICAL,
535 RK3528_PMU_CLKGATE_CON(1), 5, GFLAGS),
536 GATE(PCLK_PMU_CRU, "pclk_pmu_cru", "pclk_pmu_root", CLK_IS_CRITICAL,
537 RK3528_PMU_CLKGATE_CON(1), 6, GFLAGS),
538 GATE(PCLK_PMU_GRF, "pclk_pmu_grf", "pclk_pmu_root", CLK_IS_CRITICAL,
539 RK3528_PMU_CLKGATE_CON(1), 7, GFLAGS),
540 GATE(PCLK_PMU_WDT, "pclk_pmu_wdt", "pclk_pmu_root", 0,
541 RK3528_PMU_CLKGATE_CON(1), 10, GFLAGS),
542 GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_root", CLK_IS_CRITICAL,
543 RK3528_PMU_CLKGATE_CON(0), 13, GFLAGS),
544 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pmu_root", 0,
545 RK3528_PMU_CLKGATE_CON(0), 14, GFLAGS),
546 GATE(PCLK_OSCCHK, "pclk_oscchk", "pclk_pmu_root", 0,
547 RK3528_PMU_CLKGATE_CON(0), 9, GFLAGS),
548 GATE(PCLK_PMU_MAILBOX, "pclk_pmu_mailbox", "pclk_pmu_root", 0,
549 RK3528_PMU_CLKGATE_CON(1), 12, GFLAGS),
550 GATE(PCLK_SCRKEYGEN, "pclk_scrkeygen", "pclk_pmu_root", 0,
551 RK3528_PMU_CLKGATE_CON(1), 15, GFLAGS),
552 GATE(PCLK_PVTM_PMU, "pclk_pvtm_pmu", "pclk_pmu_root", 0,
553 RK3528_PMU_CLKGATE_CON(5), 1, GFLAGS),
554
555 COMPOSITE_NODIV(CLK_I2C2, "clk_i2c2", clk_i2c2_p, 0,
556 RK3528_PMU_CLKSEL_CON(0), 0, 2, MFLAGS,
557 RK3528_PMU_CLKGATE_CON(0), 3, GFLAGS),
558
559 GATE(CLK_REFOUT, "clk_refout", "xin24m", 0,
560 RK3528_PMU_CLKGATE_CON(2), 4, GFLAGS),
561 COMPOSITE_NOMUX(CLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0,
562 RK3528_PMU_CLKSEL_CON(5), 0, 5, DFLAGS,
563 RK3528_PMU_CLKGATE_CON(5), 0, GFLAGS),
564
565 COMPOSITE_FRAC(XIN_OSC0_DIV, "xin_osc0_div", "xin24m", 0,
566 RK3528_PMU_CLKSEL_CON(1), 0,
567 RK3528_PMU_CLKGATE_CON(1), 0, GFLAGS),
568 /* clk_32k: internal! No path from external osc 32k */
569 MUX(CLK_DEEPSLOW, "clk_32k", clk_32k_p, CLK_IS_CRITICAL,
570 RK3528_PMU_CLKSEL_CON(2), 0, 1, MFLAGS),
571 GATE(RTC_CLK_MCU, "rtc_clk_mcu", "clk_32k", 0,
572 RK3528_PMU_CLKGATE_CON(0), 8, GFLAGS),
573 GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "xin24m", CLK_IGNORE_UNUSED,
574 RK3528_PMU_CLKGATE_CON(1), 1, GFLAGS),
575
576 COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", mux_24m_32k_p, 0,
577 RK3528_PMU_CLKSEL_CON(0), 2, 1, MFLAGS,
578 RK3528_PMU_CLKGATE_CON(0), 15, GFLAGS),
579 COMPOSITE_NODIV(TCLK_PMU_WDT, "tclk_pmu_wdt", mux_24m_32k_p, 0,
580 RK3528_PMU_CLKSEL_CON(2), 1, 1, MFLAGS,
581 RK3528_PMU_CLKGATE_CON(1), 11, GFLAGS),
582
583 /* core */
584 COMPOSITE_NOMUX(ACLK_M_CORE_BIU, "aclk_m_core", "armclk", CLK_IS_CRITICAL,
585 RK3528_CLKSEL_CON(39), 11, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
586 RK3528_CLKGATE_CON(5), 12, GFLAGS),
587 COMPOSITE_NOMUX(PCLK_DBG, "pclk_dbg", "armclk", CLK_IS_CRITICAL,
588 RK3528_CLKSEL_CON(40), 1, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
589 RK3528_CLKGATE_CON(5), 13, GFLAGS),
590 GATE(PCLK_CPU_ROOT, "pclk_cpu_root", "pclk_dbg", CLK_IS_CRITICAL,
591 RK3528_CLKGATE_CON(6), 1, GFLAGS),
592 GATE(PCLK_CORE_GRF, "pclk_core_grf", "pclk_cpu_root", CLK_IS_CRITICAL,
593 RK3528_CLKGATE_CON(6), 2, GFLAGS),
594
595 /* ddr */
596 GATE(CLK_DDRC_SRC, "clk_ddrc_src", "dpll", CLK_IS_CRITICAL,
597 RK3528_DDRPHY_CLKGATE_CON(0), 0, GFLAGS),
598 GATE(CLK_DDR_PHY, "clk_ddr_phy", "dpll", CLK_IS_CRITICAL,
599 RK3528_DDRPHY_CLKGATE_CON(0), 1, GFLAGS),
600
601 COMPOSITE_NODIV(PCLK_DDR_ROOT, "pclk_ddr_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
602 RK3528_CLKSEL_CON(90), 0, 2, MFLAGS,
603 RK3528_CLKGATE_CON(45), 0, GFLAGS),
604 GATE(PCLK_DDRMON, "pclk_ddrmon", "pclk_ddr_root", CLK_IGNORE_UNUSED,
605 RK3528_CLKGATE_CON(45), 3, GFLAGS),
606 GATE(PCLK_DDR_HWLP, "pclk_ddr_hwlp", "pclk_ddr_root", CLK_IGNORE_UNUSED,
607 RK3528_CLKGATE_CON(45), 8, GFLAGS),
608 GATE(CLK_TIMER_DDRMON, "clk_timer_ddrmon", "xin24m", CLK_IGNORE_UNUSED,
609 RK3528_CLKGATE_CON(45), 4, GFLAGS),
610
611 GATE(PCLK_DDRC, "pclk_ddrc", "pclk_ddr_root", CLK_IS_CRITICAL,
612 RK3528_CLKGATE_CON(45), 2, GFLAGS),
613 GATE(PCLK_DDR_GRF, "pclk_ddr_grf", "pclk_ddr_root", CLK_IS_CRITICAL,
614 RK3528_CLKGATE_CON(45), 6, GFLAGS),
615 GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_ddr_root", CLK_IS_CRITICAL,
616 RK3528_CLKGATE_CON(45), 9, GFLAGS),
617
618 GATE(ACLK_DDR_UPCTL, "aclk_ddr_upctl", "clk_ddrc_src", CLK_IS_CRITICAL,
619 RK3528_CLKGATE_CON(45), 11, GFLAGS),
620 GATE(CLK_DDR_UPCTL, "clk_ddr_upctl", "clk_ddrc_src", CLK_IS_CRITICAL,
621 RK3528_CLKGATE_CON(45), 12, GFLAGS),
622 GATE(CLK_DDRMON, "clk_ddrmon", "clk_ddrc_src", CLK_IS_CRITICAL,
623 RK3528_CLKGATE_CON(45), 13, GFLAGS),
624 GATE(ACLK_DDR_SCRAMBLE, "aclk_ddr_scramble", "clk_ddrc_src", CLK_IS_CRITICAL,
625 RK3528_CLKGATE_CON(45), 14, GFLAGS),
626 GATE(ACLK_SPLIT, "aclk_split", "clk_ddrc_src", CLK_IS_CRITICAL,
627 RK3528_CLKGATE_CON(45), 15, GFLAGS),
628
629 /* gpu */
630 COMPOSITE_NODIV(ACLK_GPU_ROOT, "aclk_gpu_root", mux_500m_300m_100m_24m_p, CLK_IS_CRITICAL,
631 RK3528_CLKSEL_CON(76), 0, 2, MFLAGS,
632 RK3528_CLKGATE_CON(34), 0, GFLAGS),
633 COMPOSITE_NODIV(ACLK_GPU, "aclk_gpu", aclk_gpu_p, CLK_SET_RATE_PARENT,
634 RK3528_CLKSEL_CON(76), 6, 1, MFLAGS,
635 RK3528_CLKGATE_CON(34), 7, GFLAGS),
636 GATE(ACLK_GPU_MALI, "aclk_gpu_mali", "aclk_gpu", 0,
637 RK3528_CLKGATE_CON(34), 8, GFLAGS),
638 COMPOSITE_NODIV(PCLK_GPU_ROOT, "pclk_gpu_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
639 RK3528_CLKSEL_CON(76), 4, 2, MFLAGS,
640 RK3528_CLKGATE_CON(34), 2, GFLAGS),
641
642 /* rkvdec */
643 COMPOSITE_NODIV(ACLK_RKVDEC_ROOT_NDFT, "aclk_rkvdec_root", mux_339m_200m_100m_24m_p, CLK_IS_CRITICAL,
644 RK3528_CLKSEL_CON(88), 6, 2, MFLAGS,
645 RK3528_CLKGATE_CON(44), 3, GFLAGS),
646 COMPOSITE_NODIV(HCLK_RKVDEC_ROOT, "hclk_rkvdec_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
647 RK3528_CLKSEL_CON(88), 4, 2, MFLAGS,
648 RK3528_CLKGATE_CON(44), 2, GFLAGS),
649 GATE(PCLK_DDRPHY_CRU, "pclk_ddrphy_cru", "hclk_rkvdec_root", CLK_IS_CRITICAL,
650 RK3528_CLKGATE_CON(44), 4, GFLAGS),
651 GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_root", 0,
652 RK3528_CLKGATE_CON(44), 9, GFLAGS),
653 COMPOSITE_NODIV(CLK_HEVC_CA_RKVDEC, "clk_hevc_ca_rkvdec", mux_600m_300m_200m_24m_p, 0,
654 RK3528_CLKSEL_CON(88), 11, 2, MFLAGS,
655 RK3528_CLKGATE_CON(44), 11, GFLAGS),
656 MUX(ACLK_RKVDEC_PVTMUX_ROOT, "aclk_rkvdec_pvtmux_root", aclk_rkvdec_pvtmux_root_p, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
657 RK3528_CLKSEL_CON(88), 13, 1, MFLAGS),
658 GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pvtmux_root", 0,
659 RK3528_CLKGATE_CON(44), 8, GFLAGS),
660
661 /* rkvenc */
662 COMPOSITE_NODIV(ACLK_RKVENC_ROOT, "aclk_rkvenc_root", mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL,
663 RK3528_CLKSEL_CON(79), 2, 2, MFLAGS,
664 RK3528_CLKGATE_CON(36), 1, GFLAGS),
665 GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_root", 0,
666 RK3528_CLKGATE_CON(36), 7, GFLAGS),
667
668 COMPOSITE_NODIV(PCLK_RKVENC_ROOT, "pclk_rkvenc_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
669 RK3528_CLKSEL_CON(79), 4, 2, MFLAGS,
670 RK3528_CLKGATE_CON(36), 2, GFLAGS),
671 GATE(PCLK_RKVENC_IOC, "pclk_rkvenc_ioc", "pclk_rkvenc_root", CLK_IS_CRITICAL,
672 RK3528_CLKGATE_CON(37), 10, GFLAGS),
673 GATE(PCLK_RKVENC_GRF, "pclk_rkvenc_grf", "pclk_rkvenc_root", CLK_IS_CRITICAL,
674 RK3528_CLKGATE_CON(38), 6, GFLAGS),
675 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_rkvenc_root", 0,
676 RK3528_CLKGATE_CON(36), 11, GFLAGS),
677 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_rkvenc_root", 0,
678 RK3528_CLKGATE_CON(36), 13, GFLAGS),
679 GATE(PCLK_SPI0, "pclk_spi0", "pclk_rkvenc_root", 0,
680 RK3528_CLKGATE_CON(37), 2, GFLAGS),
681 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_rkvenc_root", 0,
682 RK3528_CLKGATE_CON(37), 8, GFLAGS),
683 GATE(PCLK_UART1, "pclk_uart1", "pclk_rkvenc_root", 0,
684 RK3528_CLKGATE_CON(38), 2, GFLAGS),
685 GATE(PCLK_UART3, "pclk_uart3", "pclk_rkvenc_root", 0,
686 RK3528_CLKGATE_CON(38), 4, GFLAGS),
687 GATE(PCLK_CAN0, "pclk_can0", "pclk_rkvenc_root", 0,
688 RK3528_CLKGATE_CON(38), 7, GFLAGS),
689 GATE(PCLK_CAN1, "pclk_can1", "pclk_rkvenc_root", 0,
690 RK3528_CLKGATE_CON(38), 9, GFLAGS),
691
692 COMPOSITE_NODIV(MCLK_PDM, "mclk_pdm", mux_150m_100m_24m_p, 0,
693 RK3528_CLKSEL_CON(80), 12, 2, MFLAGS,
694 RK3528_CLKGATE_CON(38), 1, GFLAGS),
695 COMPOSITE(CLK_CAN0, "clk_can0", mux_gpll_cpll_p, 0,
696 RK3528_CLKSEL_CON(81), 6, 1, MFLAGS, 0, 6, DFLAGS,
697 RK3528_CLKGATE_CON(38), 8, GFLAGS),
698 COMPOSITE(CLK_CAN1, "clk_can1", mux_gpll_cpll_p, 0,
699 RK3528_CLKSEL_CON(81), 13, 1, MFLAGS, 7, 6, DFLAGS,
700 RK3528_CLKGATE_CON(38), 10, GFLAGS),
701
702 COMPOSITE_NODIV(HCLK_RKVENC_ROOT, "hclk_rkvenc_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
703 RK3528_CLKSEL_CON(79), 0, 2, MFLAGS,
704 RK3528_CLKGATE_CON(36), 0, GFLAGS),
705 GATE(HCLK_SAI_I2S1, "hclk_sai_i2s1", "hclk_rkvenc_root", 0,
706 RK3528_CLKGATE_CON(36), 9, GFLAGS),
707 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_rkvenc_root", 0,
708 RK3528_CLKGATE_CON(37), 14, GFLAGS),
709 GATE(HCLK_PDM, "hclk_pdm", "hclk_rkvenc_root", 0,
710 RK3528_CLKGATE_CON(38), 0, GFLAGS),
711 GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_root", 0,
712 RK3528_CLKGATE_CON(36), 6, GFLAGS),
713
714 COMPOSITE_NODIV(CLK_CORE_RKVENC, "clk_core_rkvenc", mux_300m_200m_100m_24m_p, 0,
715 RK3528_CLKSEL_CON(79), 6, 2, MFLAGS,
716 RK3528_CLKGATE_CON(36), 8, GFLAGS),
717 COMPOSITE_NODIV(CLK_I2C0, "clk_i2c0", mux_200m_100m_50m_24m_p, 0,
718 RK3528_CLKSEL_CON(79), 11, 2, MFLAGS,
719 RK3528_CLKGATE_CON(36), 14, GFLAGS),
720 COMPOSITE_NODIV(CLK_I2C1, "clk_i2c1", mux_200m_100m_50m_24m_p, 0,
721 RK3528_CLKSEL_CON(79), 9, 2, MFLAGS,
722 RK3528_CLKGATE_CON(36), 12, GFLAGS),
723
724 COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_100m_50m_24m_p, 0,
725 RK3528_CLKSEL_CON(79), 13, 2, MFLAGS,
726 RK3528_CLKGATE_CON(37), 3, GFLAGS),
727 COMPOSITE_NODIV(MCLK_SAI_I2S1, "mclk_sai_i2s1", mclk_sai_i2s1_p, CLK_SET_RATE_PARENT,
728 RK3528_CLKSEL_CON(79), 8, 1, MFLAGS,
729 RK3528_CLKGATE_CON(36), 10, GFLAGS),
730 GATE(DBCLK_GPIO4, "dbclk_gpio4", "xin24m", 0,
731 RK3528_CLKGATE_CON(37), 9, GFLAGS),
732
733 /* vo */
734 COMPOSITE_NODIV(HCLK_VO_ROOT, "hclk_vo_root", mux_150m_100m_24m_p, CLK_IS_CRITICAL,
735 RK3528_CLKSEL_CON(83), 2, 2, MFLAGS,
736 RK3528_CLKGATE_CON(39), 1, GFLAGS),
737 GATE(HCLK_VOP, "hclk_vop", "hclk_vo_root", 0,
738 RK3528_CLKGATE_CON(40), 2, GFLAGS),
739 GATE(HCLK_USBHOST, "hclk_usbhost", "hclk_vo_root", 0,
740 RK3528_CLKGATE_CON(43), 3, GFLAGS),
741 GATE(HCLK_JPEG_DECODER, "hclk_jpeg_decoder", "hclk_vo_root", 0,
742 RK3528_CLKGATE_CON(41), 7, GFLAGS),
743 GATE(HCLK_VDPP, "hclk_vdpp", "hclk_vo_root", 0,
744 RK3528_CLKGATE_CON(39), 10, GFLAGS),
745 GATE(HCLK_CVBS, "hclk_cvbs", "hclk_vo_root", 0,
746 RK3528_CLKGATE_CON(41), 3, GFLAGS),
747 GATE(HCLK_USBHOST_ARB, "hclk_usbhost_arb", "hclk_vo_root", 0,
748 RK3528_CLKGATE_CON(43), 4, GFLAGS),
749 GATE(HCLK_SAI_I2S3, "hclk_sai_i2s3", "hclk_vo_root", 0,
750 RK3528_CLKGATE_CON(42), 1, GFLAGS),
751 GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vo_root", 0,
752 RK3528_CLKGATE_CON(41), 1, GFLAGS),
753 GATE(HCLK_RGA2E, "hclk_rga2e", "hclk_vo_root", 0,
754 RK3528_CLKGATE_CON(39), 7, GFLAGS),
755 GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_vo_root", 0,
756 RK3528_CLKGATE_CON(42), 9, GFLAGS),
757 GATE(HCLK_HDCP_KEY, "hclk_hdcp_key", "hclk_vo_root", 0,
758 RK3528_CLKGATE_CON(40), 15, GFLAGS),
759
760 COMPOSITE_NODIV(ACLK_VO_L_ROOT, "aclk_vo_l_root", mux_150m_100m_24m_p, CLK_IS_CRITICAL,
761 RK3528_CLKSEL_CON(84), 1, 2, MFLAGS,
762 RK3528_CLKGATE_CON(41), 8, GFLAGS),
763 GATE(ACLK_MAC_VO, "aclk_gmac0", "aclk_vo_l_root", 0,
764 RK3528_CLKGATE_CON(41), 10, GFLAGS),
765
766 COMPOSITE_NODIV(PCLK_VO_ROOT, "pclk_vo_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
767 RK3528_CLKSEL_CON(83), 4, 2, MFLAGS,
768 RK3528_CLKGATE_CON(39), 2, GFLAGS),
769 GATE(PCLK_MAC_VO, "pclk_gmac0", "pclk_vo_root", 0,
770 RK3528_CLKGATE_CON(41), 11, GFLAGS),
771 GATE(PCLK_VCDCPHY, "pclk_vcdcphy", "pclk_vo_root", 0,
772 RK3528_CLKGATE_CON(42), 4, GFLAGS),
773 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_vo_root", 0,
774 RK3528_CLKGATE_CON(42), 5, GFLAGS),
775 GATE(PCLK_VO_IOC, "pclk_vo_ioc", "pclk_vo_root", CLK_IS_CRITICAL,
776 RK3528_CLKGATE_CON(42), 7, GFLAGS),
777 GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_vo_root", 0,
778 RK3528_CLKGATE_CON(42), 11, GFLAGS),
779 GATE(PCLK_UART4, "pclk_uart4", "pclk_vo_root", 0,
780 RK3528_CLKGATE_CON(43), 7, GFLAGS),
781 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_vo_root", 0,
782 RK3528_CLKGATE_CON(43), 9, GFLAGS),
783 GATE(PCLK_I2C7, "pclk_i2c7", "pclk_vo_root", 0,
784 RK3528_CLKGATE_CON(43), 11, GFLAGS),
785
786 GATE(PCLK_USBPHY, "pclk_usbphy", "pclk_vo_root", 0,
787 RK3528_CLKGATE_CON(43), 13, GFLAGS),
788
789 GATE(PCLK_VO_GRF, "pclk_vo_grf", "pclk_vo_root", CLK_IS_CRITICAL,
790 RK3528_CLKGATE_CON(39), 13, GFLAGS),
791 GATE(PCLK_CRU, "pclk_cru", "pclk_vo_root", CLK_IS_CRITICAL,
792 RK3528_CLKGATE_CON(39), 15, GFLAGS),
793 GATE(PCLK_HDMI, "pclk_hdmi", "pclk_vo_root", 0,
794 RK3528_CLKGATE_CON(40), 6, GFLAGS),
795 GATE(PCLK_HDMIPHY, "pclk_hdmiphy", "pclk_vo_root", 0,
796 RK3528_CLKGATE_CON(40), 14, GFLAGS),
797 GATE(PCLK_HDCP, "pclk_hdcp", "pclk_vo_root", 0,
798 RK3528_CLKGATE_CON(41), 2, GFLAGS),
799
800 COMPOSITE_NODIV(CLK_CORE_VDPP, "clk_core_vdpp", mux_339m_200m_100m_24m_p, 0,
801 RK3528_CLKSEL_CON(83), 10, 2, MFLAGS,
802 RK3528_CLKGATE_CON(39), 12, GFLAGS),
803 COMPOSITE_NODIV(CLK_CORE_RGA2E, "clk_core_rga2e", mux_339m_200m_100m_24m_p, 0,
804 RK3528_CLKSEL_CON(83), 8, 2, MFLAGS,
805 RK3528_CLKGATE_CON(39), 9, GFLAGS),
806 COMPOSITE_NODIV(ACLK_JPEG_ROOT, "aclk_jpeg_root", mux_339m_200m_100m_24m_p, CLK_IS_CRITICAL,
807 RK3528_CLKSEL_CON(84), 9, 2, MFLAGS,
808 RK3528_CLKGATE_CON(41), 15, GFLAGS),
809 GATE(ACLK_JPEG_DECODER, "aclk_jpeg_decoder", "aclk_jpeg_root", 0,
810 RK3528_CLKGATE_CON(41), 6, GFLAGS),
811
812 COMPOSITE_NODIV(ACLK_VO_ROOT, "aclk_vo_root", mux_339m_200m_100m_24m_p, CLK_IS_CRITICAL,
813 RK3528_CLKSEL_CON(83), 0, 2, MFLAGS,
814 RK3528_CLKGATE_CON(39), 0, GFLAGS),
815 GATE(ACLK_RGA2E, "aclk_rga2e", "aclk_vo_root", 0,
816 RK3528_CLKGATE_CON(39), 8, GFLAGS),
817 GATE(ACLK_VDPP, "aclk_vdpp", "aclk_vo_root", 0,
818 RK3528_CLKGATE_CON(39), 11, GFLAGS),
819 GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vo_root", 0,
820 RK3528_CLKGATE_CON(41), 0, GFLAGS),
821
822 COMPOSITE(CCLK_SRC_SDMMC0, "cclk_src_sdmmc0", mux_gpll_cpll_xin24m_p, 0,
823 RK3528_CLKSEL_CON(85), 6, 2, MFLAGS, 0, 6, DFLAGS,
824 RK3528_CLKGATE_CON(42), 8, GFLAGS),
825
826 COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", mux_gpll_cpll_p, CLK_IS_CRITICAL,
827 RK3528_CLKSEL_CON(83), 15, 1, MFLAGS, 12, 3, DFLAGS,
828 RK3528_CLKGATE_CON(40), 0, GFLAGS),
829 GATE(ACLK_VOP, "aclk_vop", "aclk_vop_root", 0,
830 RK3528_CLKGATE_CON(40), 5, GFLAGS),
831
832 COMPOSITE_NODIV(CLK_I2C4, "clk_i2c4", mux_200m_100m_50m_24m_p, 0,
833 RK3528_CLKSEL_CON(85), 13, 2, MFLAGS,
834 RK3528_CLKGATE_CON(43), 10, GFLAGS),
835 COMPOSITE_NODIV(CLK_I2C7, "clk_i2c7", mux_200m_100m_50m_24m_p, 0,
836 RK3528_CLKSEL_CON(86), 0, 2, MFLAGS,
837 RK3528_CLKGATE_CON(43), 12, GFLAGS),
838 GATE(DBCLK_GPIO2, "dbclk_gpio2", "xin24m", 0,
839 RK3528_CLKGATE_CON(42), 6, GFLAGS),
840
841 GATE(CLK_HDMIHDP0, "clk_hdmihdp0", "xin24m", 0,
842 RK3528_CLKGATE_CON(43), 2, GFLAGS),
843 GATE(CLK_MACPHY, "clk_macphy", "xin24m", 0,
844 RK3528_CLKGATE_CON(42), 3, GFLAGS),
845 GATE(CLK_REF_USBPHY, "clk_ref_usbphy", "xin24m", 0,
846 RK3528_CLKGATE_CON(43), 14, GFLAGS),
847 GATE(CLK_SBPI_OTPC_NS, "clk_sbpi_otpc_ns", "xin24m", 0,
848 RK3528_CLKGATE_CON(42), 12, GFLAGS),
849 FACTOR(CLK_USER_OTPC_NS, "clk_user_otpc_ns", "clk_sbpi_otpc_ns",
850 0, 1, 2),
851
852 GATE(MCLK_SAI_I2S3, "mclk_sai_i2s3", "mclk_i2s3_8ch_sai_src", 0,
853 RK3528_CLKGATE_CON(42), 2, GFLAGS),
854 COMPOSITE_NODIV(DCLK_VOP0, "dclk_vop0", dclk_vop0_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
855 RK3528_CLKSEL_CON(84), 0, 1, MFLAGS,
856 RK3528_CLKGATE_CON(40), 3, GFLAGS),
857 GATE(DCLK_VOP1, "dclk_vop1", "dclk_vop_src1", CLK_SET_RATE_PARENT,
858 RK3528_CLKGATE_CON(40), 4, GFLAGS),
859 FACTOR_GATE(DCLK_CVBS, "dclk_cvbs", "dclk_vop1", 0, 1, 4,
860 RK3528_CLKGATE_CON(41), 4, GFLAGS),
861 GATE(DCLK_4X_CVBS, "dclk_4x_cvbs", "dclk_vop1", 0,
862 RK3528_CLKGATE_CON(41), 5, GFLAGS),
863
864 FACTOR_GATE(CLK_SFR_HDMI, "clk_sfr_hdmi", "dclk_vop_src1", 0, 1, 4,
865 RK3528_CLKGATE_CON(40), 7, GFLAGS),
866
867 GATE(CLK_SPDIF_HDMI, "clk_spdif_hdmi", "mclk_spdif_src", 0,
868 RK3528_CLKGATE_CON(40), 10, GFLAGS),
869 GATE(MCLK_SPDIF, "mclk_spdif", "mclk_spdif_src", 0,
870 RK3528_CLKGATE_CON(37), 15, GFLAGS),
871 GATE(CLK_CEC_HDMI, "clk_cec_hdmi", "clk_32k", 0,
872 RK3528_CLKGATE_CON(40), 8, GFLAGS),
873
874 /* vpu */
875 GATE(DBCLK_GPIO1, "dbclk_gpio1", "xin24m", 0,
876 RK3528_CLKGATE_CON(26), 5, GFLAGS),
877 GATE(DBCLK_GPIO3, "dbclk_gpio3", "xin24m", 0,
878 RK3528_CLKGATE_CON(27), 1, GFLAGS),
879 GATE(CLK_SUSPEND_USB3OTG, "clk_suspend_usb3otg", "xin24m", 0,
880 RK3528_CLKGATE_CON(33), 4, GFLAGS),
881 GATE(CLK_PCIE_AUX, "clk_pcie_aux", "xin24m", 0,
882 RK3528_CLKGATE_CON(30), 2, GFLAGS),
883 GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 0,
884 RK3528_CLKGATE_CON(26), 3, GFLAGS),
885 GATE(CLK_REF_USB3OTG, "clk_ref_usb3otg", "xin24m", 0,
886 RK3528_CLKGATE_CON(33), 2, GFLAGS),
887 COMPOSITE(CCLK_SRC_SDIO0, "cclk_src_sdio0", mux_gpll_cpll_xin24m_p, 0,
888 RK3528_CLKSEL_CON(72), 6, 2, MFLAGS, 0, 6, DFLAGS,
889 RK3528_CLKGATE_CON(32), 1, GFLAGS),
890
891 COMPOSITE_NODIV(PCLK_VPU_ROOT, "pclk_vpu_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
892 RK3528_CLKSEL_CON(61), 4, 2, MFLAGS,
893 RK3528_CLKGATE_CON(25), 5, GFLAGS),
894 GATE(PCLK_VPU_GRF, "pclk_vpu_grf", "pclk_vpu_root", CLK_IS_CRITICAL,
895 RK3528_CLKGATE_CON(25), 12, GFLAGS),
896 GATE(PCLK_CRU_PCIE, "pclk_cru_pcie", "pclk_vpu_root", CLK_IS_CRITICAL,
897 RK3528_CLKGATE_CON(25), 11, GFLAGS),
898 GATE(PCLK_UART6, "pclk_uart6", "pclk_vpu_root", 0,
899 RK3528_CLKGATE_CON(27), 11, GFLAGS),
900 GATE(PCLK_CAN2, "pclk_can2", "pclk_vpu_root", 0,
901 RK3528_CLKGATE_CON(32), 7, GFLAGS),
902 GATE(PCLK_SPI1, "pclk_spi1", "pclk_vpu_root", 0,
903 RK3528_CLKGATE_CON(27), 4, GFLAGS),
904 GATE(PCLK_CAN3, "pclk_can3", "pclk_vpu_root", 0,
905 RK3528_CLKGATE_CON(32), 9, GFLAGS),
906 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_vpu_root", 0,
907 RK3528_CLKGATE_CON(27), 0, GFLAGS),
908 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_vpu_root", 0,
909 RK3528_CLKGATE_CON(26), 4, GFLAGS),
910 GATE(PCLK_SARADC, "pclk_saradc", "pclk_vpu_root", 0,
911 RK3528_CLKGATE_CON(32), 11, GFLAGS),
912 GATE(PCLK_ACODEC, "pclk_acodec", "pclk_vpu_root", 0,
913 RK3528_CLKGATE_CON(26), 13, GFLAGS),
914 GATE(PCLK_UART7, "pclk_uart7", "pclk_vpu_root", 0,
915 RK3528_CLKGATE_CON(27), 13, GFLAGS),
916 GATE(PCLK_UART5, "pclk_uart5", "pclk_vpu_root", 0,
917 RK3528_CLKGATE_CON(27), 9, GFLAGS),
918 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_vpu_root", 0,
919 RK3528_CLKGATE_CON(32), 14, GFLAGS),
920 GATE(PCLK_PCIE, "pclk_pcie", "pclk_vpu_root", 0,
921 RK3528_CLKGATE_CON(30), 1, GFLAGS),
922 GATE(PCLK_UART2, "pclk_uart2", "pclk_vpu_root", 0,
923 RK3528_CLKGATE_CON(27), 7, GFLAGS),
924 GATE(PCLK_VPU_IOC, "pclk_vpu_ioc", "pclk_vpu_root", CLK_IS_CRITICAL,
925 RK3528_CLKGATE_CON(26), 8, GFLAGS),
926 GATE(PCLK_PIPE_GRF, "pclk_pipe_grf", "pclk_vpu_root", CLK_IS_CRITICAL,
927 RK3528_CLKGATE_CON(30), 7, GFLAGS),
928 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_vpu_root", 0,
929 RK3528_CLKGATE_CON(28), 1, GFLAGS),
930 GATE(PCLK_PCIE_PHY, "pclk_pcie_phy", "pclk_vpu_root", 0,
931 RK3528_CLKGATE_CON(30), 6, GFLAGS),
932 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_vpu_root", 0,
933 RK3528_CLKGATE_CON(27), 15, GFLAGS),
934 GATE(PCLK_MAC_VPU, "pclk_gmac1", "pclk_vpu_root", CLK_IS_CRITICAL,
935 RK3528_CLKGATE_CON(28), 6, GFLAGS),
936 GATE(PCLK_I2C6, "pclk_i2c6", "pclk_vpu_root", 0,
937 RK3528_CLKGATE_CON(28), 3, GFLAGS),
938
939 COMPOSITE_NODIV(ACLK_VPU_L_ROOT, "aclk_vpu_l_root", mux_200m_100m_24m_p, CLK_IS_CRITICAL,
940 RK3528_CLKSEL_CON(60), 0, 2, MFLAGS,
941 RK3528_CLKGATE_CON(25), 0, GFLAGS),
942 GATE(ACLK_EMMC, "aclk_emmc", "aclk_vpu_l_root", 0,
943 RK3528_CLKGATE_CON(26), 1, GFLAGS),
944 GATE(ACLK_MAC_VPU, "aclk_gmac1", "aclk_vpu_l_root", 0,
945 RK3528_CLKGATE_CON(28), 5, GFLAGS),
946 GATE(ACLK_PCIE, "aclk_pcie", "aclk_vpu_l_root", 0,
947 RK3528_CLKGATE_CON(30), 3, GFLAGS),
948
949 GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_vpu_l_root", 0,
950 RK3528_CLKGATE_CON(33), 1, GFLAGS),
951
952 COMPOSITE_NODIV(HCLK_VPU_ROOT, "hclk_vpu_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
953 RK3528_CLKSEL_CON(61), 2, 2, MFLAGS,
954 RK3528_CLKGATE_CON(25), 4, GFLAGS),
955 GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_root", 0,
956 RK3528_CLKGATE_CON(25), 10, GFLAGS),
957 GATE(HCLK_SFC, "hclk_sfc", "hclk_vpu_root", 0,
958 RK3528_CLKGATE_CON(25), 13, GFLAGS),
959 GATE(HCLK_EMMC, "hclk_emmc", "hclk_vpu_root", 0,
960 RK3528_CLKGATE_CON(26), 0, GFLAGS),
961 GATE(HCLK_SAI_I2S0, "hclk_sai_i2s0", "hclk_vpu_root", 0,
962 RK3528_CLKGATE_CON(26), 9, GFLAGS),
963 GATE(HCLK_SAI_I2S2, "hclk_sai_i2s2", "hclk_vpu_root", 0,
964 RK3528_CLKGATE_CON(26), 11, GFLAGS),
965
966 GATE(HCLK_PCIE_SLV, "hclk_pcie_slv", "hclk_vpu_root", 0,
967 RK3528_CLKGATE_CON(30), 4, GFLAGS),
968 GATE(HCLK_PCIE_DBI, "hclk_pcie_dbi", "hclk_vpu_root", 0,
969 RK3528_CLKGATE_CON(30), 5, GFLAGS),
970 GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_vpu_root", 0,
971 RK3528_CLKGATE_CON(32), 2, GFLAGS),
972 GATE(HCLK_SDIO1, "hclk_sdio1", "hclk_vpu_root", 0,
973 RK3528_CLKGATE_CON(32), 4, GFLAGS),
974
975 COMPOSITE_NOMUX(CLK_GMAC1_VPU_25M, "clk_gmac1_25m", "ppll", 0,
976 RK3528_CLKSEL_CON(60), 2, 8, DFLAGS,
977 RK3528_CLKGATE_CON(25), 1, GFLAGS),
978 COMPOSITE_NOMUX(CLK_PPLL_125M_MATRIX, "clk_ppll_125m_src", "ppll", 0,
979 RK3528_CLKSEL_CON(60), 10, 5, DFLAGS,
980 RK3528_CLKGATE_CON(25), 2, GFLAGS),
981
982 COMPOSITE(CLK_CAN3, "clk_can3", mux_gpll_cpll_p, 0,
983 RK3528_CLKSEL_CON(73), 13, 1, MFLAGS, 7, 6, DFLAGS,
984 RK3528_CLKGATE_CON(32), 10, GFLAGS),
985 COMPOSITE_NODIV(CLK_I2C6, "clk_i2c6", mux_200m_100m_50m_24m_p, 0,
986 RK3528_CLKSEL_CON(64), 0, 2, MFLAGS,
987 RK3528_CLKGATE_CON(28), 4, GFLAGS),
988
989 COMPOSITE(SCLK_SFC, "sclk_sfc", mux_gpll_cpll_xin24m_p, 0,
990 RK3528_CLKSEL_CON(61), 12, 2, MFLAGS, 6, 6, DFLAGS,
991 RK3528_CLKGATE_CON(25), 14, GFLAGS),
992 COMPOSITE(CCLK_SRC_EMMC, "cclk_src_emmc", mux_gpll_cpll_xin24m_p, 0,
993 RK3528_CLKSEL_CON(62), 6, 2, MFLAGS, 0, 6, DFLAGS,
994 RK3528_CLKGATE_CON(25), 15, GFLAGS),
995
996 COMPOSITE_NODIV(ACLK_VPU_ROOT, "aclk_vpu_root",
997 mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL,
998 RK3528_CLKSEL_CON(61), 0, 2, MFLAGS,
999 RK3528_CLKGATE_CON(25), 3, GFLAGS),
1000 GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_root", 0,
1001 RK3528_CLKGATE_CON(25), 9, GFLAGS),
1002
1003 COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_100m_50m_24m_p, 0,
1004 RK3528_CLKSEL_CON(63), 10, 2, MFLAGS,
1005 RK3528_CLKGATE_CON(27), 5, GFLAGS),
1006 COMPOSITE(CCLK_SRC_SDIO1, "cclk_src_sdio1", mux_gpll_cpll_xin24m_p, 0,
1007 RK3528_CLKSEL_CON(72), 14, 2, MFLAGS, 8, 6, DFLAGS,
1008 RK3528_CLKGATE_CON(32), 3, GFLAGS),
1009 COMPOSITE(CLK_CAN2, "clk_can2", mux_gpll_cpll_p, 0,
1010 RK3528_CLKSEL_CON(73), 6, 1, MFLAGS, 0, 6, DFLAGS,
1011 RK3528_CLKGATE_CON(32), 8, GFLAGS),
1012 COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "xin24m", 0,
1013 RK3528_CLKSEL_CON(74), 3, 5, DFLAGS,
1014 RK3528_CLKGATE_CON(32), 15, GFLAGS),
1015 COMPOSITE_NOMUX(CLK_SARADC, "clk_saradc", "xin24m", 0,
1016 RK3528_CLKSEL_CON(74), 0, 3, DFLAGS,
1017 RK3528_CLKGATE_CON(32), 12, GFLAGS),
1018 COMPOSITE_NOMUX(CLK_TSADC_TSEN, "clk_tsadc_tsen", "xin24m", 0,
1019 RK3528_CLKSEL_CON(74), 8, 5, DFLAGS,
1020 RK3528_CLKGATE_CON(33), 0, GFLAGS),
1021 COMPOSITE_NODIV(BCLK_EMMC, "bclk_emmc", mux_200m_100m_50m_24m_p, 0,
1022 RK3528_CLKSEL_CON(62), 8, 2, MFLAGS,
1023 RK3528_CLKGATE_CON(26), 2, GFLAGS),
1024 COMPOSITE_NOMUX(MCLK_ACODEC_TX, "mclk_acodec_tx", "mclk_i2s2_2ch_sai_src", 0,
1025 RK3528_CLKSEL_CON(63), 0, 8, DFLAGS,
1026 RK3528_CLKGATE_CON(26), 14, GFLAGS),
1027 COMPOSITE_NODIV(CLK_I2C3, "clk_i2c3", mux_200m_100m_50m_24m_p, 0,
1028 RK3528_CLKSEL_CON(63), 12, 2, MFLAGS,
1029 RK3528_CLKGATE_CON(28), 0, GFLAGS),
1030 COMPOSITE_NODIV(CLK_I2C5, "clk_i2c5", mux_200m_100m_50m_24m_p, 0,
1031 RK3528_CLKSEL_CON(63), 14, 2, MFLAGS,
1032 RK3528_CLKGATE_CON(28), 2, GFLAGS),
1033 COMPOSITE_NODIV(MCLK_SAI_I2S0, "mclk_sai_i2s0", mclk_sai_i2s0_p, CLK_SET_RATE_PARENT,
1034 RK3528_CLKSEL_CON(62), 10, 1, MFLAGS,
1035 RK3528_CLKGATE_CON(26), 10, GFLAGS),
1036 GATE(MCLK_SAI_I2S2, "mclk_sai_i2s2", "mclk_i2s2_2ch_sai_src", 0,
1037 RK3528_CLKGATE_CON(26), 12, GFLAGS),
1038
1039 /* pcie */
1040 COMPOSITE_NOMUX(CLK_PPLL_100M_MATRIX, "clk_ppll_100m_src", "ppll", CLK_IS_CRITICAL,
1041 RK3528_PCIE_CLKSEL_CON(1), 2, 5, DFLAGS,
1042 RK3528_PCIE_CLKGATE_CON(0), 1, GFLAGS),
1043 COMPOSITE_NOMUX(CLK_PPLL_50M_MATRIX, "clk_ppll_50m_src", "ppll", CLK_IS_CRITICAL,
1044 RK3528_PCIE_CLKSEL_CON(1), 7, 5, DFLAGS,
1045 RK3528_PCIE_CLKGATE_CON(0), 2, GFLAGS),
1046 MUX(CLK_REF_PCIE_INNER_PHY, "clk_ref_pcie_inner_phy", clk_ref_pcie_inner_phy_p, 0,
1047 RK3528_PCIE_CLKSEL_CON(1), 13, 1, MFLAGS),
1048 FACTOR(CLK_REF_PCIE_100M_PHY, "clk_ref_pcie_100m_phy", "clk_ppll_100m_src",
1049 0, 1, 1),
1050
1051 /* gmac */
1052 DIV(CLK_GMAC0_SRC, "clk_gmac0_src", "gmac0", 0,
1053 RK3528_CLKSEL_CON(84), 3, 6, DFLAGS),
1054 GATE(CLK_GMAC0_TX, "clk_gmac0_tx", "clk_gmac0_src", 0,
1055 RK3528_CLKGATE_CON(41), 13, GFLAGS),
1056 GATE(CLK_GMAC0_RX, "clk_gmac0_rx", "clk_gmac0_src", 0,
1057 RK3528_CLKGATE_CON(41), 14, GFLAGS),
1058 GATE(CLK_GMAC0_RMII_50M, "clk_gmac0_rmii_50m", "gmac0", 0,
1059 RK3528_CLKGATE_CON(41), 12, GFLAGS),
1060
1061 FACTOR(CLK_GMAC1_RMII_VPU, "clk_gmac1_50m", "clk_ppll_50m_src",
1062 0, 1, 1),
1063 FACTOR(CLK_GMAC1_SRC_VPU, "clk_gmac1_125m", "clk_ppll_125m_src",
1064 0, 1, 1),
1065 };
1066
1067 static struct rockchip_clk_branch rk3528_vo_clk_branches[] __initdata = {
1068 MMC_GRF(SCLK_SDMMC_DRV, "sdmmc_drv", "cclk_src_sdmmc0",
1069 RK3528_SDMMC_CON(0), 1, grf_type_vo),
1070 MMC_GRF(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "cclk_src_sdmmc0",
1071 RK3528_SDMMC_CON(1), 1, grf_type_vo),
1072 };
1073
1074 static struct rockchip_clk_branch rk3528_vpu_clk_branches[] __initdata = {
1075 MMC_GRF(SCLK_SDIO0_DRV, "sdio0_drv", "cclk_src_sdio0",
1076 RK3528_SDIO0_CON(0), 1, grf_type_vpu),
1077 MMC_GRF(SCLK_SDIO0_SAMPLE, "sdio0_sample", "cclk_src_sdio0",
1078 RK3528_SDIO0_CON(1), 1, grf_type_vpu),
1079 MMC_GRF(SCLK_SDIO1_DRV, "sdio1_drv", "cclk_src_sdio1",
1080 RK3528_SDIO1_CON(0), 1, grf_type_vpu),
1081 MMC_GRF(SCLK_SDIO1_SAMPLE, "sdio1_sample", "cclk_src_sdio1",
1082 RK3528_SDIO1_CON(1), 1, grf_type_vpu),
1083 };
1084
clk_rk3528_probe(struct platform_device * pdev)1085 static int __init clk_rk3528_probe(struct platform_device *pdev)
1086 {
1087 unsigned long nr_vpu_branches = ARRAY_SIZE(rk3528_vpu_clk_branches);
1088 unsigned long nr_vo_branches = ARRAY_SIZE(rk3528_vo_clk_branches);
1089 unsigned long nr_branches = ARRAY_SIZE(rk3528_clk_branches);
1090 unsigned long nr_clks, nr_vo_clks, nr_vpu_clks;
1091 struct rockchip_aux_grf *vo_grf_e, *vpu_grf_e;
1092 struct regmap *vo_grf, *vpu_grf;
1093 struct device *dev = &pdev->dev;
1094 struct device_node *np = dev->of_node;
1095 struct rockchip_clk_provider *ctx;
1096 void __iomem *reg_base;
1097
1098 reg_base = devm_platform_ioremap_resource(pdev, 0);
1099 if (IS_ERR(reg_base))
1100 return dev_err_probe(dev, PTR_ERR(reg_base),
1101 "could not map cru region");
1102
1103 nr_clks = rockchip_clk_find_max_clk_id(rk3528_clk_branches,
1104 nr_branches) + 1;
1105
1106 vo_grf = syscon_regmap_lookup_by_compatible("rockchip,rk3528-vo-grf");
1107 if (!IS_ERR(vo_grf)) {
1108 nr_vo_clks = rockchip_clk_find_max_clk_id(rk3528_vo_clk_branches,
1109 nr_vo_branches) + 1;
1110 nr_clks = max(nr_clks, nr_vo_clks);
1111 } else if (PTR_ERR(vo_grf) != -ENODEV) {
1112 return dev_err_probe(dev, PTR_ERR(vo_grf),
1113 "failed to look up VO GRF\n");
1114 }
1115
1116 vpu_grf = syscon_regmap_lookup_by_compatible("rockchip,rk3528-vpu-grf");
1117 if (!IS_ERR(vpu_grf)) {
1118 nr_vpu_clks = rockchip_clk_find_max_clk_id(rk3528_vpu_clk_branches,
1119 nr_vpu_branches) + 1;
1120 nr_clks = max(nr_clks, nr_vpu_clks);
1121 } else if (PTR_ERR(vpu_grf) != -ENODEV) {
1122 return dev_err_probe(dev, PTR_ERR(vpu_grf),
1123 "failed to look up VPU GRF\n");
1124 }
1125
1126 ctx = rockchip_clk_init(np, reg_base, nr_clks);
1127 if (IS_ERR(ctx))
1128 return dev_err_probe(dev, PTR_ERR(ctx),
1129 "rockchip clk init failed");
1130
1131 rockchip_clk_register_plls(ctx, rk3528_pll_clks,
1132 ARRAY_SIZE(rk3528_pll_clks),
1133 RK3528_GRF_SOC_STATUS0);
1134 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
1135 mux_armclk, ARRAY_SIZE(mux_armclk),
1136 &rk3528_cpuclk_data, rk3528_cpuclk_rates,
1137 ARRAY_SIZE(rk3528_cpuclk_rates));
1138 rockchip_clk_register_branches(ctx, rk3528_clk_branches, nr_branches);
1139
1140 if (!IS_ERR(vo_grf)) {
1141 vo_grf_e = devm_kzalloc(dev, sizeof(*vo_grf_e), GFP_KERNEL);
1142 if (!vo_grf_e)
1143 return -ENOMEM;
1144
1145 vo_grf_e->grf = vo_grf;
1146 vo_grf_e->type = grf_type_vo;
1147 hash_add(ctx->aux_grf_table, &vo_grf_e->node, grf_type_vo);
1148
1149 rockchip_clk_register_branches(ctx, rk3528_vo_clk_branches,
1150 nr_vo_branches);
1151 }
1152
1153 if (!IS_ERR(vpu_grf)) {
1154 vpu_grf_e = devm_kzalloc(dev, sizeof(*vpu_grf_e), GFP_KERNEL);
1155 if (!vpu_grf_e)
1156 return -ENOMEM;
1157
1158 vpu_grf_e->grf = vpu_grf;
1159 vpu_grf_e->type = grf_type_vpu;
1160 hash_add(ctx->aux_grf_table, &vpu_grf_e->node, grf_type_vpu);
1161
1162 rockchip_clk_register_branches(ctx, rk3528_vpu_clk_branches,
1163 nr_vpu_branches);
1164 }
1165
1166 rk3528_rst_init(np, reg_base);
1167
1168 rockchip_register_restart_notifier(ctx, RK3528_GLB_SRST_FST, NULL);
1169
1170 rockchip_clk_of_add_provider(np, ctx);
1171
1172 return 0;
1173 }
1174
1175 static const struct of_device_id clk_rk3528_match_table[] = {
1176 { .compatible = "rockchip,rk3528-cru" },
1177 { /* end */ }
1178 };
1179
1180 static struct platform_driver clk_rk3528_driver = {
1181 .driver = {
1182 .name = "clk-rk3528",
1183 .of_match_table = clk_rk3528_match_table,
1184 .suppress_bind_attrs = true,
1185 },
1186 };
1187 builtin_platform_driver_probe(clk_rk3528_driver, clk_rk3528_probe);
1188