1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * PCIe phy driver for Kirin 970
4 *
5 * Copyright (C) 2017 HiSilicon Electronics Co., Ltd.
6 * https://www.huawei.com
7 * Copyright (C) 2021 Huawei Technologies Co., Ltd.
8 * https://www.huawei.com
9 *
10 * Authors:
11 * Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
12 * Manivannan Sadhasivam <mani@kernel.org>
13 *
14 * Based on:
15 * https://lore.kernel.org/lkml/4c9d6581478aa966698758c0420933f5defab4dd.1612335031.git.mchehab+huawei@kernel.org/
16 */
17
18 #include <linux/bitfield.h>
19 #include <linux/bits.h>
20 #include <linux/clk.h>
21 #include <linux/delay.h>
22 #include <linux/device.h>
23 #include <linux/err.h>
24 #include <linux/io.h>
25 #include <linux/mfd/syscon.h>
26 #include <linux/module.h>
27 #include <linux/of.h>
28 #include <linux/phy/phy.h>
29 #include <linux/platform_device.h>
30 #include <linux/regmap.h>
31 #include <linux/types.h>
32
33 #define AXI_CLK_FREQ 207500000
34 #define REF_CLK_FREQ 100000000
35
36 /* PCIe CTRL registers */
37 #define SOC_PCIECTRL_CTRL7_ADDR 0x01c
38 #define SOC_PCIECTRL_CTRL12_ADDR 0x030
39 #define SOC_PCIECTRL_CTRL20_ADDR 0x050
40 #define SOC_PCIECTRL_CTRL21_ADDR 0x054
41
42 #define PCIE_OUTPUT_PULL_BITS GENMASK(3, 0)
43 #define SOC_PCIECTRL_CTRL20_2P_MEM_CTRL 0x02605550
44 #define SOC_PCIECTRL_CTRL21_DEFAULT 0x20000070
45 #define PCIE_PULL_UP_SYS_AUX_PWR_DET BIT(10)
46 #define PCIE_OUTPUT_PULL_DOWN BIT(1)
47
48 /* PCIe PHY registers */
49 #define SOC_PCIEPHY_CTRL0_ADDR 0x000
50 #define SOC_PCIEPHY_CTRL1_ADDR 0x004
51 #define SOC_PCIEPHY_CTRL38_ADDR 0x0098
52 #define SOC_PCIEPHY_STATE0_ADDR 0x400
53
54 #define RAWLANEN_DIG_PCS_XF_TX_OVRD_IN_1 0xc004
55 #define SUP_DIG_LVL_OVRD_IN 0x003c
56 #define LANEN_DIG_ASIC_TX_OVRD_IN_1 0x4008
57 #define LANEN_DIG_ASIC_TX_OVRD_IN_2 0x400c
58
59 #define PCIEPHY_RESET_BIT BIT(17)
60 #define PCIEPHY_PIPE_LINE0_RESET_BIT BIT(19)
61 #define PCIE_TXDETECT_RX_FAIL BIT(2)
62 #define PCIE_CLK_SOURCE BIT(8)
63 #define PCIE_IS_CLOCK_STABLE BIT(19)
64 #define PCIE_PULL_DOWN_PHY_TEST_POWERDOWN BIT(22)
65 #define PCIE_DEASSERT_CONTROLLER_PERST BIT(2)
66
67 #define EYEPARAM_NOCFG 0xffffffff
68 #define EYE_PARM0_MASK GENMASK(8, 6)
69 #define EYE_PARM1_MASK GENMASK(11, 8)
70 #define EYE_PARM2_MASK GENMASK(5, 0)
71 #define EYE_PARM3_MASK GENMASK(12, 7)
72 #define EYE_PARM4_MASK GENMASK(14, 9)
73 #define EYE_PARM0_EN BIT(9)
74 #define EYE_PARM1_EN BIT(12)
75 #define EYE_PARM2_EN BIT(6)
76 #define EYE_PARM3_EN BIT(13)
77 #define EYE_PARM4_EN BIT(15)
78
79 /* hi3670 pciephy register */
80 #define APB_PHY_START_ADDR 0x40000
81 #define SOC_PCIEPHY_MMC1PLL_CTRL1 0xc04
82 #define SOC_PCIEPHY_MMC1PLL_CTRL16 0xC40
83 #define SOC_PCIEPHY_MMC1PLL_CTRL17 0xC44
84 #define SOC_PCIEPHY_MMC1PLL_CTRL20 0xC50
85 #define SOC_PCIEPHY_MMC1PLL_CTRL21 0xC54
86 #define SOC_PCIEPHY_MMC1PLL_STAT0 0xE00
87
88 #define CRGPERIPH_PEREN12 0x470
89 #define CRGPERIPH_PERDIS12 0x474
90 #define CRGPERIPH_PCIECTRL0 0x800
91
92 #define PCIE_FNPLL_FBDIV_MASK GENMASK(27, 16)
93 #define PCIE_FNPLL_FRACDIV_MASK GENMASK(23, 0)
94 #define PCIE_FNPLL_POSTDIV1_MASK GENMASK(10, 8)
95 #define PCIE_FNPLL_POSTDIV2_MASK GENMASK(14, 12)
96 #define PCIE_FNPLL_PLL_MODE_MASK BIT(25)
97
98 #define PCIE_FNPLL_DLL_EN BIT(27)
99 #define PCIE_FNPLL_FBDIV 0xd0
100 #define PCIE_FNPLL_FRACDIV 0x555555
101 #define PCIE_FNPLL_POSTDIV1 0x5
102 #define PCIE_FNPLL_POSTDIV2 0x4
103 #define PCIE_FNPLL_PLL_MODE 0x0
104
105 #define PCIE_PHY_MMC1PLL 0x20
106 #define PCIE_PHY_CHOOSE_FNPLL BIT(27)
107 #define PCIE_PHY_MMC1PLL_DISABLE BIT(0)
108 #define PCIE_PHY_PCIEPL_BP BIT(16)
109
110 /* define ie,oe cfg */
111 #define IO_OE_HARD_GT_MODE BIT(1)
112 #define IO_IE_EN_HARD_BYPASS BIT(27)
113 #define IO_OE_EN_HARD_BYPASS BIT(11)
114 #define IO_HARD_CTRL_DEBOUNCE_BYPASS BIT(10)
115 #define IO_OE_GT_MODE BIT(8)
116 #define DEBOUNCE_WAITCFG_IN GENMASK(23, 20)
117 #define DEBOUNCE_WAITCFG_OUT GENMASK(16, 13)
118
119 #define IO_HP_DEBOUNCE_GT (BIT(12) | BIT(15))
120 #define IO_PHYREF_SOFT_GT_MODE BIT(14)
121 #define IO_REF_SOFT_GT_MODE BIT(13)
122 #define IO_REF_HARD_GT_MODE BIT(0)
123
124 /* noc power domain */
125 #define NOC_POWER_IDLEREQ_1 0x38c
126 #define NOC_POWER_IDLE_1 0x394
127 #define NOC_PW_MASK 0x10000
128 #define NOC_PW_SET_BIT 0x1
129
130 #define NUM_EYEPARAM 5
131
132 /* info located in sysctrl */
133 #define SCTRL_PCIE_CMOS_OFFSET 0x60
134 #define SCTRL_PCIE_CMOS_BIT 0x10
135 #define SCTRL_PCIE_ISO_OFFSET 0x44
136 #define SCTRL_PCIE_ISO_BIT 0x30
137 #define SCTRL_PCIE_HPCLK_OFFSET 0x190
138 #define SCTRL_PCIE_HPCLK_BIT 0x184000
139 #define SCTRL_PCIE_OE_OFFSET 0x14a
140 #define PCIE_DEBOUNCE_PARAM 0xf0f400
141 #define PCIE_OE_BYPASS GENMASK(29, 28)
142
143 /* peri_crg ctrl */
144 #define CRGCTRL_PCIE_ASSERT_OFFSET 0x88
145 #define CRGCTRL_PCIE_ASSERT_BIT 0x8c000000
146
147 #define FNPLL_HAS_LOCKED BIT(4)
148
149 /* Time for delay */
150 #define TIME_CMOS_MIN 100
151 #define TIME_CMOS_MAX 105
152 #define PIPE_CLK_STABLE_TIME 100
153 #define PLL_CTRL_WAIT_TIME 200
154 #define NOC_POWER_TIME 100
155
156 struct hi3670_pcie_phy {
157 struct device *dev;
158 void __iomem *base;
159 struct regmap *apb;
160 struct regmap *crgctrl;
161 struct regmap *sysctrl;
162 struct regmap *pmctrl;
163 struct clk *apb_sys_clk;
164 struct clk *apb_phy_clk;
165 struct clk *phy_ref_clk;
166 struct clk *aclk;
167 struct clk *aux_clk;
168 u32 eye_param[NUM_EYEPARAM];
169 };
170
171 /* Registers in PCIePHY */
hi3670_apb_phy_writel(struct hi3670_pcie_phy * phy,u32 val,u32 reg)172 static inline void hi3670_apb_phy_writel(struct hi3670_pcie_phy *phy, u32 val,
173 u32 reg)
174 {
175 writel(val, phy->base + APB_PHY_START_ADDR + reg);
176 }
177
hi3670_apb_phy_readl(struct hi3670_pcie_phy * phy,u32 reg)178 static inline u32 hi3670_apb_phy_readl(struct hi3670_pcie_phy *phy, u32 reg)
179 {
180 return readl(phy->base + APB_PHY_START_ADDR + reg);
181 }
182
hi3670_apb_phy_updatel(struct hi3670_pcie_phy * phy,u32 val,u32 mask,u32 reg)183 static inline void hi3670_apb_phy_updatel(struct hi3670_pcie_phy *phy,
184 u32 val, u32 mask, u32 reg)
185 {
186 u32 regval;
187
188 regval = hi3670_apb_phy_readl(phy, reg);
189 regval &= ~mask;
190 regval |= val;
191 hi3670_apb_phy_writel(phy, regval, reg);
192 }
193
kirin_apb_natural_phy_writel(struct hi3670_pcie_phy * phy,u32 val,u32 reg)194 static inline void kirin_apb_natural_phy_writel(struct hi3670_pcie_phy *phy,
195 u32 val, u32 reg)
196 {
197 writel(val, phy->base + reg);
198 }
199
kirin_apb_natural_phy_readl(struct hi3670_pcie_phy * phy,u32 reg)200 static inline u32 kirin_apb_natural_phy_readl(struct hi3670_pcie_phy *phy,
201 u32 reg)
202 {
203 return readl(phy->base + reg);
204 }
205
hi3670_pcie_phy_oe_enable(struct hi3670_pcie_phy * phy,bool enable)206 static void hi3670_pcie_phy_oe_enable(struct hi3670_pcie_phy *phy, bool enable)
207 {
208 u32 val;
209
210 regmap_read(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, &val);
211 val |= PCIE_DEBOUNCE_PARAM;
212 if (enable)
213 val &= ~PCIE_OE_BYPASS;
214 else
215 val |= PCIE_OE_BYPASS;
216 regmap_write(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, val);
217 }
218
hi3670_pcie_get_eyeparam(struct hi3670_pcie_phy * phy)219 static void hi3670_pcie_get_eyeparam(struct hi3670_pcie_phy *phy)
220 {
221 struct device *dev = phy->dev;
222 struct device_node *np;
223 int ret, i;
224
225 np = dev->of_node;
226
227 ret = of_property_read_u32_array(np, "hisilicon,eye-diagram-param",
228 phy->eye_param, NUM_EYEPARAM);
229 if (!ret)
230 return;
231
232 /* There's no optional eye_param property. Set array to default */
233 for (i = 0; i < NUM_EYEPARAM; i++)
234 phy->eye_param[i] = EYEPARAM_NOCFG;
235 }
236
hi3670_pcie_set_eyeparam(struct hi3670_pcie_phy * phy)237 static void hi3670_pcie_set_eyeparam(struct hi3670_pcie_phy *phy)
238 {
239 u32 val;
240
241 val = kirin_apb_natural_phy_readl(phy, RAWLANEN_DIG_PCS_XF_TX_OVRD_IN_1);
242
243 if (phy->eye_param[1] != EYEPARAM_NOCFG) {
244 val &= ~EYE_PARM1_MASK;
245 val |= FIELD_PREP(EYE_PARM1_MASK, phy->eye_param[1]);
246 val |= EYE_PARM1_EN;
247 }
248 kirin_apb_natural_phy_writel(phy, val,
249 RAWLANEN_DIG_PCS_XF_TX_OVRD_IN_1);
250
251 val = kirin_apb_natural_phy_readl(phy, LANEN_DIG_ASIC_TX_OVRD_IN_2);
252 val &= ~(EYE_PARM2_MASK | EYE_PARM3_MASK);
253 if (phy->eye_param[2] != EYEPARAM_NOCFG) {
254 val |= FIELD_PREP(EYE_PARM2_MASK, phy->eye_param[2]);
255 val |= EYE_PARM2_EN;
256 }
257
258 if (phy->eye_param[3] != EYEPARAM_NOCFG) {
259 val |= FIELD_PREP(EYE_PARM3_MASK, phy->eye_param[3]);
260 val |= EYE_PARM3_EN;
261 }
262
263 kirin_apb_natural_phy_writel(phy, val, LANEN_DIG_ASIC_TX_OVRD_IN_2);
264
265 val = kirin_apb_natural_phy_readl(phy, SUP_DIG_LVL_OVRD_IN);
266 if (phy->eye_param[0] != EYEPARAM_NOCFG) {
267 val &= ~EYE_PARM0_MASK;
268 val |= FIELD_PREP(EYE_PARM0_MASK, phy->eye_param[0]);
269 val |= EYE_PARM0_EN;
270 }
271 kirin_apb_natural_phy_writel(phy, val, SUP_DIG_LVL_OVRD_IN);
272
273 val = kirin_apb_natural_phy_readl(phy, LANEN_DIG_ASIC_TX_OVRD_IN_1);
274 if (phy->eye_param[4] != EYEPARAM_NOCFG) {
275 val &= ~EYE_PARM4_MASK;
276 val |= FIELD_PREP(EYE_PARM4_MASK, phy->eye_param[4]);
277 val |= EYE_PARM4_EN;
278 }
279 kirin_apb_natural_phy_writel(phy, val, LANEN_DIG_ASIC_TX_OVRD_IN_1);
280 }
281
hi3670_pcie_natural_cfg(struct hi3670_pcie_phy * phy)282 static void hi3670_pcie_natural_cfg(struct hi3670_pcie_phy *phy)
283 {
284 u32 val;
285
286 /* change 2p mem_ctrl */
287 regmap_write(phy->apb, SOC_PCIECTRL_CTRL20_ADDR,
288 SOC_PCIECTRL_CTRL20_2P_MEM_CTRL);
289
290 regmap_read(phy->apb, SOC_PCIECTRL_CTRL7_ADDR, &val);
291 val |= PCIE_PULL_UP_SYS_AUX_PWR_DET;
292 regmap_write(phy->apb, SOC_PCIECTRL_CTRL7_ADDR, val);
293
294 /* output, pull down */
295 regmap_read(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, &val);
296 val &= ~PCIE_OUTPUT_PULL_BITS;
297 val |= PCIE_OUTPUT_PULL_DOWN;
298 regmap_write(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, val);
299
300 /* Handle phy_reset and lane0_reset to HW */
301 hi3670_apb_phy_updatel(phy, PCIEPHY_RESET_BIT,
302 PCIEPHY_PIPE_LINE0_RESET_BIT | PCIEPHY_RESET_BIT,
303 SOC_PCIEPHY_CTRL1_ADDR);
304
305 /* fix chip bug: TxDetectRx fail */
306 hi3670_apb_phy_updatel(phy, PCIE_TXDETECT_RX_FAIL, PCIE_TXDETECT_RX_FAIL,
307 SOC_PCIEPHY_CTRL38_ADDR);
308 }
309
hi3670_pcie_pll_init(struct hi3670_pcie_phy * phy)310 static void hi3670_pcie_pll_init(struct hi3670_pcie_phy *phy)
311 {
312 hi3670_apb_phy_updatel(phy, PCIE_PHY_CHOOSE_FNPLL, PCIE_PHY_CHOOSE_FNPLL,
313 SOC_PCIEPHY_MMC1PLL_CTRL1);
314
315 hi3670_apb_phy_updatel(phy,
316 FIELD_PREP(PCIE_FNPLL_FBDIV_MASK, PCIE_FNPLL_FBDIV),
317 PCIE_FNPLL_FBDIV_MASK,
318 SOC_PCIEPHY_MMC1PLL_CTRL16);
319
320 hi3670_apb_phy_updatel(phy,
321 FIELD_PREP(PCIE_FNPLL_FRACDIV_MASK, PCIE_FNPLL_FRACDIV),
322 PCIE_FNPLL_FRACDIV_MASK, SOC_PCIEPHY_MMC1PLL_CTRL17);
323
324 hi3670_apb_phy_updatel(phy,
325 PCIE_FNPLL_DLL_EN |
326 FIELD_PREP(PCIE_FNPLL_POSTDIV1_MASK, PCIE_FNPLL_POSTDIV1) |
327 FIELD_PREP(PCIE_FNPLL_POSTDIV2_MASK, PCIE_FNPLL_POSTDIV2) |
328 FIELD_PREP(PCIE_FNPLL_PLL_MODE_MASK, PCIE_FNPLL_PLL_MODE),
329 PCIE_FNPLL_POSTDIV1_MASK |
330 PCIE_FNPLL_POSTDIV2_MASK |
331 PCIE_FNPLL_PLL_MODE_MASK | PCIE_FNPLL_DLL_EN,
332 SOC_PCIEPHY_MMC1PLL_CTRL20);
333
334 hi3670_apb_phy_writel(phy, PCIE_PHY_MMC1PLL,
335 SOC_PCIEPHY_MMC1PLL_CTRL21);
336 }
337
hi3670_pcie_pll_ctrl(struct hi3670_pcie_phy * phy,bool enable)338 static int hi3670_pcie_pll_ctrl(struct hi3670_pcie_phy *phy, bool enable)
339 {
340 struct device *dev = phy->dev;
341 u32 val;
342 int time = PLL_CTRL_WAIT_TIME;
343
344 if (enable) {
345 /* pd = 0 */
346 hi3670_apb_phy_updatel(phy, 0, PCIE_PHY_MMC1PLL_DISABLE,
347 SOC_PCIEPHY_MMC1PLL_CTRL16);
348
349 /* choose FNPLL */
350 val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_MMC1PLL_STAT0);
351 while (!(val & FNPLL_HAS_LOCKED)) {
352 if (!time) {
353 dev_err(dev, "wait for pll_lock timeout\n");
354 return -EINVAL;
355 }
356 time--;
357 udelay(1);
358 val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_MMC1PLL_STAT0);
359 }
360
361 hi3670_apb_phy_updatel(phy, 0, PCIE_PHY_PCIEPL_BP,
362 SOC_PCIEPHY_MMC1PLL_CTRL20);
363
364 } else {
365 hi3670_apb_phy_updatel(phy,
366 PCIE_PHY_MMC1PLL_DISABLE,
367 PCIE_PHY_MMC1PLL_DISABLE,
368 SOC_PCIEPHY_MMC1PLL_CTRL16);
369
370 hi3670_apb_phy_updatel(phy, PCIE_PHY_PCIEPL_BP,
371 PCIE_PHY_PCIEPL_BP,
372 SOC_PCIEPHY_MMC1PLL_CTRL20);
373 }
374
375 return 0;
376 }
377
hi3670_pcie_hp_debounce_gt(struct hi3670_pcie_phy * phy,bool open)378 static void hi3670_pcie_hp_debounce_gt(struct hi3670_pcie_phy *phy, bool open)
379 {
380 if (open)
381 /* gt_clk_pcie_hp/gt_clk_pcie_debounce open */
382 regmap_write(phy->crgctrl, CRGPERIPH_PEREN12,
383 IO_HP_DEBOUNCE_GT);
384 else
385 /* gt_clk_pcie_hp/gt_clk_pcie_debounce close */
386 regmap_write(phy->crgctrl, CRGPERIPH_PERDIS12,
387 IO_HP_DEBOUNCE_GT);
388 }
389
hi3670_pcie_phyref_gt(struct hi3670_pcie_phy * phy,bool open)390 static void hi3670_pcie_phyref_gt(struct hi3670_pcie_phy *phy, bool open)
391 {
392 unsigned int val;
393
394 regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val);
395
396 if (open)
397 val &= ~IO_OE_HARD_GT_MODE; /* enable hard gt mode */
398 else
399 val |= IO_OE_HARD_GT_MODE; /* disable hard gt mode */
400
401 regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val);
402
403 /* disable soft gt mode */
404 regmap_write(phy->crgctrl, CRGPERIPH_PERDIS12, IO_PHYREF_SOFT_GT_MODE);
405 }
406
hi3670_pcie_oe_ctrl(struct hi3670_pcie_phy * phy,bool en_flag)407 static void hi3670_pcie_oe_ctrl(struct hi3670_pcie_phy *phy, bool en_flag)
408 {
409 unsigned int val;
410
411 regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val);
412
413 /* set ie cfg */
414 val |= IO_IE_EN_HARD_BYPASS;
415
416 /* set oe cfg */
417 val &= ~IO_HARD_CTRL_DEBOUNCE_BYPASS;
418
419 /* set phy_debounce in&out time */
420 val |= (DEBOUNCE_WAITCFG_IN | DEBOUNCE_WAITCFG_OUT);
421
422 /* select oe_gt_mode */
423 val |= IO_OE_GT_MODE;
424
425 if (en_flag)
426 val &= ~IO_OE_EN_HARD_BYPASS;
427 else
428 val |= IO_OE_EN_HARD_BYPASS;
429
430 regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val);
431 }
432
hi3670_pcie_ioref_gt(struct hi3670_pcie_phy * phy,bool open)433 static void hi3670_pcie_ioref_gt(struct hi3670_pcie_phy *phy, bool open)
434 {
435 unsigned int val;
436
437 if (open) {
438 regmap_write(phy->apb, SOC_PCIECTRL_CTRL21_ADDR,
439 SOC_PCIECTRL_CTRL21_DEFAULT);
440
441 hi3670_pcie_oe_ctrl(phy, true);
442
443 /* en hard gt mode */
444 regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val);
445 val &= ~IO_REF_HARD_GT_MODE;
446 regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val);
447
448 /* disable soft gt mode */
449 regmap_write(phy->crgctrl, CRGPERIPH_PERDIS12,
450 IO_REF_SOFT_GT_MODE);
451
452 } else {
453 /* disable hard gt mode */
454 regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val);
455 val |= IO_REF_HARD_GT_MODE;
456 regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val);
457
458 /* disable soft gt mode */
459 regmap_write(phy->crgctrl, CRGPERIPH_PERDIS12,
460 IO_REF_SOFT_GT_MODE);
461
462 hi3670_pcie_oe_ctrl(phy, false);
463 }
464 }
465
hi3670_pcie_allclk_ctrl(struct hi3670_pcie_phy * phy,bool clk_on)466 static int hi3670_pcie_allclk_ctrl(struct hi3670_pcie_phy *phy, bool clk_on)
467 {
468 struct device *dev = phy->dev;
469 int ret = 0;
470
471 if (!clk_on)
472 goto close_clocks;
473
474 /* choose 100MHz clk src: Bit[8]==1 pad, Bit[8]==0 pll */
475 hi3670_apb_phy_updatel(phy, 0, PCIE_CLK_SOURCE,
476 SOC_PCIEPHY_CTRL1_ADDR);
477
478 hi3670_pcie_pll_init(phy);
479
480 ret = hi3670_pcie_pll_ctrl(phy, true);
481 if (ret) {
482 dev_err(dev, "Failed to enable pll\n");
483 return -EINVAL;
484 }
485 hi3670_pcie_hp_debounce_gt(phy, true);
486 hi3670_pcie_phyref_gt(phy, true);
487 hi3670_pcie_ioref_gt(phy, true);
488
489 ret = clk_set_rate(phy->aclk, AXI_CLK_FREQ);
490 if (ret) {
491 dev_err(dev, "Failed to set rate\n");
492 goto close_clocks;
493 }
494
495 return 0;
496
497 close_clocks:
498 hi3670_pcie_ioref_gt(phy, false);
499 hi3670_pcie_phyref_gt(phy, false);
500 hi3670_pcie_hp_debounce_gt(phy, false);
501
502 hi3670_pcie_pll_ctrl(phy, false);
503
504 return ret;
505 }
506
is_pipe_clk_stable(struct hi3670_pcie_phy * phy)507 static bool is_pipe_clk_stable(struct hi3670_pcie_phy *phy)
508 {
509 struct device *dev = phy->dev;
510 u32 val;
511 u32 time = PIPE_CLK_STABLE_TIME;
512 u32 pipe_clk_stable = PCIE_IS_CLOCK_STABLE;
513
514 val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_STATE0_ADDR);
515 while (val & pipe_clk_stable) {
516 mdelay(1);
517 if (!time) {
518 dev_err(dev, "PIPE clk is not stable\n");
519 return false;
520 }
521 time--;
522 val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_STATE0_ADDR);
523 }
524
525 return true;
526 }
527
hi3670_pcie_noc_power(struct hi3670_pcie_phy * phy,bool enable)528 static int hi3670_pcie_noc_power(struct hi3670_pcie_phy *phy, bool enable)
529 {
530 struct device *dev = phy->dev;
531 u32 time = NOC_POWER_TIME;
532 unsigned int val = NOC_PW_MASK;
533 int rst;
534
535 if (enable)
536 val = NOC_PW_MASK | NOC_PW_SET_BIT;
537 else
538 val = NOC_PW_MASK;
539 rst = enable ? 1 : 0;
540
541 regmap_write(phy->pmctrl, NOC_POWER_IDLEREQ_1, val);
542
543 time = NOC_POWER_TIME;
544 regmap_read(phy->pmctrl, NOC_POWER_IDLE_1, &val);
545 while ((val & NOC_PW_SET_BIT) != rst) {
546 udelay(10);
547 if (!time) {
548 dev_err(dev, "Failed to reverse noc power-status\n");
549 return -EINVAL;
550 }
551 time--;
552 regmap_read(phy->pmctrl, NOC_POWER_IDLE_1, &val);
553 }
554
555 return 0;
556 }
557
hi3670_pcie_get_resources_from_pcie(struct hi3670_pcie_phy * phy)558 static int hi3670_pcie_get_resources_from_pcie(struct hi3670_pcie_phy *phy)
559 {
560 struct device_node *pcie_port;
561 struct device *dev = phy->dev;
562 struct device *pcie_dev;
563
564 pcie_port = of_get_child_by_name(dev->parent->of_node, "pcie");
565 if (!pcie_port) {
566 dev_err(dev, "no pcie node found in %s\n",
567 dev->parent->of_node->full_name);
568 return -ENODEV;
569 }
570
571 pcie_dev = bus_find_device_by_of_node(&platform_bus_type, pcie_port);
572 if (!pcie_dev) {
573 dev_err(dev, "Didn't find pcie device\n");
574 return -ENODEV;
575 }
576
577 /*
578 * We might just use NULL instead of the APB name, as the
579 * pcie-kirin currently registers directly just one regmap (although
580 * the DWC driver register other regmaps).
581 *
582 * Yet, it sounds safer to warrant that it will be accessing the
583 * right regmap. So, let's use the named version.
584 */
585 phy->apb = dev_get_regmap(pcie_dev, "kirin_pcie_apb");
586 if (!phy->apb) {
587 dev_err(dev, "Failed to get APB regmap\n");
588 return -ENODEV;
589 }
590
591 return 0;
592 }
593
kirin_pcie_clk_ctrl(struct hi3670_pcie_phy * phy,bool enable)594 static int kirin_pcie_clk_ctrl(struct hi3670_pcie_phy *phy, bool enable)
595 {
596 int ret = 0;
597
598 if (!enable)
599 goto close_clk;
600
601 ret = clk_set_rate(phy->phy_ref_clk, REF_CLK_FREQ);
602 if (ret)
603 return ret;
604
605 ret = clk_prepare_enable(phy->phy_ref_clk);
606 if (ret)
607 return ret;
608
609 ret = clk_prepare_enable(phy->apb_sys_clk);
610 if (ret)
611 goto apb_sys_fail;
612
613 ret = clk_prepare_enable(phy->apb_phy_clk);
614 if (ret)
615 goto apb_phy_fail;
616
617 ret = clk_prepare_enable(phy->aclk);
618 if (ret)
619 goto aclk_fail;
620
621 ret = clk_prepare_enable(phy->aux_clk);
622 if (ret)
623 goto aux_clk_fail;
624
625 return 0;
626
627 close_clk:
628 clk_disable_unprepare(phy->aux_clk);
629 aux_clk_fail:
630 clk_disable_unprepare(phy->aclk);
631 aclk_fail:
632 clk_disable_unprepare(phy->apb_phy_clk);
633 apb_phy_fail:
634 clk_disable_unprepare(phy->apb_sys_clk);
635 apb_sys_fail:
636 clk_disable_unprepare(phy->phy_ref_clk);
637
638 return ret;
639 }
640
hi3670_pcie_phy_init(struct phy * generic_phy)641 static int hi3670_pcie_phy_init(struct phy *generic_phy)
642 {
643 struct hi3670_pcie_phy *phy = phy_get_drvdata(generic_phy);
644 int ret;
645
646 /*
647 * The code under hi3670_pcie_get_resources_from_pcie() need to
648 * access the reset-gpios and the APB registers, both from the
649 * pcie-kirin driver.
650 *
651 * The APB is obtained via the pcie driver's regmap
652 * Such kind of resource can only be obtained during the PCIe
653 * power_on sequence, as the code inside pcie-kirin needs to
654 * be already probed, as it needs to register the APB regmap.
655 */
656
657 ret = hi3670_pcie_get_resources_from_pcie(phy);
658 if (ret)
659 return ret;
660
661 return 0;
662 }
663
hi3670_pcie_phy_power_on(struct phy * generic_phy)664 static int hi3670_pcie_phy_power_on(struct phy *generic_phy)
665 {
666 struct hi3670_pcie_phy *phy = phy_get_drvdata(generic_phy);
667 int val, ret;
668
669 /* Power supply for Host */
670 regmap_write(phy->sysctrl, SCTRL_PCIE_CMOS_OFFSET, SCTRL_PCIE_CMOS_BIT);
671 usleep_range(TIME_CMOS_MIN, TIME_CMOS_MAX);
672
673 hi3670_pcie_phy_oe_enable(phy, true);
674
675 ret = kirin_pcie_clk_ctrl(phy, true);
676 if (ret)
677 return ret;
678
679 /* ISO disable, PCIeCtrl, PHY assert and clk gate clear */
680 regmap_write(phy->sysctrl, SCTRL_PCIE_ISO_OFFSET, SCTRL_PCIE_ISO_BIT);
681 regmap_write(phy->crgctrl, CRGCTRL_PCIE_ASSERT_OFFSET,
682 CRGCTRL_PCIE_ASSERT_BIT);
683 regmap_write(phy->sysctrl, SCTRL_PCIE_HPCLK_OFFSET,
684 SCTRL_PCIE_HPCLK_BIT);
685
686 hi3670_pcie_natural_cfg(phy);
687
688 ret = hi3670_pcie_allclk_ctrl(phy, true);
689 if (ret)
690 goto disable_clks;
691
692 /* pull down phy_test_powerdown signal */
693 hi3670_apb_phy_updatel(phy, 0, PCIE_PULL_DOWN_PHY_TEST_POWERDOWN,
694 SOC_PCIEPHY_CTRL0_ADDR);
695
696 /* deassert controller perst_n */
697 regmap_read(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, &val);
698 val |= PCIE_DEASSERT_CONTROLLER_PERST;
699 regmap_write(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, val);
700 udelay(10);
701
702 ret = is_pipe_clk_stable(phy);
703 if (!ret)
704 goto disable_clks;
705
706 hi3670_pcie_set_eyeparam(phy);
707
708 ret = hi3670_pcie_noc_power(phy, false);
709 if (ret)
710 goto disable_clks;
711
712 return 0;
713
714 disable_clks:
715 kirin_pcie_clk_ctrl(phy, false);
716 return ret;
717 }
718
hi3670_pcie_phy_power_off(struct phy * generic_phy)719 static int hi3670_pcie_phy_power_off(struct phy *generic_phy)
720 {
721 struct hi3670_pcie_phy *phy = phy_get_drvdata(generic_phy);
722
723 hi3670_pcie_phy_oe_enable(phy, false);
724
725 hi3670_pcie_allclk_ctrl(phy, false);
726
727 /* Drop power supply for Host */
728 regmap_write(phy->sysctrl, SCTRL_PCIE_CMOS_OFFSET, 0);
729
730 /*
731 * FIXME: The enabled clocks should be disabled here by calling
732 * kirin_pcie_clk_ctrl(phy, false);
733 * However, some clocks used at Kirin 970 should be marked as
734 * CLK_IS_CRITICAL at clk-hi3670 driver, as powering such clocks off
735 * cause an Asynchronous SError interrupt, which produces panic().
736 * While clk-hi3670 is not fixed, we cannot risk disabling clocks here.
737 */
738
739 return 0;
740 }
741
742 static const struct phy_ops hi3670_phy_ops = {
743 .init = hi3670_pcie_phy_init,
744 .power_on = hi3670_pcie_phy_power_on,
745 .power_off = hi3670_pcie_phy_power_off,
746 .owner = THIS_MODULE,
747 };
748
hi3670_pcie_phy_get_resources(struct hi3670_pcie_phy * phy,struct platform_device * pdev)749 static int hi3670_pcie_phy_get_resources(struct hi3670_pcie_phy *phy,
750 struct platform_device *pdev)
751 {
752 struct device *dev = &pdev->dev;
753
754 /* syscon */
755 phy->crgctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3670-crgctrl");
756 if (IS_ERR(phy->crgctrl))
757 return PTR_ERR(phy->crgctrl);
758
759 phy->sysctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3670-sctrl");
760 if (IS_ERR(phy->sysctrl))
761 return PTR_ERR(phy->sysctrl);
762
763 phy->pmctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3670-pmctrl");
764 if (IS_ERR(phy->pmctrl))
765 return PTR_ERR(phy->pmctrl);
766
767 /* clocks */
768 phy->phy_ref_clk = devm_clk_get(dev, "phy_ref");
769 if (IS_ERR(phy->phy_ref_clk))
770 return PTR_ERR(phy->phy_ref_clk);
771
772 phy->aux_clk = devm_clk_get(dev, "aux");
773 if (IS_ERR(phy->aux_clk))
774 return PTR_ERR(phy->aux_clk);
775
776 phy->apb_phy_clk = devm_clk_get(dev, "apb_phy");
777 if (IS_ERR(phy->apb_phy_clk))
778 return PTR_ERR(phy->apb_phy_clk);
779
780 phy->apb_sys_clk = devm_clk_get(dev, "apb_sys");
781 if (IS_ERR(phy->apb_sys_clk))
782 return PTR_ERR(phy->apb_sys_clk);
783
784 phy->aclk = devm_clk_get(dev, "aclk");
785 if (IS_ERR(phy->aclk))
786 return PTR_ERR(phy->aclk);
787
788 /* registers */
789 phy->base = devm_platform_ioremap_resource(pdev, 0);
790 if (IS_ERR(phy->base))
791 return PTR_ERR(phy->base);
792
793 hi3670_pcie_get_eyeparam(phy);
794
795 return 0;
796 }
797
hi3670_pcie_phy_probe(struct platform_device * pdev)798 static int hi3670_pcie_phy_probe(struct platform_device *pdev)
799 {
800 struct phy_provider *phy_provider;
801 struct device *dev = &pdev->dev;
802 struct hi3670_pcie_phy *phy;
803 struct phy *generic_phy;
804 int ret;
805
806 phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
807 if (!phy)
808 return -ENOMEM;
809
810 phy->dev = dev;
811
812 ret = hi3670_pcie_phy_get_resources(phy, pdev);
813 if (ret)
814 return ret;
815
816 generic_phy = devm_phy_create(dev, dev->of_node, &hi3670_phy_ops);
817 if (IS_ERR(generic_phy)) {
818 dev_err(dev, "failed to create PHY\n");
819 return PTR_ERR(generic_phy);
820 }
821
822 phy_set_drvdata(generic_phy, phy);
823 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
824
825 return PTR_ERR_OR_ZERO(phy_provider);
826 }
827
828 static const struct of_device_id hi3670_pcie_phy_match[] = {
829 {
830 .compatible = "hisilicon,hi970-pcie-phy",
831 },
832 {},
833 };
834
835 static struct platform_driver hi3670_pcie_phy_driver = {
836 .probe = hi3670_pcie_phy_probe,
837 .driver = {
838 .of_match_table = hi3670_pcie_phy_match,
839 .name = "hi3670_pcie_phy",
840 .suppress_bind_attrs = true,
841 }
842 };
843 builtin_platform_driver(hi3670_pcie_phy_driver);
844
845 MODULE_DEVICE_TABLE(of, hi3670_pcie_phy_match);
846 MODULE_DESCRIPTION("PCIe phy driver for Kirin 970");
847 MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@kernel.org>");
848 MODULE_AUTHOR("Manivannan Sadhasivam <mani@kernel.org>");
849 MODULE_LICENSE("GPL v2");
850